05.

ELECTRONICS-II
Ans. (a) : The standard binary code for the
I. Number system alphanumeric characters is ASCII (American Standard
code for Information Interchange). It uses seven bits
1. What is the decimal equivalent of the
code. If the ASCII character H is sent and the character
hexadecimal number BF9?
I is received, then single bit error is represented.
(a) 2802 (b) 3065
(c) 2048 (d) 1024 6. Express 84 in octal system.
PGCIL NR-III, 22.08.2021 (a) (1000)8 (b) (10000)8
(c) (10100)8 (d) (101000)8
Ans. (b) : RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
(BF9) 16 = (11159)16
( )
4
= (1011 1111 1001)2 Ans. (b) : 84 = 23 = 212 = 4096
=1×211+0×210+1×29+ 1×28+1×27+1×26+1×25 (10000)8
+1×24 + 1×23 +0×22+0×2+1×20
= (3065)10
2. Decimal equivalent of a binary number
1010111 is :
(a) 71 (b) 77
(c) 87 (d) 89
GSSSB AAE 2021
Ans. (c) :
(1010111)2 = 1×26 + 0×25+1×24+0×23 +1×22+1×21 +1× 20
64+0+16+0+4+2+1 = (87)10.
7. What is 10011010 in decimal?
3. Given (125)R = (203)5. The value of radix R will (a) 154 (b) 128
be (c) 142 (d) 136
(a) 16 (b) 10 PGCIL SR- II, 22.08.2021
(c) 8 (d) 6
Ans. (a) : (10011010)2 → (154)
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
= 1×27 +0 ×26 + 0×25 +1×24+1×23+0×22+1×21+0×20
Ans. (d) : (125)R= (203)5
⇒ 128 +16 +8 + 2 ⇒154
1×R2+2×R+5×R0 = 2×52 + 0 × 51 + 3 × 50
R2 + 2R + 5 = 50 + 3 8. Basically the ASCII scheme uses how many
bits for 128 different characters?
R + 2R –48 = 0
2
(a) 6 (b) 7
R = 6, – 8 (c) 8 (d) 16
Take positive value RRB JE Bhopal Paper II (Shift-II), 26.08.2015
So, radix will be- RRB SSE (shift-III), 02.09.2015
R=6 RRB JE (Shift - III) 26.08.2015
4. The decimal equivalent of hexadecimal number RRB Chandigarh 2014
of 2A0F is Ans : (b) ASCII (American standard code for
(a) 17670 (b) 17667 information interchange) can represent 128 characters.
(c) 17067 (d) 10767 It uses 7 bits to represent each character.
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II 9. What is the ‘base’ of the hexadecimal number
Ans. (d) : (2A0F)16  →(10767)10 system?
3 2 1 (a) 16 (b) 8
2 × 16 + A × 16 + 0 × 16 + F × 16º
3 2 1 (c) 2 (d) 10
= 2 × 16 + 10 × 16 + 0 × 16 + 15 × 16º
PSPCL JE 2019, Shift-I
= 2 × 4096 + 10 × 256 + 0 + 15
UPPCL JE 27.11.2019, Shift-I
= 10767 BSNL TTA 26.09.2016, 3 PM
5. If the ASCII character H is sent and the Ans. (a) : Hexadecimal: Number system the word
character I is received, what type of error is
"Hexadecimal" means sixteen because this type of
represented?
digital numbering system uses 16-different digit from 0
(a) Single bit (b) Multiple bit
(c) Burst (d) Recoverable to 9, and A to F. Thus the base of the hexadecimal
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II number system is '16'.
Electronics-II 786 YCT
10. 2’s complement of the number of 1010101 is Ans. (a) : To determine 1's compliment of binary
(a) 0101010 (b) 0101011 number, the given number is subtracted from maximum
(c) 1101010 (d) 1110011 possible number is given base.
SSC JE 26.09.2019 Shift - II Given number - 010010
HPSSSB JE 2018 (Post code 663) 1's complement =111111 - 010010
HPSSC JE 2017 (Code 580)
= 101101
Ans. (b) :
1's complement of the number 1010101= 0101010. 17. The result of binary addition of 16 and -83
2’s complement of the number of (1010101) using 2's compliment is:
= 0101010+1 (a) 10000102 (b) 10000112
= 0101011 (c) -10000102 (d) -10000112
11. Binary number 11001 is equivalent to decimal MPPKVVCL JE-2018
number: PGCIL Diploma Trainee 27.10.2018
(a) 35 (b) 15 Ans. (d) : Greater negative : add(–83)10 and (16)10
(c) 105 (d) 25 We have (1010011)2→(83)10
NMRC JE 2019 (10000)2 →(16)10
HPSSSB JE-2017 (Post code- 579)
∴ ( 0101101)2 →2's complement of 83
Ans. (d) : (11001)2 = ( )10
= 1×24+1×23+0×22+0×21+1×20 Addition of (–83) and (16)
= 16+8+0+0+1
= 25
∴(11001) 2 = (25)10
12. Which one of the following is non-valid BCD
code ?
(a) 01111001 (b) 01011011
(c) 01001000 (d) 01001001 Carry is not generated then asign 2's complement and
HPSSSB JE-2017 (Post code- 579) result is negative.
Ans. (b) : A BCD is Binary coded decimal number 1 0 1 1 1 1 0 1
BCD number range from 0 to 9 After 9 the number 10
to 15 are not part of a BCD (0 to 9) system and hence 0 1 0 0 0 0 1 0
invalid. + 1
8421 8421
the 0 1 0 0 0 0 1 1→( 67 )10
0 1 0 1 ⇒ 5 1 0 1 1 ⇒ 11
the 01011011 is not valid for BCD code The result of binary addition of 16 and -83 using 2's
13. The decimal equivalent of (1431)8 is compliment is -10000112.
(a) 793 (b) 739 18. The 2’s complement representation of 17 is
(c) 379 (d) 397 (a) 01110 (b) 11110
HPSSSB JE-2017 (Post code- 579) (c) 01111 (d) 10001
Ans. (a) : (1431)8 = 1×83+4×82+3×81+1×80 Ans. (d) : Binary number of 17 = 10001
= 512 +256 +24+1 = (793)10 ∵ We can find 2's complement of (–Ve) number only.
14. The BCD equivalent of decimal number 7 is:
(a) 0111 (b) 1110 ∴ 2's complement of 17 =10001
(c) 0011 (d) 1100 19. The octal equivalent of (177)10 is:
MPPKVVCL (Jabalpur) JE -2018 (a) (261)8 (b) (251)8
Ans. (a) : (7)10 = (111)2 (c) (231)8 (d) (162)8
↓ PGCIL Diploma Trainee 14.11.2018
( 0111)BCD Ans : (a) (177)10 =
15. What is the decimal equivalent number of
binary number 101101?
(a) 45 (b) 90
(c) 40 (d) 8
MPPKVVCL (Jabalpur) JE -2018
Ans. (a) : (101101) 2 → ( )10 Hence (177)10 = (261)8
20. What is binary equivalent of decimal number
1×25+0×24+1×23+1×22+0×21+1×2º= 45
26?
16. What is the value of 1's compliment of 010010?
(a) 101101 (b) 100110 (a) 11110 (b) 11001
(c) 011001 (d) 011101 (c) 11111 (d) 11010
MPPKVVCL (Jabalpur) JE -2018 PGCIL Diploma Trainee 14.11.2018
Electronics-II 787 YCT
Ans : (d) Ans : (b) Extracting 1's complement of-
( −01101)2 = ( 01101)2 = (10010 )2
Note: 1's complement means that instead of 1 is 0 and
instead of 0 is 1, then 1's complement will be obtained.
26. Find the decimal equivalent of the 6-bit binary
number 101.1012.
(a) 5.62510 (b) 5.2510
(c) 6.62510 (d) 5.12510
UPPCL JE 25.11.2019, Shift-I
Ans : (a)
Hence, (26)10 = (11010)2 (101.101) 2 = 1× 22 + 0 × 21 + 1× 20 + 1× 2 −1 + 0 × 2−2 + 1× 2 −3
21. What is the decimal equivalent of the
1 1
hexadecimal number (2F)16? = 4 +1+ + 0 + 3
(a) 47 (b) 572 2 2
(c) 527 (d) 74 = 5 + 0.5 + 0.125
PSPCL JE 2019, Shift-I = (5.625)10
Ans. (a) : Given hexa decimal number (2F)16 27. What is the binary equivalent of the decimal
Decimal number = ? number 13?
1
(2F)16 = 2 × 16 + 15 × 16 0
{∵ F = 15} (a) 1111 (b) 1011
= 2 ×16 + 15 × 1 (c) 1101 (d) 1001
= 32 + 15 Vizag Steel JET 25.10.2018, Shift-II
( 2F )16 = ( 47 )10 Ans. (c) : Decimal to binary
UGVCL JE - 2014

22. Let 312 as a number in the base-B number

system, where B is unknown. If (312)B = (54)10,
then what is the value of the base B?
(a) 6 (b) 5
(c) 4 (d) 12
PSPCL JE 2019, Shift-I
Ans. (c) : ( 312 )B = ( 54 )10 28. What is the binary equivalent of the decimal
number 15?
3 × B + 1 × B + 2 × B = 54
2 1 0
(a) 1101 (b) 1011
3B2 + B + 2 = 54 (c) 1111 (d) 1001
3B2 + B − 52 = 0 Vizag Steel JET 27.10.2018
B = 4, BSNL TTA 25.09.2016, 3:00 PM
23. 4F2D is a/an ____ number. Ans. (c) : The easiest way to convert decimal number
(a) binary (b) hexadecimal into binary by dividing the decimal number by 2 until
(c) octal (d) decimal the remainder reach 0 or 1. Write down the remainders
SSC JE 26.09.2019, Shift-I from bottom to Top.
Ans. (b) : 4F2D is a hexadecimal number. Convert 1510 in to binary
In this system 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 number and A, remainders.
B, C, D, E, F word are use.
24. In Excess-3 code the 4-bit group that is used
is…………..?
(a) 0001 (b) 0011
(c) 0010 (d) 1110
SSC JE 26.09.2019, Shift-II
Ans. (b) : 0011
0000 29. What is the binary equivalent of the decimal
0011 number 11?
0011 (a) 1111 (b) 1011
Excess-3 code 4-bit group 0011. (c) 1101 (d) 1001
Excess -3 code is also known as self complementary Vizag Steel 25.10.2018 Shift-I
code. Ans. (b) : (11)10→(1011)2
It is a 4 bit code and it can be delivered from BCD
code by adding "3" to each coded number.
25. What is the 1's complement of (–01101)2?
(a) 010112 (b) 100102
(c) 010102 (d) 100112
UPPCL JE 25.11.2019, Shift-I
Electronics-II 788 YCT
30. In computing and electronics systems BCD is Ans. (d) : Decimal → Binary
abbreviation of (0.0625)10 → ( )2
(a) Binary Coded Decimal 0.0625×2 = 0.125 → 0
(b) Binary Coded Digit 0.125×2 = 0.25 → 0
(c) Bit Coded Decimal 0.25×2 = 0.5 → 0
(d) Bit Coded Digit 0.5×2 = 1 → 1
UGVCL JE-2014 (0.0625)10 → (0.0001)2
Ans. (a) : In computing and electronics system BCD 35. The binary equivalent of hexadecimal number
is abbreviation of Binary Coded Decimal. A0B5 is
BCD is a class of binary encodings of decimal (a) 0101110100001010
numbers where each digit is represented by a fixed (b) 0101111101001010
number of bits, usually four or eight. (c) 1010000010110101
31. What is the binary equivalent of the decimal (d) 1011000011000101
value 2010? HPSSSC JE 2018 Code -387
(a) 110002 (b) 101002 Ans. (c) : Hexadecimal → Binary
(c) 101012 (d) 101102 (A0B5)16 → ( )2
SSC JE 29.10.2020, Shift-II Number Hexa Binary
UPPCL JE 25.11.2019 Shift - I 10 A 1010
Ans : (b) (20)10 = (10100)2 0 0 0000
11 B 1011
2 20 0 5 5 0101
(A0B5)16 → (1010000010110101)2
2 10 0
36. The binary equivalent of the decimal number
2 5 1 = (10100) 2 10 is _______.
2 2 0 (a) 10 (b) 1010
(c) 010 (d) 0010
1 1 RRB JE 19.09.2019 Shift-II
32. Consider the representation of six-bit numbers Ans. (b) : 10 in binary
in two's complement, one's complement and 10 = (1010)2
sign and magnitude format. In which
representation, the addition of integers 011000
& 011000 will result in an overflow.
(a) In two's complement only
(b) In one's complement and two's complement
(c) Sign and magnitude and one's complement
(d) In all three
ISRO TA 2016 37. Method of representing numbers such as 0's
Ans. (d) : 1's complement - and 1's is called-
The 1's complement of a binary number is obtained by (a) Secondary notation (b) Variable notation
changing its each '0' into a '1' and each '1' into a '0'. (c) Primary notation (d) Binary notation
2's complement- RRB JE 01.09.2019 Shift-I
The 2's complement of a binary number is obtained by Ans. (d) : Method of representing numbers such as 0's
adding '1' to its 1's complement. and 1's is called binary notation. Binary (or base-2) or
33. The decimal equivalent of the Hexadecimal numberic system that only uses two digits 0 and 1.
number (BAD)16 is Computers operates in binary, meaning they store data
(a) 111013 (b) 5929 and perform calculations using only zeros and ones.
(c) 3416 (d) 2989 38. What is the binary representation of 73?
HPSSSC JE 2018 Code -387 (a) 1001100 (b) 1001101
Ans. (d) : Hex → Decimal (c) 1001001 (d) 1001111
RRB JE 30.08.2019 Shift-II
(BAD)16 → ( )10
B = 11, A = 10, D = 13 Ans. (c) :
2 1 0
= 11× (16) + 10 × (16) + 13×(16)
= 2816 + 160 + 13
= 2989
(BAD)16 → (2989)10
34. The binary equivalent of decimal number
0.0625 is
(a) 1001110001 (b) 0.1001110001
(c) 0.0110001110 (d) 0.0001
HPSSSC JE 2018 Code -387 (1001001)2
Electronics-II 789 YCT
39. Find the 2'S complement of (10110010)2 Remember binary coded decimal numbers stop at 9
(a) (01001101)2 (b) (11001110)2 (1001)2.
(c) (10111110)2 (d) (01001110)2 Although other decimal numbers can be represented in
UPPCL JE 27.11.2019, Shift-I BCD code but they are classed as forbidden numbers
Ans : (d) and can not be used.
45. X = 01110 and Y = 11001 are two 5-bit binary
numbers represented in two's complement
format. The sum of X and Y represented in
two's complement format using 6 bits is.
(a) 100111 (b) 10000
] (c) 111 (d) 101001
2' S compliment (10110010)2 = (01001110)2 BSNL TTA 29.09.2016, 3 pm
Note- For 1'S compliment change 1 → 0 and 0 → 1 Ans : (c) X = 001110
For 2'S compliment add "1" in 1'S compliment. Y = 111001
40. In a binary number system, nibble means: X+Y = 000111
(a) 1 bit (b) 8 bits Carry is discarded in the addition of numbers
(c) 4 bits (d) 16 bits represented in 2's complement form. (X+Y) in 6 bits are
UPPCL JE 27.11.2019, Shift-I 000111.
Ans : (c) Each 1 or 0 in a binary number is called a bit. 46. 1's complement of 17 is:
From the a group of 4 bits is called a nibble and 8 bits (a) 01110 (b) 10001
make byte. (c) 10111 (d) 11100
41. 0110 in binary form can be written as...........in UJVNL JE 2016
decimal form– Ans. (b) : The decimal number (17), first it is converted
(a) 4 (b) 5 into binary.
(c) 6 (d) 7 2 17 R
UPPCL JE 11.11.2016
Ans : (c) (0110)2 = (?)10 2 8 1
∴ (0110)2 = (0× 23 ) + (1× 22 ) + (1× 21 ) + (0× 20 ) 2 4 0
 10 2 2 0
(0110)2 = (0 + 4 + 2 + 0)10
2 1 0
(0110)2 = (6)10 0 1
42. Which of the following is not an invalid BCD (17) = (10001)2
code? Because 1's or 2's complement can find only for -Ve
(a) 1001 (b) 1010 number.
(c) 1011 (d) 1100 ∴ 1's complement of (17) = (10001)2
UPPCL JE 27.11.2019, Shift-II 47. Excess 3 code is known as:
Ans. (a) : Up to 9 decimals are used in BCD code, it (a) Weighted code
contains 6 invalided codes. BCD code (0 to 1001) is (b) Cyclic redundancy code
used and (1010 to 1111) is not used. (c) Self complementing code
43. Binary equivalent of decimal number 14 (d) Algebraic code
(a) 1110 (b) 1010 UJVNL JE 2016
(c) 1000 (d) 0101 Ans. (c) : Excess-3 code is self complementary binary
ISRO TA 2015 coded decimal code in numerical system which has
Ans. (a) : Binary equivalent of decimal number– biased representation.
(14) 10→(1110)2 Excess-3 code is also known as self complementary
code.
It is a 4 bit code, and it can be delivered from BCD code
by adding "3" to each coded number.
48. The decimal equivalent of binary number
1001.101 is
44. Which of the following is invalid state in 8421 (a) 9.750 (b) 9.625
binary coded decimal ? (c) 10.750 (d) 10.625
(a) 1110 (b) 0001 ESE 2019
(c) 1000 (d) 0100 Ans. (b) : (1001.101)2 = ( ? )10
NLC GET 17.11.2020 = 1×23+0×22+0×21+1×20+1×2–1+0×2–2+1×2–3
Ans. (a) : BCD means binary coded decimal. The 1 1
binary coded decimal system is that each decimal digit = 8 + 0 + 0 +1+ + 0 +
2 8
is represented by a group of 4 binary digits. For the 10
5
decimal digits (0 to 9) we need a 4 bit binary code. = 9 + = 9 + 0.625 = (9.625)10
8
Electronics-II 790 YCT
49. Convert decimal 41.6875 into equivalent binary: Where W, X, Y, Z are given by (d is the
(a) 100101.1011 (b) 100101.1101 complement of D)
(c) 101001.1011 (d) 101001.1101 (a) D, d, 1, 1 (b) 1, d, D, 1
ESE 2019 (c) 1, 1, D, d (d) 1, D, d, 1
Ans. (c) : ESE 2018
Ans. (d) : The function of given truth table
F = A BC W + A BC X + A BC Y + ABC Z ...(i)
The given function is :-
f(A, B, C, D) = Σm(0, 1, 3, 4, 8, 9)
K-map of given function :-
(41)10 = (101001)2 = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
⇒ 0.6875 × 2 = 1.375 = 1 = ABC(D + D) + ABCD + ABCD + ABC(D + D)
⇒ 0.375 × 2 = .75 = 0 = ABC + ABCD + ABCD + ABC
⇒ 0.75 × 2 = 1.5 = 1 = ABC ⋅1 + ABCD + ABCD + ABC ⋅1
⇒ 0.5 × 2 = 1.0 = 1 54. The hexadecimal of the binary number
(0.6875)10 = (1011)2 (11010011)2 is
Hence (41.6875)10 = (101001.1011)2 (a) D316 (b) D416
50. The decimal value of signed binary number (c) C316 (d) C416
11101000 expressed in 1's complement is ESE 2020
(a) -223 (b) -184 Ans. (a) : During binary to Hexadecimal conversion,
(c) -104 (d) -23 We start four bits grouping from LSB to MSB and write
ESE 2019 the equivalent Hexadecimal numbers of each four bits
Ans. (d) :Binary Number = 11101000 (–Ve Number) group.
1's complement = 00010111
Decimal equivalent of 1's complement of given binary
number = (–23)10
51. What is the octal equivalent of (5621.125)10?
(a) 11774.010 (b) 12765.100
(c) 16572.100 (d) 17652.010 10, 11, 12, 13, 14, 15 ← Decimal
ESE 2017 A, B, C, D, E, F ← Hexadecimal
Ans. (b) : For integer part 55. If a negative binary number is to be
represented by n-bits, then the standard format
will be
(a) Sign bit '0' on left and magnitude on right
(b) Sign bit '1' on left and magnitude on right
(c) Sign bit '0' on right and magnitude on left
(d) Sign bit '1' on right and magnitude on left
ESE 2020
Ans. (b) : In signed binary number MSB indicates that
for decimal part 0.125 × 8 = 1 the given number is +Ve or –Ve. The other bits show
Hence, (5621.125)10 = (12765.100)8 the magnitude of the given binary number.
52. What is the hexadecimal representation of
(657)8 ?
(a) 1 AF (b) D 78
(c) D 71 (d) 32 F
ESE 2017 Positive sign bit is 0 and negative sign bit is 1.
56. Describe (407)8 in Hexadecimal.
 6 5 7  (a) (107)16 (b) (701)16
Ans. (a) : (657)8 =  110 101 111 = (1 AF)16 (c) (017)16 (d) (710)16
 
 2 (RRB Mumbai 2015)
53. The Truth table for the function f(ABCD) = Ans : (a) (407)8 Octal convert to hexadecimal
Σm(0, 1, 3, 4, 8, 9) is 4 0 7 Octal Numbers
A B C f 100, 000, 111 Binary Numbers
0 0 0 W Binary Numbers convert to hexadecimal Numbers
0 0 1 X 0001, 0 0 0 0, 0 1 1 1
0 1 0 Y 1 0 7 hexadecimal Numbers
0 1 1 0 (107)16
1 0 0 Z 57. Decimal equivalent of binary (101010)2
1 0 1 0 (a) 24 (b) 42
1 1 0 0 (c) 64 (d) 44
1 1 1 0 (RRB Mumbai 2015)
Electronics-II 791 YCT
Ans : (b) Binary convert to decimal 63. In Binary Coded Decimal (BCD) systems, the
(101010)2 =1×25+0×24+1×23+0×22+1×21+0×20 decimal number 81 is represented as–
=1×2×2×2×2×2+0+1×2×2×2+0+1×2+0 (a) 10000001 (b) 10100010
= 32 + 8 + 2 = 42 (c) 01010001 (d) 00011000
58. The number of bits in a Byte is. (RRB JE (Shift-III), 16.09.2015)
(a) 2 (b) 8 Ans : (a) BCD of 81 is-
(c) 4 (d) 16
(RRB Ajmer-2014)In BCD code,
Ans : (b)1 Byte = 8 bit system is that each decimal digit is represented by a
1024 Byte = 1 KB group of 4 binary digits.
1024 KB = 1 MB 64. Decimal equivalent of octal number 12 is?
1024 MB = 1 GB (a) 9 (b) 10
1024 GB = 1TB (c) 11 (d) 12
59. Number of bits needed to code 256 operations is: (RRB JE (Shift-3), 28.08. 2015)
(a) 4 (b) 6 Ans : (b) 12 in octal number-
(c) 8 (d) 16 (12)8 = 1 × 81 + 2 × 80 = 8 + 2
(RRB SSE (Shift-II), 03.09.2015) = (10)10
Ans (c) : 8 bits needed to code 256 operation 65. The 2's complement of binary number
2 n = 256 (00001111)2 is?
2 n = 28 (a) (00001111)2 (b) (11110000)2
(c) (10101010)2 (d) (11110001)2
n = 8 bit (RRB JE (Shift-3), 28.08. 2015)
60. The binary representation of the decimal Ans : (d) 00001111, 1's complement is 11110000.
number 45.25 is– 2's complement
(a) (101101.01)2 (b) (101101.10)2
(c) (101010.01)2 (d) (1010101.10)2
(RRB JE (Shift-I), 29.08.2015)
Ans : (a) 66. The value of the binary 11111 is:
(a) 24 –1 (b) 24
5
(c) 2 (d) 25 –1
(RRB SSE Secunderabad Red Paper, 21.12. 2014)
Ans : (d) (11111)2 = ( ) 10
4 3 2 1 0
(11111)2 = (2 ×1+2 ×1+2 ×1+2 ×1+2 ×1)
= (16+8+4+2+1)
5
= 31 = (2 –1)
(101101) 67. 2's complement of binary number (11110000)2
So, (101101.01)2 is?
61. The 2's complement of the binary number (a) (00001111)2 (b) (11110000)2
(11001100)2 is (c) (00010000)2 (d) (10101010)2
(a) (00110100)2 (b) (00110011)2 (RRB JE Bhopal Paper-I (Shift-II), 28.08.2015)
(c) (00110000)2 (d) (11110100)2 Ans : (c) Binary (11110000)2
(RRB SSE (Shift-II), 01.09.2015) 11110000
Ans : (a) 11001100, 1's complement = 00110011 1's → 00001111
So, 2's complement-
00001111
00110011
+1
+1
2's → ( 00010000 )
00110100
62. Hexadecimal equivalent of binary number = ( 00010000 )2
1010 is : 68. The 2's complement of the Binary number
(a) A (b) B (11011100)2 is–
(c) C (d) D (a) (00100011)2 (b) (11110000)2
(RRB JE (Shift-III), 16.09.2015) (c) (00100100)2 (d) (00001111)2
Ans : (a) 1010 → A (RRB JE (Shift-II), 04.09.2015)
1011 → B Ans : (c) Binary number = (11011100)2
1100 → C 1's complement = 00100011
1101 → D 00100011
1110 → E + 1
1111 → F 2's complement = 00100100

Electronics-II 792 YCT

69. The octal equivalent of decimal number 66 is– Ans : (d)
(a) 102 (b) 104
(c) 84 (d) 82
(RRB JE (Shift-2), 29.8.2015)
Ans : (a)

So, (66)10 = (102)8

70. The decimal representation of the binary
number (101010.011)2 is
= (11000011.10 )2
(a) 42.25 (b) 24.25
(c) 24.375 (d) 42.375 74. The 2's complement of the binary number
(RRB JE (Shift-2), 29.8.2015) (00000000)2 is
(a) (11111111)2 (b) (00000000)2
Ans : (d) (101010.011)2 = 1×25 + 0×24 + 1×23 + 0×22 +
(c) (10101010)2 (d) (01010101)2
1×21 + 0 ×20 + 0×2–1 + 1×2–2 + 1×2–3 (RRB JE (Shift-III), 26.08.2015)
1 1 Ans : (b) 1's complement of 00000000 = 11111111
= 32 + 0 + 8 + 0 + 2 + 0 + 0 + 2 + 3
2 2 2's complement,
1 1 11111111
= 42 + + = 42 + 0.25 + 0.125
4 8 +1
(101010.011)2 = (42.375)10
1 00000000
71. Hexadecimal equivalent of decimal number So, answer is 00000000, and left the carry 1.
210? 75. BCD coding scheme uses bits to code decimal
(a) H1 (b) F2 digits.
(c) D2 (d) H2 (RRB JE (Shift-III), 26.08.2015)
(RRB JE Secundrabad (Shift-I), 18.08.2015) (a) 4 (b) 8
Ans : (c) (c) 16 (d) 32
Ans : (a) In BCD code system is that each decimal digit
is represented by a group of 4 binary digits.
76. In a binary number, the leftmost bit is called :
So, (210)10 = (D2)16 (RRB SSE (Shift-II), 03.09.2015)
(a) Most significant bit
72. Considering 1's complement representation for (b) Least significant bit
negative numbers, -85 will be stored into an 8- (c) Carry bit
bit memory space as (d) Extra bit
(a) 10101010 (b) 10111111 Ans (a) : In a binary number, the leftmost bit is called
(c) 10100110 (d) 11101001 most significant bit.
(RRB SSE Secundrabad (Shift-I), 02.09.2015) 77. The system on which digital system usually
Ans : (a) operates is–
(RRB JE (Shift-I), 29.08.2015)
(a) binary (b) decimal
(c) octal (d) hexa-decimal
Ans : (a) The system on which digital system usually
operates is binary.
78. If (101)n = 65, where n represents the base of
the respective number system, then the value of
n is–
(a) 2 (b) 4
(c) 8 (d) 16
85 = 1010101 (RRB JE (Shift-III), 16.09.2015)
+85 = 01010101 Ans : (c) (101)n = 65
1's complement of 01010101 = 10101010 1×n2+ 0×n1 +1×n0 = 65
–85 = 10101010 n 2 + 1 = 65
73. The binary representation of 195.5 is________ n2 = 64
(a) (11000001.01)2 (b) (11000001.11)2 n=8
(c) (11000011.01)2 (d) (11000011.10)2 We take positive number
(RRB JE (Shift-III), 26.08.2015) So, base is 8.
Electronics-II 793 YCT
79. A single binary digit is called : 85. The binary code of [(10.625)]10 is:-
(a) Byte (b) Bit (a) (1010.101)2 (b) (1010.100)2
(c) Data (d) Logic (c) (1010.111)2 (d) (1010.010)2
DMRC JE 03.08.2014 UPPCL JE 11.02.2018, Shift-I
Ans. (b) : A single binary digit is called bit. Bit is the Ans : (a)
smallest unit of computer memory.
[8Bit = 1Byte]
80. The radix of binary number is
(a) 1 (b) 0
(c) 2 (d) 8
JKSSB JE 2014
Ans. (c) : Binary number consists of two digit only (10) = (1010)2
'zero' and 'one' therefore the radix of binary number is
'2'. Whenever radix of octal is '8', radix of decimal is
'10' and radix of hexa-decimal is '16'
81. What is the decimal equivalent of hexa decimal
no (8A6)? (10.625)10 = (1010.101)2
(a) 1422 (b) 1242
86. In decimal system 63 can be written in binary
(c) 2122 (d) 2214
systems as
JKSSB JE 2014
(a) 111100 (b) 111101
Ans. (d) : Given: (8A6)16 = (?)10 (c) 111111 (d) 101010
In hexa decimal A = 10 Then, BSNL TTA (JE) 25.09.2016, Shift-I
(8A6)16 = 160 × 6 + 161 × 10 + 162 × 8
Ans. (c) : Decimal number (63) written as in binary
= 1 × 6 + 160 + 256 × 8
number -
= 6 + 160 + 2048
(8A6)16 = (2214)10
82. The decimal number of the octal number 372
is:
(a) 250 (b) 210
(c) 200 (d) 215
DSSSB JE 19.03.2021, Shift-I
Ans. (a) : (372)8 = (?)10

(63)10 = (111111)2
87. The 9's complement of a decimal digit is the
(a) 1's Complement of the Excess-3 code for the
83. For the binary number 11101000, the Digit
equivalent hexadecimal number is (b) 2's Complement of the Excess-3 code for the
(a) F9 (b) F8 Digit
(c) E9 (d) E8 (c) 1's Complement of the Excess-4 code for the
HPSSC JE 2017(Code-580) Digit
Ans. (d) : Given binary number- (d) 2's Complement of the Excess-4 code for the
(11101000)2= ( )16 Digit
( 1110 1000)16 BSNL TTA (JE) 25.09.2016, Shift-I
1000 → 8, 1110 → 14 → E Ans. (a) : The 9's complement of a decimal digit is the
(1110 1000)2 → (E8)16 1's complement of the excess-3 code for the digit.
84. The hexadecimal equivalent of 43 in decimal Excess-3 code can be obtained by adding the first 3 to
numbering system is each decimal digit converting the sum to 4-bit binary
(a) B2 (b) 2B number.
(c) 3A (d) A3
BSPHCL JE 30.01.2019, Shift-II
Ans. (b) :
16 43 11 → B
2 1's complement - 0111
Complement value will be 0111 which is the excess-3
(43)10→(2B)16 code of 9's complement of 5, i.e. 4(0111).

Electronics-II 794 YCT

88. Hexadecimal equivalent of binary number 94.
Which of the following is a minimum error code?
10001101011001 is (a) Binary code (b) Excess-3 code
(a) 2359 (b) 9493 (c) Gray code (d) Octal code
(c) 8D62 (d) 8DFs BSNL TTA (JE) 14.07.2013
BSNL TTA (JE) 25.09.2016, Shift-I
Ans. : (c) Gray code changes one bit position at a time
Ans. (a) : Hexadecimal equivalent of binary number
so, this is considered as minimum error code. Gray code
10001101011001 is 2359. Because to convert from
is also known as reflected binary code.
binary to hexadecimal, we divide binary digits into groups
95. FG in Hexadecimal Systems can be written in
of four digit and write their equivalent decimal digits. The
same is the hexadecimal of that binary number. Binary System as:
(a) 11111100
Hence, (10001101011001)2 = (2359)16 (b) 11110011
89. Binary 11110 equals ––––– in hexadecimal (c) 11111111
(a) 2A (b) 2E (d) Not a valid Hexadecimal Number
(c) 1E (d) 2C BSNL TTA (JE) 27.09.2016, 10 AM
BSNL TTA (JE) 25.09.2016, Shift-I Ans. (d) Use digit in Hexadecimal Number is-
Ans. (c) : Binary 11110 equals 1E in hexadecimal. 10 11 12 13 14 15
0001 1110 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ↑ ↑ ↑ ↑ ↑ ↑
1 E
90. The number of digit '1' present in the binary A, B, C, D, E, F
representation of 3×512+7×64+5×8+3 is 96. How many bytes are there in binary number
(a) 8 (b) 9
1001101000111010?
(c) 10 (d) 12
BSNL TTA (JE) 2013 (a) 1 (b) 2
(c) 3 (d) 4
Ans. : (b) 3×512+7×64+5×8+3
= (2+1)×29+(4+2+1)×26 +(4+1)×23+(2+1) BSNL TTA (JE) 27.09.2016, 10 AM
= 210+29+28+27+26+25+23+21+1 Ans. (b) Given binary number 1001101000111010
= 210+29+28+27+26+25+23+21+20 We know that 8 bit = 1 byte
9 term is present in equation. So number of 1 is 9 and 4 bit = 1 nibble
91. What is the Gray code word for the binary so in this number 16 bit is used so that correct answer is
101011? 2 byte.
(a) 101011 (b) 110101 97. The binary equivalent of decimal number 17 is:
(c) 011111 (d) 111110 (a) 10001 (b) 0111
BSNL TTA (JE) 2013
(c) 100001 (d) 11111
Ans. : (d)
BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (a) Given, Decimal number = 17

92. What is the addition of (-64)10 and (80)16 ?

(a) (-16)10 (b) (16)16
(c) (1100000)2 (d) (01000000)2
BSNL TTA (JE) 2013 so, 17 equivalent binary is = 10001
Ans. : (d) (-64)10 = -64 98. The equipment uses Binary coded decimal
(80)16 = (128)10 = 128 (BCD) numbers is:
There addition is = (-64)10 + (80)16 (a) pocket calculator (b) electronic counter
= (-64)10+(128)10 (c) digital voltmeter (d) all of these
= (64)10
= (01000000)2 BSNL TTA (JE) 27.09.2016, 10 AM
93. If the binary number 1110 is converted to Ans. (d) The equipment which uses BCD code are:-
hexadecimal number, we get (i) Pocket calculator
(a) G (b) D (ii) Electronic Counter
(c) E (d) F (iii) Digital voltmeter
BSNL TTA (JE) 14.07.2013 99. The resultant binary of the decimal problem
Ans. : (c) Binary number 1110 equivalent hexadecimal 49 + 1 = is___:
is- (a) 00110101 (b) 01010101
1110 ⇒ (E)H (c) 00110010 (d) 00110001
1110 → (14)10 BSNL TTA (JE) 27.09.2016, 10 AM
Electronics-II 795 YCT
Ans. (c) Given, Decimal number (49±1) = 50 Ans. (c) : The reflected binary code (RBC), also known
just as reflected binary (RB) or gray code.

Hence, (50)10 · (00110010)2

100. The product of the low binary numbers 011
and 110 is:
(a) 01110 (b) 11001
(c) 10010 (d) 11100
DFCCIL-JE 11.11.2018 ∴ Gray code, 100 = 111, in binary code
Ans. (c) : 105. The relation between the number of inputs (n)
Binary Decimal and output (o) of binary coded decoder is-
0112 = 310 (a) o = 2n (b) o = n + 2
1102 = 610 (c) o = 2n (d) o = n/2
their product 3× 6 =18 BSNL TTA 26.09.2016, 10 AM
1810 = 100102 Ans. (c) : A binary decoder is a combination logic
101. State the octal equivalent of hexadecimal circuit that converts binary n
information from n-coded
number (B34)16. inputs to a maximum of 2 unique outputs.
(a) (6454)8 (b) (4564)8 output = 2n
(c) (5464)8 (d) (5645)8 106. Decimal number 74 may be written in binary
DFCCIL-JE 11.11.2018 system as-
Ans. (c) : Hexadecimal no (B34)16 = B 3 4 (a) 1001010 (b) 1001001
(c) 1001011 (d) 100011
BSNL TTA 26.09.2016, 10 AM
Ans. (a) : (74)10 = (?)2
(B34)16 → (5464)8
102. State the respective decimal equivalent and
hexadecimal equivalent of (65)8.
(a) 53, 35 (b) 46, 64
(c) 65, 46 (d) 35, 53
DFCCIL-JE 11.11.2018
Ans. (a) : (65)8
6×81 +5×8º = ( 53) 10
(65)8 → (110 101)2 in binary
= (0011 0101)
= (35)16
103. The binary equivalent of decimal 22 is:
(a) 10110 (b) 10001 (74)10 = (1001010)2
(c) 11010 (d) 11111 107. Evaluate 1101112/1012
DFCCIL-JE 11.11.2018 (a) 11102 (b) 10112
Ans. (a) : (c) 11112 (d) 10012
2 22 R BSNL TTA 26.09.2016, 10 AM
Ans. (b) : Decimal equivalent of (110111)2 = 55
2 11 0 Decimal equivalent of (101)2 = 5
2 5 1 Now,
(110111)2 ( 55 )10
2 2 1 = = (11)10 = (1011)2
2 1 0 (101)2 ( 5)10
1 108. The binary numbers A = 1100 and B = 1001 are
applied to the inputs of a comparator. What
( 22 )10 = (10110 )2 are the output levels?
104. The Reflected Binary Code (RBC) '100' is (a) A > B = 1, A < B = 0, A < B = 1
equal to –––––––––– in binary- (b) A > B = 0, A < B = 1, A = B = 0
(a) 100 (b) 110 (c) A > B = 1, A < B = 0, A = B = 0
(c) 111 (d) 101 (d) A > B = 0, A < B = 1, A = B = 1
BSNL TTA 26.09.2016, 10 AM BSNL TTA 28.09.2016, 10 AM
Electronics-II 796 YCT
Ans. (c) : The binary numbers A = 1100 and B = 1001 Ans : (d) (1111.11)2 = (?)10
are applied to the inputs of a comparator. The output 1111.11 = 1 × 23 + 1 × 22 + 1 × 21 + 1 × 20 + 1 × 2–1 +
levels are A>B=1, A<B =0, A=B=0 1 × 2–2
Both have equal numbers of 1's and 0's but the value is = 8 + 4 + 2 + 1 + 0.5 + 0.25
different, A is more than B, but the same for its next = 15.75
digit is equal to 1's (A>B=1) but for 0's B is less than A = (1111.11)2 = (15.75)10
(A<B=0) and last both are equal (A=B=0) for 0's. 113. Hexadecimal number system is-
109. Unit distance codes are also called as- (a) An absolute system no longer in use
(a) Cyclic codes (b) Non cyclic codes (b) Widely used in analyzing and programming
(c) Error codes (d) All of these microprocessors
BSNL TTA 28.09.2016, 3 PM (c) Used in calculators only
BSNL TTA 21.02.2016 (d) None of these
Ans. (a) Gray code:- It is special code used for detects BSNL TTA 26.09.2016, 3 PM
the errors. It is also known as unit distance code or Ans : (b) Hexadecimal number system is commonly
cyclic code or reflective code. It is an unweighted code. used in computer programming and microprocessors. It
Cyclic code:-Two adjacent number differ only in one is also helpful to describe colors on web pages and used
bit. to describe locations in memory for every byte.
Reflective code:- The number and its mirror image 114. ASCII stands for..................
differ in one bit. (a) American Standard Computer for
Hence, Unit distance codes are also known as cyclic Information Interchange
codes. (b) American Standard Code for International
110. Binary numbers can be converted into Interchange
hexadecimal numbers by grouping bits into (c) American Standard Code for Information
group of…....starting from…....and represented Interchange
each group as hexadecimal number. (d) American Standard Computer for
(a) Three bits, right most bit International Interchange
(b) Three bits, left most bit BSNL TTA 26.09.2016, 3 PM
(c) Four bits, right most bit BSNL TTA 25.09.2016, 3 PM
(d) Sixteen bits, left most bit Ans : (c) ASCII stands for American Standard Code
BSNL TTA 21.02.2016 for Information Interchange. It uses 128 different
BSNL TTA 28.09.2016, 10:00 AM encoding combinations, characters A to Z both upper
Ans : (c) Binary number can be converted into and lower case.
hexadecimal number by grouping bits into group of four 115. Decimal equivalent of octal number 264–
bits starting from right most bit and represented each group (a) 180 (b) 170
as hexadecimal number. To convert binary to hexadecimal (c) 166 (d) None
groups of four binary bits are formed from LSB. After that BSNL TTA 25.09.2016, 3:00 P.M.
each group is replaced by its hexa equivalent.
Ex. - In binary number 010111011001 a group of four Ans : (a) (264)8 = 2 × 82 + 6 × 81 + 4 × 80
bits can be formal from the right side as follows. =128 + 48 + 4
↓MSB ↓LBS = 180
Binary 0101 1101 1001 116. Which of the following hexadecimal numbers
Hexa equivalent 5 D 9 represents an odd decimal number :
111. An equivalent decimal number of (234.55)8 is- (a) FF (b) EE
(a) (106.703)10 (b) (156.703)10 (c) CC (d) AA
(c) (146.703)10 (d) (308.703)10 BSNL TTA 25.09.2016, 3:00 P.M.
BSNL TTA 21.02.2016 Ans : (a)
BSNL TTA 29.09.2016, 3 PM (FF)16 = 15 × 161 + 15 × 160 = 240 + 15 = 255 (odd)
Ans : (b) Given, octal number (234.55)8 (EE)16 = 14 × 161 + 14 × 160 = 224 + 14 = 238 (even)
(234)8 = 2 × 82 + 3 × 81 + 4 × 80 (CC)16 = 12 × 161 + 12 × 160 =192 + 12 = 204 (even)
= 128 + 24 + 4 (AA)16 = 10 × 161 + 10 × 160 = 160 + 10 = 170 (even)
= (156)10 117. The decimal fraction 0.375 in binary form is
(.55)8 = 5 × 8–1 + 5 × 8–2 .........
5 5 (a) 0.0011 (b) 0.111
= +
8 64 (c) 0.011 (d) 0.0111
40 + 5 45 BSNL TTA 25.09.2016, 3:00 P.M.
= = = (.703)10
64 64 Ans : (c)
(234.55)8 = (156.703)10 (0.375)10 = ( ? )2
112. (1111.11)2 equals- 0.375 × 2 = 0.750 Carry ⇒ 0
(a) (–1.01)10 (b) (–0.75)10 0.750 × 2 = 1.50 Carry ⇒ 1
(c) (15.3)10 (d) (15.75)10 0.50 × 2 = 1.00 Carry ⇒ 1
BSNL TTA 26.09.2016, 3 PM So (0.375)10 = (0.011)2
Electronics-II 797 YCT
118. The decimal equivalent of a binary number Ans : (a) (1000)10 = (?)2
1001110 is :
(a) 82 (b) 86
(c) 74 (d) 78
KVS WET 2017
Ans. (d) : The decimal equivalent of a binary number-
1001110 = 1× 26 + 0 + 0 + 1× 23 + 1× 22 + 1× 21 + 0
= 64 + 8 + 4 + 2
= 78
119. Main advantage of hexadecimal number
system is
(a) ease of conversion from hexadecimal to
decimal and vice-versa Read upward - 1111101000
(b) ease of conversion from hexadecimal to Hence, signed number (+1000)10 = (0000 0011 1110
binary and vice-versa 1000)2
(c) ease of conversion from hexadecimal to gray 123. The decimal equivalent of (11011101) is-
code and vice-versa (a) 225 (b) 229
(d) use of number and alphabets (c) 221 (d) None
BSNL TTA 29.09.2016, 10 AM BSNL TTA 27.09.2016, 3 PM
Ans : (b) The main advantage of a Hexadecimal Ans : (c)
number is that it is very compact and by using a base of (11011101)2 = (?)10
16 means that the number of digits used to represent a (11011101)2 = 1×27 + 1×26 + 0×25 + 1×24 + 1×23 +
given number is usually less than in binary or decimal. 1×22 + 0×21 + 1×20
Also, it is quick and easy to convert between = 128 + 64 + 0 + 16 + 8 + 4 + 0 + 1
hexadecimal number and binary. (11011101)2 = (221)10
120. Binary coded decimal (BCD) numbers are 124. Add (101110)2 and (111101)2
useful whenever (a) (1001011)2 (b) (1101011)2
(a) binary to BCD conversion is desired (c) (110101)2 (d) (101011)2
(b) binary to hexadecimal conversion is desired UPRVUNL JE- 21.10.2021, 2:30 PM - 5:30 PM
(c) decimal information is transferred into or out 1 0 1 1 1 0
of digital system
(d) none of these Ans. (b) : + 1 1 1 1 0 1
BSNL TTA 29.09.2016, 10 AM 1 1 0 1 0 1 1
Ans : (c) Binary-coded decimal or BCD is a way of 125. The number of bits used to store a BCD digit
representing a decimal number as a string of bits is-
suitable for use in electronic system. Rather than (a) 8 (b) 4
converting the whole number into binary. BCD splits (c) 2 (d) 1
the number up into its digits and convert each digit to 4- BSNL TTA 27.09.2016, 3 PM
bit binary. So, BCD code is very simple & we can use Ans : (b) Binary Coded Decimal (BCD):- It is simply
BCD number whenever decimal information is the 4-bit binary code representation of decimal digit
transferred into or out of digital system. with each decimal digit replaced in the integer and
121. Electronic devices are most reliable when fractional parts with its binary equivalent. BCD code uses
designed for______ operation. four bits to represent the 10 decimal digits of 0 to 9.
(a) decimal (b) hexadecimal 126. An 8-bit binary word as an integer x ranges
(c) binary (d) ASCII from
BSNL TTA 29.09.2016, 10 AM (a) –128 to 128 (b) 0 to 255
Ans : (b) The main reason why we use hexadecimal (c) 0 to 256 (d) 0 to 128
numbers is because it provides a more human-friendly JPSC AE 10.04.2021, Paper-I
representation and is much easier to express binary Ans. (b) : An 8-bit unsigned integer has a range of 0 to
number representations in hex than it is in any other 255, while on 8-bit signed integer has a range of -128 to
base number system. Computers do not actually work in 127 both representing 256 distinct number. It is
hex. important to note that a computer memory location
122. Conversion of +1000 decimal number into mainly stores a binary pattern.
signed binary word results- 127. The largest integer that can be represented in
(a) 0000 0011 1110 1000 signed 2's complement representation using n
(b) 1000 0011 1110 1000 bits is
(c) 1111 1100 0001 1000 (a) 2n – 1 (b) 2n
n–1
(d) 0111 1100 0001 1000 (c) 2 –1 (d) 2n – 1
BSNL TTA 27.09.2016, 3 PM JPSC AE 10.04.2021, Paper-I
Electronics-II 798 YCT
Ans. (c) : Range of 1's complement number Ans. (b) : ∑ ( 0, 4,5,6,9,12,13,14 )
− ( 2n −1 − 1) to + ( 2n −1 − 1) Solving use k map
Range of 2's complement representation number
−2n −1 to + ( 2n −1 − 1)
128. Two's complement of -8 is
(a) 1000 (b) 1010
(c) 110 (d) 1110
JKSSB JE 2014
Ans. (a) : Given 2's complement of –8 is –
–8 = 1000
1's complement = 0111 Using SOP method
+1
2's complement = = ABCD + ABCD + ABCD + ABCD + ABCD
1000
129. Decimal equivalent of Hexadecimal number + ABCD + ABCD
(C3B1)16 is: = BC + BD + ACD + ACD
(a) 12197 (b) 32097
(c) 52097 (d) 50097 134. The 1's complement of the binary number
RPSC Lect. (Tech. Edu. Dept.) 09.01.2016 (101100)2 is:
Ans. (d) : In decimal C = 12, B = 11 (a) (101101)2 (b) (010011)2
⇒ 12 ×163 + 3 × 162 + 11 × 161 + 1 × 160 (c) (001100)2 (d) (110011)2
UPPCL JE- 08.09.2021, Shift-II
= 50097
130. The Gray code equivalent of the decimal Ans. (b) : Given,
number 5 is- Binary number = (101100)2
(a) 0101 (b) 1000 1's complement = (010011)2
(c) 0111 (d) 1100 by complementing each binary number, we get 1's
Ans. (c) : Given that - complement of any binary number.
(5)10 = (0101)2 135. The base of octal number system is _______.
New Binary to Gray → γ = A ⊕ B (a) 8 (b) 16
(c) 10 (d) 2
→ (0111) UPPCL JE- 08.09.2021, Shift-II
131. The binary equivalent of 23 is: UPRVUNL JE 24.10.2021, 9am-12pm
(a) 10111 (b) 11011 Ans. (a) : octal number system base → 8
(c) 10110 (d) 10011
UPRVUNL JE -21.10.2021,9 am-12 pm Binary number system base → 2
Ans. (a) : (23)10 = (……)2 Hexadecimal number system base → 16
136. Which of the following binary code is also
called gray code?
(a) Reflected code (b) Excess-3 code
(c) BCD code (d) Biquinary code
UPPCL JE- 08.09.2021, Shift-II
Ans. (a) : Reflected code is also called gray code.
137. The conversion of Hexadecimal number ‘BC’
to Binary number is:
132. There are __________ number of digits in a (a) 10111100 (b) 10101011
binary number system. (c) 11001011 (d) 10111010
(a) 8 (b) 2 HPPSC PWD AE 24.08.2021
(c) 4 (d) 6 Ans. (a) :
UPPCL JE- 08.09.2021, Shift-I
Ans. (b) : There are two digits (0 and 1) used in binary
number system. The base of binary system is 2.
133. Reduce using K map. Σ (0,4,5,6,9,12,13,14) = ?
(a) BC + BD + ACD + ACD
(b) BC + BD + ACD + ACD
138. The decimal value of 0.25 is equivalent to:
(c) BC + BD + A CD + ACD (a) Binary value 0.01 (b) Binary value 0.001
(d) BC + BD + ACD + ACD (c) Binary value .0.011 (d) Binary value 0.1
ISRO VSSC (TA) 14.07.2021 HPPSC PWD AE 24.08.2021

Electronics-II 799 YCT

Ans. (a) : Decimal to binary conversion- 144. Which of the following is the Binary Coded
Decimal (BCD) representation of decimal
number (25)10?
(a) 01000101 (b) 00110101
(c) 00100101 (d) 01100101
( 0.25 )10 = ( 0.01)2 UPRVUNL JE -21.10.2021,9 am-12 pm
139. Octal discription of (A0E)16 Ans. (c) : (25)10 = (…)BCD
(a) (5016)8 (b) (5061)8
(c) (1650)8 (d) (5610)8
RRB JE (Shift-3), 28.08. 2015 = (00100101)BCD
Ans : (a) 145. 2's complement of the binary number
A 0 E (1010101)2 is
↑ | ↑ to (1010, 0000,1110 ) 2 (a) (1110011)2 (b) (1101010)2
1010 0000 1110
(c) (0101010)2 (d) (0101011)2
(1010 0000 1110)2 to octal UPRVUNL JE -21.10.2021,9 am-12 pm
101000 001110
Ans. (d) :
↑ ↑ ↑ ↑ (Octal equivalent)
5 0 1 6
(5016)8
140. What is the decimal equivalent of the
hexadecimal number AF2?
(a) 2802 (b) 10152
(c) 2048 (d) 162 146. The decimal equivalent of octal number (145)8
UPPCL JE 11.02.2018, Shift-I is:
Ans : (a) (AF2)16 = 10 × 16 +15 × 16 + 2 × 16
2 1 0 (a) (101)10 (b) (165)10
(c) (196)10 (d) (353)10
= 10 × 256 + 15 × 16 + 2
UPRVUNL JE -21.10.2021,9 am-12 pm
= 2560 + 240 + 2
Ans. (a) : (145)8 = (……)10
( AF2 )16 = ( 2802 )10 = 1 × 82 + 4 × 81 + 5 × 80
141. The 2s complement representation of decimal = 64 + 32 + 5
number [-17] is = (101)10
(a) [100110] (b) [101111] 147. How will (-9) be represented in 2’s
(c) [111110] (d) [110001] complement in eight bit notation?
UPPSC AE 13.12.2020, Paper-II (a) 00000111 (b) 11110110
Ans. (b) : Given decimal number = –17 (c) 00001001 (d) 11110111
2's complement = ? UPRVUNL JE-24.10.2021, 9 to 12PM
(17)= 010001 Ans. (a) : –9 = 11001
[-17] = 110001 (first bit is sign bit) 1’s complement = 00110
2' complement of [-17] = [101111] 2’s complement = 00111
142. The smallest integer that can be represented by ∵ In eight bit notation
an 8-bit number of 2s complement form is- ∴ 00000111
(a) −256 (b) −128 148. Gray code for decimal 5 is _________.
(c) −127 (d) 0 (a) 100 (b) 101
UPPSC AE 13.12.2020, Paper-II (c) 110 (d) 111
Ans. (b) : Given, n = 8-bit UPRVUNL JE-24.10.2021, 9 to 12PM
Range of 2's compliment number = ( −2n −1 ) to ( 2n −1 − 1) Ans. (d) : (5)10 = (101)2
So, smallest integer = -2n-1
= -2n-1= -(2)8-1 = - (2)7 = -128
143. In 2's complement representation the number
11100111 represents the decimal number:
(a) 27 (b) +27 149. What will be the decimal equivalent of
(c) -25 (d) -30 (1001.0101)2?
OPPSC AE 2021, Paper-II (a) 5.0625 (b) 9.0625
Ans. (c) : Given, (c) 5.3125 (d) 9.3125
Binary No = 11100111 UPRVUNL JE-24.10.2021, 9 to 12PM
1's complement = 0 0 0 1 1 0 0 0 Ans. (d) : (1001.0101)2 = ()10
0 0 0 1 1 0 0 0
2's complement = = 1 × 23 + 0 × 22 + 0 × 21 + 1 × 20 + 0 + 1× 2 −2 + 0 + 1 × 2 −4
+ 1
1 1
0 0 0 1 1 0 0 1 = 8 +1+ + = 9 + 0.25 + 0.0625
4 16
Number is negative because MSB = 1
Hence (0 0 0 1 1 0 0 1) = (-25) = ( 9.3125 )
2 10

Electronics-II 800 YCT

150. Find the Hexadecimal equivalent of (82.25)10. 4. How many AND and OR gates are required to
(a) 58.0 (b) 56.0 realise Y = AB+BC+CD?
(c) 52.4 (d) 56.4 (a) 2, 3 (b) 2, 1
UPRVUNL JE-24.10.2021, 9 to 12PM (c) 3, 2 (d) 2, 2
Ans. (c) : (82.25)10 = ()16 UPPCL JE- 07.09.2021, Shift-I
16 82 2 Ans. (c) :
5
= 0.25×16 = 4 = (52.4)16

II. Logic Gate & Logic Circuits Basic gate- AND, OR , NOT
1. A + AB gets simplified to Universal gate- NAND, NOR
(a) A+B (b) A 5. Identify the logic gates in the given symbol.
(c) B (d) AB
UPPCL JE- 08.09.2021, Shift-II
DFCCIL JE 11.11.2018
BWSSB Code 198, 30.05.2017 (a) NAND (b) EX-NOR
Karnataka PSC JE 2017 (c) EX-OR (d) NOR
RRB JE (Shift - I) 29.08.2015 UPPCL JE- 07.09.2021, Shift-I
Ans. (b) : A+AB Ans. (b) : Given symbol represent EX-NOR gate.
= A (1 + B) (∵1 + B = 1)
=A
2. _______ is known as universal gate.
(a) AND gate (b) NAND gate
(c) OR gate (d) NOT gate
UPRVUNL JE- 21.10.2021, 2:30-5:30 PM
UPPCL JE- 08.09.2021, Shift-I
UPPCL JE 08.09.2021, Shift-II
UPPCL JE 07.09.2021, Shift-I
BIS TA (Lab) 2020
Kerala PSC Draftman 2016, Grade II
NPCIL Stipendiary Trainee - 2016
BSNL TTA 27.09.2016, 3:00 PM 6. If the inputs are P, Q and R, then sum output
RRB JE Shift - II 04.09.2015 of full adder is
RRB JE Shift - II 29.08.2015
DMRC JE - 2015
(a) P OR Q OR R (b) P XOR Q XOR R
Mizoram PSC Nov. 2015, Paper-III (c) P OR Q AND R (d) P AND Q AND R
RRB Chandigarh 2014 UPPCL JE- 07.09.2021, Shift-I
Ans. (b) : A universal gate is a gate which can Ans. (b) :
implement any Boolean function without need to use
any other gate type.
The NAND and NOR gates are universal gate.
3. _______ is also called an anti-coincidence gate
or inequality detector.
(a) OR gate (b) X-NOR gate
(c) NOR gate (d) X-OR gate
UPPCL JE- 07.09.2021, Shift-II
Ans. (d) : X-OR gate is also called an anti - coincidence
gate or inequality detector. Because when both the input
are same, then output becomes low or logic 0 and when
both the inputs are different, then output becomes high
or logic 1

Electronics-II 801 YCT

7. Find the correct option for simplification of the Ans. (c) :
Boolean expression.
(P+Q+R)(S+T)' + (P+Q+R)(S+T).
(a) P' Q' R' (b) S+T
(c) P+Q+R (d) S'+T'
UPPCL JE- 07.09.2021, Shift-I
∵ A.A = A
( )
Ans. (c) : ( P + Q + R ) S + T + ( P + Q + R )( S + T ) Y = ( A + B ) AB 
 B.B = B
( )
= ( P + Q + R )  S + T + ( S + T )

Y = AAB + ABB
Y = AB + AB
= (P + Q + R ) Y=AB
8. Which is the correct Boolean expression of So, this logic circuit is not equivalent to an XOR gate.
output Q in the given figure? 11. A single input gate in which input and output
are same is called _______________.
(a) buffer (b) EX-NOR
(c) AND (d) inverter
UPPCL JE- 08.09.2021, Shift-II
(a) A+B' (b) A'+B Ans. (a) : A buffer is a single input and single output
(c) A'+B' (d) A'.B gate. It gives the same output as input is given. In
UPPCL JE- 07.09.2021, Shift-I boolean logic a buffer is mainly used to increase
Ans. (c) : In the given figure bubbled logic is used. propagation delay

9. ____________ in Boolean algebra is similar to

addition in ordinary algebra.
(a) NAND operation (b) NOT operation
(c) AND operation (d) OR operation 12. A 2-input gate gives high output only when
UPPCL JE- 08.09.2021, Shift-I both the inputs are low. For all other
conditions the output remains low. Identify the
Ans. (d) : OR operation in Boolean algebra is similar to gate.
addition in ordinary algebra. (a) NOR (b) NAND
(c) OR (d) EX-OR
UPPCL JE- 08.09.2021, Shift-II
Ans. (a) : According to given statement a 2-input gate
gives high output only when both the inputs are low,
that is NOR. Gate

10. Which of the following logic circuit is not

equivalent to an XOR gate
(a)

13. Which logic gate is represented by the given

symbol?

(b)

(a) AND (b) NOT

(c) OR (d) EX-OR
(c) UPRVUNL JE 21.10.2021, 2:30- 5:30 PM
UPPCL JE- 08.09.2021, Shift-II
Ans. (b) : As given

(d)

ISRO VSSC (TA) 14.07.2021

Electronics-II 802 YCT
14. Using Boolean algebra, if the following Boolean • NAND and NOR gate are universal gates because its
expression is minimised, then the result will be: repeated use can produce other logic gates.
AB + ABC + AB (D+E)
(a) AB (b) A
(c) ABC (d) ABCD
UPPCL JE- 08.09.2021, Shift-II
Ans. (a) : Let y = AB + ABC + AB(D + E)
= AB (1 + C + D + E) 18. Three Boolean operators are
= AB (by redundancy theorem) (a) NOT, OR, AND (b) NOT, NAND, OR
15. A logic gate is an electronic circuit which (c) NOR, OR, NOT (d) NOR, NAND, NOT
(a) Perform arithmetic and logic functions HPSSSB JE-2017 (Post code- 579)
(b) Attenuate noise, drift, and other unwanted HPSSC JE 2017 (Code - 579)
disturbance. BSNL TTA - 28.09.2016, 10:00 AM
(c) Invert an input signal Ans. (a) : NOT, OR, AND are the three basic Boolean
(d) Operates on binary algebra. operators and all other gates are made-up with these
HPPSC PWD AE 24.08.2021 basic operators.
Ans. (a) : A logic gate is an electronic circuit which 19. Which of the following is a universal logic gate?
perform arithmetic and logic function. (a) XNOR (b) NOR
A logic gate is a device that acts as a building block for (c) XOR (d) OR
digital circuits. They perform basic logical functions PSPCL JE 2019, Shift-I
that are fundamental to digital circuits. Most electronic KVS WET 2017
devices we use will have some form of logic gates in JKSSB JE 2014
them. For example, logic gates can be used in BSNL TTA (JE) 14.07.2013
technologies such as smartphones, tablets or within Ans. (b) : NOR Gate- The NOR logic gate is a
memory devices. universal type logic gate. NOR gate can be used to
16. ________ gate gives high output, only if all its produced any other type of logic gate function just
inputs are high. like the NAND gate and by connecting them together
(a) AND (b) NOT in various combination the three basic gate types of
(c) NOR (d) NAND AND, OR and NOT.
Vizag Steel 25.10.2018 Shift-I
RRB Allahabad - II 2014
RRB Ahmadabad 2014
RRB Ajmer 2014
Ans. (a) : AND gate Symbol of NOR gate
Input Output
A B Y =A+B
0 0 1
Input Output 0 1 0
A B y = AB 1 0 0
0 0 0 1 1 0
0 1 0 20. If the two inputs of a logic gate are 1 and 0,
1 0 0 then output of which logic gate is 1:
(a) AND gate (b) OR gate
1 1 1
(c) NOR gate (d) NOT gate
Hence AND gate gives high output only if all its input FCI JE 2015
are high.
Ans. (b) : For "OR" gate the truth table shown below
17. The basic gates are:
(a) AND, OR and NOT gate
(b) AND, NOR and NOT gate
(c) OR and NOT gate
(d) AND and NOT gate
UPPCL JE 25.11.2019, Shift-II
HPSSSB JE 2017 (Post code 579) 21. For the circuit shown in Figure, taking open as
BSNL TTA 28.09.2016, 10 AM '0' and closed as '1', the output expression Y is
Ans. (a) : A logic gate is a circuit that has one or more given as
input signals but one output signal.
• The three basic logic gates that make up all digital
circuits are :–
(i) – OR gate
(ii) – AND gate
(iii) – NOT gate

Electronics-II 803 YCT

 ( )(
(a) A(B+C+D) (b) A(BC+D)
(c) A+(B+C)D (d) A+B+C+D Z = PQ RQ .Q )
GSECL 2020 Shift-I
Ans. (b) : Z = PQ + RQ + Q
Z= P.Q + R.Q + Q
Z = Q (1 + P ) + R.Q
Z = Q + RQ
Z = Q + R.Q
We know that
Z = Q. R.Q
• Series switch acts as AND gate
Boolean function = B.C and
(
Z = Q. R + Q )
• Parallel switch acts as OR gate Z = QR + QQ
Z = QR
25. For the circuit shown in the below figure the
output F will be.
Boolean function (B.C + D)
• Again series switch

(a) 1 (b) zero

(c) X (d) X
HPSSSB JE - 2018 (Code - 663)
Y = A(B.C+D) ESE 2001
22. Logic 1 in negative logic system is represented Ans. (b) : Truth table of Ex-OR gate:-
by
(a) Zero level
(b) Lower voltage level
(c) Higher voltage level
(d) Negative level
KSEB Sub Engineer 2015
Ans. (b) : (+Ve) pulse give the higher voltage level,
whereas (–Ve) pulse gives the lower voltage level.

For 2-input XOR gate if input are same then output is

23. A(A'+C) (A'B+C)(A'BC+C') zero.
(a) AC (b) BC and X ⊕ 0 = X
(c) 0 (d) AB X⊕X = 0
MPPKVVCL (Jabalpur) JE -2018 Hence F = 0
Ans. (c) : A (A' + C) (A' B + C) (A' BC + C')
26. A + AB = A + B is stated as per:
or ⇒ AC ( A 'B + C ) (A 'BC + C')
(a) Commutative law (b) Associative law
or ⇒ AC (A' BC+C') (c) Distributive law (d) Absorptive law
or ⇒ A CC ' = 0 SJVNL 24.10.2021, 8:30AM-10:30 AM
24. From the output Z of the logic circuit shown, MPPKVVCL JE-2018
determine Z . ( )
Ans. (c) : A + AB = A + A ( A + B )
= 1( A + B ) = A + B
Distributive law A + AB = A + B
27. Which logical operation is performed by ALU
(a) Q R (b) Q R of 8085 to complement a number?
(a) AND (b) NOT
(c) RQ + P (d) P + QR (c) OR (d) EXCLUSIVE OR
MPPKVVCL JE-2018 ESE 2002
Ans. (a) : Ans. (d) : Arithmetic and logic unit (ALU) performs
arithmetic and logical functions and the complement of
operation is performed by either XOR gate or XNOR
gate. An XOR is used because it can be used both as
buffer and inverter.

Electronics-II 804 YCT

28. De Morgan's Theorem states that: Ans. (d) : The gate that assumes the 1 State, if and only
(a) Compliment of (A + B) is multiplication of if the input does not take a 1 state is called NOT gate
compliment of A and compliment of B and NOR gate.
(b) Compliment of (A * B) multiplication of
compliment of A and compliment of B
(c) Compliment of (A - B) is multiplication of A
and compliment of B
A
(d) Compliment of   is multiplication of
B
compliment of A and compliment of B
MPMKVVCL (Bhopal) JE 2018
Ans. (a) : De morgan's theorem states that
compliment of (A+B) is multiplication of compliment
of A and compliment of B.
A + B = AiB 32. Which of following logic gates provides output
as 0 when both inputs are same (either 0 or 1)?
29. Which one of the following statements is (a) XNOR (b) XOR
correct? (c) NOR (d) NAND
For a 4-input NOR gate, when only two inputs PSPCL JE 2019, Shift-I
are to be used, the best option for the unused Ans. (b) : XOR Gate- The symbol and truth table of
input is to an XOR Gate shown in the figure given below
(a) connect them to the ground Input Output
(b) connect them to VCC A B Y = A ⊕ B = AB + AB
(c) keep them open 0 0 0
(d) connect them to the used inputs 0 1 1
ESE 2004 1 0 1
Ans. (a) : 1 1 0

Symbol of XOR Gate

From the truth- table we can say that XOR logic gate
provides output as '0' when both input are same (either
'0' or '1')
33. If the input to the digital circuit of the below
figure consisting of a cascade of 20 XOR gates
Unused inputs kept at '0' or ground because enable input is X, then what is the output Y?
for NOR gate is 0.
30. Boolean algebra is also known as
(a) Gate algebra (b) Transistor
(c) Switching algebra (d) Counting algebra (a) 0 (b) 1
HPSSSB JE 2018 (Post code 663) (c) X' (d) X
Ans. (c) : Boolean algebra or switching algebra is a BSNL TTA 25.09.2016, 3:00 PM
system of mathematical logic to perform different ESE2007
mathematical operations in binary system. These are Ans. (b) :
only two elements 1 and 0 by which all the
mathematical operations are to be performed. There are
many rules in Boolean algebra by which those
mathematical operations are done.
31. The gate that assumes the 1 state, if and only if
the input does not take a 1 state is called
(a) AND
(b) NOT gate
(c) NOR gate
(d) Both NOT gate and NOR gate
BWSSB Code 127, 13.11.2016
Karnataka PSC JE-2016
Electronics-II 805 YCT
34. The AND function can be realized by using Ans. (d) : Given Boolean function.
only n number of NOR gates. What is an equal X' (X'+Y)
to? X'X'+X'Y
(a) 2 (b) 3
(c) 4 (d) 5
= X'+X'Y {∵ A.A = A}
Ans. (b) : The AND function can be realized by using =X'(1+Y) =X' {∵ 1 + Y = 1}
only 3 no of NOR gates. 38. Which of the following logic gates provides
output as 1 when both inputs are different?
(a) AND (b) XOR
(c) XNOR (d) NOR
PSPCL JE 2019, Shift-II
Ans. (b) : XOR logic gate- In an XOR logic gate
when both the inputs are different
True Table
Input Output
A B Y = A⊕B
35. Which of the following is equivalent to the
Boolean function X + XY?
(a) 0 (b) Y 0 0 0
(c) X (d) 1 0 1 1
PSPCL JE 2019, Shift-I 1 0 1
Ans. (c) : Given Boolean function- 1 1 0
F = X + XY 39. Which of the following statements related to
=X(1+Y) Boolean algebra is FALSE?
F=X {∵ 1 + something = 1} (
(a) X i X + 1 = X ) (
(b) X. X + XY = 1 )
36. In the given circuit, the output Y equals which
one of the following? (c) X + X = 1 (d) 1 + X = 1
PSPCL JE 2019, Shift-II
Ans. (b) : X. X + XY = 1( )
From L.H.S. X.X + X.XY
= 0+0
=0
From above we can see that L.H.S ≠ R.H.S. hence
(
given Boolean algebra X. X + XY = 1 is false. )
(a) A+B (b) AB + AB 40. Which one of the following is the correct output
(c) AB (d) A + B (f) of the below circuit?
ESE 2008
Ans. (d) :

(a) (a + b)(c + d ) (b) ( a + b )( c + d )

(c) ( a + b )( c + d ) (d) (a + b)(a + d )
ESE 2009
Ans. (a) :

Y = AB + AB + AB
= A + B + AB + AB
= A (1 + B ) + B (1 + A )
= A+B
37. Which of the following is equivalent to the
( )
f = a + b + (c + d)

Boolean function X'(X'+Y)?

(a) X (b) Y'
( )( )
f = a+b c+d

(c) Y (d) X' f = (a + b) c + d ( )

PSPCL JE 2019, Shift-II
Electronics-II 806 YCT
41. From the given logic circuit, determine the
expression for Z. output Q = A + B
A + B = A.B ∵X = X
at final, output will be A.B
Therefore for input A&B output is AB in case of
NAND Gate only.
(a) P + R (b) PQ + R 44. For logic circuit shown, the required inputs A,
(c) Q + P (d) Q + R B and C to make the output X = 1 are
PGCIL Diploma Trainee 27.10.2018 respectively.
Ans. (d) :

Output of NAND gate (1) = PQ (a) 1, 0 and 1 (b) 0, 0 and 1

= PQ (c) 1, 1 and 1 (d) 0, 1 and 1
Ans. (c) :
output of NAND gate (2) = QR

( ) ( )
∴ Z = PQ .Q. QR

= PQ + Q + QR = Q ( P + 1) + QR
( )( )
= Q + QR = Q + R Q + Q (distributive law)
Z=Q+R
42. In the below circuit, X=? A B XNOR AND
0 0 1 0
0 1 0 0
(a) B (b) A 1 0 0 0
(c) A+B (d) A.B 1 1 1 1
SSC JE 26.09.2019, Shift-I
∴X= (A ⊕ B).(B ⊕ C).C
Ans. (d) : The circuit shows a AND gate. in AND gate
for any input A&B the output is A.B. To make,
X=1
A ⊕ B = 1 & B ⊕ C = 1 & C = 1 Should be 1.
∴C=1
if C = 1, Then. B ⊕ C will be 1 when, B = 1
Now, if B = 1, the A ⊕ B will be 1, when, A = 1
∴ X = 1.1.1
X = 1 for inputs, A = B = C = 1
43. The output of logic circuit given below -
represents _____ gate. 45. In Boolean algebra (A. A)+ A = ?
(a) 0 (b) 1
−
(c) A (d) A
SSC JE 26.09.2019, Shift-II
RRB SSC (Shift-III) 02.09.2015
(a) NAND (b) NOR −
(c) OR (d) AND Ans. (c) : (A. A ) + A = 0 + A = A
SSC JE 26.09.2019, Shift-I 46. Four statements are given below. Identify the
Ans. (a) : At stage 1 the output will be A & B correct statement?
(a) XOR is a derived gate
at stage 2 output will be
(b) XOR is a universal gate
(c) XOR is a basic gate
(d) XNOR is a basic gate
SSC JE 26.09.2019, Shift-II
Ans. (a) : XOR gate is a derived logic gate. It can made
by AND, OR, NOT, NAND, NOR gate.
Electronics-II 807 YCT
 49. The input waves of a logic block A, B provide
the logic output X. Identify the logic operation
performed by the logic block.
A

47. If the output of a logic gate is '1' when all its

inputs are at logic '0', the gate is either X
(a) A NAND or a NOR (a) X = A + B (b) X = AB
(b) An AND or an EX-NOR (c) X = AB (d) X = A + B
(c) An OR or a NAND UPPCL JE 25.11.2019, Shift-I
(d) An EX-OR or an EX-NOR Ans : (a) It is clear from the truth table that logic block
Ans. (a) : represented by the OR operation.
For NAND gate NOR gate
A B Y A B Y
0 0 1 0 0 1
0 1 1 Y = A.B 0 1 0 Y =A+B
1 0 1 1 0 0
1 1 0 1 1 0
Hence, above the truth table, if the o/p of a logic gate is
'1' when all its inputs are at logic '0', the gate is either a
NAND or a NOR gate.
48. If A and B are the logical inputs to the X =A+B
following circuit, determine the logical relation
between the inputs and the output X. 50. Find the complement of A + AB
(a) AB (b) B
(c) A + B (d) A
UPPCL JE 25.11.2019, Shift-I
RRB JE (Shift - III) 16.09.2015
Ans : (c) Let, X = A + AB
Complement of X = X
X = A + AB ∵ X + Y = X.Y

( )
= A. AB

∵ X.Y = X + Y
(a) X = AB (b) X = AB =A A+B( )
(c) X = A+ B (d) X = A + B
UPPCL JE 25.11.2019, Shift-I ∵ X=X
Ans : (a) =A A+B( )
= A.A + AB
Y=AB
∵ X.X = 0
=AB or A.B
= AB
X=A+B
51. An XNOR gate produces an output only when
the two inputs are:
(a) same (b) low
(c) different (d) high
UPPCL JE 25.11.2019, Shift-I
Electronics-II 808 YCT
Ans : (a) In case of 4th-

It is clear from the truth table that an XNOR gate By truth table–
produces an output only when the two inputs are same. Hence, it is clear that OR operation is achieved by the
52. If A and B are the logical inputs to the given circuit.
following circuit, determine the logical relation
between the inputs and the output C. A B C
0 0 0
0 1 1
1 0 1
1 1 1
∴ C= A+B
53. Find the output X for the given logic circuit.
(a) C = A xor B (b) C = AB
(c) C = A + B (d) C = AB
UPPCL JE 25.11.2019, Shift-I
Ans : (c)

(a) X = (AB) + C (b) X = AB + C

(c) X = A+B C (d) X = (A + B) C
UPPCL JE 25.11.2019, Shift-I
Ans : (d)

In the first case–

Giving the both inputs A & B by '0'
So, X = (A + B)C
54. _______gate is called as a complement of OR
gate.
(a) NOT (b) NOR
(c) NAND (d) AND
Vizag Steel JET 25.10.2018, Shift-II
In the 2nd case– JKSSB JE 2014
Giving the input of A is '0' and input 'B' is '1' Ans. (b) : NOR gate means NOT gate and OR gate

NOR gate is called as a complement of OR gate.

In case of 3rd case-
55. Which one is not a basis logic gate?
Giving input to A logic '1' and B to '0' logic-
(a) AND gate (b) NOT gate
(c) NAND gate (d) OR gate
UPSSSC JE-2015
Ans. : (c) AND gate, OR gate, NOT gate are basic logic
gate, while NAND gate or NOR gate are universal logic
gates.
Electronics-II 809 YCT
56. Determine the logical operation of the given = (X + X Y + X.Y) ( X + Y)
circuit. = X. X + X . X Y + X .XY + XY + X Y Y + XY.Y
= XY + XY.Y
= XY + XY
T = XY ∵ X.X = X , X.X = 0
60. In Boolean Algebra F = (A + B) (Ā + C), then
(a) X = A + B + C + D (b) X = ABCD F=?
(c) X = A+B+C+D (d) X =ABCD
SSC JE 10.12.2020, Shift-II (a) F = AB + ĀC (b) F = AB + AB
(c) F = AC + ĀB (d) F = AA + ĀB
Ans (d) : The logical operation of the given circuit-
HPSSSC JE 2018 Code -387
Ans. (c) : F = (A + B)( Ā + C)
F = A. Ā + AC + BĀ + BC ∵ A. Ā = 0
F = AC + B Ā + BC
F = ĀB + AC + BC.1
x=ABCD = ĀB + AC + B.C (A + Ā)
57. The minimised form of Boolean logic = ĀB + AC + ABC + ĀBC
expression (A'B'C' +A'BC'+A'BC+ABC') can = ĀB + ĀBC + AC + ABC
be reduced to = ĀB(1 + C) + AC(1 + B)
(a) A'C' +BC' +A'B (b) A'C'+ B'C' +A'B F = ĀB + AC
(c) A'C+BC+A'B (d) AC+BC' +AB 61. The parity of the binary number 11001110
Mizoram PSC IOF 2019 Paper-III (a) is even
ISRO TA 2016 (b) is not known
Ans. (a) : Given, Boolean logic expression- (c) is odd
(A'B'C' +A'BC'+A'BC+ABC') (d) is same as the number of zeros
By using K-map HPSSSC JE 2018 Code -387
Ans. (c) : Parity bit :- It is an extra bit added to the
message in order to make total number of logic is either
even or odd. It is used for Data Transmission and
receiver communication.
So, given number is− 11001110, it has odd number of
1′s therefore it will be odd parity, to make it even parity
= AC + BC + AB have to add another 1′s as MSB.
Y = A′C′ + BC′ + A′B 62. Which of the following gates cannot be used as
58. The NAND-NAND realization is equal to an inverter?
(a) AND-NOT realization (a) NAND (b) AND
(b) AND-OR realization (c) NOR (d) EX-NOR
(c) OR-AND realization HPSSSC JE 2018 Code -387
(d) NOT-OR realization Ans. (b) : NAND, NOR and X-NOR gates can be used
HPSSSC JE 2018 Code -387 as inverter. the output of AND gate is high when all
Ans. (b) : NAND-NAND-realization– input are high and output of AND gate is low when any
one of the input is low. Then AND gate is not use in an
inverter.
C = A⋅B 63. The output is high if either of the input is high.
The above statement represents _____
Y = A⋅B = A⋅B .....(i) (a) NAND gate (b) EX-OR gate
AND-OR realization– (c) OR gate (d) AND gate
RRB JE 19.09.2019 Shift-II
C = A⋅B Ans. (b) : EX-OR gate has this property-
Y = A⋅B .....(ii) A ⊕ B = AB + AB
Equation (i) equal to equation (ii) A B A⊕B
59. What is simplified form of the Boolean
0 0 0
expression T = (X + Y) (X + Y ) ( X + Y)?
(a) XY (b) XY 0 1 1
(c) XY (d) XY 1 0 1
HPSSSC JE 2018 Code -387 1 1 0
Ans. (a) : Given,
T = (X + Y) (X + Y ) ( X + Y)
= (X.X + X Y + X.Y + Y. Y ) ( X + Y)

Electronics-II 810 YCT

64. For an m-variable Boolean function, the 67. Solve?
maximum number of prime implicants would (COMP(A)B+A+COMP(B)
be (a) 1 (b) 0
(a) m/2 (b) 2(m-1) (c) COMP(B) (d) A
(c) 2(m-1) (d) 2m NMRC JE 2019
BSPHCL JE 31.01.2019 Shift-I Ans. (a) : AB + A + B
Ans. (b) : Each individual min-term in canonical SOP
= A+ B+ B ∵ AB + A = A + B 
form is called implicant.  
For on m-variable boolean function the maximum ∵ B + B = 1
= A +1
number of primary implicants would be = 2(m-1)  
For m-variable maximum possible distinct logic
m
=1 [∵ 1 + A = 1]
functions = 22 . 68. The Boolean expression for a two input
65. Minimum number of NAND gates used for Exclusive-OR gate is:
representing EX OR and EX NOR gates are (a) Y = A – B (b) Y = A + B
_________________ respectively. (c) Y = A × B (d) Y = A ⊕ B
(a) 3, 4 (b) 4, 5 UPRVUNL JE 24.10.2021, 9am -12pm
(c) 4, 3 (d) 5, 4 UPPCL JE 27.11.2019, Shift-I
PGVCL JE 2018
BSNL TTA 28.09.2016, 3:00 PM Ans : (d) Symbol of XOR gate
Ans. (b) : X-OR gate Realization using NAND gate.

Output of X-OR gate Y = A ⊕ B EX-OR (XOR) gate gives true or high output when both
= AB + AB input different in case of same input output will low.

69. The output of a 3-input AND gate is high

( )( )
when:
Y = A.AB . B.AB = A.AB + B.AB (a) all the three inputs are high
(b) no input is high
( ) ( )
Y = A A + B + B A + B = AB + AB = A ⊕ B (c) any two inputs are high
(d) any one input is high
X- NOR Using NAND gate- UPPCL JE 27.11.2019, Shift-I
Ans : (a) The output of AND gate will be high at this
stage when all its input are high

∵X = A ⊕B
Y = X = A⊕B = A⊙B
Y = AB + AB
66. Number of NAND gates required to realise a
half adder circuit is ______.
(a) three (b) five 70. If we group four 1's from the adjacent cells of a
(c) six (d) four K-map, the group is called:
LMRC (SCTO) 17.04.2021 (a) nibble (b) quad
Ans. (b) : Total number of NAND-gates required to (c) byte (d) word
implement Half adder = 5 UPPCL JE 27.11.2019, Shift-I
While, Total 9 NAND gates are required to implement a Ans : (b) When there are four 1's type of cell in a k-map
full adder. the that group called quad
Electronics-II 811 YCT
 74. Y=A ⊙B
Which logic GATE function is represented by
above equation.
(a) NOR (b) EX-OR
(c) EX-NOR (d) NAND
UPPCL JE 27.11.2019, Shift-II
Ans. (c) :
AND AB
OR A+B
The quad is a group of four 1's that are horizontally NOT
and vertically close together. A
NAND AB
71. Simplification of the Boolean expression Y =
NOR A+B
AB + ABC + ABC' is:
(a) Y = AB (b) Y = AB + BC EX-OR A⊕B
(c) Y = BC (d) Y = ABC EX-NOR A⊙ B
UPPCL JE 27.11.2019, Shift-I 75. Write the simplified equation for the given K-
Ans : (a) y = AB + ABC + ABC Map.
= AB(1 + C) + ABC = AB + ABC
( )
= AB 1 + C = AB
72. If A = 1, B=1, what will be the values of Y and
Z?

(a) Y = B1B2 + B2 B1 (b) Y = B3 B0 + B4 B3

(c) Y = B3 B2 + B2 B3 (d) Y = B1B0 + B0 B1
(a) Y = 0, Z = 0 (b) Y = 1, Z = 1 UPPCL JE 27.11.2019, Shift-II
(c) Y = 1, Z = 0 (d) Y = 0, Z = 1 Ans. (a) :
UPPCL JE 27.11.2019, Shift-II
Ans. (d) :

By making a quad of four-

Z = (A + B) + A(A + B) Y = A ( A + B) Y = B1B2 + B2 B1
Z = A + B + AA + AB = AA + AB 76. This is the waveform of a gate. There are two
inputs A and B and one output Y. Identify the
Z = A + B + 0 + AB Y = 0+0
Logic Gate based on the output waveform.
Y =0
Z = A + B(1 + A)
(
Z = A + B ×1 1 + A = 1 )
Z = 1+1
Z =1
73. Which of the following is a Quad 2-Input OR
gate? (a) EX-OR Gate (b) NOR Gate
(a) 7408 (b) 7486 (c) AND Gate (d) NAND Gate
(c) 7400 (d) 7432 UPPCL JE 27.11.2019, Shift-II
UPPCL JE 27.11.2019, Shift-II Ans. (d) :
Ans. (d) :
7400 – NAND
7402 – NOR
7404 – NOT
7408 – AND
7432 – OR
7486 – Ex-OR
74266 – Ex-NOR
7432 represents OR gate.
Electronics-II 812 YCT
77. The output Y of the logic circuit shown in Fig. 80. Which of the following Boolean rules is
is_____. correct?
((a) A+0=0 (b) A+1=1
(c) A + A = A.A (d) A + AB = A + B
ISRO TA 2015
(a) Y = A (b) Y = A Ans. (b) : Boolean theorem
(c) Y = 0 (d) Y =1 (i) A+0=A
DGVCL JE 06.01.2021, Shift-I (ii) A+1=1
Mizoram PSC Nov. 2015, Paper - III (iii) A + A = 1
Ans. (d) : Given circuit- (vi) A+AB=A
So A + 1 = 1 is correct.
81. The truth values of fuzzy set are (is) _________.
(a) 1.0.5
(b) Between 0 and 1 both exclusive
(c) Either 0 or 1
(d) Between 0 and 1 both inclusive
NLC GET 17.11.2020
= AA + AA Ans. (d) : Fuzzy logic is a form of many-valued logic in
which the truth value of variables may be any real
= A + A =1 number between 0 and 1.
78. The minimum number of 2-input NAND gates both inclusive 0 → totally false.
required to implement a 2-input XOR gate is 1 → totally true.
_____. • The truth value of traditional set theory is either 0 or
(a) 2 (b) 5 1.
(c) 4 (d) 3
DGVCL JE 06.01.2021, Shift-I 82. NAND Gate is equal to
(a) NOR gate with negative output
Ans. (c) : The minimum number of 2-input NAND (b) NOR gate with negative input
gates required to implement a 2-input XOR gate is 4. (c) AND gate with negative input
Logic No. of NAND No. of NOR gate (d) None of these
gates gate required required BSNL TTA 29.09.2016, 3 pm
NOT 1 1 Ans : (d) NAND gate is equal to AND gate with
AND 2 3 negative output.
OR 3 2
EX-OR 4 5
EX-NOR 5 4
79. The output of a 2 input logic gate is "0" if and
only if its inputs are unequal. It is true for
(a) XNOR (b) AND
(c) NOR (d) NAND NAND Gate
ISRO TA 2015 A NAND gate is equivalent to AND gate with negative
Ans. (a) : XNOR gate is a digital logic gate whose output OR an inverted (negative) input OR gate.
function is the logical complement of the EXOR gate.
A high output (1) results if both of the inputs to the gate
are the same.
• It acts as even number of 1's detector'
• It is also called, "gate of equivalence" or coincidence
logic symbol and truth table. If both input are different
then output low (0).
83. The odd parity is generated by
(a) EX–OR gate (b) EX–NOR gate
(c) NOT gate (d) All of these
Y = A⊕B BSNL TTA 29.09.2016, 3 pm
= AB + AB Ans : (b) The odd parity is generated by Ex-NOR gate.
XNOR table:- It gives output when both the inputs are same.
Y = A ⊙ B = AB + AB

Electronics-II 813 YCT

84 The inputs of a NAND gate are connected 88. Two 2's complement numbers having sign bits
together. The resulting circuit is X and Y are added and the sign bit of the result
(a) OR gate (b) AND gate is Z. Then, the occurrence of overflow is
(c) NOT gate (d) None of these indicated by the Boolean function
BSNL TTA 29.09.2016, 3 pm (a) XYZ (b) XYZ
Ans : (c) When the inputs of a NAND gate are (c) XYZ + XYZ (d) XY + YZ + ZX
connected together then the resultant circuit is NOT ISRO TA 2017
gate
Ans. (c) : Let A and B two numbers and S = Sum
X,Y, Z are sign bits
A = X − − − −a1 a 0
85. What is the minimum number of two–input
NAND gates used to perform the function of B = Y − − − −b1 b0
two-input OR gate S = Z − − − −S1 S0
(a) 1 (b) 2 Conditions of overflow are -
(c) 3 (d) 4 1- Sum of two positive number given a negative
BSNL TTA 29.09.2016, 3 pm number, there will be overflow.
Ans : (c) 2- Sum of two negative number given a positive
number, there will be overflow.
For condition (1) -
A = positive number, X = 0
B = positive number, Y = 0
S = negative number, Z = 1
d = XYZ
It requires 3 NAND gates For condition (2) -
A = negative number, X = 1
86. For a binary half-subtractor, the correct set of B = negative number, Y = 1
logical expressions for outputs D (A minus B) S = positive number, Z = 0
and X (borrow) are
= XYZ
(a) D = AB + AB, X = AB
Then, the Boolean function = XYZ + XYZ
(b) D = AB + AB, X = B + AB
89. The logical expression, AB C + A BC + A B C is
(c) D = AB + AB, X = AB
equivalent to
(d) D = BA + AB + AB, X = AB + BA
(a) A (B + C) (b) A + B + C
ISRO TA 2017
Ans. (c) : (c) A B C (d) A( C + B )
ESE 2017
Ans. (d) : ABC + ABC + ABC
( )
= AC B + B + ABC

= AC + ABC ∵B + B = 1
 
Logical expression of half subtractor. (
= A C + BC )
Difference = AB + AB = A ⊕ B
Borrow = AB = A ( C + B) ( C + C ) ∵ C + C = 1
 
87. If X=1 in the logic equation = A ( C + B)
{ (
[X + Z Y + Z + XY )}{X + Z ( X + Y )} = 1 then 90. Which one of the following relations from the
(a) Y=Z (b) Y= Z Boolean algebra pertaining to 'AND' operation
(c) Z=1 (d) Z=0 cannot be verified when A and B can take on
ISRO TA 2017 only the value 0 or 1?
(a) AB = BA (b) AA = A
{ (
Ans. (d) : [X + Z Y + Z + XY )} X + Z ( X + Y )] = 1 (c) A1 = 1 (d) A0 = 0
ESE 2020
Given X = 1
Ans. (c) : AB = BA, AA = A and A0 = 0 can be verified
So, { (
[1 + Z Y + Z + 1.Y )} 1 + Z (1 + Y )] = 1 but A1 = 1 cannot be verified as.
A can have 0 or 1.
Z =1 [∵ 1 + A = 1] If A = 1 ⇒ A.1 = 1.1 ⇒ 1 True but
Z=0 If A = 0 ⇒ 0.1 = 1 which is not true.

Electronics-II 814 YCT

91. AND gate is a logic circuit whose output is 1 : 95. If X and Y are a astable binary, then X(X+Y) is
(a) If any two of the inputs are 1 equivalent to-
(b) If any three of the inputs are 1 A. X B. 1
(c) If and only if all its inputs are 1 C. 0 D. Y
(d) If and only if all its inputs are 0 (a) A (b) B
UPPCL JE 25.11.2019, Shift-II (c) C (d) D
Ans. (c) : AND gate is a logic circuit whose output is 1. OPPSC AE 2021, Paper-II
If and only if all its inputs are 1. (RRB JE (Shift-3), 28.08. 2015)
Y = A.B Ans : (a) If X and Y are a astable binary, then X(X+Y)
is equivalent to X.
A.( B + C ) = ( A.B ) + ( A.C ) (from distributive law)
So, X(X+Y) = (X.X) + (X.Y)
= X + XY (∴ X.X = X )
= X (1 + Y ) (∴1 + Y = 1)
=X
96. In binary Algebra, A + B can be implemented.
92. A K -map of 3 variable contains _____ cells. (a) By NAND gate only
(a) 6 (b) 8 (b) By NOR gate only
(c) 9 (d) 3 (c) By AND gate only
UPPCL JE- 08.09.2021, Shift-II (d) By (a) and (b) both
UPPCL JE 25.11.2019, Shift-II (RRB Chandigarh 2014)
Ans. (b) : A K-map of 3 variable consists 8 cells no. of Ans : (d) In binary Algebra, A + B can be implemented
cells in K-map =2n by NAND and NOR.
n = 3= 23=8 A A
93. The ………… gate produces logic high output Y =AB
for similar types of inputs only.
(a) EX-OR (b) NAND B B
(c) EX-NOR (d) NOR Y=A+ B
DGVCL JE 06.01.2021 Shift-III
Ans. (c) : EX-NOR gate

∵ NAND and NOR gate both are universal gate.

97.
The statement of demorgan's theorem is.
(a) (X+Y) = Y′+X′ (b) (X.Y)' = X′+Y′
(c) (X.Y.)′ = Y′.X′ (d) (X+Y)′ = X′+Y′
When both the input are same then output becomes high (RRB Jharkhand 2014)
or logic 1.
Ans : (b) (X.Y)′ = X′+Y′
94. The output expression ‘F’ for the De-morgan theorem-1
combinational logic circuit shown in Fig. is
A.B = A + B
given by
NAND = Bubbled OR
De-morgan theorem-2
A + B = A. B
NOR = Bubbled AND
(a) F = B (b) F = B 98. Boolean Algebra (1 + 1).( 0 + 0 ) = ?
(c) F = A (d) F = A
(a) 0 (b) 1
DGVCL JE 06.01.2021 Shift-III
(c) 2 (d) -1
Ans. (b) : Given circuit diagram- (RRB Jharkhand 2014)
Ans : (a) (1 +1 ) .( 0 + 0 ) = (1) .( 0 )
= 0.1 = 0
99. Any NOR gate is called universal logic gate
because
output (F) = A B + A + B = A.B + A.B (a) It can be used without the requirement of any
(
= A+A B ) other type of gate
(b) It can be used universally only with AND
F= B gate

Electronics-II 815 YCT

 (c) It can be used universally only with OR gate 103. Any Logic gate both of input is zero, output is
(d) It can be used universally only with NOR one, Logic gate will be-
gate 1. NAND or XOR 2. OR or XOR
(RRB Guwahati 2014) 3. AND or XOR 4. NOR or EX-NOR
Ans : (a) Any NOR gate is called universal logic gate (a) 1 (b) 2 (c) 3 (d) 4
because, it can be used without the requirement of any (RRB JE (Shift-3), 28.08. 2015), SAIL 29.3.14
other type of gate. Ans : (d) Any Logic gate both of input is zero, output is
The logic gates can be classified as- one, Logic gate will be NOR or EX-NOR.
Basic gate: NOT, AND, OR
Universal gate: NAND, NOR
Special purpose gate : EX-OR and EX-NOR
100. The output of logic gate is '1' if all its i/p are '0'
then the gates will be one of these.
(a) A NAND or an EXOR gate
(b) A NOR or an EX-NOR gate
(c) An OR or an EX-OR gate
(d) One AND or one EX-OR gate
(RRB Guwahati 2014)
Ans : (b) It can be NOR or an EX-NOR gate.
NOR → Y = ( A + B ) EX − NOR → Y = A ⊕ B
104. Output of NOR gate is high, when–
1. all i/p are high 2. any i/p are not high
3. any i/p are not low 4. all i/p are low
1 (a) 1 (b) 2
(c) 3 (d) 4
UPPCL JE-07.09.2021, Shift-I
RRB JE Shift-3, 28.08. 2015
Ans : (d)

101. Which of the following expressions represents

logical AND gate?
(a) A+B (b) A/B
(c) A>B (d) A.B
RRB JE Bhopal Paper II (Shift-II), 26.08.2015
105. The output of XOR gate is one (1) when
Ans : (d)
(a) Both inputs are different
(b) Both inputs are zero
(c) Both inputs are one
(d) Both inputs are same
(RRB JE (Shift-II), 04.09.2015)
Ans : (a) The output of XOR gate is one (1) when both
inputs are different.

So, In AND, Y = (A.B) .

102. Exclusive OR (XOR) logic gate in which can be
made up of logic gate.
(a) Only from OR gate
(b) AND & NOR gate
(c) AND, OR & NOR gate 106. How many numbers of NOR gates are required
(d) From OR and NOT gate to realize AND gate.
(RRB JE Bhopal Paper II (Shift-II), 26.08.2015) (a) 2 (b) 4
Ans : (c) Exclusive OR (XOR) logic gate in which can (c) 3 (d) 5
be made up of logic gate AND, OR & NOR gate. (RRB SSE (Shift-III), 01.09.2015)
Ans : (c)

3 NOR gates required to realize AND gate.

Electronics-II 816 YCT

107. Which of the following is the electrical Ans : (d) ( Y + XY ) = Y (1 + X )
equivalent of the given figure–
=Y (∴1 + X = 1)
113. If X is binary, then the boolean follow of X + 0
is equal.
(a) NOT Gate (b) OR Gate (a) X (b) 1
(c) NOR Gate (d) NAND Gate (c) 0 (d) X'
(RRB JE Secundrabad (Shift-I), 18.08.2015) (RRB JE Bhopal Paper II (Shift-II), 26.08.2015)
Ans : (b) The given figure represent OR Gate. Ans : (a) If X is binary, then the boolean follow of X +
0 is equal X.
According to Boolean-
A+0=A
A . 0 = 0, A.1=A
A . A = A, A+1=1
114. Which of the following Boolean expression is
NOT TRUE?
(a) A+1=A (b) A+A'=1
108. In Boolean Algebra, A (A +B') is equivalent to : (c) A.A=A (d) A.A'=0
(a) 0 (b) 1 (c) A (d) B (RRB JE (Shift-2), 29.8.2015), BSNL (TTA) 29.9.16
(RRB SSE (Shift-II), 03.09.2015) Pune Metro 18.10.2021
Ans : (c) A (A + B') = A.A + A B (by distributive law) Ans : (a) A + 1 = 1 (By Boolean law)
So, (A + 1 = A) (It is not possible)
= A + AB (∴ A.A = A ) Boolean rule-
= A (1 + B ) (∴ 1 + B = 1) A +1=1
(O R L a w )
A + A '=1
=A A .A ' = 0
109. Considering X and Y as binary variables, the (A N D L aw )
A .A = A
Boolean expression X + Y + 1 is equivalent to– 115. A+A' has the logic value–
(a) X (b) 1 (a) 0 (b) 1 (c) A (d) A'
(c) 0 (d) Y (RRB JE (Shift-2), 29.8.2015)
(RRB JE (Shift-I), 29.08.2015) Ans : (b) A + A' = 1
Ans : (b) Boolean Rule ⇒ A + 1 = 1 Boolean law-
A + A' =1 A.A ' = 0
X + Y + 1 = X + ( Y + 1) ( AND Law )
A.A = A
= X +1 = 1
A+0= A
110. Considering X and Y as binary variables, the
equivalent Boolean expression for (X . Y)' is : A +1 = 1 ( OR Law )
(a) X'+Y (b) X+Y' (c) X'+Y' (d) X'.Y'
A+ A =1
(RRB SSE (Shift-II), 01.09.2015)
Ans : (c) (X . Y)' = X' + Y' 116. Considering X and Y as binary variables, the
Boolean expression X.Y.0 is equivalent to–
De-morgan theorem-2 (a) X (b) 1 (c) 0 (d) Y
A.B = A + B (RRB JE (Shift-2), 29.8.2015)
NAND = Bubbled OR
De-morgan theorem-1
Ans : (c) X.Y.0 = 0, [∴ A.0 = 0]
117.
Which of the following statement is not correct?
A + B = A. B
(a) X + XY = X (b) X.(X + Y) = XY
NOR = Bubbled AND
111. In Boolean Algebra, A+A+A+ ....... +A is the (c) X + XY = X (d) ZX + ZXY = ZX + ZY
same as: (RRB SSE Secundrabad (Shift-I), 02.09.2015)
(a) Zero (b) A Ans : (a) Boolean law- A + A = 1
(c) nA (d) An A + 1 =1
(RRB SSE Secunderabad Red Pepar, 21.12. 2014) A+0=A
Ans : (b) A +A + A + ....... +A A.1=1
A(1 + 1 + 1+.......... +1) = (A) A.A = 0
( ∵ 1+1 =1) A + AB = A
So, A (1 + 1+ ............ +1) (a) X + XY = X
A×1=A L.H.S = X + XY
112. If X and Y is an unstable binary, then the
= X (1 + Y ) + XY = X + XY + XY
Boolean follow of Y +XY is–
(a) X (b) 1 = X + Y (X + X) = X + Y
(c) 0 (d) Y
(RRB JE Bhopal Paper-I (Shift-II), 28.08.2015) L.H.S ≠ R.H.S
Electronics-II 817 YCT
118. In boolean Algebra, A' (A + B') is equivalent to 123. An EX-OR gate produces an output only when
(a) A'B (b) AB' its two inputs are
(c) AB (d) A'B' (a) Same (b) Different
(RRB SSE (Shift-III), 03.09.2015) (c) High (d) Low
Ans : (d) A '(A + B ') HPSSC JE 2017, Code - 580
Mizoram PSC Nov. 2015, Paper-III
= A 'A + A 'B' (∴ A 'A = 0 ) Ans. (b) : For an EX-OR gate
= A ' B'
119. Considering X as a binary variable, the
Y = A⊕B = AB + AB OR Y = (A+B) A + B ( )
Boolean expression X.1 is equivalent to–
(a) X (b) 1 (c) 0 (d) X'
(RRB JE (Shift-III), 26.08.2015)
Ans : (a) X.1 = X ( Boolean Law ) A B Y
AND Operation theorem 0 0 0
A. A = A 0 1 1
A. 0 = 0
A. 1 = A 1 0 1
A. A =0 1 1 0
Hence when both inputs are different than
120. Which among the following is the dual of output will high.
Boolean expression X+YZ=(X+Y) (X+Z)?
(a) X(Y+Z)=XY+YZ 124. Which one of the following is equal to A + B ?
(b) X.(Y+Z)=X.Y+X.Z (a) A ⋅ B (b) A ⋅ B
(c) X+(Y+Z) = X.Y+Z
(d) X+(YZ) = X+Y+Z (c) A ⋅ B (d) A ⋅ B
OPPSC AE 2021, Paper-II UKPSC JE 2013, PAPER-I
JKSSB JE 2014 Ans. (d) : (i) De – Morgan's first Theorem –
Ans. (b) : "Dual expression" is equivalent to write a A + B + C + ...... + N = A.B.C.......N
negative logic of the given Boolean relation. (ii) De – Morgan's second theorem –
So given Boolen expression – X+YZ = (X + Y) (X + Z)
A.B.C.......N = A + B + C + ....... + N
and dual expression – X.(Y+Z) = X.Y + X.Z
121. The output of a 2-input OR gate is zero only 125. Consider following gates :
when NAND, NOR, X-OR GATE
(a) both inputs are 0 (b) either input is 0 Out of these gates, the universal gates are
(c) both inputs are 1 (d) either input is 1 (a) 1 and 3 only (b) 2 and 3 only
Mizoram PSC Nov. 2015, Paper-III (c) 1 and 2 only (d) 1, 2 and 3
UKPSC JE 2013, PAPER-I
Ans. (a) : Truth table of 2- input OR gate
INPUT OUTPUT Ans. (c) : Universal Gate – NAND, NOR
A B Y=A+B Basic Gate – AND, OR, NOT
Special purpose Gate – Ex-OR, Ex-NOR
0 0 0
0 1 1 126. The number of NAND gates required to
1 0 1 implement a function A + AB + ABC is equal to
1 1 1 (a) 0 (b) 1
When all input will low (0) in OR gate then output (c) 4 (d) 5
will be low (0). UKPSC JE 2013, PAPER-I
122. The POS form of expression is suitable for Ans. (a) : A + AB + ABC
circuit using = A(1 + B) + (ABC)
(a) XOR (b) NAND
(c) AND (d) NOR = A + ABC
UPPSC AE 13.12.2020, Paper - II = A(1 + BC)
Mizoram PSC Nov. 2015, Paper-III = A
Ans. (d) : The POS (product of sum) form of Conclusion-No. of NAND Gate required to implement
expression is suitable for NOR gate. function A + AB + ABC will be zero.
127. A 3 variable truth table has a high output for
the inputs 010, 011 and 110. The Boolean
expression for sum of products (SOP) can be
written as
(a) AB + BC (b) AB + BC
Y = A+ B+C+ D (c) AB + BC (d) AB − BC
Y = (A+B) (C+D) APGCL JM 2021
Electronics-II 818 YCT
Ans. (a) : 131. For the circuit in Fig., the output expression 'Y'
is given by ______.

From K-map simplification

Y = AB + BC
128. A combinational circuit has input A, B and C
and its Karnaugh map is given in figure. The (a) AB (b) A+B
output of the circuit is
(c) AB (d) A + B
DGVCL JE 0.5.01.2021, Shift-II
UKPSC JE 2013, Paper - I
Ans. (b) :

(a) (A'B –AB') (b) (A'B –AB'C)

(c) A ⊕ B ⊕ C (d) A'B'C'
APGCL JM 2021
Ans. (c) :

Y1 = A.A = A
Y2 = B.B = B
Y = Y1.Y2
= ABC + ABC + ABC + ABC = A⊕B⊕C Y = A.B
129. Y = A+B
Y=A+B
132. The Boolean expression Y = AB+CD represents
(a) Two ORs AND together
For the above circuit each NOT gate has delay (b) A 4-Input AND gate
of 10 nsec find the output frequency (c) Two ANDs and one OR Gate together
(a) 33.33 MHz (b) 3.33 MHz (d) An exclusive OR
(c) 1.667 MHz (d) 16.67 MHz BSNL TTA (JE) 25.09.2016, Shift-I
APGCL JM 2021 Ans. (c) :
Ans. (d) :
1
fo =
2nTd
1
= Hz = 16.67 MHz 133. If A and B are two input in AND gates, and
2 × 3 ×10 ×10−9 AND gate has output of 1, when the values of A
130. Which gate operation gives high output when and B are
any one of its input is high? (a) A = 0, B = 0 (b) A = 1, B = 1
(a) EX-OR Gate (b) NAND Gate (c) A = 1, B = 0 (d) A = 0, B = 1
(c) NOR Gate (d) EX-NOR Gate BSNL TTA (JE) 25.09.2016, Shift-I
UPPCL JE 11.02.2018, Shift-I
Ans. (b) : If the AND gate has two inputs A and B,
Ans : (a) Exclusive OR gate or XOR gate is a digital
logic gate that implements an exclusive OR, that is, a then the output of AND gate will be one (1) when
true output High results if one, and only one, of the A=B=1.
inputs to the gate is true.
A
Y=A+ B
B
Truth Table of Ex-OR Gate
A B Y
0 0 0 134. Which of the following can be used as an
0 1 1 inverter
1 0 1 (a) AND (b) NOR
(c) OR (d) None of these
1 1 0
BSNL TTA (JE) 25.09.2016, Shift-I
Electronics-II 819 YCT
Ans. (b) : NOR gate can be used as an inverter. For 138. The minimized expression for the given K map
inverters the output is 1 when the input is 0. There are (x:don't care) is
two ways to use the NOR gate as an inverter- (a) C + AB (b) B +AC
(c) A + B C (d) AB + C

135. In Boolean algebra, the term sum-of-products

means
(a) the AND function of several OR functions
(b) the OR function of several AND functions
(c) the OR function of several OR functions
BSNL TTA (JE) 2013
(d) the AND function of several AND functions
BSNL TTA (JE) 25.09.2016, Shift-I Ans. : (c)
Ans. (b) : In Boolean algebra, the term sum of products
means the OR function of several AND functions. i.e.
all the fundamental products of 'AND' gates are 'OR' to
obtain the sum-of-products equation.

136. A gate is a circuit with one or more input but

output is K-MAP Minimization
(a) two (b) one
F = A + BC
(c) three (d) more than
BSNL TTA (JE) 25.09.2016, Shift-I 139. The output of a EX-NOR logic gate is '1' when-
(a) The inputs are the same
Ans. (b) : A gate is a circuit with one or more input but (b) One input is high and other is low
output is one. (c) The inputs are different
A digital logic gate is an electronic circuit which makes (d) None of these
logical decisions based on the combination of digital BSNL TTA (JE) 2013
signal present on its input. Ans. : (a) The output of a EX-NOR logic gate is '1'
137. (D635)16 XOR (FE15)16 is equal to when the inputs are the same.
(a) (3320)16 (b) (FF35)16 EX-NOR gate acts like as an odd parity generator-
(c) (2820)16 (d) (3520)16
BSNL TTA (JE) 2013
Ans. : (c)

For EX-OR gate,

Boolean function of 2-input EX-NOR operation:
( )
Y = A ⊙ B = A ⊕ B = AB + AB = AB + AB
140. Which one of the following statements is not
correct?
(a) X + XY = X
(b) X( X + Y) = XY
For the same input I/P →0 (c) XY + X Y = X
For the different input I/P→1 (d) ZX + Y ZX = Z
= (2820)16 BSNL TTA (JE) 2013
Electronics-II 820 YCT
Ans. : (d) 146. In which of the following gates the output is 0 if
and only if at least one input is 1?
ZX + YZX (a) NOT (b) AND
(
= ZX 1 + Y ) (c) NOR (d) NAND
BSNL TTA 26.09.2016, 10 AM
= ZX
Ans. (c) : The NOR gate is a digital universal logic
Therefore, ZX + YZX ≠ Z gate. In NOR gate a HIGH output (1) results if both the
141. In Boolean expression (A+BC) equals inputs to the gate are LOW (0); if one or both input is
(a) (A+B)(A+C) (b) (A'+B)(A'+C) HIGH (1), then low output is obtained.
(c) (A+B)(A'+C) (d) (A+B)C
UPPSC AE 13.12.2020, Paper - II
BSNL TTA (JE) 2013
Ans. : (a) (A+BC) = (A+B) (A+C)
Proof
= A.1 +BC {A.1 = A}
= A(1+B) +BC {1+B = 1}
= A+AB+BC
= A(1+C) +AB+BC {1+C = 1}
= A+AC+AB+BC 147. The circuit shown in the figure below generates
= A.A+AC+AB+BC {A.A = A} the function of-
= (A+B) (A+C)
142. NAND operation is equivalent to
(a) A + B (b) A + B
(c) A.B (d) AB
BSNL TTA (JE) 14.07.2013
Ans. : (b) Y = A.B

143. Logic inverter can be constructed with

(a) OR gates (b) AND gates (a) x ⊕ y (b) 0
(c) AND & OR gates (d) NOR gates (c) xy + yx + yx (d) x.y
BSNL TTA (JE) 14.07.2013 ESE 2010
Ans. : (d) Logic inverter can be constructed with NOR- Ans. (a) :
gate.

144. Which of the following is called as a universal

gate?
(a) OR gate (b) AND gate
(c) NOT gate (d) NOR gate
BSNL TTA (JE) 14.07.2013
Ans. : (d) The gate which can implement any Boolean
function without need to use any other gate is called
universal gate, only NAND and NOR gates are f = (x⊕y⊕y⊕y) ⊕ (x ⊕ x⊕y⊕y)
universal gate. {y ⊕ y = 0, y ⊕ 0 = y}
145. The_____ gate is generally used to check for or
to generate the proper parity in a code. f = x⊕y⊕0 = x⊕y {x⊕x = 0}
(a) NAND (b) NOR 148. In the logic circuit of fig. the redundant gate is–
(c) EX-NOR (d) EX-OR
BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (d) EX-OR Gate is generally used to check for or
to generate the proper parity in a code.

(a) 1 (b) 2
Universal Gate NAND & NOR are made by the used of (c) 3 (d) 4
basic gate AND, OR, NOT. BSNL TTA 28.09.2016, 10 AM
Electronics-II 821 YCT
Ans. (b) : • Buffer using 2-NAND gates-

• Buffer using 1-NAND & 1-NOR gates-

Hence, We can implement buffer using all of the above.

151. For a four input OR gate the number of input
condition, that will produce HIGH output are-
(a) 1 (b) 3
(c) 15 (d) 0
BSNL TTA 26.09.2016, 3 PM
Ans : (c) OR gate is a digital logic gate. It gives high
output if any of input is high otherwise give low input.
For four input OR gate if any input is high then output
is high. The output is low when all inputs are low.
Total number of input condition for high output
= 2n − 1
output (X) = xyz + wyz = 24 −1
The redundant gate is 2. = 15
149. The minimum number of two input NAND 152. Depth of an arithmetic circuit is-
gates required to implement two input NOR (a) Number of gates in it
gate is - (b) Length of the longest path in it
(a) 2 (b) 3 (c) Sum of number of gates and length
(c) 4 (d) 5 (d) None of these
BSNL TTA 28.09.2016, 3 PM BSNL TTA 26.09.2016, 3 PM
Ans. (c) NAND, NOR are the universal gates because Ans : (b) Depth of an arithmetic circuit is the length of
they can implement any given boolean function with
longest path in it and the size of a circuit is the number
only using NAND or only using NOR.
So, NOR gate is- of gates in it.
153. Which logic gate is similar to the function of
two parallel switches?
NOR gate using NAND- (a) AND (b) NAND
(c) OR (d) NOR
BSNL TTA 26.09.2016, 3 PM
Ans : (c) Let the two switch A (sw1) and B (sw2) are
in parallel and they are connected in series with bulb.
If any of these switch is closed (High) then bulb is
start glowing (output is high).
Hence, min 4 NAND gate required to implement NOR
gate.
150. The minimum number of two input NOR &
NAND gates required to implement a Buffer
function is-
(a) 2 NOR Gates
(b) 2 NAND Gates
In matrix form-
(c) 1 NAND & 1 NOR Gate
(d) All of these A (sw1) B (sw2) Output (bulb)
BSNL TTA 28.09.2016, 3 PM 0 (open) 0 (open) 0 (not glowing )
Ans. (d) A buffer is nothing but two inverters 0 (open) 1(closed) 1 (start glowing)
connected back to back. 1 (closed) 0 (open) 1 (start glowing)
i.e. 1 (closed) 1 (closed) 1 (start glowing)
By this truth table we can say that two parallel
switches are similar to OR logic gate.
154. Implement the following Boolean function with
• Buffer using 2-NOR gates-
NAND-NAND logic.
(Y = AC + ABC + ABC + AB + D)

Electronics-II 822 YCT

 156. Which of the following does not relate to the
duality theorem?
(a)
(a) A*A=A (b) A+B=A.B
(c) A+A=A (d) A+0=A
MPPEB Sub. Engineer 0.8.07.2017 Shift-I
Ans. (b) : The law A + B = A.B does not relate duality
property.
e.g. if A = 1 and B=0
(b) A+B = 1+0=1=A
Similarly A.B. = 1.0=0=B
Hence, A + B ≠ A.B
157. The minimum number of NAND gates required
to reduce the expression ((A+B)C)D is:
(a) 6 (b) 5
(c) 8 (d) 4
(c) MPPEB Sub. Engineer 0.8.07.2017 Shift-I
Ans. (b) : NAND realization of ((A+B)C)D is shown
below in diagram-

(d) None of the above

MPPEB Sub. Engineer 0.8.07.2017 Shift-I
Ans. (b) :
It requires 5 NAND gates.
158. The Boolean function Y = AB + CD is to be
realized using only 2–input NAND gates. The
minimum of ------ required is :
(a) 2 (b) 3
(c) 4 (d) 5
MRPL (Tech. Asstt. Trainee), 21.02.2021
Given Y = AC iBCiABi D KVS WET 2017
BSNL TTA 25.09.2016, 3:00 P.M.
= AC + BC + AB + D Ans : (b) The Boolean function Y = AB + CD is to be
= AC+BC+AB+D realized using only 2–input NAND gates. The minimum
Hence, the given Boolean function can implement with of 3 NAND gates are required
NAND-NAND logic.
155. The minimized sum of products expression for
f (a,b,c,d) = Σm(0,1,5,6,7,8,9) with don't care
Σm (10,11,12,13,14,15) is _______.
(a) f ( a, b,c, d ) = bc + bd + bc
(b) f ( a, b, c, d ) = bc + bd + bc
So
(c) f ( a, b,c, d ) = bc + bd + bc
Y = AB + CD
(d) f ( a, b,c,d ) = bc + bd + bc
159. Which of the following Boolean expressions
MPPEB Sub. Engineer 0.8.07.2017 Shift-I correctly represent the relation between P, Q,
Ans. (c) : R and M1

(a) M1 = (P OR Q) XOR R
(b) M1 = (P AND Q) XOR R
(c) M1 = (P NOR Q) XOR R
(d) M1 = (P XOR Q) XOR R
f = BC + BD + BC BSNL TTA 25.09.2016, 3:00 P.M.
Electronics-II 823 YCT
Ans : (d) Ans. (a) : The block diagram-

164. For the logic circuit shown in the figure, the

required input condition (A, B, C) to make the
( ) ( )
M1 = PQ ( P + Q ) .R + R.  PQ + P + Q 

output (X) = 1 is-

= ( P + Q ) ( P + Q ) R + R  PQ + P.Q 

(a) 1, 0, 1 (b) 0, 0, 1
(c) 1, 1, 1 (d) 0, 1, 1
so BSNL TTA 29.09.2016, 10 AM
Ans : (d)
P⊕Q⊕R
output M1 = (P XOR Q) XOR R
160. NOR Gate is equal to :
(a) OR Gate with negative inputs
(b) NAND gate with negative output
(c) AND gate with negative input ( )
X = ( A ⊕ B ) . B ⊕ C .C
(d) None of these
BSNL TTA 25.09.2016, 3:00 P.M. = ( AB + AB ) . ( CB + CB ) .C
Ans : (c) For NOR gates- = ( AB + AB ) .(CCB + C.CB)
AND gate with negative inputs,
∵CC = 0 
= ( AB + AB ) (0 + BC)  
(NOR gate)  CC = C 
161. Logic 1 in positive logic system is represented = ( AB + AB ) BC
by :
(a) zero level (b) lower voltage level ∵ BB = 0 
= ABBC + AB.BC  
(c) higher voltage level (d) negative voltage  BB = B
BSNL TTA 25.09.2016, 3:00 P.M. = 0 + ABC
Ans : (c) Logic 1 in positive logic system is
represented by higher voltage level. x = ABC
162. A + AB + ABC + ABCD simplifies to : To be X = 1, We put A = 0, B = C = 1 X = 0 .1.1 = 1
(a) A (b) A + B ∴ A = 0, B = 1, C = 1
(c) A + B (d) A ⋅ B 165. The output Y in the circuit below is always '1'
when-
KVS WET 2017
Ans. (a) : A + AB + ABC + ABCD
A + AB + ABC 1 + D( )
A + AB + ABC
A + AB (1 + C ) (a) two or more of the inputs P, Q, R are '0'
(b) two or more of the inputs P, Q, R are '1'
A + AB (c) any odd number of the inputs P, Q, R is '0'
(
A 1+ B ) (d) any odd number of the inputs P, Q, R is '1'
BSNL TTA 29.09.2016, 10 AM
=A
Ans : (b)
163. The open collector output of two 2- input
NAND gates are connected to a common pull-
up resister. If the inputs of the gates are A, B
and C, D respectively, the output is equal to -
(a) A.B.C.D (b) A.B + C.D
(c) A.B + C.D (d) A.B.C.D.
Mizoram PSC IOF 2019, Paper-III
Electronics-II 824 YCT
From the fig, we can see that, 170. Logic expressions can be simplified by using-
Y = PQ.QR.PR (a) Boolean algebra method
(b) Karnaugh-map method
Y = PQ + QR + PR (By Demorgon's law) (c) Tabulation method
Y = PQ + QR + PR (d) Any of the these
So, To be Y = 1 when two or more of the I/Ps P,Q,R are 1. BSNL TTA 27.09.2016, 3 PM
166. The parity bit is added for_____ purpose BSNL TTA 21.02.2016
(a) Coding (b) Indexing Ans : (d) Logic expressions can be simplified by using
(c) Error Correction (d) Controlling following method-
BSNL TTA 29.09.2016, 10 AM • Boolean algebra method
Ans : (c) A parity bit is a check bit, which is added to a • Karnaugh-map method which is known as K-map
block of data for error detection purpose. It is used to • Tabular method or Quine-McCluskey method.
validate the integrity of the data. The value of the parity 171. An AND circuit-
bit is assigned either 0 or 1 that makes the number of 1s (a) Is a memory circuit
in the message block either even or odd depending upon (b) Gives an output when all input signals are
the type of parity. present simultaneously
167. Digital circuit can be made by the repeated use (c) Is a negative OR circuit
of (d) Is a linear circuit
(a) OR gates (b) NOT gates BSNL TTA 27.09.2016, 3 PM
(c) NAND gates (d) None of these Ans : (b) According to truth table in AND gate if
BSNL TTA 29.09.2016, 10 AM both input are high then the output will be high and
Ans : (c) NAND and NOR gate is called universal gate in other condition output will be low.
because all other logic gates such as AND, OR and Truth table
NOT can be constructed from various combinations of A B Y=AB
NAND gates. Thus, any digital circuit can be made by 0 0 0
appropriate repetitive use of NAND gate.
0 1 0
168. The K-map for a boolean function is shown in 1 0 0
the figure. The number of essential prime 1 1 1
implicates for this function is-
172. In which logic gate, the output is HIGH when
all the inputs are LOW?
(a) AND (b) OR
(c) NOR (d) NAND
BSNL TTA 27.09.2016, 3 PM
Ans : (c) In logic gate, the output is HIGH when all the
inputs are LOW is NOR gate.
(a) 4 (b) 5
(c) 6 (d) 8
BSNL TTA 27.09.2016, 3 PM
Ans : (a) Y = ACD + CAB + ABC + BCD

By analyze NOR Gate truth table high output and low

input. So, option (c) is correct.
173. Number of min terms that a truth table of n
The number of essential prime implicates = 4 variables has
169. AND operation of (79)10 and (– 56)10 result in- (a) n2 (b) (n–1)2
n
(a) 50 H (b) 48 H (c) 2 –1 (d) 2n
(c) 42 H (d) 08 H JPSC AE 10.04.2021, Paper-I
n
BSNL TTA 27.09.2016, 3 PM Ans. (d) : For n-binary variables have 2 possible
Ans : (b) (79)10 = (1001111)2 combinations and each of these possible combination is
(–56)10 = (1111000)2 called minterm or sum of product (SOP) form."
↓ "Maxterm" is the complement of corresponding
Shows negative sign "Minterm" i.e. M = m .
174. A NAND gate has inputs A and B. Its output is
connected to both of the inputs of another
NAND gate. An equivalent gate for these two
NAND gates is
(a) AND gate (b) OR gate
(c) NOR gate (d) XOR gate
JPSC AE 10.04.2021, Paper-I
Electronics-II 825 YCT
Ans. (a) : 177. The truth-table for 2-input XOR gate is given
by _____.

Hence if the output of NAND is connected to both input

of another NAND gate. Then whole circuit is an
equivalent of AND gate.
175. A bulb in a staircase has two switches, one
switch being at the ground floor and the other
one at first floor. The bulb can be turn ON and
also turned OFF by any one of the switches
irrespective of the state of other switch. The
logic of switching of the bulb resembles
(a) An AND gate (b) An OR gate
(c) A X-OR gate (d) A NAND gate
JPSC AE 10.04.2021, Paper II
ISRO TA 2016
Ans. (c) : From the EX-OR gate truth table it is clear
that the bulb can be turned ON and also can be turned
OFF by any one of the switches irrespective of the state
of the other switch.
Y=A⊕B
Ex-OR gate truth table-
A B Y =A⊕B
0 0 0
0 1 1
1 0 1
1 1 0
176. Determine the output expression 'Y' for the
circuit shown is Fig.

Vizag Steel MT 13.12.2020

Ans. (b) : XOR gate states for the Exclusive OR gate.
Symbol is ⊕
Let the input A and B
Then A ⊕ B = A ' B + AB '

(a) Y = ABCD (b) Y =A(B+CD)

(c) Y = A + B +C +D (d) Y = A + BCD
Vizag Steel MT 13.12.2020
Ans. (b) :

178. According to Boolean algebra and switching

Y = A ( B + CD ) functions. Match the following:
Expression Simplification/Result
Electronics-II 826 YCT
 (A)
( x + y )( x + y ) (L) 1
Ans. (d) :

( x + y)( x + y)
(B) Complement of (M) y

( ) ( )
 xy x   xy y 
 
(C) ( xyz ) + ( xy ) + ( xyz ) (N) 0

( )
(D) x y + z + z + xy + wz (O) x + y + z + w
(P) x + y + z
(a) A-L; B-N; C-M; D-O
(b) A-L; B-N; C-O; D-P
(c) A-N; B-M; C-O; D-P
(d) A-N; B-L; C-M; D-P
TSPSC Manager (Engg.)HMWSSB 2020
Ans. (d) : (A) (x + y) (x + y) (x + y) (x + y)
(x + x y + yx + yy) (xx + xy + yx + yy) Thus if the output of logic gate is one when all the its
Y = (x + xy + yx) (x + xy + yx + 0) input are at logic 0, then gate is either a NOR or an EX-
Truth table NOR gate.
x y Y 180. Hamming code is capable of
0 0 0 (a) Only detects single bit error
0 1 0 (b) Only corrects single bit error
1 0 0 (c) Detects and corrects single bit error
1 1 0 (d) None of the above
UPPSC AE 13.12.2020, Paper-II
Hence Y = 0
Ans. (c) : Hamming code is a block code that is capable
( )( )
(B) F(x) = xyx xyy = (x + y)x + (x + y)y of detecting up to two simultaneous bit errors and
correcting single bit errors. Hamming code for single
= (xx + yx) + (xy + yy) error correction includes two parts, encoding at the
sender's end and decoding at receiver's end.
(
= yx + xy = y + x + x + y ) ( ) ( )
181. The complement of  A.B + C .D + E  .Fis
 
(
= x+x + y+y ) ( )
F(x) = 1  ( )
(a)  A + B .C + D.E  + F


(C) F = xyz + xy + xyz  ( )

(b)  A + B .C + D + E  .F

(
= xy z + z + xy ) ( )
(c)  A + B .C + D  .E + F
 
= xy + xy = y x + x ( ) (d) 
 ( )
A + B .C + D  .E + F

F=y UPPSC AE 13.12.2020, Paper-II
Ans. (c) :
(D) F (x) = xy + z + z + xy + wz
( )
 A.B + C .D + E  .F
 
F = xy z + z + xy + wz
Complement of given above function:
( )
F = x + y z + xy + wz + z
 ( )
=  A.B + C .D + E  .F

= (x+y) z + xy + z(w + 1)
= (x + y) z + xy + z = ( A.B + C ) .D + E  + F
 
F= x+y+z
= ( A.B + C ) .D .E + F
179. The output of logic gate is 1 when all of its  
input are at logic 0. The gate is either = ( A.B + C ) + D  .E + F
(a) a NAND or an EX-OR  
(b) an OR or an EX-NOR
(c) an AND or an EX-OR  ( )
=  A.B .C + D  .E + F

(d) a NOR or an EX-NOR
UPPSC AE 13.12.2020, Paper-II ( )
=  A + B .C + D  .E + F
 
Electronics-II 827 YCT
182. A combination circuit has inputs A, B and C, Ans. (d) : Truth table of exclusive NOR gate.
its K-map is given below. The output of circuit
is given by A B Output
0 0 1
0 1 0
1 0 0
1 1 1
(a) ( AB + AB ) C (b) ( AB + AB ) C Option (a) xy + x y = x ⊙ y
Option (b) x ⊕ y = x y + xy
(c) ABC (d) A ⊕ B ⊕ C
= x y + xy = x ⊙ y
UPPSC AE 13.12.2020, Paper-II
Option (c) x ⊕ y = xy + x y = xy + x y = x ⊙ y
Ans. (d) : A combination circuit has input A, B and C
its K-map is given below- Option (d) x ⊕ y = x y + x y = xy + xy = x ⊕ y
So, option (d) is NOT represent exclusive NOR of x and y.
185.
Inputs Outputs
X Y Z
0 0 0
The output of circuit is given by- 0 1 1
Y = ABC + ABC + ABC + ABC 1 0 1
= ( AB + AB ) C + ( AB + AB ) C 1 1 0
Observe the given table. The truth table
= ( A ⊕ B) C + ( A ⊙ B) C represents…………..gate?
(a) OR (b) AND
(
= ( A ⊕ B) C + A ⊕ B C) (c) NAND (d) XOR
LMRC SCTO 17.04.2021
output = A ⊕ B ⊕ C SSC JE 26.09.2019, Shift-II
Key point- Ans. (d) : XOR In XOR gate when both input is 0 or 1
A⊕ B⊕C = A⊙B⊙C the result will be 0.
A⊕B = A⊙B
The karnaugh map(k-map) is a method of simplifying
Boolean algegra expression. XOR gate
183. The minimum number of 2-input NAND gates C = A⊕B, A.B + A.B
required to realize the logic function
186. If all the inputs of a NAND gate are connected
Y = AB + AB is together, then the resulting circuit is _____.
(a) 5 (b) 3 (a) EX-OR gate (b) NOT gate
(c) 6 (d) 4 (c) AND gate (d) OR gate
UPPSC AE 13.12.2020, Paper-II DGVCL JE 0.5.01.2021, Shift-II
Ans. (d) : Given logic function: Ans. (b) : We know that-
output of NAND gate
Y = AB + AB
= A⊕B Y = A.B
When inputs are connected together i.e. A = B
Y = A.A
Y = A this is the output of NOT gate.
187. NAND operation with x and y inputs is
(a) x + y (b) x + y
(c) ( x + y)( x + y) (d) x + y
RPSC ACF & FRO 23.02.2021
The minimum number of 2-input NAND gates required Ans. (a) :
to realize the logic function Y = AB + AB is 4.
184. Which of the following expressions does NOT
represent exclusive NOR of x and y?
(a) xy + x y (b) x ⊕ y Boolean algebraic Theorems
(c) x ⊕ y (d) x ⊕ y (1) A.B.C........... = A + B + C .............
UPPSC AE 13.12.2020, Paper-II (2) A + B + C + .......... = A.B.C............
Electronics-II 828 YCT
188. The operation of logical gate which is Ans. (c) : NAND GATE-
commutative but not associative is
(a) NOR (b) EX-OR
(c) OR (d) AND
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II Truth table
Ans. (a) : The NAND and NOR functions are the
complements of AND and OR functions respectively. A B Y
They are commutative but not associative. So there 0 0 1
functions can not be extended to multiple input 0 1 1
variables very easily.
189. Which of the following logical expressions is 1 0 1
incorrect? 1 1 0
(a) A+B=AB (b) 1 + A = 1
192. The logic performed by the circuit shown
(c) AB + A = B (d) AB=A+B
below is-
LMRC (SCTO) 17.04.2021
Ans. (c) : A + B = AB (from De-Morgon theorem)
1+A=1
AB = A + B
AB + A = A(B+1)
=A (a) NAND (b) AND
So, (AB + A) = B is wrong Answer (c) OR (d) None of these
190. What is the simplified logical expression of the BSNL TTA 26.09.2016, 3 PM
given diagram?
Ans : (b) Given circuit is-

According to the circuit-

(a) Q = ABC + A(B + C)

(
Output ( Y ) = A + B )
(b) Q = AB + AB + AC = A.B
(c) Q = ABC + AB + AC = A.B
(d) Q = ABC + AB + AC Y = A.B
Ans. (d) : Hence, logic performed by circuit is AND gate.
193. _________ gate is called as a complement of
AND gate.
(a) NOT (b) NOR
(c) NAND (d) OR
Vizag Steel JET 27.10.2018
Ans. (c) : NAND gate is the complement of AND gate.
We can make an NAND gate by adding NOT gate in
(
Q = ABC + A B + C ) the AND gate

= ABC + AB + AC
191. Which one of the following gate-symbol
combinations is false?

UKPSC JE 2013, PAPER-I

Electronics-II 829 YCT
194. Indentify the Boolean function for the given Ans. (c) : 'NAND' logic Gate- Logic NAND gates are
switching circuit. used to implement the functionality of any logic gates
and are available in standard I.C. packages such as the
very common TTL 74LS00 quadruple 2-input NAND
Gates.
Input Output
A B Y = AB
0 0 1
0 1 1
(a) ABC (b) (A+B)C 1 0 1
(c) A(B+C) (d) A+B+C 1 1 0
JMRC JE 2021
198. Boolean expression of three input AND gate is-
Ans. (c) : Given switching circuit: (a) A.B.C = D (b) A+B+C = D
(c) A.B.C = D (d) A + B + C = D
Ans. (a) Boolean expression of three input AND gate is,
A.B.C =D

The Boolean function can be obtained by consider B

and C as OR gate and we get Truth table:
Y = A(B + C)
195.
Input Output
A B A+B
0 0 1
0 1 0
1 0 0
1 1 0
Which of the following type of logic gate
represent the above truth table?
(a) NOT gate (b) NAND gate
(c) NOR gate (d) OR gate
PGCIL SR- II, 22.08.2021
b
Ans. (c) :
AND gate is also known as decoding circuit.
199. The simplified version of the expression X = (A
+ B).(A + C) is
(a) A + AB (b) A + BC
(c) AB + BC + CA (d) B + AC
UPRVUNL JE -21.10.2021,9 am-12 pm
Ans. (b) : X = ( A + B ) . ( A + C )
= AA + AC + AB + BC
= A + AC + AB + BC ∵ X.X = X
= A (1 + C ) + AB + BC ∵1 + X = 1
196. The voltage levels for a negative logic system :
(a) Must necessarily be positive = A + AB + BC
(b) Must necessarily be negative = A (1 + B ) + BC
(c) Could be negative or positive
(d) Must necessarily be either zero or –5 V X = A + BC
(RRB SSE (Shift-III), 01.09.2015) 200. What would be yielded after simplifying the
Ans : (c) The voltage levels for a negative logic system following Boolean expression:
could be negative or positive.
Bit 1 = Logic low ( ) ( )
Y = A+ B+C + B+C
Bit 0 = Logic High
197. Which of the following logic gates can be used ( ) ( )
(a) Y = ABC + B C
to implement the functionality of any logic
gate? ( )( )
(b) Y = A + B + C B + C
(a) XOR (b) XNOR (c) Y = 0
(c) NAND (d) AND (d) Y = 1
PSPCL JE 2019, Shift-II MPPKVVCL JE-2018
Electronics-II 830 YCT
 (b) an encoder circuit with enable input
( ) (
Ans. (c) : Y = A + B + C + B + C ) (c) a decoder circuit with enable input
(d) a decoder circuit
Y = ( A + B + C )(
. B + C) JMRC JE 2021

( )( ) ( ∵ B = B)
Ans. (c) : Demultiplexer circuit:- A Demultiplexer
Y = A.B.C B.C circuit is a 'decoder circuit' with enable input. It receives
information at one line and transmits it on one of 2n
( )( )
Y = A.B.C B.C possible output lines.
5. Which of the following is not a sequential
Y= 0 ∵ BB = 0 
  circuit?
(a) Flip flop (b) Counter
III. Combinational Circuit (c) Shift register (d) Multiplexer
MPPKVVCL (Jabalpur) JE -2018
1. _______converts binary-coded information to Ans. (d) :
unique outputs such as decimal, octal digits, Combinational circuit Sequential circuit
etc. Present output depends Present output depends on
(a) Decoder (b) Demultiplexing on present input only present input as well as
(c) Multiplexing (d) Encoder previous output
UPPCL JE- 07.09.2021, Shift-II No feedback is present Feedback is present
Ans. (a) : A decoder have many inputs and many No memory is present memory is present
outputs, it is a combinational circuit and decoder is used e.g. half adder, full e.g. flip-flop, counter,
to convert a particular code such as - adder, multiplexer, register
i. Binary to octal encoder, decoder.
ii. Binary to Hexa decimal 6. A combinational circuit is the one in which the
iii. BCD to decimal output depends on the :
iv. BCD to 7 segment. (a) Present input combination and the previous
2. In half adder, the total number of inputs and output
outputs are: (b) Present and the previous output
(a) 1, 2 (b) 2, 1 (c) Input combination at that time
(c) 3, 2 (d) 2, 2 (d) Present input combination and the previous
UPPCL JE- 07.09.2021, Shift-I input combination
Ans. (d) : PGCIL Diploma Trainee 14.11.2018
Ans : (c) A combinational circuit is a memory less
device. Hence its output value depends upon the present
value of input combination at that time.
7. How many input lines are there in a ‘Full
Adder’?
(a) 2 (b) 4
(c) 1 (d) 3
PSPCL JE 2019, Shift-I
Input Output Ans. (d) : A full adder circuit is central to most
A B Sum Carry digital circuit that perform addition. It is so called
0 0 0 0 because it adds together two binary digits, plus a carry
0 1 1 0 in digits to produce a sum and carry out digit.
1 0 1 0 Therefore it has three input lines and two output.
1 1 0 1
3. A frequency division multiplexing system is
used to multiplex 24 independent voice signals.
Single sideband modulation is used for the
transmission. Each voice signal is allotted a
bandwidth of 4 kHz. What is the overall Truth table-
transmission bandwidth of the channel? Input Output
(a) 4 kHz (b) 6 kHz A B Cin Sum Cout
(c) 24 kHz (d) 96 kHz 0 0 0 0 0
ESE (Pre) 18.07.2021 0 0 1 1 0
Ans. (d) : Number of independent voice signal = 24 0 1 0 1 0
Band width of each signal = 4kHz 0 1 1 0 1
Transmission Band width = 24×4 1 0 0 1 0
= 96 kHz 1 0 1 0 1
4. Demultiplexer circuit is: 1 1 0 0 1
(a) an encoder circuit 1 1 1 1 1
Electronics-II 831 YCT
8. Which of the following is a combinational logic 12. Identify the IC-74147
circuit designed to switch one of several input (a) BCD to decimal Decoder
lines to a single common output line? (b) Octal to Binary priority Encoder
(a) Flip-flop (b) Full adder (c) BCD to 7- Segment Decoder
(c) Multiplexer (d) Demultiplexer (d) Decimal to BCD priority Encoder
PSPCL JE 2019, Shift-II UPPCL JE 27.11.2019, Shift-II
Ans. (c) : Ans. (d) : IC-74147 is a Decimal to BCD priority
S1 S0 Y Encoder.
0 0 I0 13. The logic function implemented by the
0 1 I1 multiplexer circuit below is (ground implies a
1 0 I2 logic "o")
1 1 I3

Y = output = S1 S0 I0 + S1S0 I1 + S1 S0 I2 + S1S0 I3

9. In a half adder, the carry output is high if the (a) F= AND (P,Q) (b) F=OR(P,Q)
inputs are: (c) F= XNOR (P,Q) (d) F= XOR (P,Q)
(a) 0, 1 (b) 0, 0 ISRO TA 2017
(c) 1, 1 (d) 1, 0 Ans. (d) :
UPPCL JE 25.11.2019, Shift-I
Ans : (c) In a half adder, the carry output is high, if the
inputs are 1,1.

10. The combinational circuit to convert a given F = PQ × 0 + PQ ×1 + PQ × 1 + PQ × 0

decimal to binary number is………… F = PQ + PQ
(a) Encoder (b) ALU F= P⊕Q
(c) Decoder (d) MUX Using truth table-
NMRC JE 2019
Ans. (a) : Encoder is a combinational circuit. It P Q F
converts decimal to binary number. 0 0 0
11. The inputs of a Half Adder are A = 1, B = 1.
The outputs are connected to the select lines of 0 1 1
a 4 : 1 Multiplexer. What will be the output? 1 0 1
1 1 0
F = P⊕Q
14. The time delay in a look-ahead carry adder is
independent of
(a) Number of operands only
(b) Propagation delay only
adder (c) Number of bits in the operand only
(a) Y = I1 (b) Y = I3 (d) Bits in the operand, number of operands and
(c) Y = I0 (d) Y = I2 propagation delay
UPPCL JE 27.11.2019, Shift-II ESE 2019
Ans. (a) : Half adder S = AB + AB Ans. (c) : The Carry look-ahead adder calculates one or
more carry bits before the sum which reduces the wait
= 1 ×1 + 1 × 1 = 0 + 0 = 0 time to calculate the result of the larger value bits. The
Carry C = AB C = 1.1 = 1 adder with look ahead carry needs additional hardware
S1 = S = 0 S0 = C = 1 thus the time delay in a look ahead carry adder is
independent of number of bits in operand only.
Y = S1 S0 .I0 + S1S0 I1 + S1 S0 I2 + S1 .S0 I3
15. Half adder is a logic circuit that accepts........
Y = 0.1.I0 + 1.1.I1 + 0.1.I2 + 0.1I3 single bit inputs.
Y = 0 + I1 + 0 + 0 (a) Two (b) Four
(c) Three (d) Five
Y = I1 UPPCL JE 25.11.2019, Shift-II
Electronics-II 832 YCT
Ans. (a) : Half adder is a logic circuit that accepts two F = A.B + A + B
single bit inputs A and B, which add input digits and
generates a carry and a sum. The full adder circuits have F = A.B. + A.B
three inputs. Which add three input numbers and F = A.B + AB
generates a carry and sum.
• By using one Ex-OR gate and AND gate we can (
F=B A+A )
easily design a half adder. F=B (∵ A + A = 1)
19. It is required to construct a 2n-to-1 multiplexer
by using 2-to-1 multiplexers only. How many of
2-to-1 multiplexers are needed?
(a) n (b) 22n
(c) 2n-1 (d) 2 n − 1
ESE 2002
16. A 3 to-8 decoder is shown below:
All the output lines of the chip will be high, Ans. (d) : Let the number of (2-to-1) multiplexer
when all the inputs 1,2 and 3 required for (2n-to-1) multiplexer is N
2 n  2n / 2 
Then, N = +  + .... + 1
2  2 
2n 2n
= + 2 + ....... + 1
2 2
= 2 n −1 + 2n − 2 + ...1
 2n − 1 
(a) are high, and G1, G2 are low = 1 
(b) are high, and G1 is low, G2 is high  2 −1 
n
(c) are high and G1, G2 are high N = 2 –1
(d) are high, and G1 is high, G2 is low 20. Multiplexer is also known as
ESE 2002 (a) counter (b) decoder
Ans. (b) : In 3 to 8 decoder, when all the input lines are (c) data selector (d) none of these
high then all output lines of chip will be high because BSNL TTA (JE) 25.09.2016, Shift-I
outputs are active low. Ans. (c) : A multiplexer is also known as a data
So, all the output lines of chip will be high, when chip selector. It converts the 2n input to a single output with
will be disabled. help of n→select line. Multiplexer converts parallel data
When G1 = 0, G2 = 1 into serial data.
17. In a combinational circuit, which is used to
send more data through a single transmission?
(a) Encoder (b) De-multiplexer
(c) Multiplexer (d) Decoder
UPPCL JE 11.02.2018, Shift-I 21. The number of 4-line-to-16-line decoders
Ans : (c) In a combinational circuit, multiplexer is used required to make an 8-line-to-256-line decoder
to send more data through the single transmission. is
Multiplexer have many input and only one output. It is a (a) 16 (b) 17
data selector circuit. (c) 32 (d) 64
18. The output expression ‘F’ for the BSNL TTA (JE) 2013
combinational logic circuit shown in Fig. is Ans. : (b) Number of 4 × 16 MUX required
given by 256 16
= + = 16 + 1 = 17
16 16
22. The full adder adds the Kth bits of two numbers
to the
(a) Difference of the previous bits
(a) F = B (b) F = B (b) Sum of all previous bits
(c) Carry from (K-1)th bit
(c) F = A (d) F = A
(d) Sum of previous bit
DGVCL JE 06.01.2021, Shift-III
BSNL TTA (JE) 2013
Ans. (b) : Given circuit diagram-
Ans. : (c) Full adder adds the Kth bits of two numbers to
the carry from (K-1)th bit.
23. The function of a multiplexer is
(a) To select 1 out of N input data sourced & to
transmit into a single channel
(b) To transmit data in N lines
Electronics-II 833 YCT
 (c) Serial to parallel conversion Ans. : (c) To build half adder.
(d) To decode information One Ex-OR gate and one AND gate is required
BSNL TTA (JE) 14.07.2013 A B Sum Carry
Ans. : (a) The function of multiplexer is to select one 0 0 0 0
out of N input signal and transmit it into single channel.
0 1 1 0
It is also known as data selector and also known as
parallel to serial data converter. 1 0 1 0
1 1 0 1

24. Consider the following circuit:

26.
A tachometer encoder has:
(a) one output (b) two outputs
(c) three outputs (d) none of these
BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (a) A tachometer encoder has one output. A
tachometer or Rotatary pulse generator is an
electromagnetic device that converts mechanical
Which one of the following gives the function rotations into electrical pulses.
implemented by the MUX-based digital
circuit?
(a) f = C 2 .C1.S + C 2 .C1. A + B ( )
(b) f = C 2 .C1 + C 2 .C1 + C 2 .C1.S + C 2 .C1.AB
(c) f = AB + S
(d) f = C 2 .C1 + C 2 .C1.S + C 2 .C1.AB
ESE 2002
Ans. (d) :

27. Multiplexer converts-

(a) Multiple inputs to single output
(b) Single input to multiple outputs
(c) Both multiple inputs to single output &
single input to multiple outputs
Output of the given MUX, (d) None of these
f = C 2 C1I0 + C 2 C1I1 + C 2 C1I 2 + C 2 C1I3 BSNL TTA 26.09.2016, 10 AM

( )
f = C1 C 2 .1 + C1 C 2 A + B + C 2 C1 .S + C1C 2 .0
Ans. (a) : In electronics, a multiplexer or mux also
known as a data selector. It is a device that selects
= C C + C C ( AB ) + C C S
2 1 2 1 2 1
between several analog or digital input signals and
forward the selected input to a single output line.
f = C C + C C S + C C ( AB )
2 1 2 1 2 1

25. The gates required to build a half adder are

(a) Ex-OR gate and NOR gate
(b) Ex-OR gate and OR gate
(c) Ex-OR gate and AND gate
(d) four NOT gates
UPPCL JE 11.02.2018, Shift-I
BSNL TTA (JE) 14.07.2013
Electronics-II 834 YCT
28. What are the output bits S(sum ) and C (carry) (c) Parity checking
of a half adder having inputs A = 1 and B = 1? (d) Data selector
S C BSNL TTA 28.09.2016, 10 AM
(a) 1 1 Ans. (d) : Multiplexer is a circuit that have multiple input
(b) 1 0 and one output. This is a data selector circuit. Any input
(c) 0 1 can be received at the output by using only the signal in it.
(d) 0 0 The output of the circuit (which is a selector input)
ESE 2003 depends on the digital code used at the control terminals.
Ans. (c) : Half adder = 1 XOR gate + 1 AND gate 32. For a four variable K-Map, if each cell is
assigned one integer value in range 0-15 then
which is the cells adjacent to the cell
corresponding to decimal value 7?
(a) 3,5,6 and 8 (b) 3,5,10 and 11
(c) 3,5,6 and 15 (d) 4,6,8 and 15
ESE 2002
Ans. (c) : In K-map, We use gray codes to represent the
numbers.
` K-map for 4-variable -

From the given K-map, 3, 5, 6 and 15 cells adjacent to

Hence, at A=B=1 SUM = 0 the cell corresponding to decimal value 7.
CARRY (C) = 1 33. Which of the following is not a combinational
29. How many full adders are needed to construct logic circuit ?
an m-bit parallel adder? (a) Half adder (b) Counter
(a) m–1 (b) m/2 (c) Full adder (d) Full substracter
(c) m+2 (d) m GSSSB AAE 2021
BSNL TTA 26.09.2016, 10 AM Ans. (b) : Counter is an example of sequential circuit. It
Ans. (a) : We need adder for every bit. So we should may be categorized as Asynchronous (ripple) and
need m-bit adders. A full adder adds a carry bit to two synchronous counter. Half adder, full adder, and Full
inputs and produces an output and a carry. But the most substracter are example of combinational circuit. Here
significant bits can use a half adder which differs from output depends upon the present value of input only.
the full adder as in that. It has no carry input, so we 34. The device which selects one of the several
need (m−1) full adders in m-bit parallel adder. inputs and transmits it to a single output is?
30. The full adder can be made out of– (a) Decoder (b) Multiplexer
(a) Two Half-adders (c) De-multiplexer (d) Counter
(b) Two Half-adders and a NOT gate BSNL TTA 28.09.2016, 3 PM
(c) Two Half-adders and an AND gate Ans. (b) Multiplexer is a combinational logic circuit.
(d) Two Half-adders and an OR gate Multiplexer (MUX) is a device which selects one of
BSNL TTA 28.09.2016, 10 AM many inputs to a single output. The selection is done by
BSNL TTA (JE) 14.07.2013 using an input address.
Ans. (d) : The full adder can be made out of two half- • MUX is called as a data selector.
adder and one OR gate. • It has 'n' select lines to select 2n input and contact that
Half adders have only two input terminals. If the particular select input to '1' output.
numbers to be added are multi-bit numbers, then there is • It is also called as 2n×1 or N×1
no provision to add the carry received in bits in the n= number of select lines
order of full adders are made by using two half adders N= number of input, N=2n
and OR gate.

31. One application of a digital multiplexer is to

facilitate–
(a) Serial-to-parallel conversion
(b) Data generation • Multiplexer is also used as a universal logic circuit.
Electronics-II 835 YCT
35. The number of 4:1 MUX required to make Ans. (d) : The 74xx157A is a Quad 2-input multiplexer
64:1 MUX is- which selects four bit of data from two sources under
(a) 16 (b) 64 the control of common select inputs. The four outputs
(c) 20 (d) 21 present the selected data in the true (non-inverted) form.
BSNL TTA 21.02.2016 41. Which of the following circuit can parallel to
BSNL TTA 26.09.2016, 3:00 PM serial convertor :
Ans : (d) The number of 4:1 MUX required to make (a) digital counter (b) decoder
64:1 MUX is 21. (c) demultiplexer (d) multiplexer
MUX is a combinational logic circuit design to switch BSNL TTA 25.09.2016, 3:00 PM
one of several input lines through to a single common BSNL TTA 28.09.2016, 10:00 AM
output line by the application of a control signal. Ans : (d) Multiplexer can be used to parallel to serial
Number of 4:1 MUX can be calculated as- converter. Multiplexer converts 2n input signals into
64 16 4 single output with the help of select lines. Multiplexer is
= 16 , =4, =1
4 4 4 also called data selector.
Total = 16 + 4 + 1 = 21 42. Half–adder is also known as :
36. An encoder has ____input lines ______output (a) AND circuit (b) NAND circuit
lines. (c) NOR circuit (d) EX–OR circuit
(a) 2n, n (b) 2n, 2 BSNL TTA 25.09.2016, 3:00 PM
n
(c) n, 2 (d) n, n2 BSNL TTA 29.09.2016, 3:00 PM
MPPEB Sub. Engineer 0.8.07.2017 Shift-I Ans : (d) Half adder is also known as Ex-OR circuit.
Ans. (a) : For n-bit data, An encoder has 2n input lines Half adder is used to add two bit binary number.
and n output lines. It is just the reverse case of Decoder. A B (S) SUM (A+B) (C) carry (AB)
37. The logic function A+BC is the simplified form 0 0 0 0
of which of the following? 0 1 1 0
1 0 1 0
(a) AB+BC (b) AB + ABC 1 1 0 1
(c) ABC (d) ( A + B )( A + C )
ESE 2004
Ans. (d) : A+BC = A(1+B)+BC
= A+AB+BC
= A(1+C)+AB+BC
= A+AC+AB+BC
= A.A+AC+AB+BC 43. Which of the following logic circuits accepts
= A(A+C)+B(A+C) two binary digits on its inputs and produce :
= (A+B)(A+C) (a) full adder (b) half adder
(c) decoder (d) multiplexer
38. A ______is a multiple-input, multiple-output BSNL TTA 25.09.2016, 3:00 P.M.
logic circuit which converts coded inputs into
coded outputs, where the input and output code Ans : (b) Half adder is used to add two binary digits
are different. and produces two binary digits in the form of sum &
(a) decoder (b) demultiplexer carry.
(c) multiplexer (d) encoder Sum = A ⊕ B = AB + AB
MPPEB Sub. Engineer 0.8.07.2017 Shift-I carry = AB
Ans. (a) : A decoder is a multiple- input, multiple- 44. A demultiplexer can be used to realize a
output logic combinational circuit which converts coded (a) counter
inputs into coded outputs. It also has an enable input (b) shift register
line. (c) combinational circuit
39. The IC ________can be used as 1 to 16 (d) display system
demultiplexer. BSNL TTA 29.09.2016, 10 AM
(a) 74×151 (b) 74×153 Ans : (c) A demultiplexer can be used to realize a
(c) 74×152 (d) 74×154 combinational circuit. The demultiplexer is a
MPPEB Sub. Engineer 0.8.07.2017 Shift-I combinational logic circuit designed to switch one
Ans. (d) : IC 74×154 is used to the implementation of 1 common input line to one of several separate output
to 16 demultiplexer , whose output is inverted input. line. The distributor, known more commonly as a
demultiplexer or "Demux".
40. The 74xx157 is a _________which selects four
bits of data from two sources under the control
of a common select input.
(a) 8 to 1 multiplexer
(b) dual 4 to 1 multiplexer
(c) 32 to 1 multiplexer
(d) quad 2-input multiplexer
MPPEB Sub. Engineer 0.8.07.2017 Shift-I
Electronics-II 836 YCT
45. A de-multiplexer is used to 49. Which of the following is analogous to
(a) route the data from single input to one of multiplexer?
many outputs (a) Data selector (b) Data multiplexer
(b) select data from several inputs and route it to (c) Data filter (d) All of the above
single output JPSC AE 10.04.2021, Paper II
(c) perform serial to parallel conversion Ans. (a) : Multiplexer is analogous to data selector
(d) All of these which is used to select data from multiple input data. A
BSNL TTA 29.09.2016, 10 AM multiplexer with n select line has 2n input line and 1
Ans : (a) A demultiplexer can be used to realize a output line.
combinational circuit. the demultiplexer is a
combinational logic circuit designed to switch one
common input line to one of several separate output
line. The distributor, known more commonly as a
demultiplexer or "Demux".

50. For the combinational logic circuit shown in

Fig. the required inputs A, B, C and D to make
the output Y = 1 are, respectively,

46. Full subtractor can be realized by using _____.

(a) two half subtractors
(b) two half subtractors and a NOT gate
(c) two half subtractors and an AND gate
(d) two half subtractors and a OR gate (a) A = 0, B = 1, C = 0 and D = 1
GSECL 2020 Shift-I (b) A = 1, B = 0, C = 1 and D = 1
Ans. (d) : Full subtractor–Full subtractor is an (c) A = 1, B = 0, C = 0 and D = 1
electronic device or logic circuit which performs (d) A = 1, B = 1, C = 0 and D = 0
subtraction of two binary digits Vizag Steel MT 13.12.2020
Ans. (c) :

So full subtractor can be realised by 2 half subractor and

1 OR gate. ( ) ( ) (
Y = A. B + C + B + C .D = A.BC + BCD = A + D BC )
47. A half adder performs Put the value of -
(a) Decimal addition for 2 decimal inputs A = 1, B = 0, C = 0 , D = 1
(b) Binary addition for 2 binary inputs
(c) Decimal addition for 2 binary inputs
(d) Binary addition for 2 decimal inputs
JPSC AE 10.04.2021, Paper-I
Ans. (b) : A logic circuit for the addition of two binary
numbers is referred to as an "HALF ADDER". A half
adder is a logical circuit that performs an addition
operation of two binary digits. The half adder produces 51. An n bit parallel adder consist of
a sum and a carry value and both are binary digits.
n
48. Multiplexer work with (a) full adder (b) 2n half adder
(a) Analog signal 2
(b) Digital signal (c) n full adder (d) (n + 1) full adder
(c) Both analog and digital signals RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
(d) None of the above Ans. (c) : Parallel adder is nothing but a cascade of
JPSC AE 10.04.2021, Paper II several full adders. The number of full adders used will
Ans. (c) : A multiplexer can work with both analog and depends on the number of bits in the binary digits which
digital signal but the output of MUX always in digital required to be added.
form. Multiplexer can handle two type of data i.e. An n bit parallel adder consist of n full adder-
analog and digital. For analog application, multiplexer In parallel adder n full adder or {(n–1) full adder and
are built using relay and transistor switch. For digital 1 Half Adder} or {(2n–1) Half Adder and (n–1) OR
application they are build from standards logic gates. gate} are required to add two n–bit number.

Electronics-II 837 YCT

52. A combinational circuit consist of 2. A D-flip-flop can be made from a J-K flip-flop
(a) Logic elements only by making
(b) Memory elements only (a) J = K (b) J = K =1
(c) Logic Gates and a memory element (c) J = 0, K = 1 (d) J = K
(d) None of these RPSC Lect.(Tech. Edu. Dept.)16.03.2021, Paper-II
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II CGPSC AE 15.01.2021
Ans. (a) : Combinational circuit- UPPSC AE 13.12.2020, Paper-II
Present output depends on present input only. ESE 2003
No feedback is present Ans. (d) : D-flip-flop is a flip-flop which provide a
No memory is present. delay equal to exactly one cycle of clock pulse.
e.g. comparator, half adder, mux, demux, If J = K is given in the J-K flip-flop then J-K flip-flop
decoder etc.
can be converted into D flip-flop.
53. A ________ arithmetic circuit adds two binary
digits, giving a sum bit and a carry bit.
(a) full-adder (b) half-subtractor
(c) half-adder (d) full-subtractor
UPPCL JE- 07.09.2021, Shift-II
Ans. (c) : A half - adder arithmetic circuit adds two
binary digits giving a sum bit and a carry bit.
5 NAND or 5 NOR gate are required to design the half J = D and K = D
adder D flip-flop is also known as "Transparent latch" because
Qn+1= D.
3. In D flip flop the present state is 1. What will
be the next state of output at the complement
end?
(a) 01 (b) 1
54. A digital multiplexer is an example of: (c) 0 (d) 11
(a) a very large-scale integration (VLSI) device JMRC JE 2021
(b) a medium-scale integration (MSI) device Ans. (c) : In 'D' flip-flop the present state is '1' then the
(c) a small-scale integration (SSI) device next state of output at the complement end is '0'
(d) a large-scale integration (LSI) device 4. The number of flip-flop required for
UPRVUNL JE -21.10.2021,9 am-12 pm constructing a mod-12 counter is:
Ans. (b) : A digital multiplexer is an example of a (a) 3 (b) 4
medium-scale integration (MSI) device. (c) 2 (d) 1
OPPSC AE 2021, Paper-II
IV. Sequential Circuits MPPKVVCL (Jabalpur) JE -2018
Ans. (b) : MOD -12
1. In the toggle mode, a JK flip-flop has ____. N ≤ 2n
(a) J = 0 and K = 0 (b) J = 0 and K = 1 n = Number of flip flops
(c) J = 1 and K = 0 (d) J = 1 and K = 1 N = Total number of state
DGVCL JE 06.01.2021, Shift-I
12 ≤ 2n
BIS TA (Lab) 2020
BSNL TTA 28.09.2016, 3:00 PM Hence number of flip-flops required (n) = 4
Ans. (d) : In the toggle mode, a JK flip-flop has J = 1 5. What will be the maximum possible time
and K = 1. The JK flip-flop is similar to the SR flip-flop required for change of state for a 4-bit
but there is no change in state when the J and K input synchronous counter using flip-flops with
are both low. propagation delay of 15ns each?
JK flip-flop- (a) 30 ns (b) 15 ns
(c) 45 ns (d) 60 ns
OPPSC AE 2021, Paper-II
BIS TA (Lab) 2020
Ans. (b) : Maximum possible time required for change
of state for a 4 bit synchronous counter using flip flop
with propagation delay of 15ns each is 15ns.
Propagation delay time -
Time required at which output come in high state from
low state is called propagation delay time.
In synchronous counter total required time is equal to
propagation delay of one clock.
Electronics-II 838 YCT
6. The Race around condition exists in J-K Flip
flop if- (
= AQ + BQ Q + AQ + BQ Q) ( )
(a) J=0, K=1 (b) J=1, K=0
(c) J=0, K=0 (d) J=1, K=1  (  )(
=  A + Q B + Q  Q + AQ )
Mizoram PSC IOF 2019, Paper - III
HPSSC JE 2018, Code - 387 (
= AQ + BQ Q + AQ )
BSNL TTA (JE) 2013
Ans. : (d) A race around condition is an undesirable = BQ + AQ
situation that occurs in J-K flip-flops attempts to Q(n+1) = AQ + BQ … (i)
perform two or more condition at the same time. The characteristic equation of JK flip flop,
If J = K=1 then output is toggle as long as J = K = 1 this Q n +1 = JQ + KQ … (ii)
condition is called race-around condition.
from equation (i) and (ii)
7. The number of flip-flop required in a decade
counter is A = J and B = K
(a) 2 (b) 3 11. If the present state is 0 and the next state is 1,
(c) 4 (d) 10 then:
BWSSB Code 198, 30.05.2017 (a) J = 1 & K = don't care
Karnataka PSC JE 2017 (b) J = & K = 1
HPSSC JE 2017 (Code - 580) (c) J = don't care & K = 1
Ans. (c) : The number of flip-flop required in a decade (d) J = 0 & K = 0
counter is 4 MPMKVVCL (Bhopal) JE 2018
because 24 = 16 Ans. (a) : If the present state is 0 and the next state is 1,
So, 4 flip-flops measure 0 to 15. then J =1 & K = don't care.
8. How many flip flops are required to design 12. A J-K flip-flop can be made from an S-R flip-
MOD-10 counter? flop by using two additional
(a) 2 (b) 3 (a) AND gates (b) OR gates
(c) 5 (d) 4 (c) NOT gates (d) NOR gates
GSECL 2020 Shift-I ESE-2008
Ans. (d) : For a MOD-10 counter, 10 < 24 Ans. (a) :
For a MOD-16 counter,16 = 24. So 4 flip-flops are
required. J - K Inputs Outputs S - R Inputs
9. How many J-K flip-flops are required to
achieve a frequency division of 8? J K Qn Qn+1 S R
(a) 1 (b) 2 0 0 0 0 0 X
(c) 3 (d) 4 0 0 1 1 X 0
MPPKVVCL JE-2018
Ans. (c) : 3-JK flip flop are required to achieve a 0 1 0 0 0 X
frequency division of 8. 0 1 1 0 0 1
2n = 8 (n = no of flip-flops)
n=3 1 0 0 1 1 0
10. What is represented by the digital circuit given 1 0 1 1 X 0
below? 1 1 0 1 1 0
1 1 1 0 0 1

(a)An SR flip-flop with A = S and B = R

(b)A JK flip-flop with A = K and B = J
(c)A JK flip-flop with A = J and B = K So, Two AND gates will be required to make JK flip
(d)An SR flip-flop with A = R and B = S flop from S-R flip flop.
ESE-2006, 2003 13. The expression of MOD number for a ripple
Ans. (c) : From the given circuit- counter with N flip-flop is-
T = AQ + BQ (a) N (b) 2N
The characteristic equation of T-flip flop- (c) 2N–1 (d) 2N-1
Q n +1 = T ⊕ Q Ans. (b) : MOD number of a ripple counter represents
the total number of states followed by it with N flip-
∵ X ⊕ Y = XY + XY  flops, the total possible number of states that could be
(
= AQ + BQ ⊕ Q ) 
QQ = 0
 followed is 2N. A ripple counter is an asynchronous
  counter.
Electronics-II 839 YCT
14. Which of the following is an example of a 18. The D-type flip-flop is a modified SR flip-flop
sequential circuit? with the addition of an inverter. What does the
(a) Register (b) Multiplexer letter D’ mean?
(c) Full Adder (d) Decoder (a) Delay (b) Detect
PSPCL JE 2019, Shift-I (c) Distributed (d) Diverted
Ans. (a) : Register is sequential logic circuit that can be PSPCL JE 2019, Shift-II
used for the storage or the transfer of binary data. An Ans. (a) : The D-type flip-flop is a modified SR flip-
electronic register is form of memory that uses a series flop with the addition of an inverter. In D-flip-flop
of flip-flops to store the individual bit of a binary word the letter 'D' means is 'delay'.
such as a byte (8 bits) of data. The length of the store CLK D Qn +1
binary word depends on the number of flip-flop that 0 X Qn
make up the register. 1 0 0
15. A ripple counter with n-flip flop can function 1 1 1
as a
n 19. Data can be changed from special code to
(a) n : 1 counter (b) : 2 counter
2 temporal code by using
n
(c) 2n : 1 counter (d) 2 : 1 counter (a) Shift Registers
Ans. (d) : Ripple counter with n flip-flop have 2n states (b) Counters
so it can function as 2n:1 counter. A ripple counter is an (c) Combinational Circuits
asynchronous counter. The MOD of the ripple counter (d) A/D converters
or asynchronous counter is 2n if n-flip-flop are used. HPSSSC JE 2018 Code -387
16. The number of flip-flops required in a counter Ans. (a) : Data can be changed from special code to
to count 35 pulses : temporal code by using shift registers. Shift Register is
(a) 4 (b) 5 a group of flip flops used to store multiple bits of data.
(c) 6 (d) 7 20. When both are inputs of J-K flip-flop cycle, the
NPCIL Stipendiary Trainee 2016 output will-
Ans. (c) : Number of flip-flops 2n = No. of pulse (a) toggle (b) be invalid
2n = 35 (c) change (d) not change
n=6 RSMSSB JEN (Degree) 29.11.2020
17. For a JK flip-flop, Qn is output at time step tn. Ans. (d) : When both are inputs of J-K flip-flop
Which of the following Boolean expressions cycle the output will not change. After one cycle the
represents Qn+1? value of each input comes to the same value.
(a) J n Q n + K n Q n (b) J n Q n + K n Q n Eg: When J = 0, and K = 1, After 1 cycle, it becomes
as J = 0→1→0 (1 cycle complete) and K = 1→0→1
(c) J n Q n + K n Q n (d) J n Q n + K n Q n
(1 cycle complete). The J & K flip − flop has 4 stable
ESE-2003
states: Latch, reset, set and Toggle.
Ans. (a) : JK flip flop is a universal flip flop. It removes
drawbacks of SR flip flop. 21. Asynchronous inputs are __________.
(a) S, R (b) J, K
J n K n Q n Q n +1 (c) S, R, J, K (d) SET, RESET
PGVCL JE 2018
0 0 0 0
Ans. (d) : Asynchronous input on a flip-flop have
0 0 1 1
control over the output (Q and Q ) regardless of clock
0 1 0 0
Input status. These inputs are called the preset (PRE)
0 1 1 0 and clear (CLR). The preset input drives the flip-flop to
1 0 0 1 a set state while the clear input drives it to a reset state.
1 0 1 1 22. A self-starting counter is one that can start
(a) the sequence from initial count and continues
1 1 0 1 its sequence
1 1 1 0 (b) the sequence from any state among the
K-map, sequence and continues its normal count
sequence
(c) from any state but eventually reaches the
required count sequence
(d) None of the above
ESE 2015
Ans. (c) : In self-starting counter, it is possible to enter
∴ Q n +1 = J n Q n + J n Q n + Q n K n a required counter loop irrespective of the initial state.
That means, even if the circuits enters an unusual state,
Q n +1 = J n Q n + K n Q n
it will eventually end up in a valid state.
Electronics-II 840 YCT
23. The basic shift register operation is____: (c) Negative edge triggering
(a) serial in serial out (d) Negative level triggering
(b) serial in parallel out UPPCL JE 27.11.2019, Shift-II
(c) parallel in serial out Ans. (b) :
(d) All options are correct
SSC JE 01.03.2017, Shift-I
Ans : (d) General shift registers operates in four CLK
different modes.
1. Serial in serial out (SISO)
2. Serial in parallel out (SIPO)
3. Parallel in serial out (PISO) In the above flip-flop, positive edge triggering is used.
4. Parallel in parallel out (PIPO) This is positive edge triggering. Because on CLK
24. The number of flip-flops required to produce a indicates positive edge triggering.
divide by 32 counter is………………? • If CLK indicates then it is negative edge
(a) 2 (b) 5 triggering.
(c) 3 (d) 4
NMRC JE 2019
Ans. (b) : Number of flip-flop required- CLK
2n ≥ N N = number of states,
n = No.of Flip − flop
Negative edge triggering
∵ N = 32
28. Following pulse is applied to an SR flip flop.
25 = 32
∴ n=5
25. Which of the following is an example of
sequential circuit?
(a) Flip-flop (b) Code converter
(c) Encoder (d) Adder If ∆t is propagation delay, which of the
UPPCL JE 27.11.2019, Shift-I following relations should hold to avoid the
Ans : (a) Flip flop is a sequential circuit race condition?
A Sequential circuit is a logical circuit, where the output (a) t p < ∆t < T (b) ∆t < ∆t p < T
depends on the present value of the input signal as well (c) 2∆t < t p (d) 2∆t < t p < T
as sequence of past input. A sequential circuit is a
combination of combinational circuit and storage UPPCL JE 27.11.2019, Shift-II
element like - flip-flop, register, counter, clock etc- ESE 2015
26. Calculate the maximum clock frequency at Ans. (a) : To avoid race condition we need width of the
which a 4-bit asynchronous counter can input pulse<propagation delay of SR flip-flop and it is
obvious that propagation delay of SR flip-flop< time
operate reliably. Assume propagation delay of
period of pulse, so tp< ∆t < T. Thus we can avoid race
each flip-flop to be 40ns and width of strobe
around condition.
pulse to be 20ns.
(a) 5.56 MHz (b) 12.5 MHz 29. The dynamic hazard problem occurs in
(c) 16.67 MHz (d) 6.25 MHz (a) Combinational circuit alone
UPPCL JE 27.11.2019, Shift-I (b) Sequential circuit alone
Ans : (a) Overall propagation delay (T) = delay of 4 flip (c) Both sequential and combinational circuits
flops + strobe pulse time (d) None of these
= 4×40+20 BSNL TTA 29.09.2016, 3 pm
= 160+20 = 180 ns Ans : (c) The dynamic hazard problem occurs in
1 1 combinational and sequential logic circuits. Because
f max = =
T 180ns output changes more than one time for one input reason
= 0.00555×109 behind it. It is that for large circuits there are different
= 5.56MHz routes for output. If each output is different in routes,
27. Which type of triggering is used in this flip- then output will be gates causes dynamic hazard and
flop? flip-flops cause delay in sequential circuits.
30. The race hazard problem occurs due to
(a) Faulty design of logic circuits
CLK
(b) Non-redundant form of the circuit
(c) Time-delay in circuits due to high speed logic
(a) Positive level triggering (d) All of these
(b) Positive edge triggering BSNL TTA 29.09.2016, 3 pm
Electronics-II 841 YCT
Ans : (c) The Race Hazard problem occurs due to time- fc 1
delay in circuits due to high speed logic. (c) (d) N ×
N fc
where,
N is the number of stages
fc is the clock frequency
ESE 2019
Ans. (d) : In a N-bit SISO shift register, If the delay of
the one-stage is tc, then the total delay is given by
∆t = N.t c tc = clock time-period
N
∆t =
Where ∆t1 & ∆t2 are propagation delay. fc
31. A simple flip-flop is 35. The Master–Slave JK flip-flop is an example of
(a) a 2-bit memory (a) positive edge-triggered device
(b) a 1-bit memory (b) negative edge-triggered device
(c) a four state device (c) level-triggered device
(d) Obtained by cross coupling of two NAND (d) pulse-triggered device
gates DGVCL JE 06.01.2021 Shift-III
BSNL TTA 29.09.2016, 3 pm Ans. (d) : The Master–Slave JK flip-flop is an example
Ans : (b) A simple flip-flop is a 1 bit memory. Flip-flop of the pulse-triggered device. The Master-Slave JK flip
is a digital memory circuit which stores either 1 or 0. It flop eliminates all the timing problems by using two SR
has two stable states. Such a circuit is called bistable flip flops connected together in a series configuration.
circuit. It remains in single until reset to another state. One flip flop acts as the ''Master" circuit which
32. Synchronous counters eliminate the delay triggers on the leading edge of the clock pulse while
problems encountered with asynchronous other acts as the ''Slave" circuit trigger on the falling
(ripple) counter because the edge of the clock pulse.
(a) input clock pulses are applied only to the first 36. Flip-Flop is a–
and the last stages (a) 1-state device (b) 2-state device
(b) input clock pulses are applied only to the last (c) 3-state device (d) 4-state device
stage (RRB JE (Shift-II), 04.09.2015)
(c) input clock pulses are not used to activate any Ans : (b) Flip-flop is a basic memory element. Flip-flop
of the counter stages is a two state device. It can store “One bit of
(d) input clock pulses are applied simultaneously information. It has known as “bistable multivibrator”.
ESE 2013 The simples form of flip-flop is called “latch”. It can be
Ans. (d) : In asynchronous counters all flip-flops are constructed with two cross coupled NAND gate or
simultaneously triggered using a clock pulse. NOR gate.
In asynchronous counters, the output of the previous
37. To operate correctly, starting a ring counter
state is given as a clock pulse to the next state.
requires
Therefore, synchronous counters eliminate the delay (a) clearing all the flip-flops
problems encountered with asynchronous (ripple) counters. (b) presenting one flip-flop and clearing all
33. Counter is: others.
(a) Combinational circuit (c) clearing one flip-flop and presenting all
(b) Sequential circuit others
(c) Both (a) & (b) (d) presenting all the flip-flops
(d) None of the above ESE 2012
UJVNL JE 2016 Ans. (b) : In a ring counter, the feedback of the output
Ans. (b) : A counter is a sequential logic circuit that of the flip flop is fed to the some flip flops input. To
contains flip-flops. Flip-flops are the most basic element operate correctly, starting a ring shift counter requires
of sequential logic circuits and they are themselves presenting one flip flop and clearing all others. So that it
made up of more basic combinational circuits such as can shift to the next bit.
NAND and NOR gates. 38. A static memory stores its data in :
Sequential logic circuits output depends on present (a) Flip-flops (b) Inductors
input signal as well as sequence of past inputs while (c) Capacitors (d) Resistors
combinational and logic circuits depends on present
DMRC JE 03.08.2014
inputs only.
Ans. (a) : A static memory stores its data in flip-flop.
34. The time delay ∆t introduced by a SISO shift Static random access memory is a type of random
register in digital signals is given by access memory that uses flip-flop to store each bit.
1
(a) N 2 × (b) N 2 × f c Static random access memory is volatile memory, data
fc is lost when power is removed.
Electronics-II 842 YCT
39. What is the clock cycle time for a system that 44. The order in which the return addresses are
uses a clock with frequency of 150 kHz? generated and used is
(a) 55 µ sec (b) 5.5 µ sec (a) LIFO (b) FIFO
(c) 202 sec (d) 6.6 µ sec (c) Random (d) Highest priority
JKSSB JE 2014 APGCL JM 2021
Ans. (d) : Given f = 150 kHz = 150 × 103 Hz Ans. (a) : LIFO = Last in first out
clock cycle (T) = ? • It is a method of processing data in which last items
As we know that entered are the first to be removed.
1 • LIFO method is some time used by computer when
T= extracting data from array or data buffer.
f
1 • In LIFO use return addresses are generate.
= 45. In how many different modes a universal shift
150 × 103 register operates?
= 6.6 × 10–6 sec (a) 2 (b) 3
T = 6.6 µ sec (c) 4 (d) 5
40. Each flip-flop in a 4-bit ripple counter ESE 2010
introduces a maximum delay of 40 n sec. The Ans. (c) : Modes of Universal Shift Register -
maximum clock frequency is • SIPO (Serial in parallel out)
(a) 2.65 MHz (b) 6.25 MHz • SISO (Serial in serial out)
(c) 5.26 MHz (d) 6.52 MHz
• PISO (Parallel in serial out)
UKPSC JE 2013, PAPER-I
• PIPO (Parallel in parallel out).
Ans. (b) : Given, n = 4 bit
Ts = 40 ns 46. In a JK flip flop as shown in Figure, J =Q' and
f=? K =1. If the flip flop was initially cleared and
then clocked for 6 pulses, then the sequence at
1
f= the Q output will be ______.
nTs
1
f=
4 × 40 ×10−9
109 1000
f= = ×106 = 6.25 MHz
160 160
41. How many flip-flops are required to build a
binary counter circuit to count from 0 to 1023?
(a) 1 (b) 6 (a) 010011 (b) 011010
(c) 10 (d) 23 (c) 010101 (d) 010010
UKPSC JE 2013, PAPER-I DGVCL JE 0.5.01.2021, Shift-II
Ans. (c) : No. of flip–flops required to build a binary Ans. (c) : Truth table of J-K flip-flop-
counter = 2n J K Q n +1
2 n = 210 = 1024 flip-flop count 0 − 1023 0 0 Q n (hold)
n = 10 0 1 0 ( Reset )
42. In a J-K flip-flop, If J = K=1 the resulting flip- 1 0 1( set )
flop is referred as:
(a) T-flip-flop (b) D-flip-flop 1 1 Qn
(c) Memory (d) S-R-Flip-flop From given figure J = Q, K = 1
OPPSC AE 2021, Paper-II
Present state Present CLK Next State Q+
Ans. (a) : When J = K = 1 for JK Flip Flop Q input J,
then Q = 0 and Q =1 K
Q = 1 and Q =0 0 1,1 1 1
Hence, resulting flip-flop is referred as T-flip-flop. 1 0,1 2 0
0 1,1 3 1
43. For a bi-directional synchronous counter
(a) Each flip-flop divides the frequency of its 1 0,1 4 0
clock input by 2 From above table, sequence at the Q output for 6
(b) Each flip-flop output is used as the clock pulse is = 010101
input to the next flip-flop 47. A shift register with the serial output connected
(c) no decoding logic is required back to the serial input is a
(d) each flip-flop is clocked at the same time. (a) Feedback shift register
(b) Shift register counter
Ans. (d) : In synchronous counter, all flip-flop are
(c) Universal shift register
triggered with same clock simultaneously. Synchronous
(d) Serial to parallel converter
counter is also called parallel counter.
ESE 2010
Electronics-II 843 YCT
Ans. (b) : In a shift register counter the output of the 52. Transparent flip flops are also called as
first flip flop is connected to the next flip flop and so on (a) Latches
and the output of the last flip flop is a gain feedback to (b) Asynchronous flip flops
the input of the first flip flop. (c) Multiplexers
(d) Both Latches & Asynchronous flip flops
BSNL TTA (JE) 25.09.2016, Shift-I
Ans. (b) : Transparent flip-flops are also called as
asynchronous flip-flops.
48. Which of the following counter results in least 53. The number of unused states in a 4-bit Johnson
delay?
(a) Ring counter counter is
(b) Ripple counter (a) 2 (b) 4
(c) Synchronous counter (c) 8 (d) 12
(d) Asynchronous counter BSNL TTA (JE) 2013
ESE 2010 Ans. : (c) The Johnson counter is a SISO shift register
Ans. (c) : In synchronous counter, all flip flops are obtained by feedback from inverted output of last flip-
triggered by the same clock simultaneously. All flip
flop change simultaneously. So the synchronous counter flop to the input of first flip-flop.
will provide less delay as compared to other counters. Total number of unused state = 2x – 2x (Where x =
49. A 4 bit module - 16 ripple counter uses JK flip number of bit)
flop. If the propagation by each flip flop is 50 = 24 – 2×4
ns. The maximum clock frequency be used. = 16 – 8
(a) 5 MHz (b) 10 MHz =8
(c) 4 MHz (d) 20 MHz
BSNL TTA (JE) 25.09.2016, Shift-I 54. Circuit shown in the figure below is a-
ESE 2003
Ans. (a) : Propagation delay for one flip-flop = 50ns
then for four flip-flops = 4 × 50 = 200ns
1 1
clock frequency fclock = = = 5 MHz
T 200ns
50. Decimal counter using flip flops and feedback
are more popular than a decimal counter of (a) Shift register (b) binary counter
ring type because of
(a) simple decade circuitry required (c) Ripple counter (d) Sequence detector
(b) economy in the number of flip flops. ESE 2010
(c) high speed of operation Ans. (a) : A shift register is a digital circuit using a
(d) its availability in IC form cascade of flip flops where the output of one flip flop is
BSNL TTA (JE) 25.09.2016, Shift-I connect to the input of the next. They share a single
Ans. (b) : Decimal counters using the number economy clock signal which causes the data stored in the system
of flip-flops and feedback is more popular than the to shift from one location to the next.
decimal counters of the ring type. A counter with a n-
flip-flops in the decimal counter can produce maximum
output of (2n-1).
51. The characteristic equation (Q = 1) of JK flip
flop is–
(a) Q–next = JQ+QK (b) Q–next = JQ+KQ
(c) Q–next = JQ+QK (d) Q–next = JQ+QK
BSNL TTA (JE) 25.09.2016, Shift-I
55. In the circuit given in the below figure, Q = 0
Ans. (b) : At Q = 1 in JK flip-flop is called as
initially. What shall be the subsequent states of
Qnext = JQ+KQ Q when clock pulses are given?
Characteristics equation −
SR = Qnext = S + R′ Q
JK = Qnext = JQ′ + K′ Q
D = Qnext = D
T = Qnext = TQ′ + T′Q
The characteristics equation of JK flip-flop is similar to
the SR flip-flop. When J and K are replaced by S and R (a) 1,0,1,0,...... (b) 0,0,0,0,......
respectively. When both J and K = 1, then the next state (c) 1,1,1,1,.... (d) 0,1,0,1......
is equal to the compliment of the current state. ESE 2008
Electronics-II 844 YCT
Ans. (a) : Ans. : (b) Total number of flip-flop required = n for MOD
From given figure, J = 1 - 20
K = Qn N = 20, n = no. of required flip flops
N = 2n
So, we can draw the truth table, 20 = 2n
Qn J K Qn+1 20 < 25 n ≅ 5
0 1 0 1 Hence, Total 5 number of flip-flops required to build
MOD-20 counter.
1 1 1 0 59. Dynamic memory cells are constructed using
0 1 0 1 (a) Transistors (b) Flip-flops
(c) MOSFETs (d) FETs
1 1 1 0 BSNL TTA (JE) 14.07.2013
The subsequent states on application of pulse will be Ans. : (c) Dynamic memory cells are constructed using
1,0,1,0,............ MOSFETs. The examples of dynamic memories are
56. The initial contents of the 4-bit series-in- Charge Coupled Devices (CCD) and semiconductor
parallel-out, right shift, shift register as shown dynamic RAM.
in figure below are 0101. After 3 Clock pulses 60. The reduced state table of sequential machine
the contents of the shift register will be has 7 rows. What is the minimum number of
flip-flops needed to implement the machine?
(a) 0 (b) 2
(c) 3 (d) 7
ESE 2007
(a) 0000 (b) 0101 Ans. (c) : Number of states or row = 2n
(c) 1010 (d) 1110 n → no. of flip flop
BSNL TTA (JE) 2013 7 = 2n
Ans. : (d) Initial content of the 4-bit series-in-parallel 7 < 23
out is n≅3
0101 • Number of states mode for -
• After 1st clock pulse ⋅ Binary counter = 2n
output of XOR =1 ⋅ Johnson counter = 2n
Then content of shift Register is 1010 ⋅ Ring counter = n
• After 2nd clock pulse 61. Which of the following is a sequential circuit?
output of XOR =1 (a) AND gate (b) NAND gate
Then content of shift Register is 1101 (c) Ex-OR gate (d) Bistable Multivibrator
• After 3rd clock pulse BSNL TTA (JE) 14.07.2013
output of XOR = 1 Ans. : (d) Bistable multivibrator is a sequential circuit.
Then content of shift Register is 1110 Bistable multivibrator has two stable states. It switch
57. The output of a JK flipflop toggles when from one state to another when external trigger pulse is
(a) J = I, K = 0 (b) J = 0, K = 1 apply. Sequential circuit output not depends only on the
(c) J = 1, K = 1 (d) J = 0, K = 0 present input but its past input also. It requires a
BSNL TTA (JE) 14.07.2013 memory element.
Ans. : (c) JK flip-flop is most popular flip-flop. It is 62. A master-slave flip-flop has the characteristic
used in counter circuit. Truth table of JK flip-flop is that-
given below- (a) change in the input is immediately reflected
CLK J K Qn+1 in the output
Qn (last value) (b) change in the output occurs when the state of
X 0 0 the master is affected
↑ 0 1 0
1 (c) change in the output occurs when the state of
↑ 1 0 the slave is affected
↑ 1 1 Q n (Toggle ) (d) both the master and the slave states are
affected at the same time
BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (c) Output of master slave flip flop changed when
state of slave is affected. Slave removed the race around
condition of the flip flop. Master flip flop is positive
triggered and slave is negative edge triggered flip flop.

58. The number of flip-flops required to build a

mod-20 counter is
(a) 4 (b) 5
(c) 19 (d) 20
BSNL TTA (JE) 14.07.2013
Electronics-II 845 YCT
63. The frequency of the clock signal applied to the 65. A circuit has an output that is determined by
rising edge triggered D flip-flop shown in the the present input as well as previous output
below figure is 10 kHz. What is the frequency states, the circuit is known as:
of the signal available at Q? (a) Mealey machine (b) Moore machine
(c) Sequential circuit (d) None of these
BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (c) Sequential circuit:- A circuit has an output
that is determined by the present input as well as
previous state is called sequential circuit.
66. A 4-bit synchronous counter uses flip-flops
(a) 2.5kHz (b) 5 kHz with propagation delay time of 25ns each. The
(c) 10kHz (d) 20kHz maximum possible time required for change of
ESE 2007 state will be-
(a) 25ns (b) 50ns
Ans. (b) :
(c) 75ns (d) 100ns
BSNL TTA 26.09.2016, 10 AM
Ans. (a) : In synchronous counter all flip-flops are
triggered with same clock simultaneously. So 4-bit
synchronous counter propagation delay is 25 ns.
Synchronous counter does not produce any
decoding error.
Synchronous counter is also called parallel counter
exp-Ring counter, Johnson counter.
Initial state of flip flop = 0 67. In a ripple counter, the state whose output has
When, flip flop is triggered its state changes from 0 to 1 a frequency equal to 1/8th that of the clock
(Because Q is connected to D) signal applied to the first stage, also has an
For the next positive edge trigger, flip flop state changes output periodicity equal to 1/8th that of the
from 1 to 0. output signal obtained from the last stage. The
From the above graph, it is clear that time period of flip counter is
flop is double of clock. So the frequency of signal (a) Modulo-8 (b) Modulo-6
becomes half. (c) Modulo-64 (d) Modulo-16
ESE 2005
10
f = kHz Ans. (c) : Each flip-flop frequency of a ripple counter
2 becomes half of it's previous flip flop.
= 5kHz Let the input frequency of clock = fi
64. The ripple counter shown in the given figure
works as a-

(a) mod-3 up counter 1

Time period of 3rd flip flop T = = 8Ti
(b) mod-5 up counter f i

(c) mod-3 down counter 8

(d) mod-5 down counter Each flip flop time period becomes double to that of it's
BSNL TTA (JE) 27.09.2016, 10 AM previous flip flop.
Ans. (d) So, time period of last stage
TL = 8T = 8 × 8Ti
TL = 64 Ti
1
So, frequency at last stage output =
TL
fi
=
64
Input frequency
∵ Ripple counter frequency f =
Modulo number
fi fi
=
64 Modulo number
Hence, Modulo no.= 64.

Electronics-II 846 YCT

68. An SR flip-flop does not accept the input entry 73. A 12 MHz clock frequency is applied to a
when? cascaded counter containing a modulus-5
(a) Both inputs zero counter, a modulus-8 counter, and two
(b) Zero at R and one at S modulus-10 counters. The lowest output
(c) Zero at S and one at R frequency possible is–––––––
(d) Both inputs at one (a) 30 kHz (b) 3 kHz
BSNL TTA 26.09.2016, 10 AM (c) 363.6 kHz (d) None of these
Ans. (d) : A SR flip-flop does not accept the input BSNL TTA 28.09.2016, 3 PM
entry when both inputs at one. 6
Ans. (b) Given, fin = 12MHz = 12 × 10 Hz
Truth table of SR FF-
S R Qn+1 ∵ Counters are connected in cascade
0 0 Qn (Previous state) ∵ Total modulus(M) =5 × 8 × 10 × 10 = 4000
0 1 0 fin 12 × 106
1 0 1 ( )
fout
min
=
M
=
4000
= 3 × 10
3

1 1 Invalid
69. Which of the following counters has the highest
speed?
( fout )
min
= 3kHz
(a) Asynchronous counter 74. The three-stage Johnson-Ring Counter as
(b) Synchronous counter shown below is clocked at a constant frequency
(c) Ripple counter of fc from the starting state of Q0Q1Q2 = 101.
(d) Ring counter The frequency of output Q0Q1Q2 will be
BSNL TTA 26.09.2016, 10 AM
Ans. (b) : Synchronous counter doesn't have
propagation delay. In synchronous counter the clock
input of the flip-flops are all clocked together at the
same time with the same clock signal, thus there is no
inherent propagation delay, in this way overall faster
operation may be achieved in synchronous counter. fc fc
70. Popular application of flip-flop are (a) (b)
8 6
(a) counters (b) shift registers
(c) transfer register (d) all of these fc fc
(c) (d)
BSNL TTA 28.09.2016, 10 AM 3 2
Ans. (d) : Flip-flops are popularly used in all given- ESE 2003
(1) Counters:- Three master slaves in the counter are Ans. (d) : The given figure is a 3-bit Johnson ring
used in the JK flip-flop cascade. These change the counter. Johnson ring counter has a property that its
negative edge of the flip-flops state input clock pulse. modulus is equal to twice the number of flip flops used.
(II) Shift Register:- A group of flip-flops is called a According to the connections, the output is switching
register. All flip-flop of a register serves as units. between 101 and 010. So, this is a modulo-2 counter
(III) Transfer Register:- It has two methods of data and its output frequency to be divided by 2 times.
transfer from flip-flop to parallel shifting, Range shifting. f
Hence, output frequency = c
71. A flip-flop can store 2
(a) 1 bit of data (b) 2 bits of data 75. The flip-flop which acts as frequency divider
(c) 3 bits of data (d) 4 bits of data is-
BSNL TTA 28.09.2016, 10:00 AM (a) SR flip-flop (b) D flip-flop
BSNL TTA 28.09.2016, 3:00 PM (c) T flip-flop (d) None
Ans. (a) : A flip-flop can store one bit of data. A flip- BSNL TTA 21.02.2016
flop is basically a digital memory circuits. It has two BSNL TTA (JE) 27.09.2016, 10:00 AM
stages- Ans : (c) The T flip-flop acts as frequency divider. In T
One stage is '1' and other is '0'. A device or circuits that flip-flop only one inputs. This flip-flop can be made by
has two stages is called a bistable for example-Toggle. giving feedback from output to input in clocked SR
72. Divide by 78 counter can be realized using flip-flop. This flip-flop drives a train input of a very
(a) 6 number of mod-13 counters short width trigger pulse.
(b) 13 number of mod-6 counters
(c) 13 number of mod-13 counters
(d) one mod-13 counter followed by one mod-6
counter
BSNL TTA 28.09.2016, 10 AM
Ans. (d) : Divide by 78 counter can be realized using
one mod-13 counter followed by one mod-6 counter. This output waveform requires twice triggering to
The common method of creating counters of more generate one cycle. So frequency of output is half of
modulus is to use counters of less modulus end to end. input.
Electronics-II 847 YCT
76. Race around condition occur in J-K flip-flop is 80. In the circuit as shown in figure below, assuming
due to- initially Q0 = Q1 = 0. Then the states of Q0 and Q1
(a) The clock time period is less than immediately after the 33rd pulse are
propagation delay
(b) The clock time period is greater than
propagation delay
(c) Due to triggering
(d) None
BSNL TTA 21.02.2016
BSNL TTA 28.09.2016, 10:00 AM (a) 11 (b) 10
Ans : (b) Race around condition occur in JK flip-flop is (c) 01 (d) 00
due to the clock time period is greater than propagation ESE-2003
delay. Ans. (d) :
Both inputs are high (J=K=1) then JK flip-flop race
around condition occurring. Race around condition can
be avoided by using master slave flip-flop.
77. In a positive edge triggered JK flip- flop,
J=1,K= 0 and clock pulse is rising, Q will be:
(a) 0 (b) 1
(c) showing no change (d) toggle Truth table-
( n +1) ( n +1)
NSCL Diploma Trainee 24.02.2021 J0 K0 J1 K1 Q1n Q n0 Q1 Q0
Ans. (b) : Truth table of JK flip-flop is
1 1 0 1 0 0 0 1
CLK Input J Input K Output
1 1 1 0 0 1 1 0
↑ 0 0 Qn
0 1 0 1 1 0 0 0
↑ 0 1 0 1 1 0 1 0 0 0 1
↑ 1 0 1 ( n +1) ( n +1)
The state of Q1 and Q0 is repeating itself after 3-
↑ 1 1 Not allowed
From that table we can say that when J = 1, K = 0 then clock pulses. So it is MOD-3 counter and therefore after
the output will be Q = 1 33rd pulse, the state of Q 0 and Q1 will be 00.
78. Which of the following flip-flop is used as 81. Master-slave configuration is used in FF to-
latch? (a) Increase its clocking rate
(a) JK-FF (b) D-FF (b) Reduces power dissipation
(c) RS-FF (d) T-FF (c) Eliminates race around condition
NSCL Diploma Trainee 24.02.2021 (d) Improves its reliability
Ans. (c) : RS flip-flop is used as latch: BSNL TTA 26.09.2016, 3 PM
The RS flip-flop is considered as one of the most basic Ans : (c) Master-slave J-K flip-flop is designed to
sequential logic circuit. A flip-flop is a bi-stable device. eliminate the race-around condition in J-K flip-flops.
There are three classes of flip-flop they are known as Master slave flip-flops are obtained by connecting two
latches pulse triggered flip-flop, Edge-triggered flip- J-K flip-flops in series with one is positive clock trigger
flop. and other is negative clock trigger.
79. Triggering action can be obtained in a J-K FF 82. A master slave JK flip-flop consists of-
by joining- (a) A cascade of two SR flip-flops
(a) J and K points to ground (b) A JK flip-flop connected in series with a D
(b) J point X and K to X flip-flop
(c) J and K points to positive supply (c) Two SR flip-flops connected in parallel
(d) J point to positive supply (d) An SR flip-flop and a T flip-flop
BSNL TTA 26.09.2016, 3 PM BSNL TTA 26.09.2016, 3 PM
Ans : (b) To obtained triggering action from J-K flip- Ans : (a) A master slave flip-flop is the cascade
flop, We connected J to X and K to X . combination of two flip-flops among which the first is
designated as master flip-flop while the next is called
slave flip-flop. Here the master flip-flop is triggered by the
external clock pulse train while the slave is activate at its
inversion i.e. if the master is positive edge triggered, then
the slave is negative-edge triggered and vice-versa.
83. A n-state ripple counter will count up to-
(a) 2n (b) 2n– 1
(c) n (d) 2n –1
BSNL TTA 26.09.2016, 3 PM
Ans : (a) A n-bit ripple counter can count upto 2n states.
It is also known as MOD-n counter.

Electronics-II 848 YCT

84. The basic building block of sequential logic Ans. (d) :
circuit is-
1
(a) Gate (b) Flip-flop f max =
(c) ALU (d) Control unit t pd + t A
BSNL TTA 26.09.2016, 3 PM Given tpd = 50 ns = 50×10-9 second.
Ans : (b) Logic gates are the basic building block of and tA = 20 ns = 20×10-9 second
combinational logic circuits whereas flip-flops are the 1
basic building blocks of a sequential circuit. ∴ f max =
85. In _______sequential circuits, signals can affect ( 50 + 20 ) × 10−9
the memory elements only at discrete instants = 0.01428×109 Hz = 14.28 MHz
of time. 88. Latches constructed with NOR and NAND
(a) synchronous (b) asynchronous gates tend to remain in the latched condition
(c) combinational (d) none of the above due to which configuration feature?
MPPEB Sub. Engineer 0.8.07.2017 Shift-I (a) Asynchronous operation
Ans. (a) : Digital sequential circuits are divided into (b) Low input voltage
synchronous and asynchronous types. In sequential (c) Gate impedance
synchronous circuit, The state of the device changes (d) Cross coupling
only at discrete times in response to a clock signal. In ESE-2013, 2014
asynchronous circuits, The state of the device can Ans. (d) : Latch construction with NOR and NAND
change at any time in response to charging input. gate -

Latch is a type of two states bi-stable multivibrator.

Both inputs of the latch are directly connected to the
others output.
Due to cross coupling configuration, NOR and NAND
gates tend to remain in the latch condition.
89. The digital circuit using two inverters as shown
in the figure below acts as.

(a) A bistable multivibrator

Hence O/P depends on present state and input i.e. (b) A astable multivibrator
output (O) = f (I, y) (c) a monostable multivibrator
next state (Y) = f (I, y) (d) an oscillator
Present state (y) = f (Y) ESE-2010
86. Race-around condition occurs in Ans. (a) : A bistable multivibrator has both the two
(a) Multiplexer (b) ROM stable states. It required two trigger pulses to be applied
(c) Flip-flops (d) Voltage regulator to change the states. Until the trigger input is given, this
ESE-2015 multivibrator cannot change its state.
Ans. (c) : • Race around condition occurs only in level 90. In the _______triggering, the output responds
triggered flip flop and because of the feedback to the changes in the input only at the positive
connection. edge of the clock pulse at clock input.
• Output toggles many times instead of once in one (a) negative edge (b) negative level
clock pulse. It is undesirable and called as "Race (c) positive edge (d) positive level
Around condition". MPPEB Sub. Engineer 0.8.07.2017 Shift-I
• Race around condition is when J = 1 and K = 1 (flip Ans. (c) : In the positive edge triggering, the output
flop in toggling mode) and tp > tff. responds to the changes in the input only at the positive
87. Determine fmax for the 4-bit synchronous edge of the clock pulse at clock input.
counter, if tpd for each flip-flop is 50ns and tpd 91. Which of the following is correct for a gated D-
for each AND gate is 20ns. type flip flop?
(a) 1.43MHz (b) 0.143MHz (a) the output is either SET or RESET as soon as
(c) 143MHz (d) 14.3MHz the D input goes HIGH or LOW
MPPEB Sub. Engineer 0.8.07.2017 Shift-I (b) The output complement follows the input
ESE-2015 when enabled
Electronics-II 849 YCT
 (c) Only one of the inputs can be HIGH at a time 94. A _______is a register capable of counting the
(d) The output toggles if one of the inputs is held number of clock pulse arriving at its clock
HIGH input.
Ans. (a) : Truth table of D flip-flop: (a) register (b) address
(c) counter (d) latch
Clk Input Output State MPPEB Sub. Engineer 0.8.07.2017 Shift-I
1 0 0 Re set Ans. (c) A counter is defined a register capable of counting
1 1 1 Set the numbers of clock pulse arriving at its clock input.
95. A sequential circuit using D flip–flop and logic
Clk Input output gates is shown in the figure, where X and Y are
1 0 0 Reset the inputs and Z is the output. The circuit is:
1 1 1 Set
92. When both the inputs of a latch are high,
output is unpredictable. What is this condition
called?
(a) Bistable (b) Indeterminate
(c) Inactive (d) No change
MPPEB Sub. Engineer 0.8.07.2017 Shift-I
Ans. (b) : When both the inputs of a latch are high
output is unpredictable. This condition is called (a)S – R Flip–Flop with inputs X = R and Y = S
indeterminate condition As next state of two outputs are (b)S–R Flip–Flop with inputs X = S and Y = R
inverse to each other. (c)J – K Flip–Flop with inputs X = J and Y = K
93. The digital circuit as shown below represents to (d)J – K Flip–Flop with input X = K and Y = J
which one of the following? BSNL TTA 25.09.2016, 3:00 P.M.
Ans : (d) The input to the D-flip flop in the circuit is
D = XZ + YZ … (i)
When converting D-flip flop to JK flip flop we have
D = JQ + KQ … (ii)
From equation (i) and (ii) We have Z = Q
Then, X = K and Y = J
96. The following truth table has to be realized
with the circuit shown in the figure.
A B Q n +1
(a) JK flip-flop
(b) Clocked RS flip-flop 0 0 Q
'
n
(c) T flip-flop
(d) Ring counter 0 1 1
ESE-2009 1 0 Qn
1 1 0
Ans. (c) : A T-flip flop is known as a Toggle flip flop
because of its toggling operation. It is a modified form
of the JK flip flop.

What is the output of the combinational logic

circuit to the J input?
(a) AB (b) A
(c) B (d) AB
Draw the truth table of circuit, ESE-2008
Ans. (b) : The excitation table of the circuit is as
follows –
Qn A B Qn+1 J K
0 0 0 1 1 X
1 0 0 0 X 1
0 0 1 1 1 X
From the truth table, 1 0 1 1 X 0
If, X = 0 then Qn+1 = Q (No change) 0 1 0 0 0 X
1 1 0 1 X 0
X = 1 then Q n+1 = Q (toggle) 0 1 1 0 0 X
So, this circuit works as a T-flip flop. 1 1 1 0 X 1
Electronics-II 850 YCT
 Using k=map for J :- Ans : (d) Applications of flip-flops:-
• These are various types of flip-flops being used in
digital electronic circuit:-
• Counters.
• Frequency dividers
• Shift registers
• Storage registers
• Data storage
So, we can say that, the output of the combinational • Data transfer
• Transfer register
logic circuit to the J input will be A . • Latch
97. A ring counter consisting of five flip–flops will • Flip-flop
have : 102. Number of flip-flop needed to divide the input
(a) 5 states (b) 10 states frequency by 32 is
(c) 32 states (d) infinite states (a) 2 (b) 4
OPPSC AE 2021, Paper-II (c) 5 (d) 8
BSNL TTA 25.09.2016, 3:00 P.M. BSNL TTA 29.09.2016, 10 AM
Ans : (a) A ring counter consisting of five flip-flops Ans : (c) To find no. of flip-flops needed to divide the
will have 5 states. Ring counter is a shift register. In input frequency by 32 is,
which D input is controlled of first flip-flop by 2n = 32
feedback. Ring counter is a synchronous counter. 2n = 25 (n = no. of flip-flops)
Which uses serial shift register IC74164.
∴ n= 5
98. How many FFs are needed for MOD-16 ring
103. A 4-bit ripple counter and a bit synchronous
counter and MOD-16 Johnson counter?
counter are made using flip-flops having a
(a) 16, 16 (b) 16, 8
propagation delay of 10 ns each. If the worst
(c) 4, 8 (d) 8, 16
case delay in the ripple counter and the
Mizoram PSC IOF 2019, Paper-III
synchronous counter be R and S respectively,
Ans. (b) : (1) Mod Ring counter– (MOD–N)– It is also then-
called shift register counter. Number of Flip-Flops in (a) R = 10 ns, S = 40 ns
Mod-N Ring counter depends on Number ‘N’. Here in (b) R = 40 ns, S = 10 ns
this question number of N is equal to 16. So, Number of (c) R = 10 ns, S = 30 ns
flip-flops in mode Ring Counter are 16. (d) R = 30 ns, S = 10 ns
(2) MOD–N Johnson Counter– This is also known as BSNL TTA 27.09.2016, 3 PM
twisted Ring Counter. Number of Flip-flop MOD-N
Ans : (b) A 4-bit ripple counter is-
N
counter is .
2
Given that– N = 16
16
So number of flip-flops = =8. In ripple counter each flip-flop waits for its previous
2
flip-flop output-
99. Minimum number of J-K flip-flops needed to
R = 4 Td = 4 × 10 = 40 ns.
construct a BCD counter is - 4-bit synchronous counter is-
(a) 2 (b) 3
(c) 4 (d) 5
Mizoram PSC IOF 2019, Paper-III
Ans. (c) : Four JK flip flops will be required to
construct to BCD counter.
100. How many flip-flop are needed for a 4 bit
counter? In synchronous counter all flip-flops are triggered by
(a) two (b) three same clock so at a time all four flip-flop will give
(c) four (d) six output, S = 10ns.
BSNL TTA 29.09.2016, 10 AM 104. Which of the following is not a sequential
Ans : (c) Flip-flop is a single bit counter. Four flip- circuit?
flops are needed for a 4–bit counter. The maximum (a) Flip-flop (b) Counter
possible modulus is determined by the number of flip- (c) Shift register (d) Multiplexer
flops for a four-bit counter can have a modulus of upto BSNL TTA 27.09.2016, 3 PM
16 (24). Counters are generally classified as either
synchronous or asynchronous. Ans : (d) Multiplexer is not a sequential circuit because
in sequential circuit present output not only depends
101. Popular applications of flip-flop are
(a) counters (b) shift registers upon present input but also depends upon past value,
(c) transfer register (d) all of these but in multiplexer present output depends upon present
BSNL TTA 29.09.2016, 10 AM input which is a combinational circuit.
Electronics-II 851 YCT
105. Consider the D-Latch shown in the figure, 107. A sequential circuit using D flip-flop and logic
which is transparent when its clock input CK is gates is shown in Fig., where 'X' and 'Y' are the
high and has zero propagation delay. In the inputs and 'Q' is the output. The circuit is
figure, the clock signal CLK1 has 50% duty ______.
cycle and CLK2 is a one-fifth period delayed
version of CLK1. The duty at the output at the
latch in percentage is

(a) JK flip-flop with inputs X = K and Y = J

(b) JK Flip-flop with inputs X = J and Y = K
(c) SR flip-Flop with inputs X = R and Y = S
(d) SR flip-flop with inputs X = S and Y = R
Vizag Steel MT 13.12.2020
(a) 30 (b) 15
(c) 0 (d) 100 Ans. (b) :
APGCL AM 2021
Ans. (a) : Given,
CLK1 has 50% of duty cycle.
CLK 2 is one-fifth period delayed version of CLK1.
Timing diagram-
From given sequential circuit-
D = XQ n + YQ n
and if a input D = JQ n + KQ n is given to the input of D-
flip flop then D-FF is converted to J-K FF.
so, given sequential circuit is J-K FF with X=J and Y=K
108. The state diagram for the D flip-flop is ______.

T T 3T
Output pulse gets high for time = − =
2 5 10
3T /10 3
Duty cycle of output pulse (D) = =
T 10
% D = 30%
106. Using an additional NOT gate J-K flip flop can
be converted into
(a) T-Flip-Flop
(b) Master Slave Flip-Flop
(c) RS Flip-Flop
(d) D-Flip-Flop
JPSC AE 10.04.2021, Paper-I
Ans. (b) : Master - Slave flip-flop - To avoid race
around condition Master Slave FF is used.
Vizag Steel MT 13.12.2020
Ans. (b) : D flip flop
Q D Q+
0 0 0
0 1 1
1 0 0
In master slave flip-flop, output will changes only when 1 1 1
slave output change.
Master Slave flip-flop can be obtained by connecting Characteristic diagram-
two J-K flip-flop with an additional NOT gate. Q +n = D

Electronics-II 852 YCT

State diagram of D flip-flop- Ans. (a) : J-K flip-flop is called as universal flip-flop
because all flip-flop like D-FFs, SR FFs and T-FF can
be derived from it.
Characteristic table-
Q n +1 = JQ n + K Q n

109. A four flip-flop ripple counter is being

operated at a clock frequency of 32 kHz. The
frequency (kHz) of the waveform at the output
of the MSB flip-flop is
(a) 2 (b) 1
(c) 4 (d) 8
TSPSC Manager (Engg.)HMWSSB 2020
Ans. (a) : Frequency = 32 kHz
f in
fout =
MOD
MOD of ripple counter = 2n
113. A ripple counters speed is limited by the
= 24 = 16 (n = number of FF)
propagation delay of
f 32
fout = in = (a) each flip-flop
16 16 (b) all flip-flop and gates
f out = 2kHz (c) flip-flops only with gates
(d) only circuit gates
110. If an inverter is placed between the inputs of an UPPSC AE 13.12.2020, Paper-II
S-R flip-flop the resulting flip-flop is Ans. (a) : In ripple counters speed is limited by the
(a) Master slave flip-flop (b) T flip-flop propagation delay of each flip-flop. A ripple counter is
(c) D flip-flop (d) JK flip-flop an asynchronous counter where only the first flip-flop is
TSPSC Manager (Engg.)HMWSSB 2020 clocked by an external clock.
Ans. (c) : When an inverter is placed between the inputs 114. With a 100 kHz clock frequency, eight bits can
of S-R flip-flop then the resulting flip flop will be D-flip be serially entered into a shift register in
flop. (a) 08 µs (b) 80 ms
(c) 10 µs (d) 80 µs
RPSC ACF & FRO 23.02.2021
Ans. (d) : Given, fc = 100kHz, N = 8,
1 1
∆t = N × = 8 × = 80µ sec.
fc 100 × 103
Where, N = number of Flip-Flop
fc = Clock frequency.
115. A feature that distinguishes the J-K flip-flop
111. Why synchronous transmission is more from the D flip-flop is the
(a) Preset input (b) Type of clock
preferred
(c) Clear input (d) Toggle condition
(a) It has no start and stop bit RPSC ACF & FRO 23.02.2021
(b) It is cheaper than asynchronous
Ans. (d) : J-K flip-flop- (JK-FF) is also called an
(c) It is easier to implement
universal FF because the FFs like D-FFs, SR-FFs and
(d) less complex
T-FFs can be derived from it.
UPPSC AE 13.12.2020, Paper-II
Ans. (a) : In synchronous transmission both sender and
receivers access the data according to same clock. It has
no start and stop bits and thus it has more efficient.
Therefore synchronous transmission is more preferred.
112. Which of the following questions satisfy the J-
K flip-flop?
(a) Q n +1 = J n Q n + K n Q n
(b) Q n +1 = J n Q n + K n Q n
(c) Q n +1 = J n Q n + K n Q n A feature that distinguishes the J-K flip flop from the D
(d) Q n +1 = J n Q n + K n Q n flip-flop is the toggle condition which is absent in D-
UPPSC AE 13.12.2020, Paper-II FFs.
Electronics-II 853 YCT
116. An octave counter skips the binary states: 120. Which property is NOT considered in latches?
(a) 1001 to 1111 (b) 1000 to 1111 (a) Output of the latches changes as we change
(c) 1010 to 1111 (d) 0111 to 1111 the input
OPPSC AE 2021, Paper-II (b) Latches are level triggered
Ans. (b) : The octave counter count the number from (c) Latches are edge triggered
zero to 7. Hence it skip all that number which is greater (d) Latches are fast
than 7. UPPCL JE- 07.09.2021, Shift-I
1 0 0 0 to 1 1 1 1 (8 to F) Ans. (c) : Latches are level triggered instead of edge
117. In an asynchronous counter using D flip-flop, triggered, flip flop is edge triggered.
which of the following is true? Output of the latches changes as we change the input.
Latches are fast in speed as compare to flip-flop
(a) Same clock signal is given to all flip-flops.
(b) Output of one flip-flop is given as the clock to 121. One of the standardised instructions for output
the next flip-flop. of logic line "OUT" is used _______.
(c) Clock signal is derived from independent (a) to reset instruction for flip flops
signal generators. (b) to output a flip flop
(c) to output a relay
(d) Alternate flip-flops are given the same clock
(d) to denote the set
signal.
UPPCL JE- 08.09.2021, Shift-I
LMRC (SCTO) 17.04.2021
Ans. (c) : The standardised instruction for output of
Ans. (b) : An asynchronous counter using D flip-flop. logic line "OUT" is used to output a relay. Relays are
The output of one flip-flop is given as a clock to the electrically operated switches that open and close the
next flip-flop. Flip-flops store one bit of data. circuit by receiving electrical signals from outside
118. Which of the following is NOT a correct source.
application of shift registers? 122. MOD-12 and MOD-6 counters and multipliers
(a) A parallel-in serial-out shift register is used to are most commonly used as
convert parallel data to serial data (a) Frequency counters
(b) The serial-in serial-out and parallel-in (b) Multiplexed displays
parallel-out shift registers are used to (c) Power consumption meters
maintain time promptness to digital circuits (d) Digital Clocks
(c) Shift registers are used for temporary data BSNL TTA (JE) 25.09.2016, Shift-I
storage Ans. (d) : MOD-12 and MOD-6 counters and
(d) Shift registers are used for data transfer and multipliers are most commonly used as digital clocks.
data manipulation MOD-12 and MOD-6 are used in digital clock to
UPPCL JE- 07.09.2021, Shift-II display the time of day.
Ans. (b) : Shift registers - Shift register is a group of 123. The output of a sequential circuit depends on
flip - flops used to store multiple bits of data. (a) present inputs
Applications of shift registers. - (b) past outputs
• The shift registers are used for temporary data (c) both present and past inputs
storage (d) past inputs
• The shift register are also used for data transfer and BSNL TTA (JE) 25.09.2016, Shift-I
data manipulation. Ans. (c) : The output in a sequential circuit depends on
• A parallel-in serial-out shift register is used to both the present and past input. It requires a memory
element. Their designing is not easy but complicated.
convert parallel data to serial data.
Response of this circuit is slow. Examples of this circuit
• The serial-in serial-out and parallel-in parallel-out are flip-flops , latches, counters and shift registers.
shift registers are used to produce time delay to 124. If the registers have both shifts and parallel
digital circuits rather than not maintain time load capabilities, they are referred as ______.
promptness to digital circuits. (a) universal shift registers
119. Asynchronous counters are also known as (b) unidirectional shift registers
____. (c) sequential registers
(a) ripple counters (b) square counters (d) bidirectional shift registers
(c) VLSI counters (d) SSI counters MPPEB Sub. Engineer 0.8.07.2017 Shift-I
UPPCL JE- 07.09.2021, Shift-II Ans. (a) : If the registers have both shift and parallel
Ans. (a) : Ripple counters is a type of asynchronous load capabilities, they are referred to as universal shift
counters. Because in ripple counters different flip-flop registers.
are connected with different clock. Universal shift registers are used as memory elements in
It's speed also slower and only fixed court sequence is computer.
possible. 125. A shift register using flip-flops is called a
Some other example of asynchronous counter. ______.
– Ripple counters (a) static shift register
– Binary coded decimal counters. (b) flip-flop shift register
Electronics-II 854 YCT
 (c) dynamic shift register 2. An n-bit A/D converter is required to convert
(d) universal shift register an analog input in the range of 0-5 volt to an
LMRC (SCTO) 17.04.2021 accuracy of 10 mV. The smallest value of n
Ans. (a) : Flip-flop shift register is called static shift which can achieve this accuracy is
register. A set of flip-flops which are used to store 0 or (a) 9 (b) 10
1 i.e. a binary number are called registers. A set of flip- (c) 16 (d) 8
flops in which binary numbers can be shifted in and RPSC ACF & FRO 23.02.2021
shifted out is called a shift register. It is also called Ans. (a) : Given minimum analog input ( to be
static shift register. converted accurately) = 10 mV
126. The T flip-flop is a single-input version of the Maximum step size should be = 10 mV
As maximum voltage = step size.
__________________ flip-flop.
(a) D (b) clocked RS Full scale voltage (Vf )
Step size =
(c) JK (d) RS Number of steps
UPPCL JE- 08.09.2021, Shift-II 5
Ans. (c) : A 'T' flip-flop is like a JK flip-flop. These are No. of steps =
10×10-3
basically a single input version of JK flip-flops. This T
2 n − 1 = 500
flip-flop is obtained by connecting both inputs J&K
2n = 501
together. T flip-flop has only one input along with the
n ≈ 9
CLK input
3. In an 8 bit A/D converter, the quantization
127. The characteristic equation of T flip flop is : error is given by (in percent)
(a) Q = T' Q + TQ' (b) Q = T'Q' + QT' (a) 0.392 (b) 0.521
(c) Q = TQ (d) Q = TQ' (c) 0.212 (d) 0.425
BSNL TTA 25.09.2016, 3:00 P.M. RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
Ans : (a) Characteristic equation of T flip-flop Q = T'Q Ans. (a) : Maximum error acceptable in ADC|DAC is 1
+ TQ' is given. T flip-flop has only one input. This flip- LSB bit which is equal to resolution
flop can be made by giving feedback from output to 1
input in clocked RS flip-flop. T flip-flop is called toggle % resolution = n × 100
flip-flop also. In this flip-flop a narrow trigger pulse 2 −1
drives T. 1
= 8 × 100 = 0.392
128. Which one of the following can be used to 2 −1
change data from special code to temporal 4. Number of comparator required to build a 5
code? bit analog to digital type of converter is
(a) Shift register (b) Counters (a) 5 (b) 11
(c) A/D converters (d) Combinational circuits (c) 31 (d) 21
BSNL TTA 27.09.2016, 3 PM RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
Ans : (a) A shift register can be used to change data Ans. (c) : For n bit conversion flash type ADC requires
from special code to temporal code because in shift (i) 2n – 1 comparators
register when clock pulses are applied data gets shifted (ii) 2n resistors
towards left or right and it is a group of flip-flops used Hence, for 5 bit, 25 – 1 = 31 comparators required.
to store multiple bits of data. 5. A 5 bit DAC produces Vout = 0.2 V for a digital
input of 00001. Find the value of Vout for a
input of 11110.
V. A/D and D/A Converters (a) 3 V (b) 12 V
(c) 6 V (d) 9 V
1. The resolution of a 4-bit counting ADC is 0.5 RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
volts. For an analog input of 6.6 volts, the Ans. (c) : Analog output voltage of an N-bit straight
digital output of the ADC will be binary DAC.
(a) 1101 (b) 1110 V0 = K [2N–1bN–1 + 2N–2 bN–2 + ............... +22b221b1+b0]
(c) 1100 (d) 1011 Vout = 11110 = 1 × 24 + 1 × 23 + 1 × 22 + 1 × 21 + 0 × 20
RPSC ACF & FRO 23.02.2021 = 30
V Vout = 0.2 V for 1
Ans. (b) : Resolution = n
2 −1 1  → 0.2
6.6 Hence, for 30 Vout 30  → 0.2 × 30
0.5 = n
2 −1 = 6 Volt
6.6 6. A 12 bit A/D converter has a range 0 – 10 V.
2 −1 =
n
= 13.2
0.5 What is the approximate resolution of the
2 n = 14.2 converter?
(a) 1 mV (b) 2.4 mV
2n ≈ 14 (1110 )
(c) 2.4 µV (d) 24 mV
n = 4 bit RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
Electronics-II 855 YCT
Ans. (b) : The number of digits used in a digital meter Ans. (a) : Potentiometric type analog to digital
determines the resolutions converter is mostly used because of its high resolution
n = no. of bits and speed. Potentiometric A/D converter is also known
full scale voltage as successive approximation type analog to digital
Resolution (R) =
2n − 1 converter.
10 10 11. What is the value of the full scale output for an
R = 12 = = 2.4mV 8-bit digital to analog converter for 0 V to 10 V
2 − 1 4095
range?
7. Which of the following is NOT one of the
(a) 6.961 V (b) 7.891 V
analog to digital (A/D) conversion techniques?
(a) Voltage to-time conversion method (c) 8.961 V (d) 9.961 V
(b) Successive approximation method ESE (Pre) 18.07.2021
(c) Single slope integration method Ans. (d) : Given,
(d) Voltage to frequency conversion method Number of bit (n) = 8
UPPCL JE- 08.09.2021, Shift-I Full scale voltage = 10V
Ans. (c) : Analog to digital conversion Vref 10
(i) Voltage to-time conversion method LSB of DAC = n = 8 = 0.03921
(ii) Successive approximation method 2 −1 2 −1
(iii) Voltage to frequency conversion method Value of full scale output = full scale – LSB
(iv) Parllel type or flash type = 10 – 0.03921
(v) Dual slop type = 9.96078
Single slope integration method is not a type of analog ≃ 9.961V
to digital conversion techniques 12. For a full-scale voltage range of 0-5 V, the
8. A successive approximation ADC uses a 4MHz resolution of 6 bit ADC is nearest to:
clock and an 8 bit binary ladder. What is the (a) 78 mV (b) 833 mV
conversion time?
(c) 156 mV (d) 20 mV
(a) 1 µsec (b) 2 µsec
(c) 4 µsec (d) 8 µsec Ans. (a) :
ISRO VSSC (TA) 14.07.2021 Vrange
Resolution = n
Ans. (b) : For a successive approximation ADC 2
Conversion time = n × Tclk n = No. of bit
Where, n = number of bits = 8 5
Tclk = clock pulse = 6 ≃ 78mV
2
Tconv = 8 ×
1 13. Which of the following is the fastest A-D
4 ×106 convertor?
= 2 × 10 −6 sec (a) Successive approximation type
Tconv = 2 µ sec (b) Flash type
9. The resolution of an 8 bit optical encoder is (c) Integration type
(a) 0.7º (b) 1.4º (d) Ramp type
(c) 2.8º (d) 3.6º MPPKVVCL (Jabalpur) JE -2018
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II Ans. (b) : There are various types of analog to digital
360º converters
Ans. (b) : Resolution of optical encoder-
2n (1) Counter type or digital Ramp type
Where, (2) Parallel comparator /flash type
n = Number of bits (3) Successive approximation type
360º (4) Dual slope integrating type
Resolution = The parallel comparator type ADC is also called flash
2n
360° 360º type or simultaneous ADC. It is the fastest ADC among
= 8 = = 1.4º all but it require much more circuitry than the others.
2 256
for n bit conversion flash type ADC-
10. Which one of the following analog to digital (i) Number of comparators = 2n -1
conversion methods is called potentiometric
(ii) Number of resistors = 2n
type analog to digital converter?
(a) Successive approximation method 14. In order to design 5 bit comparator, how many
(b) Voltage to time conversion method output (s) is/are needed?
(c) Voltage to frequency conversion method (a) 1 (b) 2
(d) Dual slope integration method (c) 3 (d) 4
ESE (Pre) 18.07.2021 MPMKVVCL (Bhopal) JE 2018
Electronics-II 856 YCT
Ans. (c) : In order to design 5 bit comparator 3 output 19. For a 12 bit A/D converter the range of input
line are needed signal is 0 to +10V. The voltage corresponding
i) A > B to 1 LSB will be
ii) A = B (a) 0 (b) 0.0012V
iii) A < B (c) 0.0024V (d) 0.833V
For n bit conversion flash type ADC requires HPSSSC JE 2018 Code -387
2n – 1 = Comparator Ans. (c) :
2n – 1 = 5 Vfull scale 10
2n = 6 Resolution = ( No.of .bit )
= 12 = 0.0024400244V
2n < 23 2 −1 2 −1
n≅3 ≈ 2.44 mV
15. A 12 bit A/D converter has a range 0-10V. The voltage corresponding to 1 LSB is nothing but
What is the approximate resolution of the resolution corresponding to A/D converter. So
converter? appropriate answer is 0.00244 Volt.
(a) 1 mV (b) 5 mV 20. Which of the following is considered as the
(c) 2.5mV (d) 12mV slowest ADC?
Mizoram PSC Jr. Grade (PWD) 2018 Paper-I (a) Flash type
BWSSB(Code 85), 10.04.2016 (b) Successive approximation
Ans. (c) : Given data, VFS = 10V , (c) Integrating type
(d) Counting type
Number of bit (n) = 12 (e) Sigma Delta
V RSEB JE 2011
∴ Resolution of the A/D converter = n FS
2 −1 Ans. (c) : Types of ADCs are
10 10 (a) Counter type
= 12 = = 0.00244V (b) Successive approximation type
2 − 1 4095
2.44 ≅ 2.5mV (c) Flash type
(d) Dual slope type.
16. The conversion time of a 12 bit successive Flash type ADC is the fastest ADC among all
approximation A/D converter using a 1 MHz Dual slope integrating type ADC is slowest ADC.
clock is
21. A doctor is using a digital clinical thermometer,
(a) 1 µs (b) 12 µs
which employs an A/D converter. The
(c) 4096 µs (d) 4095 µs converter provides for both +ve and –ve
BWSSB Code 127, 13.11.2016 reference inputs in place of only +ve and
Karnataka PSC JE-2016 ground potential reference inputs
Ans. (b) : f = 1MHz = 1×106 Hz no of bits n = 12 bit. + -
Vref = 2.16V & Vref = 1.85V. The amplifier used
1
∴conversion time = × n for the converter input generates signal of 20
f mV per ºF of body temperature. The converter
1 output is between 00000 and 11111. Which one
= 6 × 12 = 12µs of the following is correct?
10
(a) The thermometer ranges is 92.5ºF to 108ºF
17. A successive approximation A/D converter has (b) The thermometer range is 46ºF to 216ºF
a resolution of 20 mV. What is its digital output (c) The thermometer range is 0ºF to 108ºF
for an analog input of 2.17 V? (d) The thermometer cannot by used to measure
(a) 01101100 (b) 01101101 body temperature 98.4ºF
(c) 01101011 (d) 01110100
ESE 2006
BWSSB Code 222, 26.05.2017
ESE 2006 Ans. (a) : According to the question, amplification
range is from minimum 1.85V to maximum 2.16 volt
Ans. (b) : Analog I/P = Resolution × Digital O/P range voltage is (2.16–1.85) volt
2.17 Step size is 20mv/ºF, so total number of step available
= DigitalO / P
20 ×10−3 2.16 − 1.85
= 108.5 ≈ 109 = (01101101)2 from minimum maximum = = 15.5º F
20 × 10−3
18. How many comparators would a 12-bit flash 2.16
ADC require? Max value is = 108º F & Min value is
(a) 2512 (b) 3095 20 ×10−3
(c) 4095 (d) 4000 1.85
= 92.5 ºF
UPPCL JE 2018, Shift-II 20 ×10−3
Ans. (c) : For n bit conversion flash type ADC requires : 22. What will be the resolution of 12-bit D/A
(i) 2n-1 comparators converter using a binary ladder with 10 V
having the full scale output?
(ii) 2n resistors
(a) 3.50 mV (b) 5.12 mV
(iii) one 2n ×n priority encoder (c) 4.32 mV (d) 1.22 mV
hence, a 12-bit flash ADC (e) 2.44 mV
212-1 = 4095 comparators RSEB JE 2011
Electronics-II 857 YCT
 Vfs 26. Most common error in analog to digital
Ans. (e) : Resolution = converter is
( 2n − 1) (a) Linear error
So, for n = 12 (b) Quantization error
10 10 (c) Random Noise error
= 12 = = 2.44mV
( 2 − 1) 4095 (d) Linear and Quantization error
BSNL TTA 29.09.2016, 3 pm
23. The resolution of a 12 bit analog to digital Ans : (b) Most common error in analog to digital
converter in percent is converter is quantization error because converters have
(a) 0.01220 (b) 0.02441 input quantization. So it needs a small error except
(c) 0.04882 (d) 0.09760 sustained conversion analog to digital converter
ESE-2002 converts input on time. Result is a sequence of digital
Ans. (b) : values.
1 27. What is the value of LSB of an 8 bit DAC for 0-
% Resolution = n × 100
( − 1)
2 12.8V range?
(a) 1.6V (b) 50 mV
1 (c) 0.625V (d) 1.28V
So, for n = 12 = × 100 = 0.02441
( − 1)
212 ESE-2007
24. The resolution of a D/A converter is Vrange
Ans. (b) : LSB of DAC =
approximately 0.4% of its full-scale range. It is 2n
(a) A 8-bit converter (b) A 10-bit converter n = 8 and Vrange = 12.8 V
(c) A 12-bit converter (d) A 16-bit converter 12.8 12.8
DFCCIL JE 11.11.2018 Then, LSB = 8 = = 50mV
2 256
BSNL TTA 29.09.2016, 3 pm
28. The number of comparison carried out in 4-bit
1 flash-type A/D converter is
Ans :(a) % Resolution = N × 100 {N = No. of bits}
2 −1 (a) 16 (b) 15
1 (c) 4 (d) 8
0.4 = N −1 × 100 BSNL TTA 29.09.2016, 3:00 pm
2
0.4 1 BSNL TTA 26.09.2016, 3:00 pm
= Ans : (b) The number of comparison out in 4-bit flash
100 2 N − 1 type A/D converter is 15.
1 Number of comparison = 2n –1
0.004 = N
2 −1 = 24 – 1
1 = 16 – 1
2 −1 =
N
= 15
0.004
2N = 250 + 1 29. A 10-bit D/A converter gives a maximum
2N = 251 output of 10.23 V. The resolution is
2 N ≈ 28 (a) 10 mV (b) 20 mV
So, N = 8 bit (c) 15 mV (d) 25 mV
UPPSC AE 13.12.2020, Paper-II
25. An 8-bit A/D convertor is used over a span of
zero to 2.56V. The binary representation of Ans. (a) : Given, n = 10 bit , Vm = 10.23V
1.0V signal is Resolution (R) = ?
(a) 01100100 (b) 01110001 V
Re solution ( R ) = n m
(c) 10100101 (d) 10100010 2 −1
ESE-2013 10.23
Ans. (a) : Resolution of ADC is a change in Analog =
( 2) −1
10
voltage corresponding to a 1-bit increment.
Vrange 10.23
Resolution (R) = n {n = no. of bits} =
2 −1 1024 − 1
2.56 10.23
Resolution = 8 ≃ 0.01 =
2 −1 1023
We know that,
R = 10mV
Output voltage = Resolution × Decimal
equivalent to binary input. 30. A 6-bit ladder D/A converter has a maximum
V0 = R × D output of 10V. the output for input 101001 is
approximately.
1 = 0.01× D
(a) 4.2 (b) 6.5
D = (100)10 (c) 5.5 (d) 9.2
D = (01100100)2 ISRO TA 2017
Electronics-II 858 YCT
 Reference voltage Vref
Ans. (b) : V= ×Binary equivalent Ans. (d) : % Resolution = × 100
2n ( 2n − 1)
n = number of bit
100
=
V = 6 × ( 25 + 23 + 2 0 )
10
28 − 1
2
100
10 × 41 = = 0.392%
= 255
64
Vfsd
= 6.4V ≅ 6.5V Resolution in volts =
2n − 1
31. Maximum conversion time in clock cycles for
10 10
three types of 8 bit ADCs (i) Successive = 8 = = 0.039 V
approximation, (ii) Dual slope and (iii) Parallel 2 − 1 255
= 39 mV
comparator are respectively
(a) 8,512,1 (b) 8,256,4 35. Consider the following statements :
1. Flash type ADCs are considered the fastest
(c) 16,256,2 (d) 256,8,1 2. In successive approximation type ADCs,
ISRO TA 2017 conversion time depends upon the magnitude
Ans. (a) : Maximum conversion time in clock cycles of the analog voltage
(i) Successive approximation = n clock cycle = 8Tclk 3. Counter-type ADCs work with fixed
(ii) Dual slope = 2n+1 Tclk = 512Tclk conversion time
(iii) Parallel comparator = clock cycle = 1Tclk 4. Dual slope ADCs are considered the slowest
32. An analog output voltage for the input 1001 to Which of the above statements are correct?
(a) 2 and 3 only (b) 2 and 4 only
a 4 bit D/A converter for all possible inputs (c) 1 and 4 only (d) 1 and 3 only
assuming the proportionality factor K = 1 will ESE 2018
be Ans. (c) :
(a) 9 (b) 6 ADC Types Number of Clocks Time period
(c) 3 (d) 1 Counter 2n–1 2n–1T CLK
ESE 2019 SAR n nT CLK
Ans. (a) : Analog output = Resolution × Decimal Flash 1 T CLK
equivalent of given binary input Dual slope 2n+1 2n+1T CLK
= k × 1×23+0×22+0×21+1×20 integrator
= 1 × (8+0+0+1) Hence, we can say that flash type ADC is considered
= 1×9 = 9 the fastest ADC and Dual slope type is considered the
slowest ADC.
33. What is the analog output for a 4-bit R-2R 36. An analog voltage in the range of 0-8V is
ladder DAC when input is (1000)2, for Vref = divided in eight equal intervals for conversion
5V? to 3-bit digital output. The maximum
(a) 2.333 V (b) 2.444 V quantization error is
(c) 2.5556 V (d) 2.6667 V (a) 0V (b) 0.5V
ESE 2017 (c) 1.0V (d) 2.0V
Ans. (d) : Analog output = Resolution × Decimal ESE-2015
equivalent of binary input Ans. (b) : Maximum quantization error
V0 = R ×D ∆
Q e (max) = ∆ → Step size.
V 2
V0 = n ref × decimal equivalent of input digital signal V − Vmin
2 −1 Step size ∆ = max L → No. of levels
5 L
V0 = 4 × 8 8−0
2 −1 ∆= =1
5 8
V0 = × 8 1
15 Q e (max) = = 0.5
8 2
V0 = = 2.66 V 37. The conversion time and conversion rate for a
3 counter type A/D converter which contains 4-
34. An 8-bit DAC uses a ladder network. The full- bit binary ladder and a counter driven by a 4
scale output voltage of the converter is +10V. MHz clock are
The resolution expressed in percentage and in (a) 4 µs and 250 kilo conversion/sec respectively
volts is, respectively (b) 16 µs and 250 kilo conversion/sec respectively
(a) 0.25% and 30 mV (b) 0.39% and 30 mV (c) 2 µs and 500 kilo conversion/sec respectively
(c) 0.25% and 39 mV (d) 0.39% and 39 mV (d) 16 µs and 62.5 kilo conversion/sec respectively
ESE 2018 BIS TA (Lab) 2020
Electronics-II 859 YCT
Ans. (c) : Given that- 41. In a digital voltmeter, the oscillator frequency
Clock rate = 4 MHz = 4 × 106 Hz is 400 kHz. The ramp voltage falls from 8 V to
Counter 4 bit 0 V in 20 ms. What is the number of pulses
counted by the counter?
2n −1 (a) 8000 (b) 4000
Conversion time =
Clock rate (c) 3200 (d) 1600
24 −1 ESE 2009
= Ans. (a) :
4 ×106 Hz No. of pulses counted by the counter
8
= × 10−6 =
Pulse width
4 Time period of oscillator
= 2 × 10–6 sec
= 2 µ sec Wp 20 × 10−3
= =
1 1 1
Conversion rate =
tC f 400 × 103
No. of pulses = 400 × 103 × 20 × 10–3 = 8000
1
= 42. The output voltage of a 5-bit D/A binary ladder
2 ×10−6 that has a digital input of 11010 (Assuming 0=0
= 500 × 103 conversion/sec V and 1 = +10V) is
= 500 kilo conversion/sec (a) 3.4375 V (b) 6.0 V
• Conversion times vary widely from ns for flash ADC (c) 8.125 V (d) 9.6875 V
to µs for successive approximation ADC and hundreds BSNL TTA (JE) 2013
of microsecond for dual slope integrator ADC. Ans. : (c) Input, N =11010
38. What is essential for a successive
= 1 × 24 + 1× 23 + 0 × 2 2 + 1 × 21 + 0 × 20
approximation N bit ADC?
(a) 2N clock pulses for conversion, an up- = 16 + 8 + 2 = 26
downcounter and a DAC. V
V0 = refn × N
(b) N clock pulses for conversion, a binary 2
counter and a comparator. 10 26
(c) 2N clock pulses for conversion and a binary Output voltage (V ) = 5 × 26 = × 10
counter only. 2 32
(d) N clock pulses for conversion, an up-down = 8.125 Volt.
counter and a DAC. 43. If a mod-6 counter is constructed using 3 flip-
JKSSB JE 2014 flops the counter will skip ––––– counts-
Ans. (d) : For a successive, approximation N-bit analog (a) 4 (b) 3
to digital converter (ADC) N clock pulses for (c) 2 (d) 1
conversion, an up-down counter and a digital to analog BSNL TTA 26.09.2016, 10 AM
converter (DAC) are essential. Ans. (c) : If we are using 3 flip-flops, then number of
39. Which of the following ADC has highest total states = 23 = 8
accuracy? For mod-6 counter,
(a) Successive is approximation type Used state in mod-6 counter = 6
∴ Unused state = 8 – 6 = 2
(b) Flash or parallel type
So, the counter will skip 2 counts.
(c) Single slope integration type
(d) Dual slope integration type 44. Sample and hold circuits in analog to digital
ESE 2014 converters (ADCs) are designed to :
(a) sample and hold the output of the binary
Ans. (d) : Dual slope ADC has greater noise immunity counter during the conversion process
compare to other ADC types. It is the slowest ADC (b) stabilize the comparator's threshold voltage
among all types ADC and it has highest accuracy. during the conversion process
40. The full scale output of an 8 bit DAC for 0 to (c) stabilize the input analog signal during the
10 V range is conversion process
(a) 1.961 V (b) 9.961 V (d) sample and hold the D/A converter staircase
(c) 96.11 V (d) 1.996 V waveform during the conversion process
UKPSC JE 2013, PAPER-I BSNL TTA 28.09.2016, 10 AM
Ans. (b) : Full scale output = (Full scale voltage - LSB) Ans. (c) : Sample and hold circuits in analog to digital
 10  converters (ADC) are designed to stabilize the input
= 10 − 8  analog signal during the conversion process.
 2  Analog to digital converters use a constant
= 10 - 0.03906 approximation type ADC sample and hold circuit
= 9.96094 separate from ADC, where the signal remains constant,
= 9.961V while A to D conversion is taking place.
Electronics-II 860 YCT
45. A 'n' bit flash type ADC requires maximum of 49. The resolution of an n bit D/A converter with a
–––– to complete conversion maximum input of 5V is 5mV. The value of n is-
(a) "n" Clock pulses (a) 8 (b) 9
(b) "2n+1" Clock pulses (c) 10 (d) 11
(c) one clock pulse BSNL TTA 26.09.2016, 3 PM
(d) "2n–1" Clock pulses Ans : (c) Given, Resolution = 5mV
BSNL TTA 28.09.2016, 10 AM Maximum input Vmax = 5V
Ans. (c) : A 'n' bit flash type ADC requires maximum We know that-
of one clock pulse to complete conversion. Flash type V
ADC conversion is also known as parallel comparator Resolution = nmax
2 −1
ADC or some time is called converter. This is the 5
highest speed ADC. 5mV = n
46. Consider the following statements. The A to D 2 −1
converter used in a digital instrument could be 2 n − 1 = 1000
(i) Successive approximation converter type. n = 9.962
(ii) Flash converter type. n ≃ 10
(iii) Dual slope converter type. 50. An 8-bit successive approximation A-to-D
The Correct sequence in the increasing order converter is driven by a 2 MHz clock. Its
of the conversion time taken by these types are conversion time is
(a) (i), (ii) and (iii) (b) (ii), (i) and (iii) (a) 18 µs (b) 16 µs
(c) (i), (iii) and (ii) (d) (ii), (iii) and (i)
(c) 8 µs (d) 4.5 µs
ESE 2010 ESE 2016
Ans. (b) :
Ans. (d) : Conversion time = ADC Clock period × No.
ADC Types Time period of bits being converted
Counter 2n–1T CLK
1
SAR nT CLK = × 8 = 4µs
Flash T CLK 2 ×106
Dual slope integrator 2n+1T CLK • Conversion times vary widely from ns for flash ADC
Flash type < SAR < Counter < Dual slop integrater to µs for successive approximation ADC and hundreds
47. A 4-bit R/2R digital to analog (DAC) converter of microsecond for dual slope integrator ADC.
has a reference of 5 volts. What is the analog 51. Resolution of analog to digital converter
output for the input code 1010? ranging from –5V to +5V with 8 bits coding is-
(a) 0.3125 V (b) 3.125 V (a) 3.9V (b) 0.39V
(c) 1.5625 V (d) 3.75 V (c) 3.9mV (d) 39mV
UPPSC AE 13.12.2020, Paper-II BSNL TTA 26.09.2016, 3 PM
BSNL TTA 28.09.2016, 3 PM Ans : (d) Given Data-
Ans. (b) Given, VR = 5Volts Range of input = –5 to 5 = 10V
Number of bit (k) = 8
Digital input code=1010 Vrange 10 10
In decimal = 10 Resolution of ADC = n
= 8 =
For R/2R Ladder DAC- 2 2 256
V Resolution = 39.06 mV
V0 = refn ( Binary equivalent decimal ) 52. Analog-to-digital converter with the minimum
2 number of bits that will convert analog input
5 50 signals in the range of 0-5 V to an accuracy of
V0 = × 10 = = 3.125
16 16 10 mV is
48. Quantization error occurs in ––––––– systems. (a) 6 (b) 9 (c) 12 (d) 15
(a) Analog to digital conversion ESE 2016, 2003
(b) Digital to analog conversion Ans. (b) : Accuracy of an ADC is equivalent to
(c) Both analog to digital conversion & digital to resolution or error .
analog conversion V
(d) None of these Resolution = n FS
2 −1
BSNL TTA 28.09.2016, 3 PM 5
Ans. (a) The difference between an input value and its 10mV = n
quantized value is called a quantization error. An analog 2 −1
−3 5
to digital converter (ADC) works as a quantizer. For a 10 × 10 = n
sine wave, quantization error appears as extra 2 −1
harmonics in the signal for music or program material, 1000
2n − 1 = = 500
the signal is constantly changing and quantization error 2
appears as wideband noise, clearly referred to as 2 n − 1 = 500
"quantization noise" it is extremely difficult to measure
2 n = 501
or quantization noise, since it only exists when a signal
is present. n≈9

Electronics-II 861 YCT

53. An 8-bit DAC has resolution of 20mV/LSB. Ans. (c) : Number of comparator = 2n –1
Find V0 if the input is (10000000)2 = 23 − 1 = 7
(a) 256V (b) 2560V
57. The accuracy of A/D conversion is generally
(c) 2.56V (d) 25.6V
1
MPPEB Sub. Engineer 0.8.07.2017 Shift-I (a) ± LSB (b) ± LSB
Ans. (c) : Analog output voltage 2
5
= Resolution × Decimal equivalent of binary data (c) ± LSB (d) None
= 20 × 10–3 × 128 4
= 2.560 Volt JPSC AE 10.04.2021, Paper-I
54. The reference voltage and the input voltage are Ans. (a) : A/D converter stands for analog to digital
sequentially connected to the integrator with converter.
the help of a switch in a (i) Voltage Range
(a) Successive approximation A/D converter Voltage range = Vmax – Vmin
(b) Dual slope integration A/D converter (ii) Resolution
(c) Voltage to time converter Vrange
(d) Voltage to frequency converter Resolution = n
2 −1
ESE 2005 1
Ans. (b) : Dual slope integration ADC - (iii) Accuracy = ± LSB
2
58. Find the resolution of a 10-bit AD converter for
an input range of 10V?
(a) 97.6 mV (b) 9.77 mV
(c) 0.977 mV (d) 0.786 mV
JPSC AE 10.04.2021, Paper II
Ans. (b) : For n - bit ADC
V 10
Resolution = n ref = 10
2 −1 2 −1
10
Resolution = = 9.77mV
1023
During discharging the capacitor, the reference voltage 59. A binary input 000 is fed to a 3 bit DAC/ADC.
and the input voltage are connected to the integrated The resultant output is 101. Find the type of
with the help of a switch in a dual slope integration error.
ADC. (a) Settling error
(b) Gain error
55. If the range of an analog transducer is 0 to
(c) Offset error
10V, then for a resolution of 5mV, the bits of
(d) Linearity error
ADC will be...............
JPSC AE 10.04.2021, Paper II
(a) 8 (b) 9
(c) 10 (d) 11 Ans. (c) : Offset error implies that the output of the
SSC JE 02.03.2017, Shift-II DAC is not zero when the binary inputs are all zero.
Ans : (d) Output voltage of ADC is given 60. Find out the integrating type analog to digital
V0 = k ( 2n − 1)
converter from the following.
(a) Flash type converter
Where, k = resolution (b) Tracking converter
n = number of bits. (c) Successive approximation type converter
10 = 5 × 10–3(2n–1) (d) Dual-slope analog to digital converter
10 10 × 103 UPPSC AE 13.12.2020, Paper-II
2n − 1 = =
5 ×10−3 5 Ans. (d) : The example of integrating type analog to
2 − 1 = 2000
n digital converter is dual slope analog to digital
2n = 2001 converter. An integrating analog to digital converter is a
n = 11 bits (approximate) type of analog to digital converter that converts an
unknown input voltage into a digital representation
56. The comparators required in a 3-bit
through the use of an integrator.
comparators type ADC is
Dual slope ADC slowest among all.
(a) 2 (b) 3
Most accurate ADC
(c) 7 (d) 8
Maximum conversion time = 2n+1 TCLK
MRPL (Tech. Asstt. Trainee), 21.02.2021
Electronics-II 862 YCT
 VI. Logic Families Ans. (c) :

1. TTL circuits with active pull up are preferred

because of their suitability for-
(a) Wire and operation
(b) Bus operated system
(c) Wired logic operation
(d) Reasonable dissipation and speed of operation
MRPL (Tech. Asstt. Trainee), 21.02.2021
BSNL TTA 26.09.2016, 3 PM A pull-up resistor pulls-up the data line to high voltage.
Pull-up resistor connects unused input pins (AND and
Ans : (d) TTL circuits with active pull-up are preferred
NAND gate) to the dc supply voltage (VCC) to keep the
because of their reasonable dissipation and speed given input high. It's needed for an open collector gate
operation. In standard TTL families, Totem pole output provided the high voltage.
transistor are often used to improve switching speeds. In
this circuit, the bottom transistors (Tu) provides the active 7. TTL stands for:
pull down and upstream transistor (T3) active pull-up. (a) Transistor-Transistor Logic
(b) Transistor-Thermocouple Logic
2. Which of the following logic gates dissipates (c) Transistor-Thermostat Logic
minimum power? (d) Transistor-Thermistor Logic
(a) RTL (b) TTL MPPKVVCL (Jabalpur) JE -2018
(c) MOS (d) ECL
Ans. (a) : TTL - transistor - transistor logic
UPPCL JE-07.09.2021, Shift-II TTL is a logic family that has been in operation for a
BSNL TTA 29.09.2016, 10 AM long time and is considered as standard.
Ans : (c) MOS logic gates dissipates minimum power TTL is a modification of the DTL (diode transistor
while ECL logic gates dissipates maximum power MOS logic) gate.
logic gates are very useful for fabrication of ICS due to 8. Which one of the following is not a
less area covered on chip area so, large no. of gates characteristic of RTL logic families?
fabricated on a single chip. (a) High switching speed
3. Which of the following IC logic families has (b) Poor noise immunity
minimum value of fan-out? (c) Low power dissipation
(a) Low power Schottky TTL (d) Fan out is 5
(b) ECL ESE 2010
(c) Standard TTL Ans. (a) : Characteristics of RTL logic family :-
(d) CMOS • The basic RTL device is a NOR gate.
UPPCL JE- 08.09.2021, Shift-II • RTL does not have high switching speed.
Ans. (c) : The fan-out is the number of gate inputs • Poor noise margin.
driven by the output of another single logic gate. • Low power dissipation.
standard TTL has minimum value of Fan out. • Low speed.
4. The basic circuit for the ECL family is the • Poor fan out capability.
_____________ gate.
9. In TTL family HIGH output corresponds to:
(a) AND (b) OR/NOR (a) 2.4 V to 5 V (b) 2 V to 5 V
(c) NAND (d) XNOR (c) 0.8 V to 2 V (d) 0.4 V to 2.4 V
UPPCL JE- 08.09.2021, Shift-II MPPKVVCL (Jabalpur) JE -2018
Ans. (b) : ECL (Emitter Coupled Logic) is a high speed Ans. (a) : The two voltage level of the TTL gate are 0
integrated circuit bipolar transistor logic family. The to 0.2 V for the low level and from 2.4 to 5V for the
basic circuit for the ECL family is OR/NOR gate it is high level.
the fastest of all digital logic families.
10. The following circuit behaves as a:
5. SSI refers to ICs with
(a) Less than 12 gates on same chip
(b) Less than 8 gates on same chip
(c) Less than 6 gates on same chip
(d) Less than 3 gates on same chip
HPSSSB JE-2017 (Post code- 579)
Ans. (a) : Small Scale Integration (SSI) refers to ICs
which has less than 12 gates on same chip.
6. Pull-up register is needed for an open collector
gate
(a) to provide VCC for the IC
(b) to provide ground for the IC
(c) to provide the HIGH voltage (a) AND Gate (b) NAND Gate
(d) to provide the Low voltage (c) OR Gate (d) NOR Gate
ESE 2012 MPPKVVCL JE-2018
Electronics-II 863 YCT
Ans. (d) : When both the inputs will be low the 15. When the output of a tri-state shift register is
transistor will not ON and the supply voltage will come disabled, the output level is placed in a
across output (a) float state
Vout = +6V = logic1 (b) low state
(c) high impedance state
and in any other case (0,1)(1,0)(1,1) output will be at (d) float state and a high impedance state
logic 0 ESE 2013
for NOR gate Ans. (d) : A tri-state shift register has an output enable
Y =A+B pin.
11. In the CMOS inverter, the power dissipation is If, output enable pin = 1 (set) then contents present on
(a) low only when VIN is low its output pins.
(b) low only when VIN is high output enable pin = 0(reset) then output pins are in a
(c) high during dynamic operation high impedance state or floating state and tri-state shift
(d) low during dynamic operation register is disabled.
ESE 2001 16. As far as speed is concerned, the fastest type of
Ans. (d) : The total power of CMOS inverter is logic is
combined of static power and dynamic power. During (a) TTL (b) RTC
dynamic operations, the power dissipation of CMOS (c) Schottky TTL (d) ECL
inverter is very low. BSNL TTA 29.09.2016, 3 pm
12. Which of the following logic families dissipates Ans : (d) As for as speed is concerned the fastest type
of logic is ECL because of the emitters of many
minimum power? transistors are coupled together which results in the
(a) CMOS (b) DTL highest transmission rate.
(c) ECL (d) TTL
17. How is the speed-power product of a logic
UPJN 2013
family determined?
Ans : (a) (a) The propagation delay in ms is multiplied by
CMOS logic family dissipates minimum power. the power dissipation in mW.
In CMOS P-channel and n-channel MOSFET device (b) The propagation delay in ms is multiplied by
are fabricated on the same chip, which makes it the power dissipation in mW.
fabrication more complicated and reduce the package (c) The propagation delay in ns is multiplied by
density but it passes the important advantage of higher the power dissipation in mW.
speed and low power consumption which make it (d) The propagation delay is ns is multiplied by
suitable for the use in battery operated system. the power dissipation in W.
13. The standard 2-input TTL gate for the below ESE 2013
shown electrical symbol is_____: Ans. (c) : Figure of merit is a product of propagation
delay and power dissipation. Propagation delay is in
terms of nano sec. (ns) and power dissipation in terms
of milliwatt (mW).
(a) 7400 (b) 7402 Figure of merit = propagation delay × power dissipation
(c) 7410 (d) 7500 = ns × mW
SSC JE 01.03.2017, Shift-I = pJ
Ans : (a) 18. The most commonly used logic family is
(a) ECL (b) TTL
(c) CMOS (d) PMOS
HPSSC JE 2017(Code-580)
The standard 2-input TTL gate for the below shown Ans. (c) : The most commonly used logic family is
electrical symbol is 7400. CMOS. The main family CMOS (Complementary metal
for NAND gate with 3 input – 7410 oxide semiconductor) made from MOSFETs, ECL
for NOR gate with 2 input – 7402 (Emitter coupled logic).
14. The fan out value of Transistor Transistor 19. The integrated injection logic has high density
Logic (TTL) is: of integration than TTL because it
(a) 25 (b) 10 (a) does not require transistors with high current
(c) 50 (d) 20 gain and hence they have smaller geometry
UPPCL JE 27.11.2019, Shift-I (b) uses bipolar transistor
Ans : (b) Fan out is the number of gate inputs driven by (c) does not require isolation diffusion
the output of another single logic gate. (d) uses dynamic logic instead of static logic
Logic family Number of fan out ESE 2013
RTL 5 Ans. (b) : In the integrated injection logic (I2L) family,
DTL 8 p-n-p and n-p-n transistors are integrated. Due to this
TTL 10 reason transistors will take less space. So the density of
ECL 25 I2L family is more than any other logic family.

Electronics-II 864 YCT

20. The figure of merit of a logic family is given by– • B (OR) C = (B + C)
(a) Gain × bandwidth • A (AND) B (OR) C = A.(B + C)
(b) Propagation delay time × power dissipation • D (AND) E = D.E
(c) fan-out × propagation delay time Hence, F = [A (AND) B (OR) C] (NOR) [D (AND) E]
(d) Noise margin × power dissipation
F = A.(B + C) + D.E
BSNL TTA (JE) 2013
Ans. : (b) Figure of merit 24. Which one of the following is not a
= Propagation delay time (ns) × Power dissipation (mW) characteristic of CMOS configuration?
• For the best operation of ICs, figure of merit (FOM) (a) CMOS devices dissipate much lower static
should be as small as possible. power than bipolar devices
(b) CMOS devices have low input impedances
21. What is the major advantage of ECL logic?
(c) CMOS devices have higher noise margins
(a) very high speed
(d) CMOS devices have much lower
(b) wide range of operating voltage
transconductance than bipolar devices
(c) very low cost
ESE 2006
(d) very high power
BSNL TTA (JE) 2013 Ans. (b) : Characteristics of CMOS family :-
Ans. : (a) The major advantage of ECL logic is it has very • Very large fan-out (>50).
high speed of operation. ECL offers an incredible delay of • Excellent noise immunity amongst all logic families.
only 1ns. It offers high speed operation by employing a • High input impedance.
relatively small voltage swing and preventing transistor • Least propagation delay in comparison with TTL and
from entering in saturation region. CMOS fan out capacity ECL.
>50 and its power dissipation is 0-0.01 mW. • Works well over a wide range.
22. Which one of the logic families has maximum 25. The noise margin of a TTL gate is about-
fan-out capacity? (a) 0.2 V (b) 0.4 V
(a) RTL (b) ECL (c) 0.6 V (d) 0.8 V
(c) MOS (d) CMOS BSNL TTA 28.09.2016, 3 PM
BSNL TTA 28.09.2016, 10 AM Ans. (b) Noise Margin- Maximum noise that can be
Ans. (d) : The CMOS logic families has the maximum tolerated without affecting the performance.
fan out capacity among all logic families, as it has low (NM) H = VOH − VIH
power loss. In CMOS logic, p-type and n-type
MOSFET are fabricated on a single chip. (NM) L = VIL − VOL
Although CMOS is slower than other logic families. Its NM = ( VNH − VNL )
packing density is high.
Parameter TTL ECL
23. An NMOS circuit is shown in the below figure.
Fan out 10 25
The logic function for the output (output) is
Propagation delay 10ns 500ps
Power dissipation 10mW 50mW
Noise margin 0.4 V 0.3V
Figure of merit
or 144-132pJ 55 – 160 pJ
Speed power
product
Hence, The noise margin of TTL gate is about 0.4 V.
26. Which out of the following logic family is most
expensive?
( A + B).C + D.E. ( )( )
(a) RTL (b) TTL
(a) (b) AB + C . D + E (c) DTL (d) ECL
BSNL TTA 28.09.2016, 3 PM
(c) A.( B + C ) + D.E (d) ABCDE
Ans. (a) The basic RTL device is a NOR gate. Inputs
ESE 2001 represent either logic HIGH (1) or Low (0). It involved
Ans. (c) : a minimum number of transistor, which was an
important consideration before integrated circuit
technology, as transistors were the most expensive
component to produce, therefore RTL is most expensive
device.
27. Switching speed of ECL logic is very high
because-
(a) It uses positive logic
(b) It uses negative logic
(c) It uses high speed transistors
(d) Its transistors remain unsaturated
BSNL TTA 28.09.2016, 3 PM
Electronics-II 865 YCT
Ans. (d) Switching speed is always determined in 31. An inverter gate has guaranteed output levels as:
terms of the access time. During switching any device logic '1' = 3.8V and logic '0' = 0.7V. The maximum
may take more access time in the saturation region, low level input voltage at which the output remains
whereas in the ECL logic as the transistor is prevented high = 2V. The minimum high level input voltage
from going into the saturation, results in very low at which the output remains low = 3.1V. What are
access time i.e. high switching speed. the noise margins of this gate?
28. Which one of the following statements is (a) NMH = 2.4V, NML = 1.8V
correct? Removing the small resistance (b) NMH = 1.8V, NML = 1.3V
(~100Ω) in the collector lead of the pull-up (c) NMH = 0.7V, NML = 1.8V
transistor of a totem pole output gate, will (d) NMH = 0.7V, NML = 1.3V
result in ESE 2004
(a) reduced switching time from Vout(1) to Vout (0)
Ans. (d) : Noise margin at high level logic
(b) incorrect operation of the gate
(c) lower power dissipation NMH = (VOH(min) ∼ VIH(min))
(d) more noise generation in the power supply = 3.8 – 3.1
distribution at high frequency = 0.7V
ESE 2005 Noise margin at low level logic
Ans. (d) : When we remove the small resistance NML = (VOL(max) ∼ VIL(max))
(~100Ω) in the collector lead of the pull-up transistor of = (2 – 0.7)
a totem pole output gate, more noise power generate in = 1.3 V
the power supply distribution at high frequency. NMH = 0.7V, NML = 1.3V
29. The below shown NMOS circuit is a gate of 32. The figure of merit of logic family is often
type measured in the unit of :
(a) megahertz (b) picojoules
(c) nanoseconds (d) microwatts
KVS WET 2017
Ans. (b) : Figure of merits is a product of propagation
delay(ns) and power dissipation(mW). It is measured in
terms of picojoule(pJ). Current and voltage parameters
define the minimum and maximum limits of current and
voltage for input and output of a logic family.
33. Arrange the following logic families in the
(a) NAND (b) NOR order of increasing speed : CMOS, low power
(c) AND (d) EXCLUSIVE-OR Schottky TTL, ECL, Schottky TTL, low power
ESE 2005, 2003 TTL, TTL :
Ans. (a) : In given circuit, output will be Low(0) only (a) Low power TTL, CMOS, TTL, Schottky
when Both input (A and B) are high (1) and for other TTL, low power Schottky TTL and ECL
inputs, output will be high. (b) ECL, Schottky TTL, low power Schottky
Hence, we can say that the given circuit is a NAND TTL, TTL, low power TTL and CMOS
gate. (c) TTL, low power TTL, ECL, CMOS, low
A B Y power Schottky TTL, Schottky TTL.
(d) CMOS, low power TTL, TTL, low power
0 0 1 Schottky TTL, Schottky TTL and ECL.
0 1 1 KVS WET 2017
1 0 1 Ans. (d) : The ECL (Emitter coupled logic) have
highest speed and consume more power because CMOS
1 1 0
and TTL families can now operate at similar speed
Y = AB means low speed.
30. The logic which has the highest speed is? The arrangement of logic families increasing order speed
(a) DTL (b) RTL CMOS < low power TTL < TTL < low power Schottky
(c) ECL (d) TTL TTL< Schottky TTL < ECL.
BSNL TTA 26.09.2016, 3 PM
ESE 2001 34. A Darlington emitter follower circuit is
Ans : (c) ECL is a non saturated logic. sometimes used in the output stage of a TTL
It is the fastest logic among the all logic family gate in order to-
hence called "current mode logic". (a) increase its IOL
It provides wired "OR" logic. (b) reduce its IOH
It uses negative power supply to avoid glitches and (c) increase its speed of operation
noise. (d) reduce power dissipation
Any floating input in ECL is considered as logic '0'. BSNL TTA 29.09.2016, 10 AM
Electronics-II 866 YCT
Ans : (c) The advantage of using an arrangement such Ans. (d) : Not gate transistor circuit-
as this, is that the switching transistor is much more
sensitive as only a tiny base current is required to switch
a much larger load current as the typical gain of a
Darlington configuration can be over 1000. So a
Darlington emitter follower circuit is sometimes used in
the output stage of a TTL gate in order to increase its
speed of operation.
35. Which of the 74 series of TTL-IC has the best
figure of merit–
(a) 74H (b) 74L
(c) 74LS (d) 74ALS
BSNL TTA 29.09.2016, 10 AM
Ans : (d) 74ALS of the 74 series of TTL-IC has the
best figure of merit. Figure of merit is a product of
propagation delay and power dissipation It is measured A NOT gate simply inverts inputs. If the input is high,
in terms of Pico-Joules (pJ). 74 ALS has a pJ figure of the output is low, and if the input is low, the output is
merit. 74ALS, L represents Low dissipation. In 74 high. Such a circuit is easy to build, using a single
series, the input impedance is very high, so the power
transistor and a pair of resistors.
dissipation is very low. In 74 series time propagation
delay is 9 nano second. When even number of not gates are connected in series
then it acts as like buffer circuit.
36. Transistor-Transistor Logic (TTL) is a class of
digital circuits built from 39. The minimum number of pins required in an
(a) Transistors only (b) BJT IC with two 4-input gates is
(c) resistors (d) BJT and resistors (a) 12 (b) 14
Haryana SSC JE 08.04.2018, Shift-I (c) 16 (d) 18
Ans. (d) : Transistor-Transistor Logic (TTL) is a class HPSSSC JE 2018 Code -387
of digital circuits built from bipolar junction transistors Ans. (b) : The CD4012 is a CMOS technology based, 4
(BJT) and resistors. However resistors have a small role input NAND gate. Dual package, i.e. the IC has two
to play and both logic gate and amplifying functions are NAND gates which can operate independently and each
performed by the transistors. gate can take in four inputs. It is commonly used in
37. The factor is not important while selecting a buffer circuits, logic inverter circuit etc. It is also
logic technology is- available in 14 pin PDIP, GDIP, PDSO packages. IC
(a) Cost (b) Power dissipation CD4012 circuit is shown below.
(c) Number of pins (d) Speed of operation
BSNL TTA 26.09.2016, 10 AM
Ans. (c) : The factor is important while selecting a
logic technology is-
Cost
Power dissipation
Speed of operation
Size.
But "numbers of pins" is not important factor while 40.
In a 2 input CMOS logic gate, one input is left
selecting a logic technology. floating i.e. connected neither to ground nor to
38. Which one is a NOT gate ? a signal. What will be the state of that input?
(a) 1
(b) 0
(c) same as that of the other input
(d) indeterminate (neither 1 nor 0)
ESE 2015
Ans. (d) : A CMOS digital input has very high
impedance. CMOS inputs are sensitive to high voltages
generated by electrostatic sources and can be triggered
into high (1) or low (0) states.
As a result, when it is not triggered, it will float creating
undetermined input logic level as neither 1 nor 0.
41. Which one of the following logic families can be
------ using supply voltage from 3V to 15 V ?
(a) TTL (b) ECL
(c) PMOS (d) CMOS
KVS WET 2017 BSNL TTA 25.09.2016, 3:00 P.M.
Electronics-II 867 YCT
Ans : (d) CMOS can supply 15V. CMOS is short form 2. When the input to a seven segment decoder is
of complementary MOSFET. It has two MOSFET with "0100" the number on display will be-
both N-channel & P-channel. Both MOSFETs operate (a) 0 (b) 2
in common source mode. This circuit works as an (c) 4 (d) 9
inverter amplifier. TTL are operated with the supply BSNL TTA 21.02.2016
BSNL TTA 25.09.2016 3pm.
voltage from 0V to 5V.
Ans : (c) When the input to a seven segment decoder is
42. Technology used for manufacturing of RAM "0100" the number on display will be 4. 7 Segment
for computing devices is LED display is widely used in digital system. This
(a) NMOS (b) PMOS display is used to change the BCD data.
(c) CMOS (d) FET
BSNL TTA 29.09.2016, 10 AM
Ans : (c) CMOS technology:- complementary metal-
oxide-semi conductor (CMOS) is used to construct ICs
and this technology is used in digital logic circuits,
The decoder circuit consist of four input line ABCD.
microprocessors, microcontrollers and static RAM. The through which BCD input is given. Decoder has 7
main features of CMOS technology are low static power output lines.
consumption and high noise immunity 3. In radiating coupling, the emitter radiation
43. Which of the following logical operations could field
be computed by the given network? (a) Decays as 1/R where R is the separation
distance between the emitter and the receptor
(b) Decays as R, where R is the separation
distance between the emitter and the receptor
(c) Decays as 1/2R, where R is the separation
distance distance between the emitter and the
receptor
(d) Decays as 2R, where R is the separation
(a) C = AB (b) C = A+B distance between the emitter and the receptor
(c) C = AB (d) C = A + B Karnataka PSC JE 2017
SSC JE 10.12.2020, Shift-II Ans. (a) : In radiating coupling, the emitter radiation
Ans (b) : 1
field decays as , where R is the separation distance
R
between the emitter and the receptor.
4. An infra Red LED is usually fabricated from
(a) Ge (b) Si
(c) GaAs (d) GaAsP
KSEB Sub Engineer 2015
Ans. (c) : GaAs → Red
Truth Table:- GaAsP → Green, Yellow
A B D1 D2 Y 5. Which of the following is not a fundamental
0 0 OFF OFF 0 property of a laser light?
0 1 OFF ON 1 (a) It possesses high degree of coherence
1 0 ON OFF 1 (b) It can be generated with low intensity
1 1 ON ON 1 (c) It can be produced with narrow line width
(d) It can be produced with narrow beam width
VII. Display Devices MPPKVVCL JE-2018
Ans. (b) : Lasers have three properties:- Coherency,
1. Which is not most commonly used display in collimation and monochromatic properties.
LASER- Light Amplification by stimulated Emission of
the digital electronics field? Radiation.
(a) Incandescent display 6. Find the value of R in the circuit shown, so that
(b) Micro-phoretic image display a current of 20 mA flows through the "on"
(c) Liquid vapour display diode. Both the diodes have a reverse
(d) Gas discharge plasma display breakdown voltage of 3 V and an average turn-
UPPCL JE- 08.09.2021, Shift-I on voltage of 2 V.
Ans. (b) : Most commonly used display in digital
electronics field are incandescent display, liquid vapour
display and gas discharge plasma display. These give
better visualization.
Micro-phoretic image display can not commonly used
display in the digital electronics field.
Electronics-II 868 YCT
 (a) 30Ω (b) 300Ω 9. A logic probe is placed on the output of a
(c) 3KΩ (d) 30KΩ digital circuit and the probe lamp is dimly lit.
MPPKVVCL JE-2018 This display indicates –––––––––
Ans. (b) : (a) That an open or bad logic level exists
(b) A high level output
(c) A high-frequency pulse train
(d) That the supply voltage is low
BSNL TTA 26.09.2016, 10 AM
Ans. (a) : A logic probe is placed on the output of a
digital circuit and the probe lamp is dimly lit. This
display indicates that an open or bad logic level exists.
10. A device used to display one or ------ signals so
that they can be compared to expected timing
diagrams for the signals is a:
(a) DMM (b) Spectrum analyzer
(c) Logic Analyzer (d) Frequency counter
BSNL TTA 25.09.2016, 3:00 P.M.
Ans : (c) A device used to display one or more signals
Green diode is connected with forward & Red diode so that they can be compared to expected timing
connected in Reverse biased mode.
diagrams for the signals is a logic analyzer.
So,
Red diode is turn off. 11. BCD input 1000 is fed to a segment display
through a BCD to 7 segment decoder/driver.
V 8− 2 6 ×10 3
Then R= = = = 300 Ω The segments which will lit up are?
I 20 × 10−3 20 (a) a, b, d (b) a, b, c
7. Which of the following is required for the (c) a, b, g, c, d (d) a, b, g, c, d, e, f
LEDs for their display? BSNL TTA 27.09.2016, 3 PM
(a) a voltage of 1.2 V and a current of 100 mA Ans : (d) BCD input displays 8 in 1000 decimals to
(b) a voltage of 25 V and a current of 25 mA display 8 in 7 segments.
(c) a voltage of 15 V and current of 20 mA
(d) a voltage of 25 V and a current of 25 mA
(e) a voltage of 1.2 V and a current of 20 mA
RSEB JE 2011
Ans. (e) : Most common LED's require a forward
operating voltage of between approximately 1.2 to 3.6
Fig-seven segment display
volts with a forward current rating of about 10 to 30mA,
with 12 to 20 mA being the most common range. 12. A Ruby MASER is considered to be superior to
an Ammonia MASER because of-
8. Which logic inputs should be given to the input
(a) high power output
lines I0, I1, I2 and I3, if the MUX is to behave as
(b) low signal to noise ratio
two point input XNOR gate? (c) greater bandwidth
(d) Low amplification factor and low noise level
BSNL TTA (JE) 2013
Ans. : (c) A ruby maser is superior to ammonia maser
on the behalf of greater bandwidth.
13. Laser is a-
(a) Light source
(b) Light detector
(c) Both light source & light detector
(d) None of these
BSNL TTA 26.09.2016, 10 AM
(a) 0110 (b) 1001 Ans. (a) : Laser is a light source. It is a device that
(c) 1000 (d) 1111 stimulates atoms or molecules to emit light at particular
ESE 2017 wavelength and amplifies that light, typically producing
Ans. (b) : For XNOR gate, f = xy + x y.....(i) a very narrow beam of radiation.
LASER stands for- "Light Amplification by
output of the MUX
Stimulated Emission of Radiation."
( ) ( ) ( )
f = Io xy + I1 xy + I 2 xy + I3 ( xy ) .....(ii) 14. Laser light is different from others because-
For both equations (i) and (ii) to be equal (a) It is coherent (b) It is incoherent
Io = 1, I1 = 0, I 2 = 0, I3 = 1 (c) High intensity (d) High speed
BSNL TTA 26.09.2016, 10 AM
Electronics-II 869 YCT
Ans. (a) : A laser (LASER - Light Amplification by 19. Laser light is intense because-
Stimulated Emission of Radiation) is a monochromatic (a) It has very less number of photons that in
and coherent source of radiation that emits one specific phase
frequency or wavelength of radiation. (b) It has very less number of photons that are
15. Which of the following are the characteristics not in phase
of LASER beam (c) It has very large number of photons that are
1. Directionality in phase
2. Coherence (d) It has very large number of photons that are
3. Monochromaticity not in phase
options. BSNL TTA 26.09.2016, 3 PM
(a) 1 & 2 only (b) 1 & 3 only Ans : (c) Laser light is intense because it has very large
(c) 2 & 3 only (d) 1, 2 & 3 number of photons that are in phase. Its spectral
BSNL TTA 28.09.2016, 10 AM intensity in a narrow bandwidth would be for greater
Ans. (d) : LASER (Light amplification by stimulated than sunlight.
Emission of Radiation). A laser is an unusual light 20. Laser is a device for :
source. (a) production of beam of white light
Characteristics of LASER beam - (b) producing a beam of non-chromatic light
(I) Directionality (c) producing a beam of high intensity rays
(II) Coherence (Spatial and temporal) (d) producing a beam of highly penetrating x–
(III) Monochromaticity rays
(IV) Brightness BSNL TTA 25.09.2016, 3:00 P.M.
16. LCDs have response time of the order of Ans : (c) Laser is a device for producing a beam of
(a) is few ns high intensity rays.
(b) tens of ns 21. The colour of the light emitted by LED depends
(c) a few milliseconds on the type of material. Which light is emitted
(d) hundred of milliseconds when the LED is reverse biased?
BSNL TTA 28.09.2016, 10 AM (a) Green (b) Yellow
Ans. (d) : LCDs have response time of the order of (c) Red (d) No light
UPRVUNL JE-24.10.2021, 9AM-12PM
hundred of milliseconds. There is less power loss in
this. Its turn ON and turn OFF time is more. It is mostly Ans. (d) : The colour of the light emitted by LED
used in calculators and digital watches as it is often depends on the type of material. No light is emitted
available in these formats. Its operation requires AC when the LED is reverse biased.
voltage in place of DC, which often has a frequency 22. ________ Bit is an extra bit added to a string of
between 30Hz to 1000 Hz. The response time of LCD is data bits in order to detect any error that
100ms - 300 ms. might have crept into it while it was being
17. Laser light is –––––––– emission. stored or processed and moved from one place
(a) Coherent to another in digital system.
(a) Hamming (b) Repetition
(b) Stimulated
(c) Cyclic (d) Parity
(c) Spontaneous
UPRVUNL JE-24.10.2021, 9AM - 12PM
(d) Coherent and stimulated
BSNL TTA 28.09.2016, 3 PM Ans. (d) : Parity bit is an extra bit added to a string of
data bits in order to detect any error that might have
Ans. (d) Light Amplification by Stimulated crept into it while it was being stored or processed and
Emission of Radiation (Laser):- It is a device that moved from one place to another in digital system
emits light through a process of optical amplification
23. This BCD code is used for arithmetic
based on the stimulated emission of electromagnetic
operations as it overcomes the shortcomings
radiation. Laser can also have high temporal coherence,
encountered while using 8421 BCD code to add
which allows them to emit light with a very narrow
two decimal digits whose sum exceeds 9. What
spectrum, i.e. they can emit a single colour of light. is this code?
18. Potential energy source for inducing fusion (a) 4221 BCD code
reaction is- (b) Higher density BCD code
(a) X-ray (b) Laser (c) Excess 3 BCD code
(c) Ultraviolet (d) Microwave (d) 5421 BCD code
BSNL TTA 28.09.2016, 3 PM UPRVUNL JE-24.10.2021, 9AM-12PM
Ans. (b) Potential energy source for inducing fusion Ans. (c) : This BCD code is used for arithmetic
reaction is laser. Nuclear fusion is the phenomenon of operations as it overcomes the shortcomings
combining or fusing two or more lighter nucleus to encountered while using 8421 BCD code to add two
form a more stable heavy nucleus with the liberation of decimal digits whose sum exceeds 9. This code is
vast amounts of energy. Excess 3 BCD code.
Electronics-II 870 YCT
 VIII. Microprocessors 6. The number of memory cycle required to
execute the following 8085 instructions:
1. The number of status flags in 8085 (I) LDA3000H (II) LXI D, F0F1 H would be
microprocessor is: (a) 4 for (I) and 3 for (II)
(a) 6 (b) 4 (b) 3 for (I) and 3 for (II)
(c) 3 (d) 5 (c) 3 for (I) and 4 for (II)
CGPSC AE 15.01.2021 (d) 2 for (I) and 2 for (II)
MPPKVVCL (Jabalpur) JE -2018 RPSC ACF & FRO 23.02.2021
HPSSSC JE- 2018 (Code 387) Ans. (a) : LDA: Load Accumulator Direct
BSNL TTA (JE) 25.09.2016, 3PM Opcode Operand Bytes M-cycles T-state
ESE-2006 LDA 16-bit 3 4 13T
Ans. (d) : The flags generally reflect the status of address
arithmetic or logical operation. LXI D, F0F1 H requires 3 bytes, 3-machine cycles
(opcode fetch, memory read, memory write) and 10 T
state for execution.
7. An I/O processor control the flow of
Carry flag (CY) information between
Parity flag (P) (a) Cache memory and I/O devices
Auxiliary Carry flag (AC) (b) Two I/O devices
Zero Flag (Z) (c) Cache and main memories
Sign flag (S) (d) Main memory and I/O devices
2. In 8085 microprocessor, the general purpose RPSC ACF & FRO 23.02.2021
register (GPR) are: Ans. (d) : An input processor control the flow of
(a) A B C D E F (b) A B C D H F information between main memory and input output
(c) B C D H L M (d) B C D E H L device.
HRRL E1 & E2 07.08.2021 8. In 8085 processor SOD and SID pins are used
UJVNL JE 2016 for
Ans. (d) : Register B, C, D, E, H and L are general (a) Providing power supply to the processor
purpose register in 8085 microprocessor. All these (b) Serial communication
general purpose registers are 8- bits wide. (c) Providing system clock
3. In 8085 microprocessor system, the direct (d) Providing reset signal to processor
addressing instruction is - RPSC ACF & FRO 23.02.2021
(a) MOV A, B (b) MOV B, 0AH Ans. (b) : In 8085 processor SOD and SID pins are
(c) MOV C, M (d) STA addr used for serial communication.
HRRL E1 & E2 07.08.2021 Serial input port-
Mizoram PSC IOF 2019, Paper-III (i) SID (Serial Input Data) : This pin is used for
Ans. (d) : STA-Store accumulator, 8 bit content will be receiving the data into microprocessor serially.
stacked in a memory location. 16 bit address is (ii) SOD (Serial output Data): This pin used for sending
indicated in the instruction as a 16 bit address locations. the data from the microprocessor serially.
4. The data bus of any microprocessor is always 9. In 8086 microprocessor the following has the
(a) unidirectional highest priority among all type interrupts.
(b) bidirectional (a) DIV 0 (b) TYPE 255
(c) either unidirectional or bidirectional (c) OVER FLOW (d) NMI
(d) None of the above RPSC ACF & FRO 23.02.2021
CGPSC AE 15.01.2021 BSNL TTA (JE) 2013
Ans. (b) : The data bus of any microprocessor is always Ans. (d) : NMI (Non maskable interrupt) is the highest
bidirectional. Hence can transfer in both direction. priority interrupt in 8086. It is a single pin, non-
maskable, hardware interrupt which can't be disabled.
5. In 8085 micro processor, data bus and address
bus are multiplexed in order to 10. In 8086 the overflow flag is set when
(A) Increase the speed of microprocessor (a) Signed numbers go out of their range after an
(B) Reduce the number of pins arithmetic operation
(C) Connect more peripheral chips (b) Carry and sign flags are set
Which of the above statements is/are correct? (c) During subtraction
(a) (B) only (b) (B) and (C) only (d) The sum is more than 16 bits
(c) (A), (B) and (C) (d) (A) only RPSC ACF & FRO 23.02.2021
RPSC ACF & FRO 23.02.2021 Ans. (a) : In 8086 micro-processor overflow flag will
Ans. (a) : Lower byte of address bus (A0-A7) are be set if the result of signed numbers go out of their
multiplexed with data bus (AD0-AD7) to reduce the range after an arithmetic operation or if the result of a
number of pins of microprocessor. This multiplexed signal operation is too large to fit in the number of bits
address is controlled by ALE signal. available to represent it, otherwise reset.
Electronics-II 871 YCT
11. Which of the following instructions is a 3-byte 17. How many Initialization command words are
instruction? essential if 8259 is used in single chip with
(a) LDA XB (b) MOV A, M special fully nested mode configuration?
(c) JMP 2050 (d) MVIA (a) 2 (b) 3
RPSC ACF & FRO 23.02.2021 (c) 4 (d) 1
Ans. (c) : JMP 2050 is a 3-byte instruction. ESE-2012
The size of 8085 instructions can be 1 byte, 2 bytes or 3 Ans. (a) : The 8259 A require two types of command
bytes. The 1-byte instruction has one opcode alone. words. Initialization command words (ICWs) and
The 2 bytes instruction has one opcode followed by an operational command words (OCWs). The 8259A can
eight bit address or data. The 3-bytes instruction has be initialized with four (ICWs) the first two are
one opcode following by 16 bit address or data. essential and other two are operational based on the
12. In a microprocessor, the address of the next modes being used.
instruction to be executed, is stored in 18. The programm counter in an 8085
(a) Stack pointer microprocessor is a 16 bit register because
(b) Address latch (a) It counts 16 bit at a time.
(c) Program counter (b) There are 16 address lines.
(d) General purpose register (c) It facilitates the user storing 16 bit data
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II temporarily.
LMRC (SCTO) 17.04.2021 (d) It has to fetch two 8 bit data at a time.
RPSC Lect. (Tech. Edu. Dept.) 09.01.2016 RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
Ans. (c) : In program counter (PC) the address of next Ans. (b) : Key points of 8085 -
instruction to be executed in stored. It is a 8-bit processor
13. The 8085 assembly language instruction that It has total 16 address lines with address capacity of
stores the contents of H and L registers into the 64 KB.
memory locations 2050H and 2051H, 19. A programmable ROM has a decoder at the
respectively, is: input and OR gates at the output with
(a) SPHL 2050H (b) SPHL 2051H (a) both these blocks being fully programmable
(c) SHLD 2050H (d) STAX 2050H (b) both these blocks being partially
RPSC Lect. (Tech. Edu. Dept.) 09.01.2016 programmable
Ans. (c) : SHLD 2050H : stores the content of H and L (c) only the latter block being programmable
in 2050H and 2051H respectively. (d) only the former block being programmable
14. In an 8085 microprocessor, after the execution ESE-2013
of XRA A instruction Ans. (c) : A programmable ROM has a decoder at the
(a) the carry flag is set input and OR gates at the output with only the latter
(b) the accumulator contains FFH block being programmable.
(c) the zero flag is set 20. In 8085, if the clock frequency is 5 MHz, the
(d) the accumulator contents are shifted left by time required to execute an instruction of 18 T-
one bit states is (µs)
RPSC Lect. (Tech. Edu. Dept.) 09.01.2016 (a) 3.0 (b) 3.6
Ans. (c) : After the execution of XRA A instruction in (c) 4.0 (d) 6.0
8085 microprocessor the zero flag is set. RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
15. A microprocessor is Arithmetic logic unit 1 1
Ans. (b) : Time T = = = 0.2µs
(a) And control unit on a single chip. f 5MHz
(b) And memory on a single chip. Then, 18 T = 18 × 0.2 µs = 3.6µs
(c) Register unit and I/O device on a single chip 21. NOP instruction is used to
(d) Register unit and control unit on a single chip.
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II (a) Replace the existing instruction
Ans. (d) : Microprocessor is a programmable (b) Debug the program
integrating device has computing, storing, retrieving (c) Insert the delay
and decision making capacity. (d) all of these
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
A microprocessor has Arithmetic logic unit, register
unit and control unit on a single chip. Ans. (d) : A NOP is most commonly used for limiting
purposes, to force memory alignment, to prevent
16. Which interrupt has the highest priority?
hazard, to occupy a branch delay slot, to render avoid an
(a) RST 7.5 (b) RST 7
existing instruction such as a jump, or as a place-holder
(c) RST 6.5 (d) INTR
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
to be replaced by active instructions.
Ans. (a) : The 8085 microprocessor has five interrupt 22. The contents of the accumulator in an 8085
signals that can be used to interrupt a program microprocessor is altered after the execution of
execution. the instruction:
(a) CMPC (b) CPI 3A
In interrupts priority order is
(c) ANI 5C (d) ORA A
TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
Electronics-II 872 YCT
Ans. (c) : Compare instruction do not alter the Ans. (c) : In an 8086 microprocessor, in order to enable
accumulator content and ORA A gives the same output higher order byte of data, BHE signal is used.
as A. AND instruction changes the content of It is a 16 bit microprocessor having 20 address lines and
accumulator. 16 data lines that provides upto 1 MB storage.
23. Which of the following 8085 assembly language 28. 8086 microprocessor is designed to have ____
instructions does not affect the contents of the
data lines and _____ address line.
accumulator?
(a) 12; 16 (b) 16; 20
(a) CMA (b) CMPB
(c) DAA (d) ADDB (c) 16; 16 (d) 20; 16
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II LMRC (SCTO) 17.04.2021
Ans. (b) : CMPB instruction in 8085 does not affect the Ans. (b) : 8086 microprocessor is designed to have 16
contents of the accumulator. While CMPB instruction data lines and 20 address line.
executes, microprocessor compares the contents of Data line is Bidirectional and address line is
register B with the contents of the accumulator. The unidirectional 16 address lines and 8 data lines have in
comparison is shown by setting all the flags. The flags 8085 microprocessor.
S,P, AC are modified and flag Z and CY reflects the 29. In which of the following modes in 8255 A PPI
result of the operation so, all flags will be affected. can part A be used as a bidirectional data bus?
24. What is the number of machine cycles in the (a) BSR mode (b) Mode 1
instruction LDA 2000 H that consist of thirteen (c) Mode 2 (d) Mode 0
states? LMRC (SCTO) 17.04.2021
(a) 2 (b) 3 Ans. (c) : 8255A has three different operating modes-
(c) 4 (d) 5 Mode 0- In this mode, port A and B is used as two 8-bit
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
ports and port C as two 4-bit ports. Each port can be
Ans. (c) : LDA: Load Accumulator Direct programmed in either input mode or output mode where
Opcode Operand Bytes M-Cycle T-states outputs are latched and inputs are not latched. Ports do
LDA 16-bit 3 4 13T not have interrupt capability.
adress
Mode 1-In this mode, Port A and B is used as 8-bit 1/0
25. The contents of the Accumulator after the ports. They can be configured as either input or output
execution of the following programme will be ports. Each port uses three lines from port C as
MVI A C5H handshake signals for data transfer. The remaining three
ORA A
signals from port C can be used either as simple I/O or
(a) 45 H (b) C5H
(c) C4H (d) None of these as handshake for port B.
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II 30. In 8085 microprocessors, MVI A, 23H is an
Ans. (a) : As given, example of which addressing mode?
MVI A, C5H ; C5H→A (a) Direct addressing
ORA A ; Reset carry flag (b) Register addressing
RAL ; Rotate A left through (c) Indirect addressing
; Carry, A= 8AH (d) Immediate addressing
RRC ; Rotate A right, A = 45H LMRC (SCTO) 17.04.2021
RRC instruction rotates the accumulator right and D0 is Ans. (d) : In 8085 microprocessor MVI A, 23H is an
placed in D7. example of immediate addressing mode.
26. Which of the following is not correct? 31. The 8251A programmable communication chip
(a) Bus is a group of wires. is designed for:
(b) Bootstrap is a technique or device for loading (a) synchronous and asynchronous serial data
first instruction. communication
(c) An instruction is a set of bits that defines a (b) synchronous and asynchronous parallel data
computer operation. communication
(d) An interrupt signal is required at the start of (c) synchronous parallel data communication only
every program. (d) synchronous serial data communication only
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
LMRC (SCTO) 17.04.2021
Ans. (d) : Interrupt is a signal which required for
interruption of main program to perform a subroutine. It Ans. (a) : The 8251 A programmable communication
may be used at the start of some program as per chip is designed for synchronous and asynchronous
requirement but it is not mandatory at start of every serial data communication.
program. 32. Which of the following will be done in an 8085
27. In an 8086 microprocessor, in order to enable microprocessor when an instruction LXI H
higher order byte of data, ______ signal is used. 2070H is executed?
(a) Content of the memory 2070H is loaded in H
(a) ALE (b) DEN register
(c) BHE (d) DT/R (b) 70 H is loaded in H register and 20 H is
LMRC (SCTO) 17.04.2021 loaded in L register.
Electronics-II 873 YCT
 (c) 2070H is loaded in H register. (a) 2 times (b) 3 times
(d) 20 H is loaded in H register and 70 H is (c) 4 times (d) 5 times
loaded in L register ISRO VSSC (TA) 14.07.2021
LMRC (SCTO) 17.04.2021 Ans. (b) :NOP
Ans. (d) : An instruction L × IH, 2070 H. It means that 1st A ← 20H
the 2070H is loaded into the HL register pair. RLC A ← 40 H
20H is loaded in H register and 70H is loaded in L
register. 2 nd A ← 50H
33. When light is produced by fittings that throw RLC A ← A0H
all the light on the ceiling, from where it is 3rd A ← B0H
reflected to the area to be lighted, this method RLC A ← 61H
of lighting arrangement is known as: Hence, NOP instruction executes only 3 times.
(a) general diffusing system
38. Memory refreshing may be done by:
(b) semi-direct system
(a) DMA controller
(c) indirect lighting arrangement
(b) Stack pointer
(d) direct lighting arrangement
(c) External refresh controller.
UPPCL JE- 07.09.2021, Shift-II
(d) CPU.
Ans. (c) : In an indirect lighting arrangement, more than HPPSC PWD AE 24.08.2021
90% of the total light flux or lumen is made thrown
upward to the ceilings for diffuse reflection. Ans. (c) : Memory refreshing may be done by external
the glare is reduced to minimum in this lighting system. refresh controller.
Application - Mostly used for decoration purposes, Memory refresh is a charging cycle that a computer’s
cinema halls theaters and hotels. RAM goes through on a periodic basis. When the
computer reads data the information is stored as 1 or 0,
34. _______ are used to detect the occurrence of on or off respectively.
external events. It is a retentive type of
instruction and can be reset to zero using the 39. In microprocessor, Stack pointer is a register
reset (RES) instruction. which comes into use whenever:
(a) Bit instructions (a) A data is written into the memory.
(b) Base instructions (b) The output variable is sent out of the CPU.
(c) Call instructions (c) A data is read from the memory.
(d) Counter instructions (d) An interrupt or high priority call comes from
UPPCL JE- 08.09.2021, Shift-I external devices.
Ans. (d) Counter instructions are used to detect the HPPSC PWD AE 24.08.2021
occurrence of external event. It is a retentive type of Ans. (d) :
instruction & can be reset to zero using the reset (RES) In Microprocessor, stack pointer is a register which
instruction. comes into used whenever an interrupt or high
35. _________ is a programming language that priority call cones from external devices.
utilises statements to determine what to A stack pointer is small register that stores the
execute. address of the last program request in a stack.
(a) Function block diagram 40. In microprocessor architecture, flag indicates
(b) Structured text programming the:
(c) Sequential block diagram (a) Internal status of CPU.
(d) Instruction programming (b) Bit -size of microprocessor.
UPPCL JE- 08.09.2021, Shift-I (c) Time for which the output data remain valid
Ans. (b) : Structured text programming is a output when the device is no longer selected.
programming language that utilises statement to (d) A halt state of CPU..
determine what to execute. HPPSC PWD AE 24.08.2021
36. ____________ is used to store program codes Ans. (a) :
(a) System memory (b) Data memory The flag register is the status register that contains
(c) User memory (d) Executive memory the current status of CPU. The size and meanings of
UPPCL JE- 08.09.2021, Shift-I the flag bits are architecture dependent.
Ans. (c) : User memory is used to store the program Information about restrictions placed on the CPU
codes. operation at the current time.
37. An intel 8085 processor is executing the 41. Which one of the following is not correct for
program given below. The number of times the the AAA instruction in 8086 microprocessors ?
loop executed is (a) It works only on the AL register.
MVI A, 20H (b) It updates AF and CF.
(c) It checks the result for correct unpacked BCD.
MVI B, 10H
(d) It updates all the flags.
LOOP: ADD B
ESE (Pre) 18.07.2021
RLC
JNC LOOP Ans. (d) : AAA instruction in 8086 affect only CF and
HLT AF. Remaining flags are not affected.
Electronics-II 874 YCT
42. A 512MB RAM is connected to a 47. Memory-mapped I/O-scheme for the allocation
microprocessor with data bus length of 8. The of address to memories and I/O devices, is used
size of memory that will remain unutilized is: for
(a) 256 MB (b) 128 MB (a) small systems
(c) Zero (d) 192MB (b) large systems
OPPSC AE 2021, Paper-II (c) both large and small systems
Ans. (a) : Remain space = 512 – 2n (d) very large systems
n = No. of bus ESE-2002
= 512 – 28 Ans. (a) : Memory-mapped I/O-scheme for the
= 256 MB allocation of address to memories and I/O devices is
43. Which of the interrupts of 8085 microprocessor used for small systems.
has highest priority? • Memory-mapped I/Os share the memory space with
(a) INTR (b) TRAP external memory. So total addressed capacity is
(c) RST 7.5 (d) RST 5.5 memory connected only.
TSPSC Manager (Engg.)HMWSSB 2020
Mizoram PSC IOF 2019, Paper-III 48. An RRC instruction in 8085 will affect which
BSNL TTA 21.02.2016 flag?
BSNL TTA 28.09.2016, 10 AM (a) CY (b) Z
ESE-2008, 2007 (c) S (d) AC
MPPKVVCL (Jabalpur) JE -2018
Ans. (b) : TRAP interrupt of 8085 µp has highest
priority. A TRAP interrupt is a non maskable interrupt, Ans. (a) : In 8085 instruction set RRC stands for
which implies that whenever this pin is activated, it is "Rotate Right Accumulator". Each binary bit of the
executed first of all interrupts. accumulator is rotated right by one position. Bit D0 is
44. In 8085 microprocessor, stack works on– placed in the position of D7 as well as in the carry flag
(a) LILO (b) LIFO (CY).
(c) FIFO (d) None of these 49. The interfacing device used for the generator of
BSNL TTA (JE) 25.09.2016, Shift-I accurate time delay in a microcomputer system
BSNL TTA 26.09.2016, 10 AM is
ESE-2009, 2004 (a) Intel-8251 (b) Intel-8257
Ans. (b) : In 8085 microprocessor, stack works on LIFO (c) Intel-8253 (d) Intel-8259
system. The stack is portion of read/ write memory set ESE-2002
aside by the user for purpose of storing information Ans. (c) : The INTEL-8253 is programmable interval
temporarily. When the information is written on the stack, timer or counter. It used for the generation of accurate
the operation is called PUSH. When the information is time delay in a microcomputer system.
read from stack, operation is called. It can be used for applications such as real time clock an
45. What are the sets of commands in a program event counter, a square wave generator etc.
which are not translated into machine 50. Which of the following is a two byte instruction
instructions during assembly process, called? is 8085 microprocessor?
(a) Mnemonics (b) Directives (a) MOV (b) CMA
(c) Identifiers (d) Operands (c) ADD (d) MVI
GSSSB SI 08.04.2018 MPPKVVCL (Jabalpur) JE -2018
ESE-2007 Ans. (d) : MVI : Move Immediate 8-bit
Ans. (b) : A directives is a language construct that opcode operand Bytes M-cycles T-states
specifies how a compiler (or translator) should process MVI R/M, 8-bit 2 2/3 7T/10T
its input. Directives are not a part of programmar of a data
programming language. It may vary from compiler to The 8-bit data are stored in the destination register or
compiler. Directives are not translated into machine memory .
instruction during assembly process. e.g.
46. An interrupt in which the external device
supplies its address as well as the interrupt
request is known as
(a) Vectored interrupt
(b) Maskable interrupt 51. Which one of the following statement about
(c) Non-Maskable interrupt RAM is NOT correct?
(d) Designated interrupt (a) RAM stands for random-access memory
KSEB Sub Engineer 2015 (b) It is also called read/write memory
Ans. (a) : Non- vectored interrupt does not have address (c) When power supply is switched off, the
and it will use the address of software interrupts. information in RAM is usually lost
Whereas vectored interrupt is an interrupt in which the (d) The binary contents are entered or stored in
external device supplies its address as well as the the RAM chip during the manufacturing state
interrupt request. ESE-2003
Electronics-II 875 YCT
Ans. (d) : RAM– Operand PSW (Program status word) represented the
• RAM stands for Random Access Memory content of accumulator and the flag register, the
• It is a form of temporary memory where the memory accumulator and flag register, the accumulator is the
content is lost it power is switched off. higher order register and flag are the lower order
• It is used to form the working memory of the computer. register, one fetch and 2 memory write cycle.
• One can both read and write data to a RAM. 56. In 8085, what is the output after the execution
• Used as cache memory of the following instructions:
• Faster, expensive and large size MVI A, 06H
• Long life and no need to refresh MVI L, 04H
52. The interface chip used for data transmission ADD L
between 8085 and a 16 bit ADC is (a) 0A H (b) 10 H
(a) Intel 8257 (b) Intel 8253 (c) 06 H (d) 04 H
(c) Intel 8259 (d) Intel 8251 MPPKVVCL (Jabalpur) JE -2018
Ans. (b) : The interface chip used for data transmission Ans. (a) :
between 8085 and a 16 bit ADC is Intel 8253. The MVI A, 06H → A = 06H
interface chip used for data transmission between 8086 MVI L, 04H → L = 04H
and a 16 bit ADC is Intel 8255. ADD L → A = A+L
53. Ports are used to connect the CPU to which of output = A+L
the following units? = 06H + 04H
1. Printer = 0AH
2. floppy disk drives
3. Video display unit 57. The total addressable memory size of 8085 is-
4. Incoming power supply (a) 16 kb (b) 32 kb
Select the correct answer using the codes given (c) 64 kb (d) 128 kb
below BSNL TTA 26.09.2016, 10 AM
(a) 1 and 2 (b) 2 and 3 Ans. (c) : 8085 has a 16-bit address bus.
(c) 3 and 4 (d) 1 and 3 ∴ It can access 216 = 65536 memory location.
ESE-2003 ∴ 64 kB memory
Ans. (d) Ports are used to connect the CPU to input/output The memory address range is from 0000H to FFFFH.
devices such as printer, video display unit (VDU). 58. When RET instruction is executed by any
Printer port (port 631) is the parallel port of a computer subroutine then
used by printer. (a) the top of the stack will be popped out and
54. The address bus width of 8085 microprocessor assigned to the PC
is: (b) without any operation, the calling program
(a) 32 bit (b) 8 bit would resume from instruction immediately
(c) 16 bit (d) 64 bit following the call instruction
MPPKVVCL (Jabalpur) JE -2018
(c) the PC will be incremented after the
BSNL TTA (JE) 27.09.2016, 10 AM
UJVNL JE 2016 execution of the instruction
(d) without any operation, the calling program
Ans. (c) : Key points of 8085-
would resume from instruction immediately
• It is 8-bit processor.
following the call instruction, and also the PC
• It has 8 data bus lines, which is the bit capacity of
the microprocessor. will be incremented after the execution of the
• It has total 16 address lines with addressing capacity instruction
of 64 KB. ESE-2001
55. How many and which types of machine cycles Ans. (a) : Two bytes from the top of stack will be
are needed to execute PUSH PSW by an Intel popped out and assigned to the program counter and the
8085 A microprocessor? program counter begins at the new address when RET
(a) 2; Fetch and Memory write instruction is executed by any subroutine.
(b) 3; Fetch and 2 Memory write 59. 8086 has maximum clock frequencies ranging
(c) 3; Fetch and 2 Memory read from:
(d) 3; Fetch, Memory read and Memory write (a) 5 MHz - 8 MHz (b) 6 MHz - 10 MHz
ESE-2003 (c) 5 MHz - 15 MHz (d) 5 MHz - 10 MHz
Ans. (b) : PUSH instructions has 3 machine cycle MPMKVVCL (Bhopal) JE 2018
(fetch, write, write) 12T states and 1 byte instructions. BSNL TTA 28.09.2016, 10AM
Opcode Operand Bytes M T Hex code
cycle states Ans. (d) : 8086 MPU-
• Clock frequency - 5 MHz to 10 MHz
Register Hex
• Data width - 16 Bits
PUSH Reg. 1 3 12 PSW F5 • Address width - 20 Bits
Pair B C5 • Supply voltage - +5 V
Electronics-II 876 YCT
60. A memory system of 64 Kbytes needs to be 64. Memory chips of four different sizes as below
designed with RAM chips of 1 Kbyte each, and are available:
a decoder tree constructed with 2:4 decoder 1. 32 K × 4 2. 32K×16
chips with "Enable" input. What is the total 3. 8 K × 8 4. 16 K ×4
number of decoder chips? All the memory chips as mentioned in the
(a) 21 (b) 64 above list are read/write memory. What
(c) 32 (d) 25 minimum combination of chips or chip alone
ESE 2004 can map full address space of 8085
64k microprocessor?
Ans. (a) : Number of RAM chip = = 64 (a) 1 and 2 (b) 1 only
1k (c) 2 only (d) 4 only
For 64 chip decoder required = 6: 64
ESE 2005
6 : 64 decoder design by 2 : 4
Ans. (c) : Size of memory = 2n × m bits
1K bytes = 1024 bytes
In 8085 microprocessor
No. of address line n = 16
= 16 + 4 + 1 No. of data lines m = 8
= 21 Size of memory = 2n × m bits
61. In 8086, single step interrupt belongs to: = 216 × 8 bits
(a) TYPE-1 (b) TYPE-2 = 26 × 210 × 8 bits
(c) TYPE-3 (d) TYPE-4 = 25 × 210 × 2 × 8 bits
MPMKVVCL (Bhopal) JE 2018 = 32 K ×16
Ans. (a) : If the trap flag is set, the 8086 will 65. Which of the following flags is NOT present in
automatically do a type-1 interrupt after each instruction 8085?
executes. when the 8086 does a type 1 interrupt, it (a) Sign (b) Parity
pushes the flag register on the stack. (c) Trap (d) Auxiliary carry
62. Consider the execution of the following MPMKVVCL (Bhopal) JE 2018
instructions by an 8085 microprocessor: Ans. (c) : In 8085 microprocessor, the flags register can
LXI H, 01FFH have a total of eight flag. Thus a flag can be represented
SHLD 2050H by 1 bit of information. But only five flags are
After execution the contents of memory implemented in 8085 and they are :
locations 2050 H and 2051 H and the registers • Carry flag (CY)
H and L, will be • Auxiliary carry flag (AC)
(a) 2050 H→FF; 2051H→01; H→FF;L→01 • Sign flag (S)
(b) 2050H→01;2051H→FF;H→FF;L→01 • Parity flag (P)
(c) 2050H→FF;2051H→01;H→01;L→FF • Zero flag (Z)
(d) 2050H→FF;2051H→01;H→00;L→00 66. Consider the following statements: In
ESE-2002 memories,
Ans. (c) : LXI RP data (16bit) → Load register pair Rp 1. ROMs are used for temporary program and
with immediate data data storage.
The higher order data goes into higher register (H) and 2. Dynamic RAM is less expensive than static
lower order data goes into lower order register (L). RAM
SHLD address (16bit)→ Data from higher order 3. MASK ROM is used in high volume
register (H) is stored in higher order memory location microprocessor based system.
and data from lower order register (L) is stored in Which of these statements is/are correct?
higher order memory location. (a) 1 only (b) 1 and 2
LXI H, 01FFH→[H] →01 (c) 2 and 3 (d) 1, 2 and 3
[L] →FF ESE 2005
SHLD 2050H, Ans. (c) : • Dynamic RAM is less expensive than static
2050H→[H] →01 RAM.
2051H→[L] →FF • Dynamic RAM speed is lower than static RAM.
63. The arithmetic operation NEG invert: • DRAM has higher packing density than SRAM.
(a) each bit of a specified byte or word and adds 1 • Mask ROM (MROM) chips are used in high volumes
(b) each bit of a specified byte or word microprocessor based system that requires long-term
(c) the least significant bit of a specified byte or sustainability.
word • MROM are used in network operating system are
(d) the least significant bit of a specified byte or server operating system.
word and adds 1 67. Which one of the following functions is
MPMKVVCL (Bhopal) JE 2018 performed by the 8085 instruction MOV H, C?
Ans. (a) : The arithmetic operation NEG inverts each (a) Moves the contents of H register to C register
bit of a specified byte or word and adds 1. (b) Moves the contents of C register to H register
Electronics-II 877 YCT
 (c) Moves the contents of C register to HL pair Ans. (d) : Data that are stored at a given address in a
(d) Moves the contents of HL pair to C register random access memory are lost when-
ESE-2002 • Power goes off
Ans. (b) : This instruction moves the content of a C • New data are written at the address
register to H register and content of C register remains • RAM is a volatile memory.
unchanged. • RAM gives applications a place to store and access
1- byte instruction data on a short term basis.
Machine cycle-opcode fetch.
73. Assembly language uses abbreviated English
68. Find the physical address if words like ADD, JUMP, MUL, etc. These
ss:50000 words
sp:FFE0 are called:
(a) 14 FE0 (b) 15 FF0 (a) mnemonics (b) thesaurus
(c) 25 FF0 (d) 5 FEE0 (c) pseudo codes (d) symbols
MPMKVVCL (Bhopal) JE 2018 PSPCL JE 2019, Shift-I
Ans. (d) : Ans. (a) : Assembly language uses abbreviated English
words like ADD, JUMP, MUL, etc. These words are
called mnemonics.
74. Which of the following acts as a temporary
69. The maximum number of bytes of instructions storage location to hold an intermediate result
8086 bus interface unit consists of is: in mathematical and logical calculations?
(a) 4 bytes (b) 6 bytes (a) RAM
(c) 8 bytes (d) 10 bytes (b) Accumulator
MPMKVVCL (Bhopal) JE 2018 (c) Program Counter
Ans. (b) : The maximum number of bytes of instructions (d) Memory Address Register (MAR)
8086 bus interface unit consists of is 6 Bytes. PSPCL JE 2019, Shift-I
8086 is designed to operate in two modes, Minimum Ans. (b) : Accumulator act as a temporary storage
and Maximum. It can prefetches upto 6 instruction location to hold an intermediate result in mathematical
bytes from memory and queues them in order to speed and logical calculation.
up instruction execution.
75. Suppose 64 kB, ROM ICs are available in
70. For 8085 microprocessor, the instruction RST6 abundance. 1 MB ROM can be obtained from
restarts subroutine at address (a) 16 ICs in a row
(a) 00H (b) 03H (b) 16 ICs in a column
(c) 30H (d) 33H (c) 8 ICs in a column and 2 ICs in a row
ESE-2002 (d) None of the above
Ans. (c) : To calculate vector address of RSTn ESE 2006
n × 8 = (X)10 = ( Y )16 1 MB 1× 220
For RST 6, Ans. (b) : No. of chip required = = 6 10
64 KB 2 × 2
So, ( 6 × 8 )10 = ( 48 )10 
Hexa decimal
→ ( 30 ) H = 2 4 = 16
71. What will be the maximum number of Hence, we obtain 16 ICs a column.
addressable locations in a memory using 9 76. Which of the following CPU registers contains
address lines? the address of the next instruction to be fetched
(a) 511 (b) 512 from the main memory when the previous
(c) 128 (d) 256 instruction has been successfully completed?
PSPCL JE 2019, Shift-I (a) MDR
Ans. (b) : Given: Address lines number (n) = 9 (b) MAR
maximum number of addressable location = ? (c) Accumulator
Maximum number of addressable location (N) = 2n (d) Program Counter (PC)
= (2)9 PSPCL JE 2019, Shift-II
N = 512 Ans. (d) : Program counter (PC) is the CPU register
72. Consider the following statements: contain the address of the next instruction to be fetch
Data that are stored at a given address in a from the main memory when the previous instruction
random access memory are lost. has been successfully completed. It is a 16 bit register.
1. When power goes off 77. If a memory has 10 address lines and the size of
2. When the data are read from the address
3. When new data are written at the address each addressable location (block) is 4 bytes,
4 because it is non-volatile memory then what is the maximum storage capacity of
Which of these statements are correct? the memory?
(a) 1 and 2 (b) 1, 2 and 4 (a) 4 kilobyte (b) 2 kilobyte
(c) 2 and 3 (d) 1 and 3 (c) 1 kilobyte (d) 3 kilobyte
ESE 2006 PSPCL JE 2019, Shift-II
Electronics-II 878 YCT
Ans. (a) : Given: N = 4 byte, address line (n) = 10 Ans. (d) :
Maximum storage capacity = ?
Maximum storage capacity of memory = N. 2n
= 4 × ( 2)
10

= 4 × 1024 B
= 4 × 1kB {∵1024B = 1kB}
= 4 kilobyte From above address of port C = FEH
78. After an arithmetic operation, the flag register 82. A direct memory access (DMA) transfer
of a 8085 microprocessor has the following implies
look: (a) Direct transfer of data between memory and
accumulator
D7 D6 D5 D4 D3 D2 D1 D0
(b) Direct transfer of data between memory and
1 0 X 1 X 0 X 1 I/O device without the use of microprocessor
The arithmetic operation has resulted in (c) Transfer of data exclusively within
(a) A carry and an odd parity number having 1 as microprocessor registers
the MSB (d) A fast transfer of data between
(b) Zero and the auxiliary carry flag being set microprocessor and I/O devices
(c) A number with even parity and 1 as the MSB ESE-2003
(d) A number with odd parity and 9 as the MSB Ans. (b) : A 'DMA' transfer implies direct transfer of
ESE-2003 data between memory and input device without the use
Ans. (a) : of MP but in microprocessor based system DMA
D7 D6 D5 D4 D3 D2 D1 D0 facility is required to increases the speed of data transfer
1 0 X 1 X 0 X 1 between the memory and the input devices.
Carry flag cy = 1 83. In a microprocessor, op- code fetch cycle is?
Parity flag P = 0 i.e. odd parity (a) Last part of instruction cycle
Auxiliary carry = 1 (b) First part of instruction cycle
Zero flag = 0 (c) Intermediate part of instruction cycle
Sign flag = 1 i.e., at MSB (d) Data reception through bus
ISRO TA 2016
79. If 8255 a chip is selected when A2 to A7 bits are ESE -2011, 2008
all 1, what is the address of port A?
Ans. (b) : The op-code fetch cycle, fetches the instruction
(a) 80 (b) FA from memory and delivers it to the instruction register of
(c) FB (d) FC the microprocessor. For any instruction cycle, op-code
ESE-2007 fetch is the first machine cycle.
Ans. (d) : When chip select- 84. Consider the following statements:
A1 A0 1. The process of entering data is called burning
Port A → 0 0 in ROM.
Port B → 0 1 2. ROMs are volatile memories.
Port C → 1 0 3. ROMs are used in microcontroller security
Control register → 1 1 systems.
What of these statements are correct?
(a) 1,2 and 3 (b) 1 and 2
(c) 2 and 3 (d) 1 and 3
ESE-2007
Then address of port A is FC. Ans. (d) : The process of entering data is called burning
80. NMI stands for in ROM. ROMs are used in microcontroller security
(a) Non-mask interface systems. ROM is non volatile memory. In ROM data
(b) Non-maskable interrupt stored permanently.
(c) Non-mask interaction 85. In 8085 microprocessor, how many interrupts
(d) None of there are maskable?
UPSSSC JE-2015 (a) Two (b) Three
Ans. : (b) NMI stands for Non-maskable interrupt. It is a (c) Four (d) Five
hardware interrupt that standard interrupt- masking HPSSSC JE 2018 Code -387
technique in the system can not ignore. It typically occurs Ans. (c) : Maskable Interrupts−Maskable Interrupts
to signal attention for non-recoverable hardware errors. are there which can be disabled or ignored by the
81. If 8255 A chip is selected when A2 to A7 pins are microprocessor. These interrupts are either edge-
1, what is the address of port C? triggered or level-triggered, so they can be disabled
(a) FC (b) FD INTR, RST 7.5, RST 6.5, RST 5.5 are maskable
(c) FB (d) FE interrupts in 8085 microprocessor and TRAP is a non-
ESE-2007 maskable interrupt.
Electronics-II 879 YCT
86. The power failure alarm must be connected to (c) selecting which peripheral should be
which of the following inputs of 8085? addressed
(a) RST 7.5 (b) TRAP (d) Storing instructions
(c) INTR (d) HOLD (e) for carrying out logical operations
HPSSSC JE 2018 Code -387 RSEB JE 2011
ESE- 2007 Ans. (a) : An accumulator is a type of register included
Ans. (b) : TRAP is a non-maskable interrupt. It consists in a CPU. It acts as a temporary storage location which
of both level as well as edge triggering and is used in holds an intermediate value in mathematical and logical
critical power failure condition. So the power failure calculations.
alarm must be connected to TRAP. 92. Consider the following statements:
87. An 8254 programmable interval timer consists 1. The output unit of a computer communicate
of independent 16-bit programmable counters. the response of the computer to the uses.
This number is 2. Read/write memory is volatile.
(a) 2 (b) 3 3. the flip-flops in a register are connected in
(c) 4 (d) 5 parallel.
ESE-2008 Which of these statements is/are correct?
Ans. (b) : The 8254 programmable interval timer (a) 1 only (b) 1 and 2
includes 3 identical 16 bit counters that can operate (c) 2 and 3 (d) 3 only
independently in any one of six modes. It is 24 Pin IC ESE-2009
and power supply +5 Volt. Ans. (b) : The output unit of a computer communicate
88. A handshake signal in a data transfer is the response of the computer to the uses. Read/write
transmitted memory is volatile.
(a) Along with the data bits Read/write memory also known as random access
(b) Before the data transfer memory.
(c) After the data transfer The flip-flops in a register are connected in series.
(d) Either along with the bits or after the data 93. In microprocessor 8085, LDA 2000H is
transfer ________
ESE-2003 (a) Direct addressing mode
Ans. (b) : Handshaking mechanism has two hardware (b) Indirect addressing mode
lines-strobe and acknowledge. The sender provides the (c) Implied addressing mode
signal on the strobe line and the receiver provides the (d) Immediate addressing mode
signal on the acknowledge line before the data transfer. PGVCL JE 2018
89. In a µP based system, the stack is always in Ans. (a) : In 8085 Instruction set LDA is a mnemonic
(a) µP (b) RAM that stands the contents of a memory location, specified
(c) ROM (d) EPROM by a 16-bit address in the operand, are copied to the
HPSSSC JE 2018 Code -387 accumulator.
Ans. (b) : Stack pointer is nothing but the register LDA: Load Accumulator
which holds the address of the top of the stack, resides Opcode Operand Bytes M-cycles T-states
with the microprocessor. In a microprocessor based LDA 16-bit 3 4 13T
system the stack is always in Random Access memory address
(RAM). Thus, LDA 2000H is direct addressing mode.
90. What is the total number of memory locations 94. In microprocessor 8085, CALL instruction
and input-output devices that can be addressed have ______.
with a processor having 16-bits address bus, (a) 3 bytes, 18 T states (b) 3 bytes, 16 T states
using memory maped I/O? (c) 2 bytes, 16 T states (d) 2 bytes, 10 T states
(a) 64K memory locations and 256 I/O devices PGVCL JE 2018
(b) 256 I/O devices and 65279 memory locations Ans. (a) : The instruction CALL requires 3 Bytes, 5-
(c) 64 K memory locations and no I/O devices machine cycles (OP code fetch, memory Read, Memory
(d) 64K memory locations or input-output Read, Memory write, Memory write ) and 18 T- states
devices for execution in timing.
ESE-2004 95. In a microprocessor, the service routine for a
Ans. (d) : Memory Mapped I/O → In mapped I/O the certain interrupt starts from a fixed location of
I/O devices are also treated as memory location, under memory which cannot be externally set, but the
that assumption they will be given 16 bit address. interrupt can be delayed or rejected such an
memory locations = 216 = 26 × 210 = 64 K memory interrupt is–
locations. (a) Non-maskable and non-vectored
91. What is the main purpose of Accumulator? (b) Maskable and non-vectored
(a) temporary data storage (c) Non-maskable and vectored
(b) keeping track of the next instruction to be (d) Maskable and vectored
executed BSNL TTA 29.09.2016, 3 pm
Electronics-II 880 YCT
Ans : (d) In a microprocessor, the service routine for a 100. An 8085 microprocessor based system uses a
certain interrupts starts from a fixed location of memory 4k×8 bit RAM Whose starting address is
which cannot be externally set, but the interrupt can be AA00H. The address of the last byte in this
delayed or rejected such an interrupt is maskable and RAM is
vectored. (a) 0FFF H (b) 1000 H
96. In Intel 8085, the interrupt enable flip-flop is (c) B9FF H (d) BA00 H
reset by ISRO TA- 2017
(a) DI instructions only BSNL TTA 27.09.2016, 3PM
(b) System RESET only ESE- 2012
(c) Interrupt acknowledgement only Ans. (c) : Given,
(d) either DI or system RESET or interrupt The size of RAM = 4k × 8bit
acknowledgement = 2 2 × 210 × 8 bit
ESE-2004
= 212 × 8 bit
Ans. (d) : In intel 8085, the interrupt enable flip flop is
reset by either DI or system RESET or interrupt So, 12 address lines will be engaged,
acknowledgement. Hence,
The DI instruction stand for 'disable interrupts'. It is an Number of address location in RAM = 0FFF H
1 byte instruction. When this instruction is executed, the Starting address = AA00H (Given)
IE (interrupt enable) flip flop is reset. The disable the
8085 interrupt system except for the TRAP pin.
97. In how many different modes a universal shift
register operates
(a) 5 (b) 4
(c) 3 (d) 2 101. The interrupt vector table IVT of 8086 contains
BSNL TTA 29.09.2016, 3 pm (a) The contents of CS and IP of the main
Ans : (b) A universal shift register operates in four program address to which the interrupt has
modes. occurred.
Its operating modes are following (b) The contents of CS and IP of the main
Inhibit clock (Temporary data latch) program address to which the control has to
Shift Right (towards QD in direction of QA) come back after the service routine.
Shift Left (towards QA in direction of QD) (c) The starting CS and IP values of the interrupt
Parallel (Broadside) load service routine
98. The non-maskable interrupt pointer of 8086 is (d) The starting address of the IVT.
stored at ESE 2005
(a) 00000H (b) 000FFH Ans. (c) : In the real mode address space of the 8086,
(c) 00000 - 00008H (d) 00000 - 0003FFH 1024(1k) bytes are reserved for the interrupt vector
BSNL TTA 29.09.2016, 3 pm table (IVT). This table contains an interrupt vector for
Ans : (c) The non maskable interrupt pointer of 8086 is each of the 256 possible interrupts. Every interrupt
stored at 00000-00008H because 8086 automatically vector in real mode consists of four bytes and gives the
responses type-2. The 8086 has two hardware interrupt jump address of the ISR for the particular interrupt in
pins i.e. NMI and INTR. NMI is a non maskable segment: offset format.
interrupt and INTR is a maskable interrupt having lower When an interrupt is issued, the processor automatically
priority. One more interrupt P in associated in INTA transfer the current flags. The code segment CS and the
called interrupt acknowledge. instruction pointer EIP (or IP in 16 bit mode) on to the
99. What will be the contents of register AL after stack. The interrupt number is internally multiplied by
the following has been executed four and then provides the offset in the segment 00H
where the interrupt vector for handling the interrupt is
MOV BL, 8C
located. The processor then loads EIP and CS with the
MOV AL, 7E
values in the table. That way CS:EIP of the interrupt
ADD AL, BL vector gives the entry point of the interrupt handler. The
(a) 0A return to the original program that launched the
(b) 0A and carry flag is set interrupt occurs with an IRET instruction.
(c) 6A and the carry flag is set
102. The ALU of a microprocessor performs
(d) 6A and the carry flag is reset
operations of 8-bit two's complement operands.
BSNL TTA 29.09.2016, 3 pm
What happens when the operation 7AH–A2H is
Ans : (b) When performed?
MOV BL, 8C (a) Result=D8H, Overflow and negative flags set.
MOV AL, 7E (b) Result=D8H, Negative flag is set.
ADD AL, BL (c) Result= D8h, No flags set.
is executed the contents of register AL will be 0A and (d) Result= 28H, Overflow flag set.
carry flag is set. ISRO TA 2017
Electronics-II 881 YCT
Ans. (b) : The ALU of microprocessor perform 108. The Central Processing Unit (CPU) consists of
operation of 8 bit two’s complement operands. (a) ALU and Control unit only
operation of 7AH − A2H (b) ALU, Control unit and Registers only
= D8H negative flag is set (c) ALU, Control unit and System bus only
103. In 8085 microprocessor, database byte is of: (d) ALU, Control unit, Registers and Internal bus
(a) 8 bit (b) 16 bit ESE 2019
(c) 4 bit (d) 24 bit Mizoram PSC Nov. 2015, Paper-III
UJVNL JE 2016 Ans. (d) : The CPU consists of following component
BSNL TTA 25.09.2016, Shift-I ALU = Arithmetic and logic unit
Ans. (a) : Data bus used for transfer of data between Control unit
memory and processor or between output device. 8085 Register
microprocessor has 8 bit data bus. Internal bus
104. Which of the following does NOT take place 109. The total average read or write time Ttotal is
when 8085 processor is reset? 1 b 1 b
(a) TS + + (b) TS + +
(a) 8085 gives reset out signal to reset external 2r N 2r rN
hardware T b b
(b) 8085 resets program counter to FFFFH (c) S + (d) TS + 2r +
(c) The interrupt system is disabled rN N rN
(d) The buses are tristated Where,
ESE-2005 TS = average seek time
b = number of bytes to be transferred
Ans. (b) : • In 8085 µp when reset pin goes active all N = number of bytes on a track
internal operations are suspended and the program r = rotation speed, in revolutions per second
counter holds 0000H. ESE 2019
• RESET in pin is used to reset the 8085 µp by setting Ans. (b) : Total average read or write time
the program counter to zero. = Seek time + Total Delay + Time require to read b
• RESET OUT pin is used to reset all the connected bytes
devices when the microprocessor is reset. Given: Seek time= Ts
105. Which among the following is the basic Rotation speed = r revolution/second
memory cell of dynamic RAM? ∵ r revolution in 1 second
(a) MOSFET (b) Transistor and a capacitor 1
(c) Capacitance (d) Flip-flop ∴ revolution in second
NMRC JE 2019 r
1
Ans. (b) : The basic memory cell of dynamic RAM is Total delay =
transistor and a capacitor. DRAM stores bit as a charge. 2r
The advantage of DRAM are that it has high density Number of bytes on a track = N
and low power consumption cheaper than static 1
N bytes can be transferred in second
memory. r
106. Which one of the following is the software 1
1 byte can be transferred in second
interrupt of 8085 microprocessor? rN
(a) RST 7.5 (b) RST 7 b
(c) TRAP (d) INTR b bytes can be transferred in second
ESE-2006 rN
total average read or write time.
Ans. (b) : Software interrupt of 8085 microprocessor 1 b
provides 8 RESTART instruction: RST 0 - RST 7. = Ts + +
Each of these would send the execution to a 2r rN
predetermined hard wired memory location. The 110. Which one of the following statement
function of these ISR is defined by the user. corresponding to execution of SIM instruction
107. Which of the following memories requires is not correct?
refreshing cycle? (a) It will selectively mark all the interrupts of
(a) RAM (b) ROM 8085
(c) Dynamic MOS (d) All of these (b) Contents of bit (D7) are copies on SOD pin
BSNL TTA 28.09.2016, 3 PM only if bit b6 in accumulator is '1'
Ans. (c) Dynamic RAM uses a transistor and capacitor (c) RST 7.5 can reset without executing ISR for
pair that needs frequent power refreshing to retain its RST 7.5
charge because reading a DRAM discharges its (d) It can handle interrupts and serial I/O
contents, a power refresh is required after each read ESE-2007
apart from reading, just to maintain the charge that Ans. (a) : SIM- (Set Interrupt Mask) is a multipurpose
holds its content in place, DRAM must be refreshed 1-byte instruction. The main uses of SIM are-
after a specified number of cycles. DRAM is the least • It can handle interrupts and serial I/O data.
expensive kind of RAM. • Masking /unmasking of RST 7.5, RST 6.5 and RST 5.5
Electronics-II 882 YCT
• Reset 0 to RST 7.5 flip-flop 115. The contents of the accumulator and register C
• RST 7.5 can reset without executing ISR for RST 7.5 are 2EH and 6CH respectively. The instruction
• If bit D6 in accumulator is one then contain of bit D7 ADD C is used. The values of AC and P flags
are copies on SOD pin. are
(a) 0 and 0 (b) 1 and 1
(c) 0 and 1 (d) 1 and 0
ESE 2019
Ans. (b) : Given, The content of accumulator = 2E H
Content of register C = 6C H

111. Features of solid state drives (SSDs) are

1. High performance in input/output operations
per second
2. More power consumption than comparable
size HDDs
3. Lower access times and latency rates
4. More susceptible to physical shock and
vibration Hence, Auxiliary carry (AC) = 1
(a) 2 and 3 only (b) 2 and 4 only Parity (even) (P) = 1
(c) 1 and 3 only (d) 1 and 4 only 116. Which one of the following is the correct
ESE 2019 sequence of steps for executing an instruction
Ans. (c) : SSD can locate, retrieve or write data during CPU's processing?
instantly. There is no any movable read write head like (a) Fetch instruction, Read data, Decode
hand disk (HDD). SSD uses software- instructions to go instruction, Store data and Execute instruction
directly to the location where data is stored. So access (b) Decode instruction, Read data, Execute
time is reduced. instruction, Fetch Next instruction and Store
Since, there is no any moving parts in SSD. So there are data
less power consumption while working and while idle. (c) Decode instruction, Decode Next operands,
Fetch Next instruction, Execute instruction
112. Which of the following instructions of 8085 are and Store data
the examples of implied addressing? (d) Fetch instruction, Decode instruction, Read
1. CMA operands, Execute instruction and Store data
2. IN byte ESE 2020, 2012
3. RET Ans. (d) : The basic steps in the instruction cycle-
(a) 1, 2 and 3 (b) 1 and 2 only
(c) 2 and 3 only (d) 1 and 3 only • First of all the op-code is fetched by microprocessor
from a stored memory location.
ESE 2019
• Then it is decoded by the microprocessor
Ans. (d) : Implied addressing refers to instructions that
• If an instruction contains data or operand address
comprise only an op-code without an operand.
which is still in the memory, the CPU has to perform
For example- INCA (Increment accumulator) read operation to get the desired data.
CMA (Complement accumulator)
• Finally receiving data will be execute the operation
RET (Return)
Fetch→decode→read operands→execute →store data.
113. In microprocessor interface, the concept of
detecting some error condition such as 'no 117. The instruction ANA M is
(a) Four byte instruction
match found' is called
(b) Three byte instruction
(a) Syntax error (b) Semantic error
(c) Two byte instruction
(c) Logical error (d) Error trapping
(d) One byte instruction
ESE 2019
BIS TA (Lab) 2020
Ans. (d) : The concept of detecting some error
condition such as “no match found” is called error Ans. (d) : In 8085 microprocessor, instruction ANA M
trapping. Error trapping is a very important part of real is one byte instruction
programs. Mnemonics Bytes
AND A - 1
114. The maximum number of input or output AND B - 1
devices that can be connected to 8085 AND C - 1
microprocessor are AND D - 1
(a) 8 (b) 16 AND E - 1
(c) 40 (d) 256 AND H - 1
ESE 2019 AND L - 1
Ans. (d) : 8085 microprocessor has 8 bit address Hence AND M - 1
28 = 256. I/O devices can be connected. ANI Data - 2
Electronics-II 883 YCT
In 8085 instruction set, ANA is mnemonic, which (b) Acknowledges interrupt and branches off
stands for "AND Accumulated" and M stands for one subroutine
of the memory location pointed by HL register pair. (c) Acknowledges interrupt and continuous
There are eight op-codes for this type of instruction. It interrupt
is occupies only 1-byte in memory. (d) Acknowledges interrupt and waits for the
118. The contents of memory location 4 FFFH are next instruction from the interrupting device.
11011011. The memory word could not be RRB SSE Bilaspur Yellow paper, 21.12.2014
interpreted as which one of the following? Ans : (d) In a microprocessor when a CPU is
(a) 2's complement number interrupted, it acknowledges interrupt and waits for the
(b) 1's complement number next instruction from the interrupting device.
(c) Octal number 123. An Intel 8085A microprocessor is operated at a
(d) BCD number frequency of 2 MHz. If the instruction LXIH,
ESE-2007 E000H that takes ten 'T' states, is executed,
Ans. (d) : The content of memory location 4 FFFH are then what is the instruction cycle time?
11011011. The memory word could not be interpreted (a) 10 µs (b) 5µs
as BCD number. (c) 4 µs (d) 2.5µs
In BCD code each decimal number is represented by a 4 ESE-2008
bit binary number. In BCD only 4 bit binary number 1 1
valid from 0000 to 1001. Ans. (b) : T = = = 0.5 µ sec
f 2MHz
119. The timer clock frequency and its period for Instruction cycle = 10 × T states
the crystal frequency of 13 MHz will be = 10 × 0.5 µ sec = 5 µsec
(a) Clock frequency = 1.08 Hz and Time Period 124. What language is understood by 'Micro
= 0.9s processor'?
(b) Clock frequency = 1.08 Hz and Time Period (a) Binary (b) Fortran
= 0.9µs (c) Instruction (d) C++
(c) Clock frequency = 1.08 MHz and Time JKSSB JE 2014
Period = 0.9µs Ans. (a) : The microprocessor is a multipurpose, clock -
driven, register - based, digital integrated circuit that
(d) Clock frequency = 1.08 MHz and Time
accepts binary data as input, processes it according to
Period = 0.9s instructions stored in its memory, and provides result
BIS TA (Lab) 2020 (also in binary form) as output.
Ans. (c) : Given that- 125. Three devices P,Q and R have to be connected
Crystal frequency = 13 MHz to an 8085 microprocessor. Device P has the
In 8051 microcontroller clock frequency highest priority and device R has the lowest
Crystal frequency priority. In this context, which of the following
= is the correct assignment of interrupt inputs?
12
(a) P uses TRAP, Q uses RST 5.5 and R uses
13
= = 1.08MHz RST 6.5
12 (b) P uses RST 5.5, Q uses RST 6.5 and R uses
1 1 RST 7.5
Time period (T) = = = 0.92 µ sec (c) P uses RST 7.5, Q uses RST 6.5 and R uses
f 1.08
= 0.9 µ sec RST 5.5
(d) P uses RST 5.5, Q uses RST 6.5 and R uses
120. What is the number of machine cycles in the TRAP
instruction LDA 2000H that consists of ESE-2014, 2008
thirteen states? Ans. (c) : In interrupts priority order is
(a) 2 (b) 3 TRAP>RST7.5>RST6.5>RST5.5>INTR.
(c) 4 (d) 5
ESE-2008 126. In microprocessor architecture, flag indicates
(a) the number of the microprocessor
Ans. (c) : Instruction LDA 2000H required 3 bytes, 4
(b) the name of the manufacturer
machine cycles (Opcode Fetch, Memory Read, Memory (c) the internal status of the CPU
Read, Memory Read) and 13T states for execution. (d) the bit size of the microprocessor
121. Program counter (PC) register is an integral Mizoram PSC Nov. 2015, Paper-III
part of : BSNL TTA (JE) 14.07.2013
(a) Hard Disk (b) RAM Ans. (c) In microprocessor architecture, flag indicates the
(c) Cache memory (d) CPU
internal status of central processing unit (CPU). In 8085
RRB SSE (Shift-II), 03.09.2015
microprocessor, flag register consists of 8 bit but 8085
Ans : (d) Program counter (PC) register is an integral microprocessor has 5 active flag namely sign (S), zero (Z),
part of CPU.
Auxiliary carry (AC), carry (CY) and parity (P) flag.
122. In a microprocessor when a CPU is
interrupted, it
(a) Stop execution of instructions
Electronics-II 884 YCT
127. What are the number of memories required of 132. To address the memory 14 bits are used. Then
size 16 × 4 to design a memory of size 64 × 8 ? what is the address of the last memory
(a) 2 (b) 4 location?
(c) 6 (d) 8 (a) 16382 (b) 16383
ESE-2009 (c) 16384 (d) 16385
64 × 8 ESE-2009
Ans. (d) : Number of memory chip = =8 Ans. (b) :
16 × 4
128. An output device is interfaced with an 8085
microprocessor as memory-mapped I/O. The
address of the device is 1000H. In order to output
data from the accumulator to the device, what
will be the sequence of instructions?
(a) LXIH, 1000H MOV A, M ≡ ( 3FFF )16 = (16383)10
(b) LXI H, 1000H MOV M, A 133. The TIMER of PPI 8155 is of
(c) LHLD 1000H MOV A, M (a) 16 bits (b) 14 bits
(d) LHLD 1000H MOV M, A (c) 12 bits (d) 8 bits
ESE-2009 Mizoram PSC Nov. 2015, Paper-III
Ans. (b) : LXI Rp d-16→ Load the 16 bit data into the Ans. (a) : The timer of PPI of 8055 is of 16 bit (two 8-
register pair bit) 8155 is a programmable timer microprocessor.
MOV M r → Copy 8-bit data from the ‘r’ to the 134. A microprocessor contains ROM chip which
memory location as pointed by HL register pair. contain
In order to output data from the accumulator to the (a) Control function
device the sequence of instructions will be LXIH, (b) Arithmetic function
1000H MOV M, A. (c) Instruction to execute data
129. Instruction RET (Return) of a 8085 (d) Memory functions
microprocessor Mizoram PSC Nov. 2015, Paper-III
(a) Stack Pointer and program counter Ans. (d) : A microprocessor contain ROM chip which
(b) Stack Pointer only contain memory function. ROM (read only memory) is
(c) Program counter only an electronic storage elements which contain the data in
(d) Set interrupt mask and accumulator it.
Mizoram PSC Nov. 2015, Paper-III
135. Handshaking mode of data transfer is
Ans. (d) : RET is the instruction used to mask the end
(a) Synchronous data transfer
of sub routine. It has no parameter after execution of
(b) Asynchronous data transfer
this instruction program control is transferred back to
main program from where it had stopped. A value of PC (c) Interrupt driven data transfer
(Program counter) is retrieved from the memory stack (d) Level mode of DMA data transfer
and value of SP (Stack pointer) is incremented by 2. ESE-2010
130. For 16 bit address- but, if an 8K RAM chip is Ans. (b) : Handshaking mode of asynchronous data
selected when A13, A14 and A15 address bits are transfer-
all one, then what is the range of the memory • The clock rates for sender and receiver may be
address? quite different.
(a) E000H-EFFFH (b) E000H-FFFFH • The sender needs to know whether the receiver has
(c) F000H-FFFFH (d) F000H-FEEEH received the information.
ESE-2009 • Handshaking is a way to enable sender and receiver
Ans. (b) : to coordinate data transfers.
Types of handshaking-
• Simple output
• Simple strobe
• Single handshaking
Hence, range = E000H to FFFFH. • Double handshaking
131. Instruction CALL of a 8085 microprocessor has 136. The program counter in a 8085 microprocessor
(a) 1 byte (b) 2 bytes is a 16-bit register, because
(c) 4 bytes (d) 3 bytes (a) It counts 16 bits at a time
Mizoram PSC Nov. 2015, Paper-III (b) There are 16 address lines
Ans. (d) : In 8085 Microprocessor, the instruction CALL (c) It facilities the user storing 16 bit data
is a 3 byte instruction. The address of the next instruction temporarily
after the CALL instruction is called the return address. (d) It has to fetch two 8-bit data at a time
This is the address to which the program flow returns Mizoram PSC Nov. 2015, Paper-III
when the RET instruction is executed by the 8085 ESE 2003
Mnemonics operand − CALL label Ans. (b) : The program counter in a 8085 micro
Op code (in HEX) − CD processor is a 16 bit register because there are 16
Bytes − 3 address line.
Electronics-II 885 YCT
137. When memory write or I/O read are active, Ans. (a) : When CPU of an 8085 µp receives an
data remains _______of the processor. interrupt then-
(a) Input (b) Output
(c) Processor (d) None of these • First of all, the current task will finish.
UPPSC AE 13.12.2020, Paper-II • After completion of current instruction, it goes to the
Ans. (b) : When memory write or I/O read are active interrupt service routing.
data remains output of the processor and when memory 143. The basic memory cell in a DRAM is a
read or I/O write are active data remains input of the (a) MOSFET
processor. (b) Capacitor
138. In mode '0' (zero) operation of 8255, the ports (c) Capacitor and a MOS switch
can be used as port: (d) Flip-Flop
(a) A as input port only UKPSC JE 2013, PAPER-I
(b) B as output port only Ans.(c): Dynamic random– access memory is a type of
(c) A as output port only random–access semiconductor memory that stores each
(d) A as input or output port bit of data in a memory cell consisting of a tiny
ESE-2010 capacitor and a transistor, both typically based on
Ans. (d) : The 8255 can operate in 3 I/O modes. metal–oxide–semiconductor technology.
(i) Mode 0 (ii) Mode 1 (iii) Mode 2 Dynamic RAM Data is stored in MOS switch and
In mode 0, port A and port B can be configured as capacitor.
simple 8-bit input or output port without hand shaking. In static RAM data is stored like flip-flop.
139. Both the ALU and control section of CPU 144. Which of the following are 3 byte instruction set?
employ which special purpose storage (a) MVI A, 32 H (b) JMP 2085 H
locations? (c) MOV C, A (d) ADD B
(a) Buffers (b) Decoders UKPSC JE 2013, PAPER-I
(c) Accumulators (d) Registers Ans. (b) : MVIA, 32 H – 2 byte instruction
BSNL TTA 26.09.2016, 3PM MOVC, A – 1 byte instruction
Mizoram PSC Nov. 2015, Paper-III ADDB – 1 byte instruction
Ans. (c) : Both the ALU and control section of CPU JMP2085H – 3 byte instruction
employ store in accumulator. Accumulator is a 8 bit 145. Memory range of a memory chip 1 K is
general purpose register. An accumulator is a type of (a) 0000H to 03FFH (b) 0001H to 01FFH
register included in a CPU it acts as a temporary storage
(c) 0000H to 02FFH (d) 0000H to 04FFH
location which is used for almost all arithmetic and
logic operation. UKPSC JE 2013, PAPER-I
140. After completing the execution, microprocessor Ans. (a) : The range of memory chip of 1K is given by
returns to from 0000H to 03FFH.
(a) Halt state (b) Execute state 146. ALE stands for
(c) Fetch state (d) Interrupt state (a) Address latch enable
Mizoram PSC Nov. 2015, Paper-III (b) Accumulator latch enter
Ans. (c) : After completing the execution of any code or (c) Address latch enter
program the micro-processor return to fetch state after (d) None of the above
fetching the instruction it provide the output. HPSSC JE 2017(Code-580)
141. Which one of the following is a non-maskable Ans. (a) : ALE is stand for address latch enable. ALE is
interrupt? control signal which is nothing but a positive going
(a) RST 7.5 (b) RST 6.5 pulse generated when a new operation is started by
(c) RST 5.5 (d) TRAP microprocessor so when pulse goes high means ALE=1.
UKPSC JE 2013, PAPER-I 147. Which value a program counter will have when
non maskable interrupt of 8085 microprocessor
Ans. (d) : TRAP – non maskable interrupt
is serviced?
RST – 7.5 – maskable interrupt (a) 0004H (b) 0014H
RST – 6.5 – maskable interrupt (c) 0024H (d) 0034H
RST – 5.5 – maskable interrupt ESE-2011
142. On receiving an interrupt the CPU of an 8085 Ans. (c) :.
microprocessor Interrupt Triggering Vectored Maskable/No
(a) completes the current instruction and then Address n-maskable
goes to the interrupt service routing
TRAP Edge and 0024H Non-maskable
(b) Branches off the the interrupt service routing
level
immediately
(c) hands over control of address bus and data RST 7.5 Edge 003CH Maskable
bus to the interrupting device RST 6.5 Level 0034H Maskable
(d) Goes to HALT state for pre determined RST 5.5 Level 002CH Maskable
period INTR Level Non Maskable
ESE-2010 vectored
Electronics-II 886 YCT
148. What is the functionality of the program given Ans. (d) : For given chip selection
below? A15 = 1, A14 = 0, A13=0, A12 = 0, A11 = 0
MOV A, #0
MOV R2, #10
AGAIN: ADD A, # 03
DJNZ R2, AGAIN
MOV R5, A
(a) It clears the accumulator and add value 3 to Then range = 8800H-8FFFH
the accumulator 10 times. 152. In an 8085 microprocessor, the instruction
(b) It adds the content of R2 and A and then store CMP B has been executed while the content of
the result in accumulator the accumulator is less than that of register B.
(c) It decrements the register R2 10 time and then
As a result
store value 3 to the accumulator.
(d) It clears the accumulator and then add value (a) Carry flag will be set but Zero flag will be reset
13 to the accumulator 10 time. (b) Carry flag will be reset but Zero flag will be set
BSPHCL JE 30.01.2019, Shift-II (c) Both Carry flag and Zero flag will be reset
Ans. (a) : The given program first clear the accumulator (d) Both Carry flag and Zero flag will be set
and than add value 3 to the accumulator 10 times. BSNL TTA (JE) 25.09.2016, Shift-I
149. The appropriate return addresses are obtained Ans. (a) : In an 8085 microprocessor, the instructions
with the help of —————— in case of nested CMP B has been excuted while the content of the
routines. accumulator is less than that of register B. As a result
(a) Memory Address Register carry flag will be set but zero flag will be reset.
(b) Memory Data Register 153. The contents of accumulator after the
(c) Buffers execution of following instructions will be–
(d) Stack-pointers MVI A, B7H
APGCL JM 2021
ORA A
Ans. (d) : A stack pointer is a register, that stores the RAL
address of the last program request in a stack. (a) 6EH (b) 6FH
• A stack is a specialized which store data from the top (c) EEH (d) EFH
to down. As new requests come in they “push down”
the older ones. BSNL TTA (JE) 25.09.2016, Shift-I
• The appropriate return addresses are obtained with the Ans. (a) : The content of accumulator after the
help of stack pointers in case of nested routines. execution of given instruction will be 6EH.
150. The number of memory cycles required to MVI A, B7H
execute the following 8085 instructions A = B7
(i) LDA 3000 H ORA A
(ii) LXI D, FOF 1 H A+A = A
would be– A = B7
(a) 2 for (i) and 2 for (ii) A = 1011 0111
(b) 4 for (i) and 3 for (ii)
(c) 3 for (i) and 3 for (ii)
(d) 3 for (i) and 4 for (ii)
BSNL TTA (JE) 25.09.2016, Shift-I
Ans. (b) : The number of memory cycles required to
excute the given 8085 instructions A = 0110 1110
(c) LDA 300 H A=6E
(II) LXI D, FOF 1H
would be 4 for (I) and 3 for (II). 154. Which one of the following statements is not
correct?
151. The logic circuit used to generate the active low (a) CMPA is a single byte instruction and CMA
chip select signal ( CS ) by in Intel 8085 is not an instruction
(b) The instruction SUB a sets the zero flag
microprocessor to address to address a
(c) Bus is a group of wires
peripheral is shown in figure. The peripheral
(d) Instruction INR does not affect carry flag
will respond to address in the range.
ESE-2011
Ans. (a) : CMP A – CMPA is a single byte instruction.
It stand for ‘compare with accumulator’. It is an implicit
addressing mode.
CM A – CMA is also a single byte instruction. It stand
(a) 7800H-7FFFH (b) 1000H-1EFFH
for ‘complement the content of accumulator’.
(c) 8000H-8FFFH (d) 8800H-8FFFH
ESE-2011 It is also an implicit addressing mode.

Electronics-II 887 YCT

155. To execute the following instructions Ans. (b) : NMI input is an edge triggered and positive
(i) LDA 2100H edge i.e. 0 to 1 transition.
(ii) LXIH, 2100H
In computing, a non-maskable interrupt (NMI) is a
By an Intel 8085 microprocessor the numbers
of memory cycles required are hardware that can not ignore standard interrupt masking
(a) 2 for (i) and 2 for (ii) technology in the system. This usually indicates
(b) 4 for (i) and 2 for (ii) attention to non-recoverable hardware error.
(c) 3 for (i) and 3 for (ii) 159. An example of 8085-instruction that uses direct
(d) 4 for (i) and 3 for (ii) addressing is
ESE-2011 (a) RLC (b) STA
Ans. (d) : (c) RRC (d) CMA
Parameter LXIH 2100 H LDA 2100 H ESE-2010
operation this instruction this instruction Ans. (b) : Direct Addressing mode- STA, LDA
loads 2100 H in loads 2100H in Implicit addressing mode- RLC, CMA, RRC .
the accumulator. the HL register
pair. 160. ––––––– data transmission is more useful when
addressing mode direct Immediate sending information for long distances
T-stable 13 10 (a) Serial (b) Parallel
Machine cycle 4 3 (c) Either (d) Neither
156. The total size and the total number of BSNL TTA (JE) 25.09.2016, Shift-I
Interrupts procedures that can be defined in Ans. (a) : The serial data transmission mode is a mode
this memory of 8086 is in which the data bits are sent serially one after the
(a) 256 Bytes, 256 Procedures other at a time over the transmission channel. It needs a
(b) 1K Bytes, 256 Procedures single transmission line for communication. In serial
(c) 256 Bytes, 1K Procedures
data transmission the system takes several clock cycles
(d) 1K Bytes, 1K Procedures
BSNL TTA (JE) 25.09.2016, Shift-I to transmit the data stream.
This type of transmission mode is best suited for long
Ans. (b) : The total size and the total number of
distances data transfer.
interrupts procedures that can be defined in this memory
of 8086 is 1K Byte, 256 procedures. It is a two byte 161. Which of the following instruction of 8085
instruction, the first byte provides the OP code and the microprocessor has maximum T states when
second byte provides the interrupt type number. There compared to others?
are 256 interrupt types under this group. (a) DAD (b) ADI
157. According to Flynn's classification, which (c) XCHG (d) SUI
architecture is of only theoretical interest and TSPSC Manager (Engg.)HMWSSB 2020
no practical system has been developed based Ans. (a) : DAD instruction of 8085 microprocessor has
on it? maximum T states (10) compared to others. In 8085
(a) Single instruction single Data (SISD) instruction. DAD SP instruction is a special case of
(b) Single Instruction Multiplied Data (SIMD) DAD rp instruction. In this instruction contents of HL &
(c) Multiple Instruction Single Data (MISD) SP will get added and produced will get stored onto HL
(d) Multiple Instruction Multiple Data (MIMD)
resistor pair.
ESE-2013
Ans. (c) : Flynn’s classification is based on the number 162. In a microprocessor based system, DMA
of instruction and data streams. There are four facility is required to increase the speed of the
categories of computing systems- data transfer between the
• SISD system (a) microprocessor and the I/O memory
• SIMD system (b) microprocessor and I/O devices
• MISD system (c) memory and the I/O devices
• MIMD system (d) memory and register
MISD (Multiple instruction single data) is a ESE-2013
multiprocessor machine capable of executing different Ans. (c) : • DMA (Direct memory Access) is a feature
instructions on different PEs but all of them operating on of computer systems that increases the speed of the data
the same data set. No practical system only theoretical
transfer between the memory and the I/O devices.
interest system has been developed based on it.
• DMA is used when a large amount of data is to be
158. NMI input is
printed out from the memory of a computer.
(a) Edge Triggered on Negative edge i.e. 1 to 0
transition • DMA allows certain hardware subsystem to access
(b) Edge Triggered on Positive edge i.e. 0 to 1 main system memory (RAM) independent of the CPU.
transition 163. The brain of any computer is
(c) Level triggered on 1 (a) ALU (b) CPU
(d) Level triggered on 0 (c) ROM (d) RAM
BSNL TTA (JE) 25.09.2016, Shift-I BSNL TTA (JE) 25.09.2016, Shift-I
Electronics-II 888 YCT
Ans. (b) : The brain of any computer system is CPU. Ans. (a) :
The CPU collects the input information in a coded • Input mapped system identify their input/output
system and reads it and send it to the output via screen. devices by given them on 8 bit port number.
Central processing unit (CPU) consists of the fallowing Multiplexing is done to reduce the number of pins
features- in the microprocessor.
(i) CPU is considered as the brain of the computer. • If address and data bus are not multiplexed then
(ii) CPU performs all types of data processing operations. number of pins required are 16 for address bus and
(iii) It controls the operation of all parts of the computer. 8 for data bus, total 24 pins are required.
164. Programmable logic Array (PLA) uses–––––– • With multiplexing, 8 pins are common used
(a) PROM matrices (b) RAM matrices between address and data pins and thus total pins
(c) Silo memory (d) ROM matrices
required are 16.
BSNL TTA (JE) 25.09.2016, Shift-I
169. A microprocessor is called an 'n-bit
Ans. (d) : Programmable logic array (PLA) uses ROM
microprocessor' depending on-
matrices. The desired output for each combination of
(a) Register length
input is programmed into the ROM, with the input
loaded into address bus and read as output data. (b) Size of the internal data bus.
Programmable connection for both AND and OR arrays (c) Size of external data base
of PLA, so it is most flexible type of PLD. (d) None of these
165. Debug is synonymous to ––––––––––– BSNL TTA (JE) 2013
(a) Erase (b) exponent Ans. : (b) If a microprocessor is called 'n-bit
(c) trouble shoot (d) emulate microprocessor' then n refers to size to internal data bus.
BSNL TTA (JE) 25.09.2016, Shift-I 170. In 8085 microprocessor, the RST6 instruction
Ans. (c) : Debug is synonymous to trouble shoot. transfer programme execution to following
Debugging is subset of troubleshooting. It requires location
finding problems as they relate to computer code. As (a) 0030H (b) 0024H
programmer, when you are tasked with debugging a (c) 0048H (d) 0060H
module of code you find what is causing the problem Haryana SSC JE 08.04.2018, Shift-I
and then fix it. Ans. (a) : In 8085 instruction set, RSTn is actually
166. Sixty-four number of 256×1 bit RAM IC is standing for "Restartn" and in this case, n has value
arranged in 8 rows and 8 columns to get from 0 to 7.
memory
(a) 1 kB (b) 2 kB RSTn = CALLn × 8
(c) 4 kB (d) 8 kB According questions-
ESE-2010 RST 6 = 6 × 8
Ans. (b) : Memory size = 256 ×1× 64 RST 6 = 48
= 28 × 26 = 2 × 210 × 23 16 48 0
= 2kB Hexadecimalof 48 = 3
167. As compared to 16 bit microprocessors. 8 bit
microprocessors are limited in-
(a) Speed So, RST 6 Instruction = CALL 0030H
(b) Data handling capability 171. In a 5 × 7 dot matrix format
(c) Directly addressable memory (a) 64 bits are required to store 64 alphanumeric
(d) All of the above characters.
BSNL TTA (JE) 2013
(b) 560 bits are required to store 64 alphanumeric
Ans. : (d) We compare 16bit microprocessor and 8 bit
microprocessor. characters.
16 bit 8 bit (c) 1120 bits are required to store 64
microprocessor microprocessor alphanumeric characters
Speed High low (d) 2240 bits are required to store 64
Data More Less alphanumeric characters
handling ESE-2014
capability Ans. (d) : An ASCII code there 10 decimal number, 28
Memory Large Small letters and 26 selected symbols i.e. altogether 64 alpha
8 bit microprocessor is limited for all of above. numeric characters, so that group code convertor would
168. I/O mapped system identify their input/output require 5 × 7 × 64 = 2240 bits.
devices by giving them an 172. The pin configuration of 8086 is available in
(a) 8 bit port number
(b) 16 bit port number the___
(c) 8 bit buffer number (a) 40 pin (b) 50 pin
(d) 16 bit buffer number (c) 30 pin (d) 20 pin
ESE-2013 BSNL TTA (JE) 2013
Electronics-II 889 YCT
Ans. : (a) In microprocessor 8086 has 40 pins. Ans. : (d) Mnemonic codes are used to assist human
memory and it is widely used in computer programming
and communication system operations to specify
instructions.
177. Direct memory access channel (DMA)
facilitates data to move in and out of the system
(a) on first-come first serve basis
(b) with equal time delay
(c) without a sub-routine
(d) without program intervention
BSNL TTA JE 27.09.2016, 10 AM
ESE-2014
Ans. (d) : The problem of slow data transfer between
input-output port and memory or memory to memory is
reduced by DMA technique.
DMA facilitates data to move in and out of the system
without program intervention.
DMA increase the speed of the data transfer between
the memory and the I/O devices..
173. In order to generate continuous square wave 178. The number of 256 × 4 bits RAM chips
using 8254 timer, it must be programmed in required to get 1 K Byte of memory size is
(a) mode 0 (b) mode 1 (a) 1 (b) 8
(c) mode 2 (d) mode 3 (c) 4 (d) None
ESE-2014 JPSC AE 10.04.2021, Paper-I
Ans. (d) : 8254 is a programmable interval timer. There size of M 2
are six operating modes of 8254 timer. Ans. (b) : Number of chips required (n) =
size of M1
1. Mode 0- Interrupt on terminal count
2. Mode 1- Hardware retriggerable one shot M1 = Available capacity
3. Mode 2- Rate generator M2 = Memory to be designed
4. Mode 3- Square wave generator 1024 × 8bit
n= =8
5. Mode 4- Software triggered strobe 256 × 4bit
6. Mode 5- Hardware triggered strobe
179. Intel 8085 is an____MPU:
174. Microprocessor 8085 can address location up (a) 8 bit NMOS (b) 8 bit CMOS
to (c) 8 bit PMOS (d) 8 bit HMOS
(a) 32K (b) 128K BSNL TTA (JE) 27.09.2016, 10 AM
(c) 64K (d) 1M
Ans. (a) 8085 is a 8-bit N-MOS microprocessor and it is
Mizoram PSC IOF-2019, Paper-III
a chip fabricated 40 pin IC [integrated circuit]. +5V DC
BSNL TTA (JE) 2013
supply used in 8085 microprocessor. Its operating
Ans. : (c) In 8085 microprocessor, frequency is almost 3MHz and its time period is 300 n
Total number of address bus ( n ) = 16 sec.
So maximum address location = 2n = 216 It have 74 instruction and 246 opcodes.
= 26×210 180. A device or a peripheral equipment which is
= 64K not is direct communication with CPU of a
175. The smallest valid signed integer that can be computer is called
stored in a memory location of a 4K × 8 bit (a) off line device (b) on line device
RAM is (c) active device (d) slow device
(a) 0 (b) -128 ESE-2014
(c) -2048 (d) -65536 Ans. (a) : Off line peripheral device communicate with
ESE-2010 CPU indirectly. Off line devices are not connected to
Ans. (b) : In computer 2’ complement representation CPU.
generally used. For 8 bit 181. For a 4096 × 8 EPROM, the number of address
Maximum positive number = 2 n −1 − 1 = 28−1 − 1 = +127 lines is:
(a) 14 (b) 12
Maximum negative number = −2 n −1 = −28−1 = −128 (c) 10 (d) 8
So smallest valid signed integrator is = –128. BSNL TTA (JE) 27.09.2016, 10 AM
176. Mnemonic codes are used Ans. (b) 2 N × M
(a) To denote address
Where N → Address line
(b) To employ hamming code
(c) To denote errors and M → data lines
(d) To assist human memory ∵ Given as - 4096×8
BSNL TTA (JE) 14.07.2013 ∴ 212 × 8
Electronics-II 890 YCT
 ∴ Address lines (N) = 12 (c) handle one more interrupt requests with a
In these microprocessor system, Read/ write memory delay
have 12 address line in this location, 4096×8 EPROM (d) handle no interrupt request
stored in machine code. Initial address line in this BSNL TTA (JE) 27.09.2016, 10 AM
location is 4096. Ans. (b) The need of programmable interrupt control
182. Shifting the contents of a register, left by one unit is when more interrupt is managed of a time in
place, is equivalent to: microprocessor, If INTR means interrupt request is
(a) Dividing the contents by 10 provided to microprocessor then we have to connect are
(b) Dividing the contents by 2 out side chip is needed.
(c) Multiplying the contents by 2 187. To interface a slow memory, wait states are
(d) None of these added by
BSNL TTA (JE) 27.09.2016, 10 AM (a) extending the time of the chip select logic
Ans. (c) Shifting a binary number by one bit to left is (b) causing READY signal to go low
equal to multiplying by 2. (c) causing READY signal to go high
(d) by increasing the clock frequency
and when shifting a binary number by one bit to right is
ESE-2015
divide by 2.
BSNL TTA (JE) 14.07.2013
183. Which one of the following is used for serial Ans. (b) : When microprocessor needs to interface with
I/O transfer in 8085 based system? a slow external memory. It starts placing the address of
(a) 8251 (b) 8255 the requested information on the address BUS.
(c) 8259 (d) 8279 It then must wait for the answer, each of the cycles
ESE-2015 spent waiting is called a wait state that helps to interface
Ans. (a) : The 8251 is a Universal Synchronous slow peripherals to the memory.
Asynchronous Receiver Transmitter (USART) for serial The wait states are added by causing a READY signal
data communication. As a peripheral device of a to go low.
microcomputer system, the 8251 receives parallel data 188. A semiconductor ROM is preferred to a
from the microprocessor, converts it into serial data and semiconductor RAM because-
then transmits the serial data. (a) ROM is cheaper than RAM
184. Simple Delay Circuit can be constituted by: (b) ROM is faster
(a) Shift Registers (b) Flip Flops (c) ROM does not require power supply for their
(c) Multiplexer (d) All of these operation
BSNL TTA (JE) 27.09.2016, 10 AM (d) Program stored in the ROM cannot be altered
Ans. (a) Simple delay circuit made by shift registers. ESE- 2011
Ans. (d) :
• ROM is a semiconductor memory.
• The stored data of ROM remains same when power
goes off.
• ROM is a non-volatile memory
• The program stored in ROM can not be altered by
the power or user.
189. The correct sequence of steps to perform
"Fetch" operation in microprocessor is:
1. Opcode is decode
2. Places the address of first byte of instruction on
the address bus
3. Gets opcode on the data bus
(a) 1, 2, 3 (b) 3, 1
(c) 2, 1 (d) 2, 3, 1
BSNL TTA (JE) 27.09.2016, 10 AM
185. Five memory chips of 16 × 4 size have their Ans. (d) The correct sequence of steps to perform
address buses connected together. This system "Fetch" operation in microprocessor is-
will be of size: 1. Places the address of first byte of instruction on the
(a) 16 × 16 (b) 16 × 20 address bus.
(c) 20 × 16 (d) 16 × 64 2. Gets opcode on the data bus.
BSNL TTA (JE) 27.09.2016, 10 AM 3. Opcode is decode.
Ans. (b) Five memory chips each size = 16×4 190. SD RAM refers to:
(a) Static DRAM (b) Synchronous DRAM
Here, data bus = 16 and address bus = 20 (because 5 × (c) Semi DRAM (d) All of these
4=20) BSNL TTA (JE) 27.09.2016, 10 AM
so system size is 16×20.
Ans. (b) Synchronous DRAM :- Synchronous dynamic
186. The Programmable interrupt controller is RAM is a memory which synchronized with watch
required to: which is suitable for microprocessor. SDRAM speed is
(a) handle one interrupt request measured in MHz rather than nano second.
(b) handle one or more interrupt request at a time
Electronics-II 891 YCT
191. In 8085 microprocessor with memory mapped Ans. : (a) Address bus is unidirectional because data
I/O, which one of the following is correct? flow in one direction, from microprocessor to memory
(a) I/O devices have 16 bit addresses or from microprocessor input/output device. Address
(b) I/O devices are accessed during In and Out bus carries address only.
instructions 196. The 8085 is an enhancement of the popular
(c) There can be a maximum of 256 input and INTEL ______ microprocessor:
256 output devices (a) 8080 (b) 8155
(d) Logic operation cannot be performed (c) 8355 (d) 8086
ESE-2015 BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (a) : Ans. (a) The microprocessor 8085 is an enhancement of
Memory mapped I/O I/O mapped I/O the popular Intel-8080. 8080 microprocessor is 8-bit
1. In this device address 1. In this I/O device microprocessor and also 8085 microprocessor is 8-bit
is 16 bit. Thus A0 to address is 8 bit. Thus A0 microprocessor.
A15 lines are used to to A7 or A8 to A15 lines 8080 microprocessor has 40-pin DIP It has 8-bit data bus
generate device are used to generate and 16-bit address bus . It is made by 6000 transistor.
address. device address. 197. Which of the following is a DMA controller?
2. MEMR and MEMW 2. IOR and IOW control (a) Intel 8257 (b) Intel 8259
(c) Intel 8255 (d) Intel 8253
control signal are used signals are used to BSNL TTA (JE) 27.09.2016, 10 AM
to control read and control read and write Ans. (a) INTEL 8257 is direct memory access
write I/O operations. I/O operations. controller. 8257 is used for high speed and a brush of
3. Data transfer is 3. Data transfer is between data transfer in between input and output devices I/O
between any register accumulator and I/O status check and I/O interrupt data transfer method
and I/O device. devices. reliable low speed process because in execution of
192. A stack is normally send in digital computers every instruction, more time is needed.
to store the return address at the time of a 198. The length of a bus cycle in 8086/8088 is four
subroutine call because: clock cycles, T1, T2, T3, T4 and an
(a) Stack are nonvolatile memories indeterminate number of wait state clock cycles
(b) Stacks have large capacity denoted by Tw. The wait states are always
(c) Information in a stack cannot be altered by inserted between.
other instructions (a) T1 and T2 (b) T2 and T3
(d) Stack permit easy nesting of subroutine (c) T3 and T4 (d) T4 and T1
BSNL TTA (JE) 27.09.2016, 10 AM ESE-2001
Ans. (d) A stack is normally send in digital computers Ans. (b) : The wait state are extra clock pulses inserted
to store the return address at the time of a subroutine when the processor is accessing slow memory or
call because stack permit easy nesting of subroutine. input/output devices.
In 8086/8085, a wait state (Tw) is an extra clock period
193. Multiplexing of address and data lines is used inserted between T2 and T3 to the length of a bus cycle.
in:
(a) Intel 8086 (b) Z-80
(c) 6502 (d) MC-68000
BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (a) INTEL 8086 is a 16-bit HMOS microprocessor
. It have 40 pin IC (integrated circuit) and 20 bit address
bus and 16-bit data bus these buses are multiplexed with
status signal liner. Lower 8-bit AD0 to AD7 is called
address bus and upper 8-bit AD8 - AD15 is used for
control bus is a microprocessor. 199. To address the full memory space of an Intel
8085 microprocessor four RAMs of different
194. In 8085 MPU, the flag flip flops have_____ sizes are available:
status indicators. 1. 8K ×8 2. 16 K×4
(a) 5 (b) 2 3. 32 K × 4 4. 32 K × 16
(c) 4 (d) 1 What minimal combination of chip (s) will
BSNL TTA (JE) 27.09.2016, 10 AM serve the purpose?
BSNL TTA (JE) 28.09.2021, 10 PM (a) 1,2,3 and 4 (b) 2
Ans. (a) In microprocessor 8085 have 5 flags that is - S, Z, (c) 3 (d) 4
AC, P, CY. Flags are flip-flops that store bit 0 (zero) or ESE- 2011
1(one) based on the arithmetic or logical operation Ans. (c) : Total memory size of 8085 µp = 64 kB
performed by an arithmetical and logical unit (ALU).In = 64k×8 bits
most of the operations, result is store in the accumulator. = 512 k bits
= 32×16 k bits
195. Address bus is If there are four RAMS
(a) Unidirectional (b) Bidirectional 32k × 16
(c) Non-directional (d) Multi-directional Then the size of each = = 32k × 4
BSNL TTA (JE) 14.07.2013 4
Electronics-II 892 YCT
200. An I/O processor control the flow of 205. The 8259 A programmable Interrupt controller
information between: can
(a) cache memory and I/O devices 1. Manage eight interrupts
(b) main memory and I/O devices 2. Vector an interrupt request anywhere in
(c) two I/O devices memory map
(d) cache and main memories 3. Have 8 bit or 16- bit interval between
BSNL TTA (JE) 27.09.2016, 10 AM interrupt vector locations
Ans. (b) I/O processor control the flow of information 4. Initialized with operational command words
between main memory and I/O devices for controlling (OCW's)
of data transfer , microprocessor generate control signal Which are the above statements are correct?
From which read and write operation is done on (a) 1 and 2 (b) 2 and 3
microprocessor. (c) 3 and 4 (d) 1,2,3 and 4
201. Choose the incorrect statement. During DMA ESE-2011
transfer, the processor Ans. (a) : The 8259 A interrupt controller can-
(a) Continues its normal operations Manage eight interrupt according to instructions
(b) Suspends its normal operations written into its control registers.
(c) Needs to initiate read (write) command Vector an interrupt request anywhere in the memory
(d) Needs to check if the I/O device is ready for map. However, all light interrupts are spaced at
data transfer interval of either four or eight locations.
BSNL TTA (JE) 14.07.2013 Mask each interrupt request individually.
Ans. : (a) During DMA transfer, the processor 206. To address a memory location out of N
continues its normal operations, is the incorrect memory locations, the number of address lines
statement. required is-
202. The number of output pins of a 8085 (a) Log N (to the base 2)
microprocessor are (b) Log N (to the base 10)
(a) 40 (b) 27 (c) Log N (to the base e)
(c) 21 (d) 19 (d) Log (2N) (to the base e)
RPSC Lect. (Tech. Edi. Dept.) 16.03.2021, Paper-II BSNL TTA 26.09.2016, 10 AM
Mizoram PSC IOF 2019, Paper-III Ans. (a) : The bits in a selected location are accessible
BSNL TTA 28.09.2016, 3PM
ESE-2002
using data bus. for N memory locations, logN (to the
base of 2) address lines required.
Ans. (b) : The number of output pins of a 8085
Example- For addressing 4k bytes of memory, 12
microprocessor are 27 and input pins in 8085 are 21,
address lines are required since,
because 8 pins are multiplexed, so 8 pin count in both
log2 (4 kB) = log2(4×1024)
input/output pins. Thus total number of pins are 40.
= log2212
203. A shift register can be used for-
(a) Parallel to serial conversion only
= 12 {∵ log 2 2 = 1}
(b) Serial to parallel conversion only 207. What are level triggering interrupts?
(c) Digital time delay only (a) INTR & TRAP
(d) All of these (b) RST 6.5 & RST 5.5
BSNL TTA 26.09.2016, 10 AM (c) RST 7.5 & RST 6.5
Ans. (d) : (d) None of these
A shift register can be used for- BSNL TTA 26.09.2016, 10 AM
Serial to serial conversion Ans. (b) : Interrupts Triggering
Parallel to serial conversion RST 7.5 Positive edge triggered
Serial to parallel conversion RST 6.5 Level triggered
Digital time delay RST 5.5 Level triggered
Parallel to parallel conversion TRAP Both edge and level triggered
204. The number of hardware interrupts (which 208. A microprocessor is ALU
require an external signal to interrupt present (a) and control unit on a single chip
in an 8085 microprocessor are––––––– (b) and memory on a single chip
(a) 1 (b) 4 (c) register unit and I/O device on a single chip
(c) 5 (d) 13 (d) register unit and control unit on a single chip
Mizoram PSC IOF 2019, Paper-III ESE-2003
BSNL TTA 26.09.2016, 10 AM Ans. (d) : Microprocessor is a controlling unit of
BSNL TTA (JE) 27.09.2016, 10 AM microcomputer, and fabricated on a small chip capable
Ans. (c) : Hardware interrupts- When microprocessor of performing ALU (Arithmetic Logical Unit)
receive interrupt signals through pins (hardware) of operation and communicating with the other devices
microprocessor, they are known as hardware interrupts. connected to it. ALU perform arithmetical and logical
There are 5 hardware interrupts in 8085 microprocessor. operations on the data received from the memory or an
They are-INTR, RST 7.5, RST 6.5, RST 5.5, TRAP. input device.
Electronics-II 893 YCT
209. Cycle stealing mode of DMA operation involve- Ans. (d) : We use timing and controlling unit in 8085 for
(a) DMA-controlled taking on the address, data the generation of timing signals and the signals to control
and control buses while a block of data is all the operations and functions both interior and exterior
transformed between memory and I/O device. of a microprocessor are controlled by this unit. Thus,
(b) While the microprocessor is executing a control and timing section of CPU affects and sequences
program an interface circuit takes control of all events within the CPU and the microcomputer.
the address, data and control buses, when not 213. Output of the assembler in machine codes is
in use by the microprocessor. referred to as
(c) Data transfer takes place, between I/O device (a) Object program (b) Source program
and memory during every alternate clock cycle. (c) Macroinstruction (d) Symbolic
(d) The DMA controller working for the addressing
microprocessor to finish execution of the Mizoram PSC Nov. 2015, Paper-II
programme and then takes over the buses. ESE-2003
BSNL TTA 26.09.2016, 10 AM Ans. (a) : Assembler is a program that converts the
ESE 2013 mnemonics into a machine code or binary code. This
Ans. (b) : In computing, traditionally cycle stealing is a machine code is referred to as object program.
method of accessing computer memory (RAM) or bus 214. The 8085 MPU can address-
without interfacing with the CPU. Cycle stealing mode (a) 28 memory locations
of DMA operation takes place while the microprocessor (b) 212 memory locations
is executing a program and an interface circuit takes (c) 216 memory locations
over control of address, data and control buses when not (d) 232 memory locations
in use by microprocessor. BSNL TTA 26.09.2016, 10 AM
210. In Intel 8085 A microprocessor ALE signal is Ans. (c) : 8085 MPU has 8 bit data bus and 16 bit
made high to address bus, thus it is capable of addressing 64 kB (216
(a) Enable the data bus to be used as low order memory location) of memory.
address bus 215. An interrupt breaks the execution of
(b) To latch data D0-D7 from data bus instructions and diverts its execution to–
(c) To disable data bus (a) Interrupt service routine
(d) To achieve all the functions listed above (b) Counter word register
ESE-2003 (c) Execution unit
Ans. (a) : In 8085, ALE (Address latch enable) is the (d) control unit
control signal which is nothing but a positive going BSNL TTA 28.09.2016, 10 AM
pulse generated when a new operation is started by Ans. (a) : An interrupts breaks the execution of
microprocessor. So when pulse goes high means ALE = instruction and diverts its execution to interrupt service
1, It makes address bus enable and when ALE = 0 routine. The interrupts service routine (ISR) transfer
means low pulse makes data bus enable. control to interrupt. After executing the ISR the control
211. The control signal ALE is sent by Intel-8085 in is again transferred to the main program.
order to- 216. Which one of the following statements for Intel
(a) Inform I/O device that address is being sent 8085 is correct?
over the AD line (a) Program counter (PC) specifies the address of
(b) Achieve separation of address from data. the instruction last executed
(c) Inform the memory device that address is (b) PC specifies the address of the instruction
being sent over the AD line being executed
(d) Inform I/O and memory that data is being (c) PC specifies the address of the instruction to
sent over the AD line be executed
BSNL TTA 26.09.2016, 10 AM (d) PC specifies the number of instructions
Ans. (b) : ALE (Address Enable Latch) is the control executed so far
signal which is nothing but a positive going pulse ESE-2015, 2004
generated when a new operation is started by Ans. (c) : Program counter is a 16 bit resister. Program
microprocessor. So when pulse goes high means ALE = counter contain that very memory address from where
1, it makes address bus enable and when ALE = 0, the next instruction is to be fetched for execution it is a
means low pulse makes data bus enable. Thus, the self-incrementing counter.
control signal ALE is sent by Intel 8085 in order to 217. ALU of an 8085 MPU consists of
achieve separation of address from data. (a) Accumulator, temporary register, arithmetic
212. Which section of the CPU affects and and logical circuit
sequences all events within the CPU and the (b) Accumulator, arithmetic, logical circuit, and
entire microcomputer? five flags
(a) Registers (c) Accumulator, temporary register, arithmetic,
(b) ALU logical circuit, five flags
(c) Instruction decoding circuitry (d) None of these
(d) Control and timing section BSNL TTA 28.09.2016, 10 AM
BSNL TTA 26.09.2016, 10 AM ESE- 2011
Electronics-II 894 YCT
Ans. (c) : ALU of an 8085 MPU consists of Ans. (b) : Dynamic RAM is easier to interface with a
accumulator, temporary register, arithmetic and logic microprocessor. Because the user writes the required
circuits, five flags. The ALU executes all mathematical instruction and data in memory by an input device and
and logic instructions. directs the microprocessor to do a particular task and
218. A good assembly language programmer should get the answer. The working style of dynamic memory
uses general purpose registers rather than is simple which makes it easy to interface.
memory in maximum possible ways for data 223. In 8085 MPU, sequencing the execution of
processing. This is because. instructions is done by the
(a) Data processing with registers is easier than (a) accumulator (b) flag
with memory. (c) stack pointer (d) program counter
(b) Data processing with memory requires more BSNL TTA 28.09.2016, 10 AM
instructions in the program than that with Ans. (d) : In 8085 MPU, sequencing the execution of
registers. instructions is done by the program counter.
(c) Of limited set of instructions for data 224. The order of priority for interrupts in 8085
processing with memory. MPU is
(d) Data processing with registers takes fewer (a) RST 7.5, RST 6.5, RST 5.5, TRAP
cycles than that with memory. (b) TRAP, RST 7.5, RST 6.5, RST 5.5
ESE-2011, 2005 (c) RST 5.5, RST 6.5, RST 7.5, TRAP
Ans. (d) : Data processing with registers takes fewer (d) TRAP, RST 5.5, RST 6.5, RST 7.5
cycle than with memory which require extra memory UPRVUNL JE 21.10.2021, 9AM-12PM
read or write signal. MPPKVVCL (Jabalpur) JE 2018
So, a good assembly language programmer should uses BSNL TTA 28.09.2016, 10 AM
a GPRs rather than memory. BSNL TTA 28.09.2016, 3 PM
219. After completing the execution, the ESE- 2010
microprocessor returns to Ans. (b) : The order of priority for interrupts in 8085
(a) Halt state (b) Fetch state MPU is TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
(c) Execute state (d) Interrupt state Each of these can be programmed. TRAP has the
BSNL TTA (JE) 14.07.2013 highest probability of all interrupts. This interrupts can
Ans. : (b) After completing the execution the not be masked and is not affected by the any other mask
microprocessor returns to fetch state. or interrupt enable.
220. Which of the following is not correct? TRAP> RST 7.5>RST 6.5> RST 5.5 > INTR.
(a) Bus is a group of wires 225. The cycle required to fetch and execute an
(b) Bootstrap is a technique or device for load instruction in a 8085 microprocessor is which
(c) An instruction is a set of bits that defines a one of the following?
computer operation. (a) Clock cycle (b) Memory cycle
(d) An interrupt signal is required at the start of (c) Machine cycle (d) Instruction cycle
every program ESE-2007
ESE-2005 Ans. (d) : The instruction cycle (also known as the
Ans. (d) : An interrupt is required for interruption of fetch-decode execute cycle or simply the fetch-execute
main program to perform a subroutine service. cycle) is the cycle that the central processing unit
Interrupt may be used to start some programs as per (CPU) follows from boot-up until the computer has shut
requirement, but it is not mandatory at start of every down in order to process instruction.
program. instruction cycle (IC) = Fetch cycle (FC) + execute
221. Which of the following does not constitute the cycle (EC)
minimum architectural unit of a 226. The present microinstruction fetched from a
microprocessor? microprogrammed control unit is held in the
(a) ALU (a) next address register
(b) Program Counter (b) control address register
(c) Programmable Timers (c) control data register
(d) BUS Buffer and Latches (d) pipeline register
BSNL TTA 28.09.2016, 10 AM ESE-2012
Ans. (c) : Programmable timers does not constitute the Ans. (b) : Control address register contains the address
of the next microinstruction to be executed. When the
minimum architectural unit of a microprocessor. ALU is present microinstruction fetched from a micro-
the minimum unit of the microprocessors, the program programmed control unit is held in it.
counters, the BUS buffers and the latches units. ALU Whether the control data register contains the
performs mathematical and logic operation. microinstruction to be executed.
222. Which type of RAM is easier to interface with a 227. Both the ALU and control section of CPU employ
microprocessor? which special purpose storage locations?
(a) static (b) dynamic (a) Buffers (b) Decoders
(c) both static and dynamic (d) none of these (c) Accumulators (d) Registers
BSNL TTA 28.09.2016, 10 AM ESE-2008
Electronics-II 895 YCT
Ans. (c) : Accumulator is a 8-bit resistor it is used in 232. A shift register is operating/connected with 100
various mathematical and logical operation. For kHz clock. The time taken to feed the 2 bytes of
example in the process of adding two 8-bit numbers one data serially in to it is-
number may be in an accumulator and the other in a (a) 2 µsec (b) 80 µsec
memory or register. The result of mathematical (c) 160 µsec (d) 16 µsec
operations are stored in the accumulator. This Resistor BSNL TTA 28.09.2016, 3 PM
is called A and it is also represented by ACC. Ans. (c) Given, f=100 kHz = 100 × 103 Hz
228. The number of first practical microprocessor 2 byte = 16 bit, t = ?
was– 1 1 −5
(a) Intel 4004 (b) M 6800 ∵T = = = 10
f 100×103
(c) Intel 8080 (d) Intel 4001 T = 10µs
BSNL TTA 28.09.2016, 10 AM
Hence, t = 16 × 10 = 160µs
Ans. (a) : The number of first practical microprocessor
was intel 4004. The Intel 4004 was a 4-bit central 233. The field, which is never present in an
processing unit (CPU) released in 1971 by Intel assembly language statement, is
corporation. It was the first commercially available (a) Op-code (b) Operand
microprocessor by Intel. (c) Continue (d) Comment
ESE-2009
229. A microprocessor with a 12 bit address bus will
Ans. (c) : A program written in an assembly language
be able to access–––––––
for a particular machine can be processed only on that
(a) 0.4 kbytes memory (b) 8 kbytes memory
machine and not on any other.
(c) 4 kbytes memory (d) 1 kbytes memory
OP code, operand and comment are present in an
BSNL TTA 28.09.2016, 10 AM
assembly language but continue do not present in an
Ans. (c) : The microprocessor will able to reach 212 = 22 assembly language.
×210 = 4k byte with 12 bit address bus. 234. The contents of register (B) and accumulator
230. In an Intel 8085 A microprocessor, why is (A) of 8085 microprocessor are 49H and 3AH
READY signal used? respectively. The contents of A and status of
(a) To indicate to user that the micro-processor is carry (CY) and sign (S) after execution SUB B
working and is ready for use. instructions are-
(b) to provide proper WAIT states when the (a) A = F1, CY = 1, S = 1
microprocessor is communicating with a slow (b) A = 0F, CY = 1, S = 1
peripheral device. (c) A = F0, CY = 0, S = 0
(c) To slow down a fast peripheral device so as to (d) A = 1F, CY = 1, S = 1
communicate at the microprocessor's device. HRRL E1 & E2 07.08.2021
(d) None of the above BSNL TTA 28.09.2016, 3 PM
ESE-2014, 2008 Ans. (a) Accumulator (A) = 3AH =00111010
Ans. (b) : • A READY signal is used in microprocessor Register (B) = 49H=01001001
to communicate with slow peripheral device or A←A−B
memory. 00111010
• READY signal provides proper synchronization − 01001001
between microprocessor and slow peripheral devices.
• If READY signal is high (1) then the peripheral 11110001
device can transfer the data. If READY signal is low (0) A=F1H
then microprocessor wait until READY signal is high S Z AC P CY
(1).
1 1 1 1 0 0 0 1
231. Normally a microprocessor cycles between––––
(a) fetch and halt state The carry flag is set since the first operand is less than
(b) fetch and interrupt state the second operand. Since the result produces the
(c) fetch and execute state negative result sign flag is set.
(d) halt and execute state i.e. CY=1
S=1
BSNL TTA 28.09.2016, 10 AM
Hence, A=F1H, CY=1, S=1
Ans. (c) : Normally a microprocessor cycles between
235. Which components are NOT found on chip in a
fetch and execute state. In the fetch operation, the microprocessor but may be found on chip in a
microprocessor takes the address of the first byte of the microcontroller?
instruction to the address bus with a control signal and (a) SRAM and USART
reads the instruction from the memory location. Execute (b) EPROM and PORTS
operation after receiving all instructions, the (c) EPROM, USART and PORTS
microprocessor finishes the tasks given in these special (d) SRAM, EPROM and PORTS
instructions. This process is called execution. ESE-2011
Electronics-II 896 YCT
Ans. (c) : Erasable programmable that PROM, which Ans. (a) In Direct Memory Access (DMA) transfer, the
can be erased by ultraviolet rays and can be DMA controller sends a DMA request to the CPU, in
reprogrammed, is called EPROM. To erase the EPROM response to which CPU puts all its address, data and
the chip is removed from the circuit and ultraviolet rays control bus lines in the high impedance states. The
are injected into it for some time. DMA controller can then transfer data directly between
device and memory without CPU intervention. Clearly,
USART- USART stands for universal synchronous,
it is more suitable for devices with high data transfer
Asynchronous Receiver Transmitter. it is some times rates like hard disk.
called the serial communication Interface or SCI. The
239. The output data lines of microprocessors and
must common use of the USART in asynchronous memories are usually tristated because
made is to communicate to a PC serial port using the (a) More than one device can transmit
RS-232 Protocol. information over the data bus by enabling
236. If CS = A15 A14 A13 is used as the chip select only one device at a time
(b) More than one device can transmit over the
logic of a 4K RAM in an 8085 system, then its data bus at the same time.
memory range will be- (c) The data lines can be multiplexed for both
(a) 3000 H - 3 FFF H input and output
(b) 7000 H - 7 FFFH (d) It increases the speed of data transfer over the
(c) 5000 H - 5 FFF H and 6000 H - 6 FFF H data bus
(d) 6000 H - 6 FFF H and 7000 H - 7 FFF H ESE-2011
BSNL TTA 28.09.2016, 3 PM Ans. (a) : Tristate means three states Viz. logic 0 Logic 1
Ans. (d) Given, CS = A15 A14 A13 and high impedance state in high High impedance state the
pin neither connected to supply nor to ground. Hence
4k = 2 2 × 210 = 212 impedance at this pin is very high with respect to supply as
Therefore, Address line =12 well as ground. Some pins of 8085 have three states.
A15 A14 A13 A12 A11 - A8 A7 - A 4 A3 - Ao 240. HOLD & HLDA pair provides the
handshaking signals required for ––––––––
0 1 1 0 0000 0000 0000 operation.
0 1 1 1 1111 1111 1111 (a) UART (b) USART
(c) DMA (d) All
If, A12 = 0 ⇒ 6000 - 6FFF
BSNL TTA 28.09.2016, 3 PM
And, if A12 = 1 ⇒ 7000 - 7FFF Ans. (c) Using a Direct Memory Access (DMA), the
Hence, 6000H-6FFF and 7000H-7FFF H device (DMA) requests the CPU to hold its data address
237. Consider the following 8086 assembly language and control bus, so the device is free to transfer data
program: directly from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.
MOV AX, BB11H
∵ HLDA→HOLD acknowledge
MOV CX, 1122H
241. The address bus of Intel 8085 is 16-bit wide and
ADD AX, CX
hence the memory which can be accessed by
HLT this address bus is
The result of this program is: (a) 2 k bytes (b) 4 k bytes
(a) CX = CC33H (b) AX = CC33H (c) 16 k bytes (d) 64 k bytes
(c) CX = BB11H (d) AX = BB11H ESE-2012, 2010
MPPKVVCL JE-2018 Ans. (d) : Memory location = 2n = 216
Ans. (b) : Consider the following 8086 assembly = 26 × 210
language program = 64 k bytes
MOV AX, BB11H, 242. "Cycle steal" operation is with
MOV CX, 1122H (a) DMA controller
ADD AX, CX (b) Interrupt controller
B B 1 1 H (c) Keyboard display controller
+ 1 1 2 2 H (d) Microcontroller
BSNL TTA 28.09.2016, 3 PM
C C 3 3 H Ans. (a) In cycle stealing Direct Memory Access
HLT (DMA) transfer, the DMA controller requests only one
The result of this program is AX = CC33H. or two memory cycles from the CPU at a time. If the
CPU is trying to access memory that time, it will wait
238. For which of the following devices, is DMA the otherwise CPU can continue with its internal operation
most suitable- that does not require access to the memory bus. So CPU
(a) Hard disk (b) Key board and DMA cycles can be overlapped. Cycle stealing
(c) Mouse (d) Joy stick mode is not suitable for large block transfers since the
BSNL TTA 28.09.2016, 3 PM overhead will be high.
Electronics-II 897 YCT
243. Microprocessor is- It has the following configuration-
(a) ALU and memory on a single chip • 8 - bit data bus
(b) ALU and I/O devices on a single chip • 16 - bit address bus, which can address up to 64 kB
(c) ALU and control unit on a single chip • Requires + 5V supply to operate at 3.2 MHz single
(d) ALU, register unit and control unit on a phase clock
single chip • A 16 - bit program counter
LMRC (SCTO) 17.04.2021 • A 16 - bit stack pointer
BSNL TTA 28.09.2016, 3 PM • Six 8 - bit registers arranged in pairs : BC, DE, HL
Ans. (d) A microprocessor consists of an ALU, control • It is used in washing machines, microwave ovens,
unit and register array. Where ALU performs arithmetic mobile phones etc.
and logical operations on the data received from an 247. The register which holds the information about
input device or memory control unit controls the the nature of results of arithmetic or logic
instructions and flow of data within the computer and operations is called as
register array consists of registers identified by letters (a) Accumulator
like B, C, D, E, H, L and accumulator. (b) Condition code register
Block diagram of a Microcomputer- (c) Flag register
(d) Process status registers
ESE-2012
Ans. (c) : The flags generally reflect the status of
arithmetic or logic operation.

248. The address bus of 8085 MPU is-

(a) Multi directional (b) Bi-directional
(c) Unidirectional (d) None of these
BSNL TTA 28.09.2016, 3 PM
244. Which of the following is a 16-bit register for Ans. (c) There are three types of buses-
8085 microprocessor (i) Address bus -: It is a group of conducting wires
(a) Stack pointer (b) Accumulator which carries address only. It is unidirectional because
(c) Register B (d) Register C data flow in one direction, from microprocessor to
BSNL TTA 28.09.2016, 3PM memory or from microprocessor to input/output
BSNL TTA 29.09.2016, 10AM devices.
Mizoram PSC Nov. 2015, Paper-III (ii) Data bus -: It is a group of conducting wires which
ESE-2012 carries data only. Data bus is bidirectional because data
Ans. (a) : Stack pointer is a 16-bit register and hold the flow in both directions, from microprocessor to memory
address of the stack TOP. There are some memory or input/output devices and from memory or
locations in the stack, external memory (RAM) which input/output devices to microprocessor.
the programmer indicates in his program. Stack work (iii) Control bus -: Control bus are various lines which
on the principle of LIFO (LAST IN FIST OUT) The have specific functions for coordinating and controlling
date is PUSH IN and POP OUT by some special microprocessor operations. The control bus carries
instruction in the stack. The stack is used to handle control signals partly unidirectional, partly bidirectional
interrupts sub-routines and input output device. control signals are things like read or write.
245. The 8th bit of program status word (PSW) of 249. In 8085 microprocessor, the first machine cycle
8086 microprocessor represents which of the of every instruction is:
following flags? (a) I/O Read Cycle
(a) Overflow flag (b) Direction flag (b) Memory Write Cycle
(c) Interrupt enable flag (d) Trap flag (c) Opcode Fetch Cycle
MPPKVVCL JE-2018 (d) Memory Read Cycle.
Ans. (d) : The 8th bit of program status word (PSW) of MPPKVVCL JE-2018
8086 microprocessor represents - TRAP flag. Ans. (c) : In 8085 microprocessor, the first machine
246. 8085 operates with- cycle of every instruction is opcode fetch cycle.
(a) 1 MHz single phase clock 250. When referring to instruction words, a
(b) 2 MHz single phase clock mnemonic is
(c) 2 MHz two phase clock (a) a short abbreviation for the operand address.
(d) 3 MHz single phase clock (b) a short abbreviation for the operation to be
BSNL TTA 28.09.2016, 3 PM performed
BSNL TTA 28.09.2016, 10 AM (c) a short abbreviation for the data word stored
Ans. (d) 8085 is pronounced as "8085" microprocessor. at the operand address
It is an 8-bit microprocessor designed by Intel in 1977 (d) Shorthand for machine language
using NMOS technology. ESE-2012
Electronics-II 898 YCT
Ans. (b) : The mnemonic in the microprocessor is 255. A bus connected between the CPU and the
abbreviation, for operation to be performed. It is used main memory that permits transfer of
mnemonics in instruction code to make easy and information between main memory and the
suitable coding. CPU is known as
Mnemonics codes are widely used in computer (a) DMA bus (b) Memory bus
programming and communications system operations to (c) Address bus (d) Control bus
specify instructions. ESE-2014
251. When an instruction is read from the memory, Ans. (b) : Data bus (memory bus) is bidirectional
it is called? because data flow in both directions, from µp to
(a) Memory read cycle memory or I/O devices and from memory or I/O
(b) Fetch cycle devices to microprocessor length of data bus of 8085
(c) Instruction cycle µp is 8 bit (That is, two Hexadecimal disits)
(d) Memory write cycle 256. Each Push and POP operation involves …… at
BSNL TTA 21.02.2016 a time.
Ans : (b) When an instruction is read from the (a) A single bit (b) A single nibble
memory, it is called fetch cycle. (c) A single byte (d) A double byte
Fetch cycle is a standard process describe the step BSNL TTA 21.02.2016
which is needed for processing of a data. In fetch cycle, Ans : (c) Each PUSH and POP operation involves a
CPU fetch some data or instruction from main memory single byte at a time. In stack terminology, insertion
then store it into its internal memory called register, this operation is called PUSH and removal operation is
stage is called fetch cycle. called POP. In PUSH and POP operations involves
252. The……. is set (to 1) if there is a carry from the with registers pair.
low nibble (lowest four bits) to the high nibble 257. In an 8085 µP system, the RST instruction will
(upper four bits), or borrow from the high nibble- cause an interrupt-
(a) Carry flag (b) Auxiliary carry flag (a) Only if an interrupt service routine is not
(c) Sign flag (d) Parity flag being executed
BSNL TTA 21.02.2016 (b) Only if a bit in the interrupt mask is made 0
Ans : (b) The auxiliary carry flag is set (to 1) if there is (c) Only if interrupts have been enabled by an EI
a carry from the low nibble (lowest four bit) to highest instruction
nibble (upper four bits) or borrow from the high nibble. (d) None of these
253. In a 8085 microprocessor system with memory BSNL TTA 26.09.2016, 3 PM
mapped I/O, which of the following is true? Ans : (c) In 8085 microprocessor, the RST instruction
(a) Devices have 8-bit address line will cause an interrupt only if interrupts have been
(b) Devices are accessed using IN and OUT enabled by an EI instruction.
instructions 258. The operations executed by two or more
(c) There can be maximum of 256 input devices control units are referred as
and 256 output devices (a) Micro-operations
(d) Arithmetic and logic operations can be (b) Macro-operations
directly performed with the I/O data. (c) Multi-operations
ESE-2013 (d) Bi control-operations
Ans. (d) : In a 8085 µp memory mapped I/O is an ESE-2014
Arithmetic and logic operations can be directly Ans. (b) : The operations executed by two or more
performs with the I/O data because there is only one control units are referred as macro-operation. It requires
address space in the memory mapped I/O scheme. The a set of micro-operation.
meaning of address space whose set the address space 259. Which one of the following is not a vectored
which µ.p can generate some address are given to the interrupt?
memory and some to the device. A I/O device is also (a) TRAP (b) RST 7.5
treated the same as a memory. (c) RST 3 (d) INTR
254. In 8085 microprocessor, assume that the stack Mizoram PSC IOF- 2019 Paper-II
pointer is pointer to the memory location BSNL TTA- 26.09.2016, 3 PM
2000H and register DE contains value 1050H. ESE-2003
After the execution of instruction PUSH D, the Ans : (d) Non vectored interrupts: Those vectored in
stack pointer would be pointing at: which vector address is not predefined. The interrupting
(a) 2000H (b) 1FFDH device gives the address of sub routine for these
(c) 1FFFH (d) 1FFEH interrupts. INTR is the only non-vectored interrupt in
8085 microprocessor.
MPPKVVCL JE-2018
260. Pseudo instructions are basically-
Ans. (d) : In 8085 microprocessor, assume that the
(a) False instructions
stack pointer is pointer to the memory location 2000H (b) Instructions that are ignored by micro
and register DE contains value 1050H. After the processor
execution of instruction PUSH D, the stack pointer (c) Assembler directives
register is decrement by 2 from memory location and (d) Instructions that are treated like comments
then result in stack pointer would be 1 FFEH. BSNL TTA 26.09.2016, 3 PM
Electronics-II 899 YCT
Ans : (c) Pseudo instructions are basically assembler 266. Cache memory is inserted between-
directives which are provided by the assembler tools. (a) The memory and CPU
All pseduo instructions are 2-5 letters in length and they (b) The secondary storage and main memory
varied from version to version of assembler. (c) The archival storage and secondary storage
261. Which of the following statement is true? (d) The secondary storage and CPU
(a) The group of machine cycle is called state BSNL TTA 26.09.2016, 3 PM
(b) A machine cycle consists of one or more
instruction cycles Ans : (a) Cache memory is used to reduce the average
(c) An instruction cycle is made up of machine time to access data from main memory. It is inserted
cycles and a machine cycle is made up of between main memory and CPU. The size of cache
number of states memory is much smaller than main memory.
(d) All of these 267. During which T-state, contents of OP code
BSNL TTA 26.09.2016, 3 PM from memory are loaded into IR (instruction
Ans : (c) An instruction cycle is made up of machine register)?
cycle and a machine cycle is made up of number of (a) T1 OP code Fetch (b) T2 OP code Fetch
states. (c) T3 OP code Fetch (d) T4 OP code Fetch
262. Number of address lines necessary to connect ESE-2015
8K memory chip is
(a) 10 (b) 11 Ans. (c) : During T-state contents of OP-code from
(c) 12 (d) 13 memory are loaded into IR (instruction register) then
ESE-2012 T3 time period OP code from memory are loaded into
Ans. (d) : Memory size = 2m IR. During T1 state microprocessor uses IO / M , S0,S1
Where n = number of address lines. signals are used to instruct µp to fetch OP code. Thus
8 × 210 = 2n
when IO / M , S0= S1 = 1 it indicates OP codes fetch
23 × 210 = 2n
operation.
213 = 2n
n = 13 268. Identify the 4-bit microprocessor from the
263. What will be the content of accumulator after following list.
the execution of XRA A instruction? (a) Intel 8085 (b) Intel 4010
(a) 1 (c) Intel 4004 (d) Intel 8086
(b) 0 MPPEB Sub. Engineer 0.8.07.2017 Shift-I
(c) Depends upon the current content of the Ans. (c) :
accumulator Intel 8085 →8-bit µP
(d) None of these
BSNL TTA 26.09.2016, 3 PM Intel 4010 →8-bit µP
Ans : (b) XRA A performs EX-OR operation between Intel 4004 →4 bit µP
source operand and destination operand and store the Intel 8086 →16-bit µP
result in the accumulator. 269. Assuming LSB is at position 0 and MSB at
Here source and destination operand both are same i.e. position 7, which bit positions are not used
A. Therefore, the result after performing EX-OR (undefined) in flag register of an 8085
operation, stored in the accumulator is 00. microprocessor?
264. The first microprocessor to include virtual (a) 1,3,5 (b) 2,3,5
memory in the Intel microprocessor family is (c) 1,2,5 (d) 1,3,4
(a) 80286 (b) 80386
(c) 80486 (d) Pentium ESE-2015
ESE-2014 Ans. (a) : The flags generally reflect the status of
Ans. (a) : The intel 80286 is a 16-bit microprocessor arithmetic or logical operation in flags register bit
that was introduced on February 1, 1982 it was the first positions 1, 3 and 5 Not used.
80286 based CPU with separate, non, multiplexed Microprocessor, flag register consists of 8 bits and only
address and data buses also the first with memory 5 flag, 8 bit which is useful.
management and wide protection abilities.
D7 D6 D5 D 4 D3 D2 D1 D0
265. The 8085 MPU requires a power supply of-
(a) +5V single (b) +5V dual S Z X AC X P X CY
(c) +12V single (d) +12V dual
BSNL TTA 26.09.2016, 3 PM 270. At the output, the content of A is:
UJVNL JE 2016 MOVA,#33H
Ans : (a) The 8085 MPU requires a power supply of ORL A,#01H
+5V single and clock frequency is 3 MHz. 8085 has 8 ANL A,#10H
bit data bus and 16 bit address bus. It has capable of (a) 0001 0000 (b) 0011 0010
addressing 64 kB of memory. It has 40-pin IC uses +5V (c) 0011 1011 (d) 0011 0011
for power. MPPEB Sub. Engineer 0.8.07.2017 Shift-I
Electronics-II 900 YCT
Ans. (a) : Ans : (d) The range of address where the interrupt
service procedures are stored is (00000–003FFH).
Interrupts can be classified into different categories
have different parameters.
(i) Hardware and software interrupts.
(ii) Vector and non-vector interrupts.
There are 8 software and vector interrupts RST 0, RST
1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7, &
Hardware interrupts- TRAP (RST 4.5), RST 5.5, RST
6.5, RST 7.5, INTR.
276. For CALL or For JUMP is to branch if
program area is outside ......... segment in 8086.
(a) 4K Byte (b) 16K Byte
(c) 32K Byte (d) 64K Byte
At the output the content of accumulator (A) will be BSNL TTA 25.09.2016, 3:00 P.M.
10(0001 0000). Ans : (d) For CALL or for JUMP is to branch if
271. The condition for 8086 microprocessor to work program area is outside 64 kilobyte segment in 8086.
as multiprocessor system is: 277. Which of the following instructions are not
used by the 8080 MPU?
(a) M / IO is high (b) M / IO is low
(a) RIM, STA (b) SIM, STA
(c) MN / MX is low (d) MN / MX is high (c) STA, XCHG (d) RIM, SIM
MPPEB Sub. Engineer 0.8.07.2017 Shift-I BSNL TTA 25.09.2016, 3:00 P.M.
Ans. (c) : The condition for 8086 microprocessor to Ans : (d) RIM, SIM instructions are not used by 8080
MPU (Microprocessor). 8080 microprocessor 8-bit
work as multiprocessor system is MN / MX is low.
microprocessor and made by NMOS.
272. At the beginning of a fetch cycle, the contents 278. Consider the symbol shown below.
of the program counter are
(a) incremented by one
(b) transferred to address bus
(c) transferred to memory address register What function does the above symbol represent
(d) transferred to memory data register in a program flow chart?
ESE-2015 (a) A process (b) Decision making
Ans. (c) : At the beginning of fetch cycle the contents (c) A subroutine (d) Continuation
of the program counter are transferred to memory ESE-2016
address Register. Ans. (c) : After execution of this instruction programm
Program counter is a 16-bit register. PC contains that
control is transferred to a sub-routine whose starting
very memory address from where the next instruction is
to be fetched for execution. address is specified in the instruction in µ.p a subroutine
is a sequence of program instructions that perform a
273. The peripheral that belongs to the category of specific task, package as a unit.
special purpose peripherals is:
(a) Programmable interval timer 279. Which of the following functions is not
(b) Programmable DMA controller performed by a microprocessor ?
(c) Programmable interrupt controller (a) Controlling timing of information flow
(d) Programmable keyboard and display interface (b) Performing the computing tasks specified in
MPPKVVCL JE-2018 a program
Ans. (d) : Special purpose peripherals is programmable (c) Communicating with all peripherals using
keyboard and display interface. system bus
274. The relation among IC (instruction cycle), FC (d) Storing results and data
(Fetch cycle) and EC(execute cycle) is BSNL TTA 25.09.2016, 3:00 P.M.
(a) IC = FC-EC (b) IC = FC+EC Ans : (d) Storing results and data are not performed by
(c) IC = FC+2EC (d) EC=IC+FC the microprocessor. Microprocessor is a multi purpose
ESE-2015 and programmable device which reads binary input by
Ans. (b) : The CPU fetches one instruction from the its memory and accepts binary data as I/P then gives
memory at a time and executes it one instruction cycle output after processing data according to instructions.
can consists of 1-6 machine cycle. 280. When a peripheral is connected to the
An instruction cycle consists of a fetch cycle and microprocessor in input/output mode, the data
execute cycle. transfer takes place between
275. The range of address where the Interrupt (a) any register and I/O device
service procedures are stored is : (b) memory and I/O device
(a) 00000 – 000FFH (b) 00000 – 001FFH (c) accumulator and I/O device
(c) 00000 – 002FFH (d) 00000 – 003FFH (d) HL register and I/O device
BSNL TTA 25.09.2016, 3:00 P.M. ESE-2016
Electronics-II 901 YCT
Ans. (c) : An input device is something you connect to 285. If instruction RST-5 is written in a program.
a µp that send information into the computer. An output The programme will jump to location -
device is something you connect to a computer that has (a) 0020 H (b) 0024 H
information sent to it. (c) 0028 H (d) 002 CH
The accumulator is an 8-bit resister that is a part of Mizoram PSC IOF 2019, Paper-III
arithmetic logic unit (ALU). This resister is used to Ans. (c) : RST 5 = CALL 5×8
store 8-bit data and to perform arithmetic and logical = CALL 40
operations. The results of an operation is stored in the = CALL 0028H
accumulator. 286. In an 8085 microprocessor system with
281. The number of bytes in an instruction for 8085 memory mapped I/O -
can be : (a) I/O devices have 16 bit addresses
(a) One or two (b) One, two or three (b) I/O devices are accessed using IN and OUT
(c) Two only (d) One only instruction
BSNL TTA 25.09.2016, 3:00 P.M. (c) there can be a maximum of 256 input devices
Ans : (b) The number of bytes in an instruction for and 256 output devices
8085 can be 1 byte, 2 bytes or 3 bytes. The 1 byte (d) arithmetic and logic operations can be
instruction has an opcode alone. The 2 bytes instruction directly performed with the I/O data
has an opcode followed by an eight-bit address or data. Mizoram PSC IOF 2019, Paper-III
The 3 bytes instruction has an opcode followed by 16
Ans. (d) : In an 8085 microprocessor system with
bit address or data.
memory mapped I/O arithmetic and logic operations
Example- 1-byte instruction-
can be directly performed with the I/O data.
MOV A,C
LDAX B 287. The stack pointer in the 8085 microprocessor is
2-byte instruction a-
MVIA, 28H (a) 16 bit register that point to stack memory
IN 56H locations
3-byte instruction (b) 16 bit accumulator
LDA, 2005H (c) memory location in the stack
JMP, 2056H (d) flag register used for the stack
282. While execution of I/O instruction takes place, Mizoram PSC IOF 2019, Paper-III
the 8-bit address of the port is placed on Ans. (a) : In the programmer's view of 8085 only the
(a) lower address bus general purpose resisters A, B, C, D, E, H and L and the
(b) higher address bus flags registers were discussed so for but in the complete
(c) data bus programmer's view of 8085 there are two more special
(d) lower as well as higher order address bus purpose registers each of 16 bit width.
ESE-2016
Ans. (d) : Low order address bus (AD0 –AD7) is
multiplexed with data bus in order to reduce the number
of pins
if ALE = 1 Address transfer to bus
ALE = 0 Data transfer to bus.
283. The memory addressing capacity of 8086 is :
(a) 32 KB (b) 64 KB
(c) 1 Megabyte (d) 32 Megabyte
BSNL TTA 25.09.2016, 3:00 P.M.
Ans : (c) In 8086 microprocessor is 16-bit
microprocessor. It has 20 bit address bus provides a
1Mb physical space.
284. In 8086, the physical address of an instruction 288. In 8085 microprocessor, assume the
contains ......... bits : accumulator contains AAH and CY = 0. How
(a) 10 (b) 16 many times the instruction RAL must be
(c) 18 (d) 20 executed so that the accumulator reads A9H.
UPRVUNL JE 21.10.2021, 9AM-12PM What will be the CY bit reading at that
BSNL TTA 25.09.2016, 3:00 P.M. instant?
Ans : (d) The 8086 processor has a 20-bit address bus, (a) 4 times; CY= 1 (b) 2 times; CY= 0
which gives a physical address space up to 1MB (220), (c) 4 times; CY= 0 (d) 2 times; CY= 1
addressed as 00000H to FFFFFH. MPPKVVCL JE-2018
Electronics-II 902 YCT
Ans. (b) : Given, 291. When a subroutine is called, the address of the
Accumulator = AAH, CY = 0. instruction following the CALL instruction is
stored in/on the -
(a) Stack pointer (b) Accumulator
(c) Program counter (d) Stack
Mizoram PSC IOF 2019, Paper-III
Ans. (d) : A set of instruction which are used repeatedly
in a program can be referred to as subroutine. Only on
copy of this instruction is stored in memory. When a
subroutine is required it can be called many times
during the execution of the particular program.
292. The synchronization between microprocessor
2 times the instruction RAL must be executed so that and memory is done by -
the accumulator reads A9H, at that instant CY will be 0. (a) ALE signal (b) HOLD signal
289. Check the following program in 8085 (c) READY signal (d) None of these
microprocessor. Mizoram PSC IOF 2019, Paper-III
MVIA, 8FH BSNL TTA (JE) 2013
MVIB, 68H Ans. (c) :
ADD B
The status of CY, AC, P and S for the program
is:
(a) AC = 1; CY = 0; S = 1; P = 0
(b) AC = 0; CY = 0; S = 1; P = 0
(c) AC = 0; CY = 1; S = 0; P = 1 READY SIGNAL- This is an active high input control
(d) AC = 1; CY = 1; S = 0; P = 1 signal. It is used by microprocessor to detect whether a
MPPKVVCL JE-2018 peripheral has completed (or is ready for) the data
Ans. (a) : PSW or flag register of 8085 microprocessor transfer or not. The main function of this pin is to
has following specifications- synchronize slower peripheral to fast microprocessor.
293. In the 8085 microprocessor, the RST6
instruction transfers the program execution to
the following locations -
(a) 30H (b) 24H
(c) 48H (d) 60H
Mizoram PSC IOF 2019, Paper-III
Ans. (a) : We know that RST n = CALL n ×8
Then RST 6 = CALL 6×8
Calculation- = CALL 48
MVI A, 8FH; A ← 8FH = CALL 30H
MVI B, 68H; B ← 68H 294. If the accumulator of an Intel 8085 A
ADD B; A ← A+B ⇒ A ← 8F+68 microprocessor contains 37 H and the previous
A=F7=(1111 0111)2 operation has set the carry flag, the instruction
As the output has odd number of 1s in the binary ACI 56 H will result in -
format, the parity will be zero i.e. P = 0 (a) 8E H (b) 94 H
After the addition of MSB no carry is generated (c) 7E H (d) 84 H
therefore CS =0 Mizoram PSC IOF 2019, Paper-III
After addition of first 4 bit (starting from LSB) a
carry of 1 is generated then AC = 1 Ans. (a) : ACI = 56H ; A + 56A+CY→A
Sign flag is the value of MSB of the accumulator, 37H+56H+1 = 8EH
hence S = 1 295. The contents of accumulator after the
290. For a memory system, the cycle time is execution of following instruction will be -
(a) same as the access time MVI A, A7H
(b) larger than the access time ORA A
(c) shorter than the access time RLC
(d) sub-multiple of the access time (a) CFH (b) 4FH
ESE-2012 (c) 4EH (d) CEH
Ans. (b) : If a number of unrelated location have to be Mizoram PSC IOF 2019, Paper-III
quickly accessed one after the other, there is a limit to Ans. (b) : MVI A, A7H, ;A7H→A
the speed with which this can be achieved. This ORA A ;set 7 Flag CY = 1
obviously, depend on the access time (Ta). In general, RLC ;Rotate accumulator left
cycle time (Tc) is significantly larger than nTa. The contents of bit D7 are placed in bit D0
TC > nTa Before RLC 10100111
Where n = number of words. After RLC 01001111
Electronics-II 903 YCT
296. The instruction that does not clear the Ans. (d) : In microprocessor there are two types code.
accumulator of 8085 is - (a) OP code– It is a part of instruction that tells the
(a) XRA A (b) ANI 00H processor what should be done.
(c) MVI A, 00H (d) None of these (b) Operand– It is a part of instruction that contains the
Mizoram PSC IOF 2019, Paper-III data to be acted on or the memory location of the data in
Ans. (d) : All instructions clear the accumulator a resister.
XRA A ; A⊕ A Total No. of address line = 24 bits
ANI 00H ; A AND 00 In which op code line = 10 bits
MVI A ; 00-A The reminder of operand = 24 – 10 = 14 bits
297. Effective address is calculated by adding or 301. The following is not true for RS 232 standard:
subtracting displacement value to - (a) It establishes the way data is coded
(a) immediate address (b) relative address (b) If defines signal voltage levels
(c) absolute address (d) base address (c) Does not decide data transmission rate
Mizoram PSC IOF 2019, Paper-III (d) It defines standard connector configurations
Ans. (d) :A base address is a unique location in primary ESE-2012
storage (or main memory) that serves as a reference Ans. (c) : The RS 232 standard covers the following
point for other memory locations called absolute areas.
addresses. In order to obtain an absolute address a • It establishes the way data is coded
specific displacement (or offset) value is added to the • If defines signal voltage levels
base address. • It defines standard connector configurations
298. A 8085 microprocessor program uses all • The mechanical characteristics of the interface
available Jump instructions, each only once. • The electrical signals across the interface
For this program, the total memory (in Bytes) • The function of each signal
occupied by the Jump instructions is - • Subsets of signals for certain applications.
(a) 30 (b) 27 302. The 8259 A programmable interrupt controller
(c) 24 (d) 18 in cascade mode can handle interrupt of
Mizoram PSC IOF 2019, Paper-III (a) 8 priority levels (b) 16 priority levels
Ans. (b) : (c) 32 priority levels (d) 64 priority levels
Ans. (d) :
• Intel 8259 is designed for Intel 8085 and Intel 8086
microprocessor.
• In can be programmed either in level triggered or in
 JC − 3byte edge triggered interrupt level.
CY  • We can mask individual bits of interrupt request
 JNC − 3byte register.
 JZ − 3byte • We can increases interrupt handling capability up to
I 64 interrupt level by cascading further 8259 PIC
JNZ − 3byte • Clock cycle is not required.
JP − 3byte 303. Adder circuits are widely used in the
S
 JM − 3byte ____section of a microprocessor.
(a) input device (b) memory
 JPE − 3byte (c) control unit (d) ALU
P
 JPO − 3byte BSNL TTA 29.09.2016, 10 AM
24 byte Ans : (d) Adder circuit are widely used in the ALU
section of microprocessor. The ALU unit performs
24 byte + 3 byte = 27 byte mathematical and logic operations e.g. (i) Addition (ii)
299. Which one of the following 8085 assembly Subtraction (iii) OR, NOT, AND, XOR etc (iv) Shift the
language instructions does not affect the information 1 bit right or left (v) Comparison.
contents of the accumulator? 304. Intel 8086 is a_______ bit microprocessor
(a) CMA (b) CMP B (a) 8 (b) 12
(c) DAA (d) ADD B (c) 16 (d) 32
Mizoram PSC IOF 2019, Paper-III BSNL TTA 29.09.2016, 10 AM
Ans. (b) : Assembly language instruction CMP B in Ans : (c) The 8086 (also called iAPX 86) is a 16-bit
8085 microprocessor does not affect the content of microprocessor chip designed by Intel blue early 1976 and
accumulator. June 8, 1978, when it was released. Which eventually
300. A microprocessor has 24 address lines and 32 became Intel's most successful line of processors.
data lines. If it uses 10 bits of op-code, the size 305. A microprocessor, on arrival of RESET signal
of its Memory Buffer Register is - returns from HALT state to ________
(a) 22 bits (b) 24 bits (a) fetch state (b) execute state
(c) 32 bits (d) 14 bits (c) interrupt state (d) none of these
Mizoram PSC IOF 2019, Paper-III BSNL TTA 29.09.2016, 10 AM
Electronics-II 904 YCT
Ans : (a) When the reset signal is reached, the 309. In the instruction MOV A, M
microprocessor returns from the HALT state to the fetch (a) The content of memory addressed by HL pair
state. In fetch operation, the microprocessor takes the is moved to A register
address of first byte of instruction to the address bus (b) The content of A register is moved to
with a control signal and reads the instruction from the memory location addressed by HL pair
memory location. (c) The 8 bit data is moved to A register
(d) None of these
306. The sticker over the EPROM window protects
BSNL TTA 27.09.2016, 3 PM
the chip from
Ans : (a) In 8085 instruction set, MOV R, M is an
(a) infrared light from sunlight
instruction where the 8-bit data content of the memory
(b) UV light from fluorescent lights and sunlight location as pointed by HL register pair will be moved to
(c) magnetic field the register R. This is an instruction to load register R
(d) electrostatic field with the 8-bit value from a specified memory location
ESE-2016 whose 16-bit address is in HL register pair.
Ans. (b) : The 2732 EPROM chip erasing and So, MOV A, M the content of memory addressed by
programming an EPROM is handled by special HL pair is moved to A register.
equipment called PROM burners. After erasing and 310. Why a ROM does not have data inputs?
reprogramming it is common to protect the EPROM (a) It does not have a WRITE operation
window indicated, with opaque sticker. The sticker over (b) Data input are integrated with data outputs
the EPROM window protects the chip from ultraviolet (c) Data inputs are integrated with address inputs
(UV) lights and sunlight. (d) ROM is sequentially accessed
307. Access time in memories is equal to- ESE-2016
(a) Latency time (b) Seek time Ans. (a) : ROM – Data stored in ROM cannot be
(c) Transfer time (d) Sum of all these electronically modified after the manufactured of the
BSNL TTA 27.09.2016, 3 PM memory device.
Ans : (d) Access time:- Access time is defined as the • ROM does not have data inputs because it does not
have a write operation.
setup time before the actual data transfer takes place for
example, the read/write head is on track 1 but we need 311. Which of the following instruction can alter the
to read data from another track or segment. Thus, the normal incrementing of the program counter?
(a) Interrupt (b) Call
read/write head will move to the data block location
(c) Branch (d) All of these
before the actual transfer can take place. This delay is
BSNL TTA 27.09.2016, 3 PM
called access time.
Ans : (d) Instruction which can alter the normal
Access time is calculated by summation of the
incrementing other program counter is-
following
• Interrupt- It is a signal emitted by hardware or
• Latency time software when a process or an event needs
• Seek time immediate attention.
• Transfer time. • Call subroutine- The program counter is pushed on
308. Consider the following statements: to the stack, and it is changed to the first instruction
1. RAM is a non-volatile memory of the subroutine.
2. RAM is a volatile memory whereas ROM is a • Branch instruction- The program counter is
non-volatile memory. changed to the new location.
3. Both RAM and ROM are volatile memories 312. A memory system has a total of 8 memory
but in ROM data is nor when power is chips, each with 12 address lines and 4 data
switched off. lines. The total size of the memory system is
Which of the above statements are correct? (a) 32 k bytes (b) 48 k bytes
(a) 1 only (b) 2 only (c) 64 k bytes (d) 16 k bytes
(c) 3 only (d) none of the above ESE-2015
ESE-2016 Ans. (d) : Given,
Ans. (b) :RAM is a volatile memory, ‘volatile memory Number of address line = 12
is a computer memory that requires power to maintain Number of data line = 4
the store information. Most modern semiconductor Each memory size = 212 × 4
volatile memory in either static RAM or dynamic RAM. = 2 × 210 × 8 = 2 kbytes
ROM is a non-volatile memory. Non volatile memory is For 8 chip, total memory size = 8 × each memory size
computer memory that can retain the store information = 8× 2 kbytes
even when not powered.’ = 16 kbytes
Electronics-II 905 YCT
313. Which device convert a decimal input number 316. If the memory chip size is 1024 ×4, the number
to binary? of memory chips required to design 8K
(a) Accumulator memory is
(b) Encoder (a) 8 (b) 256
(c) ALU (c) 16 (d) 32
(d) Memory ESE-2014
BSNL TTA 27.09.2016, 3 PM Ans. (c) : Chip size = 1024 ×4 = 512×8
Ans : (b) Encoder is used for converts a decimal input = 512 bytes
to binary such as a BCD code it has a number of input Memory size = 8 K bytes = 8 × 1024 bytes
lines but only one of the inputs is activated at a given 8 ×1024
time and produces an n-bit output code that depends on Number of chips required = = 16 .
512
the activated input.
317. When the signal on RESET IN goes low, which
314. Each cell of a static RAM contains of the following happens in 8085?
(a) 4 MOS transistors
(a) The program counter is set to zero
(b) 4 MOS transistors and 1 capacitor
(b) The buses are tristated
(c) 2 MOS transistors
(c) The MPU is reset
(d) 4 MOS transistors and 2 capacitors
(d) All of these
ESE-2015
BSNL TTA 27.09.2016, 3 PM
Ans. (a) : SRAM-
Ans : (d) Reset signals:- When the signal RESET IN
• Each cell of a SRAM contains 4 or 6 MOS
goes low then.
transistors
MUP 8085 has-
• It has a lower access time, so it is faster compared
• The program counter is set to zero
to DRAM.
• The buses are tristate
• It is costlier than DRAM
• The MPU is reset.
DRAM-
• Each cell of a DRAM contains 1 MOS transistor 318. Consider the following statements:
and 1 capacitor. 1. SRAM is made up of flip-flops.
• It has higher access time, so it is slower than 2. SRAM stores bit as voltage
SRAM. 3. DRAM has high speed and low density
• It costs less compared to SRAM. 4. DRAM is cheaper than SRAM
Which of the above statements are correct?
315. There are ................. types of flags in 8086.
(a) 1,2, and 3 (b) 1, 3 and 4
(a) 8 (b) 9
(c) 2, 3 and 4 (d) 1, 2 and 4
(c) 7 (d) 4
ESE-2014
BSNL TTA 27.09.2016, 3 PM
Ans. : (b) There are total 9 flags in 8086 and the flag Ans. (d) :
register is divided into two types • SRAM is made up of flip-flops
(a) Status flags- There are 6 flag registers in 8086 • SRAM stores bit as voltage
microprocessor which become set (1) or reset (0) • DRAM is cheaper than SRAM
depending upon condition after either 8-bit or 16-bit • DRAM has lower speed and high density and lower
operation. The 6 status flags are- power consumption.
• Sign flag (S) 319. In 8085, instruction ADD IMMEDIATE to
• Zero flag (Z) ACCUMULATOR WITH CARRY is
• Auxiliary carry flag (AC) represented by the opcode-
• Parity flag (P) (a) ADC (b) ACI
• Carry flag (CY) (c) ADD (d) ADI
• Overflow flag (0) BSNL TTA 27.09.2016, 3 PM
(b) Control flag- The control flags enable or disable Ans : (b) In 8085, instruction ADD immediate to
certain operations of the microprocessor. accumulator with carry is represented by the opcode
The 3 control flags are- ACI which mean 8-bit data and the carry flag are added
• Directional flag (D) to the contents of the accumulator and the result is
• Interrupt flag (I) stored in the accumulator.
• Trap flag (T) Example − ACI 55H

Electronics-II 906 YCT

 3. An operational amplifier has a differential gain
IX. Operational Amplifier of 100 and a common mode gain of 0.10. Its
CMRR will be
1. An ideal Op-amp has which of the following (a) 20 dB (b) 40 dB
characteristics? (c) 60 dB (d) 80 dB
(a) Ri = ∞ Av = ∞ R0 = 0 NSCL Diploma Trainee 24.02.2021
UKPSC JE 2013, PAPER-I
(b) Ri = 0 Av = ∞ R0 = 0 BSNL TTA (JE) 14.07.2013
(c) Ri = ∞ Av = ∞ R0 = ∞ RSEB JE 2013
(d) Ri = 0 Av = ∞ R0 = ∞ Ans. (d) CMRR (dB) = 20log
Ad
SJVNL 24.10.2021,8:30 AM - 10:30 AM Ac
LMRC (SCTO) 17.04.2021
100
HPSSSB JE 2018 (Post code 663) = 20log
BSNL TTA (JE) 25.09.2016, Shift-I .01
BWSSB Code 127, 13.11.2016 = 20log 10000
Karnataka PSC JE 2016
= 20log10 4
Ans. (a) : An ideal operational amplifier
characteristics– CMRR = 80dB
Infinite open loop gain
4. An ideal Op-Amp has impedance
Infinite input impedance
(a) Very high input and output
Zero output impedance
(b) Very low input and out-put
Infinite Bandwidth (c) Low input impedance and high output
Zero offset voltage (d) Infinite input impedance and zero output
Infinite common mode rejection ratio (CMRR) UPRVUNL AE 04.07.2021
2. The given circuit represents a Nagaland PSC CTSE (Diploma) 2017, Paper-I
BSNL TTA (JE) 14.07.2013
Ans. (d) : An ideal op-Amp should have infinite input
impedance and zero output impedance.
5. Virtual ground property of operational
amplifier indicates that
(a) inverting and non-invering terminals are
connected to ground
(b) inverting and non-inverting terminals are at
the same potential
(c) system is at rest
(a) monostable multivibrator (d) any one terminal is connected to ground
(b) astable multivibrator OPPSC AE 2021, Paper-II
HRRL E1 & E2 07.08.2021
(c) Schmitt trigger ESE-2012
(d) bistable multivibrator
DGVCL JE 06.01.2021, Shift-III
Ans. (b) : Virtual ground-
LMRC JE 2015
SSC JE 2013
Ans: (c) Schmitt trigger is a device that has separate
thresholds for a rising signal and a falling signal.

As the name indicates it is virtual, not real ground. For

some purpose we can consider it as equivalent to
ground. The term virgual ground means that the voltage
at the particular node is almost equal to ground voltage
(0V). It not physically connected to ground. This
concept is very useful in analysis of op-amp circuits and
it will make a lot of calculations very simple.
6. If the circuit of the following figure has R1 =
100 k Ω and Rf = 500 k Ω , what output voltage
V0 results for an input of V1 = 2V?

→ The positive feedback is introduced by adding a

part of the output voltage to the Input voltage
Electronics-II 907 YCT
 (a) 12 V (b) −2.4 V Vout = A 0L ( V+ − V− )
(c) −12 V (d) 2.4 V
Vout
RPSC ACF & FRO 23.02.2021 = V+ − V−
Ans. (a) : Given circuit diagram- A 0L
If we assume that A 0L is ∞ .
V+ = V−
For this buffer amplifier-
Vout = V− = V+ = Vin
and derive the gain of the buffer amplifier-
Vout = Vin
V0  R f  9. A differential amplifier has an open circuit
= 1 +  voltage gain of 100. The input signals are 3.35
V1  R1  V and 3.25 V. Determine the output voltage.
 500  (a) 5 V (b) 15 V
V0 =  1 +  × 2 = 12 volt (c) 10 V (d) 20 V
 100  GSECL 2020 Shift-I
7. Which of the following circuits may be used for Ans. (c) : The differential amplifies the voltage
converting a sine wave into square wave? difference present on its inverting and non-inverting
(a) Schmitt trigger inputs.
(b) Bi-stable multivibrator Output voltage V0 = A(V1 – V2)
(c) Monostable multivibrator Here, A = 100, V1 = 3.35 V
(d) A stable multivibrator V2 = 3.25 V
CPCL JE 2019 V0 = 100(3.35 – 3.25)
Ans. (a) : Schmitt Trigger- It is a comparator circuit V0 = 10V
with positive feedback 10. An operational amplifier is a
In Schmitt Trigger circuit input sine wave is converted (a) dependent source (b) Independent source
into a square wave. (c) model source (d) None of above
KSEB Sub Engineer 2015
Ans. (a) An op-Amp is a voltage controlled voltage source
type device. So, it can be defined as dependent source.
11. One of the characteristic of the Emitter
Follower is its
(a) Low input resistance
(b) Low current gain
(c) Low voltage gain
(d) High output resistance
KSEB Sub Engineer 2015
Ans. (c) : Characteristic of a emitter follower-
• Voltage gain-Very low
• Current gain-High
• Input resistance- High
• Output resistance- Low
• Phase difference between input and output-00
12. Which of the following Op-Amp system is non
linear?
(a) Current to Voltage Converter
8. Gain of a buffer amplifier is: (b) Logarithmic Amplifier
(a) Dependent on the circuit parameters (c) Active Filter
(b) unity (d) Delay Equalizer
(c) infinity KSEB Sub Engineer 2015
(d) zero Ans. (b) :
DSSSB JE 05.11.2019
Ans. (b) : Gain of a buffer amplifier is unity. It has high
current gain, high input impedance and low output
impedance. It is used to avoid loading of the signal source.

Logarithmic Amplifier- A logarithmic amplifier is an

electronic circuit that produces an output that is
proportional to the logarithmic of the applied input. It is
a non-linear amplifier.
Electronics-II 908 YCT
13. An integrator contains a 100 kΩ and 1µF Ans. (c) : Inverting amplifier-
capacitor. If the voltage applied to the
integrator input is 1 V, what is the voltage
present at the integrator output after 1 s?
(a) 1 V (b) 5 V
(c) 2 V (d) –10 V
MPPKVVCL (Jabalpur) JE -2018
Ans. (d) :

V0 R
=− f
Vi R1
25
V0 = − × 5 = −12.5V
10
Integrator 16. Active load is used in the collector of the
differential amplifier of an op-amp to
−1 t
RC ∫0
Vo = Vi dt + Vc (0+ ) (a) increase the output resistance
(b) increases the differential gain Ad
−1 1 (c) increases maximum peak to peak output voltage
−6 ∫0
= dt (d) eliminate load resistance from the circuit.
100 × 10 × 1×10
3
ESE-2001
V0 = –10V
Ans. (b) : In the differential amplifier of an op-amp, the
14. In a non-inverting OP - AMP, if R1 = 20K ohms active load is used in the collector by replacing the
and Rf = 200K ohms, then find the gain of the resitive load for the following purpose-
amplifier. • To increase the differential gain
(a) 11 (b) 10 • To improve the common-mode rejection rotation
(c) 1.1 (d) 100 (CMRR)
MPPKVVCL (Jabalpur) JE -2018 • Active load provides large ac resistance.
Ans. (a) : Non-inverting Amplifier 17. An Op-Amplifier Comparator circuit employs
(a) No feedback (b) +ve feedback
(c) – ve feedback (d) Both (b) & (c)
HPSSSB JE 2018 (Post code 663)
Ans. (a) : An op-amp comparator circuit employs no
feedback. An op-Amp comparator circuit is used to
compare the difference between voltage level of two
inputs (inverting and non inverting) and also determines
which one is greater. It requires no feedback circuit.
18. The slew rate of an op-amp is 0.5 V/µsec. The
maximum frequency of a sinusoidal input of 2
Gain of amplifier Vrms with unity gain that can be handled
V  R  without excessive distortion is
A v = 0 = 1 + f  (a) 3 kHz (b) 30 kHz
V1  R 1 
(c) 200 kHz (d) 2 MHz
 R   200  ESE-2001
gain (Av) = 1 + f  = 1 +  = 11
 R1   20  Ans. (b) : For a sinusoidal signal of general form
Vi = Vm sin ωt the maximum votlage rate of change can
15. If the input voltage Vi = 5V, the output voltage
V0 is: be shown to be
 dVi 
  = Vm ω cos ωt
 dt  maximum
To prevent distortion at the output the rate of change
must also be less than the slew rate, that is,
SR
∴ f≤ Hz
2πVm
Voltage gain = 1;
for Vm = 2 2V and SR = 0.5 V / µs
0.5
(a) -2 V (b) 2 V ∴ Input f max = −6
10 × 2 × π × 2 × 2
(c) - 12.5 V (d) 12.5 V
MPPKVVCL JE-2018 = 28.13kHz ≃ 30kHz
Electronics-II 909 YCT
19. A circuit with op-amp is shown in the below So, current i through diode D (When Vi>0)
figure. The voltage V0 is i = I0  eV / ηVT − 1 ....................(i)
Where I0 = reverse saturation current.
VT = Voltage equivalent of temperature
Now current,
V − V1 Vi
i1 = i =
R R
(a) 3 VS1–6VS2 (b) 2VS1-3VS2 ∵ Current inside the op-amp is zero
(c) 2VS1–2VS2 (d) 3VS1–2VS2 (∵ R i → ∞ )
ESE-2001 ∴ i = i1
Ans. (d) : V
i.e. I0 e V / ηVT − 1 = i
R
V / ηVT Vi
e = 1+
I0 R
 V 
V = ηVT ℓ n 1 + i 
From virtual short method,  I0 R 
Point A voltage = Vs1 ∵ I 0 << 0
V
Nodal analysis at point A, So, i >> 1
Vs2 − Vs1 Vs1 − V0 I0 R
= So, we can write,
R 2R
2Vs2 − 2Vs1 = Vs1 − V0  V 
V = ηVT ℓ n  i 
2Vs2 − 3Vs1 = −V0  I0 R 
V
V0 = 3Vs1 − 2Vs2 − V0 = ηVT ℓ n i
I0 R
20. In the op-amp circuit shown below, Vi>0 and
i= I0eV/VT. The output V0 will be proportional to V0 = −ηVT ℓ n Vi
I0 R
V0 = −ηVT ℓ n kVi
V0 ∝ ℓ n kVi
21. In general, if a sine wave is fed into a Schmitt
trigger, the output will be
(a) a square wave
(b) a saw-tooth wave
(c) an amplified sine wave
(d) a triangular wave
(a) Vi (b) Vi SSC JE 2012
Ans:(a)
(c) e kvi (d) l n ( kVi )
ESE-2002
Ans. (d) :

Virtual short-
V1 = V2
∵ V2 = 0
∴V1 = 0
So, net voltage across diode D
V = V1 − V0 In Schmitt trigger the sine wave is fed the output will
= 0 − V0 = −V0 be a square wave.

Electronics-II 910 YCT

22. In the inverting op-amp circuit shown below, 26. An op-amp has a differential gain of 103 and a
the resistance Rg is chosen as R1||R2 in order to CMRR of 100. The output voltage of the op-
amp with inputs of 120 µV and 80 µV will be-
(a) 26 mV (b) 41 mV
(c) 100 mV (d) 200 mV
OPPSC AE 2021, Paper-II
ESE-2003
A
Ans. (b) : V0 = A d Vd + A c Vc and CMRR = d
Ac
 1 VC 
V0 = A d Vd  1 + 
 CMRR Vd 
1
(a) increase gain (b) reduce offset voltage VC = (120 + 80 ) = 100 × 10−6 V
(c) reduce offset current (d) increase CMRR 2
ESE-2002 Vd = 120 − 80 = 40 × 10 −6 V
Ans. (c) : Rg is chosen such that it is equal to
 1 10−4 
impedance seen from the -ve terminal by replacing all ∴ V0 = 103 × 40 × 10−6 ×  1 + × −6 
the sources by their internal impedances and this is done  100 40 × 10 
for reducing the effect of offset current. ∴ V0 = 41 mV
23. The use of OP-AMP is generally not preferred 27. Which one of the following causes phase shift
as through an op-amp?
(a) sub tractor (b) differentiator (a) Internal RC circuit
(c) divider (d) integrator (b) External RC circuit
UGVCL JE-2014 (c) Gain roll off of the internal transistor
Ans. (c) : The use of OP-AMP is generally not (d) Negative feedback
preferred as divider. It is used operations such as HPSSSC JE 2018 Code -387
addition, subtraction, integration and differentiation. Ans. (a) : An internal RC circuit is present in an op-
24. The gain of an operational amplifier will be amp and causes a propagation delay from the input to
the output. This propagation delay creates a phase shift
maximum at-
between the input signal and the output signal.
(a) 1Hz (b) 50Hz
(c) 100Hz (d) DC 28. In the op-amp circuit as shown below, the
current iL is
Ans. : (d) The gain of an operational amplifier will be
maximum at D.C.
25. Another name for a unity gain amplifier is?
(a) Voltage follower
(b) Difference amplifier
(c) All of these
(d) Comparator
UPPCL JE 2018, Shift-II
Ans. (a) : Voltage follower
Vi Vi
(a) (b)
ZL Z L + R1
Vi  1 1 
(c) (d) Vi  + 
Ri  R1 ZL 
ESE-2003
Ans. (c) :

If Rf =0 (Short ciruit)
Ri = ∞ (open circuit)
Voltage gain =1
ν 0 = νi
A voltage follower is also known as a unity gain
amplifier, a voltage buffer, or an isolation amplifier. In According by virtual short -
a voltage follower circuit, the output voltage is equal to V+ = V−
the input voltage. V
iL = i
Vout = Vin R1

Electronics-II 911 YCT

29. If the output of the circuit is 'triangular wave', Ans. (b) :
the input of the circuit must be:

Apply virtual short-

Va = Vb = Vs
Vb − 0 Vs
I 1= =
Rs Rs
(a) Sine wave (b) Step signal
(c) Square wave (d) Triangular wave I = 0
Negligible input current in op-amp
JMRC JE 2021
NCL GET 17.11.2020 I0 = I1 (∵ I = 0 )
Ans. (c) : Given circuit is an integrator circuit- V
I0 = s
Rs
31. A differential amplifier has a differential gain
of 20,000 and CMRR is 80 dB. Then the
common mode gain is given by-
(a) 25 (b) 1
(c) 2 (d) 0.5
RSMSSB JEN (Degree) 29.11.2020
Ans. (c) : Given that,
Ad = 20000 CMRR = 80 dB AC = ?
CMRR dB = 20 log [CMRR]
80 = 20 log [CMRR]
CMRR = 104
If the output of the circuit is a "triangular wave" the Common mode gain can be given by-
input of the circuit must be square wave. Ad
AC =
CMRR
20000
AC =
10000
AC = 2
32. Consider the following circuit.

30. Which one of the following is the correct

expression for the current I0?

What is the output voltage V0 in the above circuit?

(a) 9.5V (b) 3V
(c) 32.2V (d) 1 V
ESE-2004
Ans. (d) :

VS .R L VS
(a) (b)
RS (R L + RS ) RS
VS  1 1 
(c) (d) VS  + 
RL R
 L R S 

ESE-2007, 2001
Electronics-II 912 YCT
Applied nodal analysis at node A, 35. For the operational amplifier circuit shown in
1 − Vn 1 − Vn 1 − Vn the figure below, what is the maximum possible
+ + =0 value of R1, if the voltage gain required is
1 1 1
1 − Vn + 1 − Vn + 1 − Vn between –10 and –25? (The upper limit on RF is
=0 1MΩ)
1
3 − 3Vn = 0
Vn = 1V
At virtual ground-
Vn = node B = 1V
Applied nodal analysis at node B,
1 − Vn 1 − Vn 1 − Vn 1 − V0
+ + =
1 2 3 1
1 − V0
0+0+0 = (a) Infinity (b) 1 MΩ
1
1–V0 =0 (c) 100 kΩ (d) 40 kΩ
V0 = 1V ESE-2007
33. Which of the following is used to obtain Rf
Ans. (c) : Gain, A v =
triangular wave? R1
(a) differentiate a square wave Rf
(b) differentiate a sine wave ∴ R1 = −
Av
(c) integrate a sine wave
(d) integrate a square wave 1
R1 will be ∝
(e) first integrate and then differentiate a square Av
wave. lesser the gain higher will be R1
RSEB JE 2011 for Av = –10
Ans. (d) : The output waveform of the integrator is R1 will be maximum
triangular, if its input is square wave. Therefore, a −R f
triangular wave generator can be obtained by ∴ R1 =
connecting an integrator at the square wave generator. −10
34. Based on the operation of op amp and diodes, R f 1×106
= = = 105 Ω
the below circuit is called as ________. 10 10
R1 = 100 kΩ
36. A non inverting amplifier is nulled at 25 degree
Celsius with a gain of 100. Calculate the output
voltage when the temperature rises to 50
degree Celsius for an offset drift voltage of 0.15
millivolt per degree Celsius.
(a) 3.75 mV (b) 37.5 mV
(c) 375 mV (d) 2.75 mV
PGVCL JE 2018
Ans. (c) : Voffset = 0.15 ( 50 − 25 ) mV
(a) Positive clipper circuit
(b) Negative clipper circuit Voffset = 0.15 × 25
(c) Clamper circuit Voffset = 3.75 mV
(d) V to I converter circuit
PGVCL JE 2018 Vout = Voffset × A v
Ans. (a) : The circuit diagram of positive clipper- Vout = 3.75 × 100 ∵ A V = 100
= 375 mV
37. Assume that the operational amplifier shown in
the figure is ideal. The current I, through the
1 kΩ resistor is

A positive clipper is a clipper that clips only the positive

portion of the input signal.

Electronics-II 913 YCT

 (a) –4 mA (b) –2 mA V
(c) –3 mA (d) –1 mA V1 = b
2
SSC JE 03.03.2017 Shift-II V = V (By virtual concept)
1 2
Ans : (a) Vb Vb
− Va − V0
2 + 2 =0
50 250
Vb − 2Va Vb − 2V0
+ =0
100 500
5Vb − 10Va + Vb − 2V0 = 0
2V0 = 6Vb − 10Va
Node at point Q V0 = −5Va + 3Vb
0 − V0
= 2 × 10−3 39. In the below given network, the ideal closed
2 × 103 loop voltage gain is...........
V0 = –4V
V0 −4
I0 = = = −2mA
2 × 10 3
2 ×103

I + 2 × 10–3 = –2 × 10–3 (a) 1 (b) –1

I = –4 × 10 = –4mA
–3
(c) ∞ (d) 50
38. What is the output voltage V0 of the given SSC JE 01.03.2017, Shift-II
circuit? Ans : (a) Ideal voltage gain-
V
AV = 0
Vi
But this circuit is a buffer amplifier-
So,
Vi = V0
V
Gain Av = 0 = 1
Vi
40. An OP AMP has an offset voltage of 1 mV and
(a) –5Va + 2.5Vb (b) –5Va + 3Vb is ideal in all other respects. If this OP AMP is
(c) –2.5 Va+ 2.5Vb (d) –2.5Va + 3Vb used in the circuit shown in the figure, the
ESE-2008 output voltage will be approximately
Ans. (b) :

(a) 3V (b) 2V
(c) 1V (d) 3.5V
SSC JE 01.03.2017, Shift-II
Ans : (c)
Apply nodal analysis at node V1-
V1 − Vb V1 − 0
+ =0
50 50
(∵ op-amp is ideal No current flow in op-amp)
2V1 = Vb

Electronics-II 914 YCT

Given, Vi0 = 10 −3 V
R 2 + R1
V0 = .Vi0
R1
1× 106 + 1× 103
V0 = × 10−3
1× 103
V0 ≃ 1V
41. The circuit shown is

43. In the inverting amplifier circuit shown in Fig,

R1=1kΩ and Rf = 3kΩ. Determine the output
(a) A low pass filter voltage 'V0' when the input voltage is Vin = 1V.
(b) A clamper
(c) A lag compensated inverting amplifier
(d) A narrow band video amplifier
ESE-2011
1
Ans. (a) : In low frequency ZC = X C = =∞
jωC
R
So, output V0 = − f Vi (a) V0 = -3V (b) V0 = 3V
Ri (c) V0 = 1.5V (d) V0 = 1.5V
We will get the output for high frequency DGVCL JE 06.01.2021, Shift-I
1 Ans. (a) : Given, R1 = 1kΩ, Rf = 3 kΩ, Vin =1V
ZC = =0
jωC
∴ output V0 ≅ 0
So, cut the high frequency
So it is a low pass filter
42. The circuit shown is
In an inverting amplifier the output voltage-
−R f
V0 = Vin
R1
3
= − ×1
1
V0 = −3 volt
44. Ideal operational amplifier has input
impedance of
(a) 1MΩ (b) infinity
(a) A low-pass filter (b) A high-pass filter (c) zero (d) 1Ω
(c) A comparator (d) An all-pass filter ISRO TA 2015
ESE-2011 HPSSC JE 2017 (Code 580)
Ans. (d) : All pass filter - All pass filter in that which Ans. (b) : Properties of op-amp-
Parameters Ideal value Practical value
passes all frequency components of the input signal
voltage gain ∞ 106
without attenuation but provides predictable phase shift Input impedance ∞ 106Ω to 1 MΩ
for different frequencies of the input signals. The all Output impedance 0 10Ω to 100 Ω
pass filter are also called delay equalizer or phase CMMR ∞ 106 or 120 dB
correctors. An all pass filter with the output lagging B-W ∞ 106Hz or 1MHz
behind the input is illustrated in figure. slew rate ∞ 80V/ 4 µ sec.
Electronics-II 915 YCT
45. In the given circuit, the magnitude of the 47. A comparator circuit is used to
output voltage. (a) mark the instant when an arbitrary waveform
attains some reference level.
(b) switch off a circuit when output becomes zero
(c) switch on and off a circuit alternately at a
particular rate.
(d) mark the instant when the input voltage
becomes constant
ESE-2012
Ans. (a) : A comparator circuit is one which may be
|V0|=3V1+2V2+7V3, then the values of R1, R2, used to mark the instant when an orbitary waveform
R3 and R4 are: attains some reference level.
(a) 3kΩ,2kΩ,7kΩ and 1kΩ Application of comparators-
• Measurement of time delays.
1 1 7
(b) kΩ, kΩ, kΩ and 12kΩ • Timing markers generated from sine wave
4 6 12 • Phase meter
12 • Square waves from sine waves.
(c) 4kΩ,6kΩ, kΩ and 12 kΩ
7 48. Assume that the op-amp of the figure is ideal.
1 1 1 If Vi is a triangular wave then V0 will be–
(d) kΩ, kΩ, kΩ and 12 kΩ
3 2 7
ESE-2010
Ans. (c) : Using Nodal analysis:
R  R   R 
V0 = − 4 V1 +  − 4  V2 +  − 4  V3
R1  R 2   R3 
R R R 
= −  4 V1 + 4 V2 + 4 V3 
 R1 R2 R3  (a) Square wave (b) Triangular wave
R R R (c) Parabolic wave (d) Sine wave
| V0 |= 4 V1 + 4 V2 + 4 V3 BSNL TTA 29.09.2016, 3 pm
R1 R2 R3
Given , Ans : (a)
| V0 |= 3V1 + 2V2 + 7V3
R R R
∴ 4 = 3, 4 = 2, 4 = 7
R1 R2 R3
∴ R1 : R 2 : R 3 : R 4
1 1 1
: : :1
3 2 7
Multiplying by 12 we get
12 12 12 The given figure is a square wave generator when the
: : :12
3 2 7 input is triangular, it produces square wave output.
12 49. An operation amplifier is connected in votlage
4kΩ : 6kΩ : kΩ :12kΩ
7 follower configuration. Input given to this is
46. An Op-Amp has a common mode gain of 0.01 3sin10 3 πt. Compute the slew rate of operation
and a differential mode gain of 105. Its common amplifier.
mode rejection ratio would be : (a) 6π × 10 −3 V / µ sec (b) 1.5π × 10−3 V / µ sec
(a) 10–3 (b) 107
(c) 10 3
(d) 10–7 (c) 3π × 10−3 V / µ sec (d) π × 10−3 V / µ sec
NLC GET 17.11.2020 ESE-2013
ESE-2013
Ans. (c) : V = 3sin103 πt
Ad
Ans. (b) : CMMR = dV
Ac Slew Rate =
dt max
Where, Ad = Deferential voltage gain
Ac = common mode voltage gain =| 3 × 103 π × cos 3 πt |max
A 105 = 3π × 103 V / sec
CMRR = d = = 107
A c 0.01 = 3π × 10−3 V / µ sec

Electronics-II 916 YCT

50. In the circuit of the ideal Op- Amp, Vo is 52. For an op-amp having a slew rate of 2V/µs, if
the input signal varies by 0.5V in 10 µs, the
maximum closed-loop voltage gain will be
(a) 50 (b) 40
(c) 22 (d) 20
ESE 2019
∆Vi
Ans. (b) : Slew Rate = A CL( max ) .
(a) -1V (b) 2V ∆t
(c) +1V (d) +15V 0.5
ISRO TA 2017 2 × 10 = A CL( max ) .
6
10 × 10−6
Ans. (d) : Given, op-amp is in positive feedback, act as
A CL( max ) = 40
saturation region ± Vsat .
So, V0 = + Vsat 53.
How fast can the output of an OP Amp change
= +15V by 10 V, if its slew rate is 1 V/µs?
51. For the ideal Op- Amp circuit shown in the (a) 5 µs (b) 10 µs
figure, Vo is (c) 15 µs (d) 20 µs
ESE 2017
Ans. (b) : Slew rate of op-amplifier is maximum rate of
change of output voltage with time.
Given that, Slew rate = 1V/µs
We know that,
dv
Slew rate (S.R.) =
dt
10V
1V / µs =
t
(a) -2 V (b) -1V t = 10 µs
(c) -0.5 V (d) 0.5 V
ISRO TA 2017 54.
Ans. (c) :

An ideal operational amplifier is connected as

shown in figure. What is the output voltage V2?
(a) 3 V1 (b) 2 V1
V
(c) 1 V1 (d) 1
3
KCL at point ‘b’ ESE 2018
b −1 b − 0 Ans. (a) :
+ =0
1 1
b −1 + b = 0
2b = 1
b = 0.5V
According to virtual ground method b = 0.5 = a
a = 0.5
KCL at point ‘a’ The input is at the +Ve terminal, so it acts like non-
1 − 0.5 0.5 − V0 inverting op-amp
= so the output is :-
1 2
 R 
0.5 = 0.5 − V0 V2 = 1 + f  V1 (∵ In case of ideal op-amp)
 R
1 = 0.5 − V0
 2R 
1 − 0.5 = −V0 ∴ V2 = 1 + V1 = 3V1
 R 
V0 = −0.5V V2 = 3V1

Electronics-II 917 YCT

55. In order to balance the offset voltage of an V1 + V2 150 + 140 290
operational amplifier, a small DC voltage is Vc = = = = 145µV
2 2 2
applied to input terminals where the A
connection is CMRR = d
(a) Series with both inverting as well as non- Ac
inverting input 4000
(b) Series with non-inverting input 100 =
Ac
(c) Shunt with inverting input
(d) Shunt with non-inverting input 4000
Ac =
ESE 2020 100
Ans. (a) : Due to offset voltage, Op-amp gives finite Ac = 40
output even if input is zero, this is eliminated by V0 = Vd Ad +Vc Ac
applying a voltage in series with both inverting as well = (10 × 4000 + 145 × 40) × 10–6
as non-inverting inputs. = (40000 + 5800) × 10–6
= 45800 × 10–6
V0 = 45.8 mV
59. The gain and distortion of an amplifier are
respectively 150 and 5%. When used with a
10% negative feedback the % distortion would
be
Offset voltage compensation of OPAMP 5 9
56. Schmitt trigger exhibits ________ Effect? (a) (b)
16 16
(a) Accelerator (b) Illumination
(c) 6 (d) 8
(c) Hysteresis (d) Hall
ESE-2014
UPPCL JE 25.11.2019, Shift-II
Ans. (a) : Gain without feedback, AV = 150
Ans. (c) : Schmitt trigger exhibits hysteresis effect.
Distortion without feedback, D = 5% = 0.05
• Schmitt trigger is a comparator circuit with hysteresis Feedback fraction, mv = 10% = 0.1
implemented by applying positive feedback to the non If Df is the distortion with negative feedback, then,
inverting input of a comparator or differential amplifier.
D 0.05 5
It is an active circuit which is an analog input signal to aDf = = = %
digital output signal. 1 + A v m v 1 + 150 × 0.1 16
57. An op-amp has a slew rate of 5 V/µs . The 60. An op-amp having a slew rate of 62.8 V/µsec, is
largest sine wave output voltage possible at a connected in a voltage follower configuration.
frequency of 1MHz is If the maximum amplitude of the sinusoidal
(a) 10πV (b) 5V input is 10 V, then the minimum frequency at
5 5 which the slew rate limited distortion would set
(c) V (d) V in at the output is
π 2π (a) 1 MHz (b) 6.28 MHz
ESE-2013 (c) 10 MHz (d) 62.8 MHz
Ans. (d) : SR ≥ 2πf Vm V / s JKSSB JE 2014
Given, SR = 5V/µs Ans. (a) : Given: slew Rate (s) = 62.8 V/m sec
F = 1MHz= 1×106 Hz Vin = 10 V , f = ?
5 In a voltage follower V0 = Vm sinωt
= 2π× 1× 10 × Vm
6
dV
10−6 s slew rate= in = ωVm cosωt
5 dt
Vm = Slew Rate = 2πf Vm
2π
58. What is the Output voltage of Op-amp for SR
f=
input voltage of Vi1 =150 µV, Vi 2 =140 µV if the 2πVm
amplifier has differential gain of Ad = 4000 62.8
=
and value of CMRR is 100 2 × 3.14 × 10 × 10−6
(a) 45.8 mV (b) 40.006 mV 62.8
=
(c) 10 μV (d) 145 μV 6.28 × 10 × 10−6
JKSSB JE 2014 f = 1 MHz
Ans. (a) : Given V1 = 150 µV V2 = 140 µV 61. A two stage amplifier with negative feedback
Ad = 4000 (a) can become unstable for large values of β.
CMRR = 100 output (V0) = ? (b) becomes unstable at high and very low
Vd = V1 – V2 = 150 – 140 =10µV frequencies if A is very large
Electronics-II 918 YCT
 (c) becomes unstable when the pole frequencies (a) 2V1 + V2 − 2V3 (b) 2(V1 + V2 ) − V3
become complex (c) V1 + V2 + V3 (d) V1 + 2V2 − V3
(d) is always stable
ESE-2014 UKPSC JE 2013, PAPER-I
Ans. (d) : Negative feedback makes the amplifier stable Ans. (a) : Given circuit diagram–
and gain is reduced because output is compared through
feedback with input and errors are redcued.
62. Three identical amplifiers each having a
voltage gain of 50 are cascaded. The open loop
voltage gain of the combined amplifier is
(a) 71 dB (b) 82 dB
(c) 91 dB (d) 102 dB At Node voltage 'VA',
ESE-2016
0 − V1 0 − V2 0 − VA
Ans. (d) : 20log10 A1A 2 A 3 = 20log 50 × 50 × 50 + + =0
10 20 20
= 102dB
VA = − ( 2V1 + V2 )
63. An input of Vi = 5.0 cos ωt is given to an Op-
Amp integrator circuit. If R = 2.0 M ohm and This voltage VA and V3 are the inputs of the second op-
C = 1.0 µF, then output will be 0 + 2V1 + V2 V3 V0
amp circuit that is − =
(a) 10 ω sin ωt (b) 5 ω sin ωt 10 5 10
(c) –2.5 ω sin ωt (d) –0.5 ω sin ωt V0 2V1 + V2 − 2V3
UKPSC JE 2013, PAPER-I =
10 10
Ans. (c) : Given, input equation–
or V = 2V + V2 − 2V3
Vi = 5 cosωt, C = 1µF = 1 × 10–6F 0 1

R = 2 MΩ = 2 × 10 Ω 6
66. An operational amplifier has a slew rate of
1 dvi 1 d(5cos ωt) 2 V/µ sec. If the peak output is 12V, what will
Output = = −6
×
RC dt 2 × 10 × 1× 10
6
dt be the power bandwidth?
−5ω sin ωt (a) 36.5 kHz (b) 26.5 kHz
= (c) 22.5 kHz (d) 12.5 kHz
2
ESE-2016
Output = −2.5ω sin ωt
SR 2 × 10 6
64. The operational amplifier circuit shown in Ans. (b) : f m = =
figure having a votlage gain of unity has 2π× Vm 2 × π× 12
= 26.5kHz
67. For the non-inverting amplifier as shown, find
the closed loop voltage gain.

(a) high input impedance and high output

impedance
(b) high input impedance and low output
impedance
(c) low input impedance and low output
impedance
(d) low input impedance and high output
impedance
ESE-2016 (a) 100 (b) 10
Ans. (b) : The voltage follower provides no attenuation (c) 101 (d) 11
or amplification- only buffering. SSC JE 24.03.2021, Shift-I
A voltage follower circuit has a very high input Ans. (d) : Non - inverting amplifier-
impedance and low output impedance. This
characteristic makes it a popular choice in many
different type of circuit that require isolation between
the input and output signal.
65. In the following Op-Amp circuit, the output Vo is

Electronics-II 919 YCT

Output voltage • In non inverting Schmitt trigger the input signal is
 R  applied at the non inverting terminal of op-amp.
Vout = 1 + f  Vin • Feedback is given at non inverting terminal.
 Ri  • Inverting terminal is grounded.
Vout  R f  71. There are three terminals in an operational
Closed loop voltage gain = = 1 +  amplifier, they are 2 inputs and 1 output. What
Vin  R i 
does the third one represent?
100 (a) Source and Drain
Av = 1 + (b) Sink and Source
10
(c) Drain and Gate
A v = 11 (d) Inverting and Non-inverting
68. A special case of non-inverting amplifier in UPPCL JE 11.02.2018, Shift-I
which all of the output voltage is fed back to Ans : (b) Op–Amp (Operational Amplifier) can
the inverting input of the op-amp is called: perform many operations as it’s name indicates.
(a) integrator Amplifiers such as BJT, FET etc can amplify signals
(b) voltage follower only but op-amp can be used as adder, subtractor,
(c) differentiator differentiator, integrator, filter, comparator, square
(d) logarithmic amplifier wave generator etc.
SSC JE 24.03.2021, Shift-I It has three terminals-
Ans. (b) : In voltage follower, all output voltage is fed (i) Input
back to the inverting terminal of op-amp. This is a (ii) Output
special case of non-inverting amplifier. (iii) Sink and Source
72. Choose the characteristics which is not related
to an ideal op–amp.
(a) Very high gain
(b) Very high input impedance
(c) Very low CMRR
69. A voltage follower is used as
1. An isolation amplifier (d) Very low output impedance
2. A buffer amplifer UPPCL JE 11.02.2018, Shift-I
Which of the above statements is/are correct? Ans : (c) The characteristics which is not related to an
(a) 1 only (b) 2 only ideal op–amp is very low CMRR. In ideal op amp have
(c) Both 1 and 2 (d) Neither 1 nor 2 input impedance infinite, output impedance zero, gain
ESE-2016 infinite, CMRR (common mode rejection ration)
Ans. (c) : infinite.
73. If the differential voltage gain and the common
mode voltage gain of a differential amplifier
are 46 dB and 2 dB respectively, then its
Voltage follower- A voltage follower (also known as a common mode rejection ration (CMRR) is
buffer amplifier, unity gain amplifier, or isolation ______.
amplifier) is an op-amp circuit whose output voltage is (a) 24 dB (b) 44 dB
equal to the input voltage (it “follows” the input (c) 48 dB (d) 22 dB
voltage). Hence a voltage follower op-amp does not DGVCL JE 0.5.01.2021, Shift-II
amplify the input signal and has a voltage gain of 1.
Ans. (b) : We know that-
70. Identify the function of the circuit
A
CMRR = d
A cm
20 log (CMRR) = 20 log Ad - 20 log Acm
= 46 - 2
= 44 dB
(a) non inverting amplifier 74. The voltage gain versus frequency curve of an
(b) inverting amplifier Op-Amp is shown in the given figure. The gain-
(c) non inverting schmit trigger bandwidth product of the Op-Amp is
(d) triangular wave form generator
APGCL JM 2021
Ans. (c) :

Electronics-II 920 YCT

 (a) 30KHz (b) 50KHz R1 = 10KΩ
(c) 200KHz (d) 2 MHz R 2 = 100KΩ
BSNL TTA (JE) 2013
R 3 = 10KΩ
Ans. : (b) Gain Av = 60 dB
BW = 50Hz R 4 = 100KΩ
A v dB = 20log10 A V Vout = ?
60 = 20log10 A V R2
Vout = ( V2 − V1 ) ×
By taking anti log- R1
A v = 103 100
= (1 − 2 ) × = −10 Volt
So, Gain Bandwidth product = Gain × Bandwidth. 10
= 103 × 50 = 50kHz 77. For a given op-amp, CMRR=105 and
75. An operational amplifier possesses- differential gain = 105. What is the common
(a) Very large input resistance and very large mode gain of the op-amp?
output resistance (a) 1010 (b) 2×105
5
(b) Very small input resistance and very small (c) 10 (d) 1
output resistance BSNL TTA (JE) 2013
(c) Very large input resistance and very small Mizoram PSC IOF 2019, Paper-III
output resistance Ans. : (d) CMRR = 105
(d) Very small input resistance and very large output Differential gain (Ad) = 105
Common mode gain (Acm) = ?
resistance
A
BSNL TTA (JE) 2013 CMRR = d
Ans. : (c) Property of an ideal operational amplifier- A cm
Input resistance infinite Ad 105
Output resistance zero A cm = = 5 =1
Offset voltage leakage current are zero CMRR 10
Not any noise present on output 78. The output waveform of an Op-Amp
Parameter does not depend on temperature differentiator for triangular wave input is
Common mode rejection ratio is infinite (a) Square (b) Ramp
Output voltage is equal to maximum supply value (c) Sinusoidal (d) Sawtooth
76. Consider the following Op-Amp circuit BSNL TTA (JE) 14.07.2013
Ans. : (a)

The output of differential op-amp is the differentiation

What is the output voltage V0 in the above Op- of input signal.
Amp circuit? d
(a) +10 V (b) – 10 V V0 = Vin
dt
(c) +11 V (d) – 11 V If the input triangular wave then the output must be
BSNL TTA (JE) 2013 square wave because differentiation of triangular wave
Ans. : (b) Given circuit diagram- is square waves.
79. The following circuit is used for

Given– (a) Summation (b) Subtraction

V1 = +2V (c) Differentiation (d) Integration
UPPCL JE 11.11.2016
V2 = +1V BSNL TTA (JE) 14.07.2013
Electronics-II 921 YCT
Ans. : (d) Ans. (b) : The common mode rejection ratio of an ideal
differential amplifier is infinity. Its basic function is to
amplify the difference between the two inputs signals.
The main factor of op-amp is its ability to discard the
unwanted signals. Due to the change in temperature, the
drift does not occur in its characteristics.
83. The closed loop gain of the given amplifier for
R1 = 5.5 kΩ and R2 = 3.3 kΩ is:
From virtual ground concept
voltage at point a
is zero i.e. Va = 0
Then no current flow inside the op-amp i.e.
iin = i f
(a) 0.60 (b) 2.66
Vin − 0 0 − V (c) 1.60 (d) 1.00
=
R 1 UPRVUNL JE -21.10.2021,9 am-12 pm
CS Ans. (c) :
V0 −1  −1  1
= = ×
Vin RCS  RC  S
−1
H (s ) =
RCS + –
This is the transfer function of an integrator. Hence By virtual ground concept (V = V )
given circuit is used for integration. Apply nodal analysis at point A-
80. A 741 Op-amp has: Vin − 0 Vin − Vout
+ =0
(a) 8 pins (b) 9 pins 5.5 3.3
(c) 7 pins (d) 6 pins 10Vin 10Vin − 10Vout
DFCCIL-JE 11.11.2018 + =0
55 33
Ans. (a) :
30Vin + 50Vin − 50Vout
=0
165
80Vin = 50Vout
Vout 80
=
Vin 50
Vout
= 1.60
Vin
An op-amp 741 total 8 pin represented.
84. In the circuit shown below, the op-amps are
81. Which of the following is not a characteristic of ideal. Then Vout in Volts is-
ideal operational amplifier?
(a) BW = ∞
(b) Perfect balance V0 = 0 when V1 = V2
(c) Gain is =∞
(d) Input resistance = 0
BSNL TTA 26.09.2016, 10 AM
BSNL TTA 21.02.2016
Ans. (d) :
Parameter Ideal op-amp
DC open loop gain ∞ (a) 4 (b) 8
Input impedance ∞ (c) 6 (d) 10
Input offset-voltage 0 BSNL TTA 28.09.2016, 3 PM
Output impedance 0 Ans. (b) In the given circuit is-
slew rate ∞
BW ∞
CMRR ∞
82. The common mode rejection ratio of an ideal
diff-amp is
(a) zero (b) infinity
(c) less than unity (d) greater than unity
DFCCIL JE- 11.11.2018
BSNL TTA 28.09.2016, 10 AM
Electronics-II 922 YCT
  −R f   Rf 
V1 =   (Vin ) +  1 +  (Vin )
 R1   R1 
 −1   1
=   (−2) +  1 +  (1)
 1   1
=2+2
V1 = 4V
 R   1
Now, Vout = 1 + f  (V 1 ) = 1 +  (4)
 R1   1
=2(4) (a) 0.33(Va – Vb) (b) 4.2(Va – Vb)
(c) –4.2(Va – Vb) (d) 3(Va – Vb)
Vout = 8V
UPRVUNL JE -21.10.2021,9 am-12 pm
85. In differential amplifier, CMRR can be Ans. (d) :
improved by using an increased-
(a) Emitter resistance
(b) Collector resistance
(c) Power supply voltages
(d) Source resistance
BSNL TTA 28.09.2016, 3 PM
Ans. (a) CMRR stands for Common Mode Rejection
Ratio, which can be defined as "The ratio between the
differential mode voltage gain (Ad) and the common
mode voltage gain ( A c )" Voltage at node A-
A 6.3 × Va
i.e. CMRR = d VA =
Ac 2.1 + 6.3
VA = 0.75Va
−R c
A d ≅ g m .R c , A c = By virtual concept (V– = V+)
2R E V– = 0.75Va
As, ↑ R c → A d ↑ &A c ↑ by same amount → CMRR Apply nodal analysis at inverting terminal-
does not change 0.75Va − Vb 0.75Va − Vout
+ =0
So, ↑ R E → A c ↓ & A d remains 2.1kΩ 6.3kΩ
A 2.25Va − 3Vb 0.75Va − Vout
constant → CMRR = d ↑ + =0
Ac 6.3kΩ 6.3kΩ
Hence, CMRR can be improved by using an increased Vout = 3Va–3Vb
emitter resistance. Vout = 3(Va–Vb)
86. The loop gain of a Schmitt trigger is always- 88. Miller sweep has the following data R= 1k
(a) 0 (b) Less than 1 ohms, C = 1pF, V=10 Volts. Its sweep speed is-
(c) Greater than 1 (d) Non (a) 103V/s (b) 106V/s
4
BSNL TTA 21.02.2016 (c) 10 V/s (d) 1010V/s
BSNL TTA 28.09.2016, 3 PM BSNL TTA 21.02.2016
Ans : (c) The loop gain of a Schmitt trigger is always Ans : (d) Rate of change of output voltage by any op-
greater than one. amp is called sweep rate.
Given, R = 1kΩ, C= 1pF, ∆V0 =10V
∆V0
i.e. SR =
∆t
∆t = CR = 1×10−12 × 1×103
t = 1 × 10–9
10
The circuit gives a square wave in the output when SR =
slowly changing waveform give in the input square 1×10−9
wave takes less time to rise and fall. It has a permanent SR = 1010V/s
state and rapidly enters another state upon input. The 89. For any inverting amplifier, the input
width of output depends on the size of input wave. In capacitance due to Miller effect------
Schmitt trigger circuit applied the feedback. (a) increases (b) decreases
87. For the given circuit R1 = 2.1 kΩ and R2 = 6.3 (c) remains constant (d) None of these
kΩ, find the expression of output voltage in NSCL Diploma Trainee 24.02.2021
terms of Va and Vb. UKPSC JE 2013, Paper-I
Electronics-II 923 YCT
Ans. (a) : The Miller effect accounts for increasing in From equation (i) and (ii)
the equivalent input capacitance of an inverting voltage Vo1 − Vo2 = 3V1 − 2V2 − 3V2 + 2V1
amplifies due to amplification of the effect of = 5V1 − 5V2
capacitance between the input & output terminals. Vo1 − Vo2 = 5 (V1 − V2)
• Virtually increased input capacitance due to Miller 92. A certain diff. amplifier has a differential
effect is given by. voltage gain of 2000 and a common mode gain
CM = C (1 + A V ) of 0.2. The CMRR in decibels (dB) is :
where, (a) 10,000 dB (b) 80 dB
AV = Voltage gain of inverting amplifier (Av is +ve) (c) 200 dB (d) 100 dB
C = feed back capacitance KVS WET 2017
if there is some capacitance between the input & output Ans. (b) : Given that,
of an inverting voltage amplifier then it will appear to Voltage gain (Ad) = 2000
be multiplied by the gain of the amplifier. The common mode gain (A ) = 0.2
C
additional amount of capacitance will be due to their
effect so it is called Miller capacitance. A
CMRR (dB) = 20 log d dB
90. In a Schmitt Trigger UTP = 12V, LTP = 8V, AC
the hysteresis VH is Differential mode gain
(a) 12V (b) 8V =
(c) 4V (d) 20V Common mode gain
BSNL TTA 25.09.2016, 3:00 P.M. 2000
Ans : (c) In Schmitt trigger UTP = 12 V = 20log
0.2
& LTP = 8 V
Then hysteresis voltage VH = UTP - LTP = 20 log 10000 = 20 log 104
Then hysteresis voltage VH = 12–8 = 4 V = 20 × 4
91. In the circuit configuration of figure given CMRR = 80 dB
below the output voltage (Vo1 – Vo2) is : 93. The circuit configuration shown in the figure
below generates :

(a) 7(V1 – V2) (b) 2(V1 – V2) (a) triangular wave and square wave
(c) 3(V1 – V2) (d) 5(V1 – V2) (b) triangular wave and sinusoidal wave
KVS WET 2017 (c) square wave and saw-tooth wave
Ans. (d) : Given circuit is− (d) saw-tooth wave and exponential wave
KVS WET 2017
Ans. (a) :

(i) Inverting is grounded

(ii) Non inverting terminal is grounded
V1 − Vo1 V1 − V2 (i) First output is triangular wave
+ =0
20 10 (ii) Second output is square wave
V1 −Vo1 + 2V1 − 2V2 = 0 94. A triangular-square wave generator uses -
3V1 − 2V2 = Vo1 ............ (i) (a) A sine wave oscillation and a comparator
V2 − V1 V2 − Vo2 (b) An integrator and a comparator
+ =0
10 20 (c) A differentiator and a comparator
2V2 − 2V1 + V2 − Vo2 = 0 (d) A sine wave oscillator and a clipper
3V2 − 2V1 = Vo2 ........... (ii) Mizoram PSC IOF 2019, Paper-III
Electronics-II 924 YCT
Ans. (b) A triangular- square wave generator uses two Differential amplifier is designed to amplify the
op-amps, one op-amp generates square wave. When the difference between the two inputs applied to its inputs
square wave is applied to another op-amp, it generates terminal.
triangular wave. Triangular wave has equal rise and fall CMRR ∝ R E C
time. Ad
∝ RE
Ac
1
Ac ∝
RE
So, for infinite RE(internal resistance of current source)
The first op-amp works as comparator and the 2nd op- the common mode gain is zero.
amp works as integrator. The ideal amplifier has a common mode voltage gain of
95. A differential amplifier is invariably used in the zero.
input stage of all op-amps. This is done basically 97. A 741-type op-amp has a gain-bandwidth
to provide the op-amps with a very high- product of 1 MHz. A non inverting amplifier
(a) CMRR (b) Bandwidth using this op-amp and having a voltage gain of
(c) Slew rate (d) Open-loop gain
20 dB will exhibit a −3 dB bandwidth of-
Mizoram PSC IOF 2019, Paper-III
(a) 50 kHz (b) 100 kHz
Ans. (a) : A differential amplifier is invariably used in
(c) 1000/17 kHz (d) 1000/7.07 kHz
the input stage of all op-amps. This is done basically to
provide the op-amps with a very high CMRR (common BSNL TTA 29.09.2016, 10 AM
mode rejection ratio). Ans : (b) Given that−
A Gain × B⋅W. = 1 MHz
CMRR = d
Ac
Differential amplifier gives higher differential mode
gain (Ad) and less common mode gain (Ac).
So, CMRR is high.
96. In the differential amplifier of the figure, if the
source resistance of the current source IEE is
infinite, then the common-mode gain is-
B⋅W = fH − fL
B⋅W = fH − 0 = fH
fH = (B⋅W)3dB
gain × (B⋅W)3dB = 1MHz
Gain (in dB)
20dB = 20log (gain)
Gain = 10
10 × (B⋅W)3dB = 1MHz
1000×103
B⋅W =
10
(a) Zero (b) Infinite B⋅W = 100 kHz
Vin1 + Vin 2 98. Which among the following is the most widely
(c) Indeterminate (d)
2VT used constant-gain amplifier circuit?
BSNL TTA 29.09.2016, 10 AM (a) Inverting amplifier
Ans : (a) A differential amplifier is said to be in (b) Subtractor amplifier
common mode when same signal is applied to both (c) Non-inverting amplifier
inputs and the expected output will be zero, i.e. ideally (d) Summing amplifier
common mode gain is zero. PGCIL SR- II, 22.08.2021
Ans. (a) : Inverting amplifier

Electronics-II 925 YCT

 −R f 102. The feedback path in an ideal active OP-AMP
V0 = Vi
R1 integrator consists of _____.
Inverting amplifier is the most widely used constant- (a) resistor in series with a capacitor
gain amplifier circuit. (b) capacitor only
99. The operational amplifier used in analog (c) resistor only
computers should have- (d) resistor in series with an inductor
(a) Very high gain Vizag Steel MT 13.12.2020
(b) Very low gain Ans. (b) : The feedback path in an ideal active OP-
(c) Gain is not important AMP integrator consists of capacitor only.
(d) Low input resistance
BSNL TTA 27.09.2016, 3 PM
Ans : (a) Operational amplifier:- It is also known as
op-amp is a two-input single-output differential voltage
amplifier which is characterized by high gain, high
input impedance and low output impedance. The
operational amplifier is called so because it has origins
in analog computers, and was mainly used to perform
mathematical operations.
100. What is the hysteresis voltage for the Schmitt
trigger circuit shown in the figure below 103. For the input-output characteristic of amplifier
shown in fig. below the voltage gain is

(a) 1.90 V (b) 1.45 V

(c) 1.00 V (d) 0.90 V
APGCL AM 2021
Ans. (c) : Given Schmitt trigger circuit- Fig : Typical input-output characteristic of
inverting amplifiers.
(a) A = 50 (b) A = – 50
(c) A = 0.08 (d) A = – 0.08
UPPSC AE 13.12.2020, Paper-I
Ans. (b) :
V
Voltage gain (A) = 0 = slope of given characteristic
5 5 Vi
β= = = 0.05
95 + 5 100 2 2 ×103
Hysteresis voltage = = −
−40 × 10−3 40
( Vh ) = VUTP − VLTP = +βVcc − ( −βVcc ) 2000
A=−
= 0.05 × 10 − (−0.05 × 10) 40
= 0.50 + 0.5 A = –50
= Vh = 1V 104. For the circuit shown in figure below the value
V
101. An ideal OP-amp is an ideal of AV = o is
(a) VCVS (b) VCCS Vi
(c) CCCS (d) CCVS
JPSC AE 10.04.2021, Paper-I
Ans. (a) : An ideal op-amp is an ideal voltage
controlled voltage source.
Parameters Ideal Practical
Voltage gain ∞ 106
Input resistance ∞ 106 Ω or 1MΩ (a) – 10 (b) 10
output resistance 0 10 Ω to 100 Ω (c) –11 (d) 11
B.W. ∞ 106 Hz or 1MHz UPPSC AE 13.12.2020, Paper-I
Electronics-II 926 YCT
Ans. (a) : Given circuit is inverting amplifier. Ans. (d) :
For inverting amplifier-

 R  From virtual ground concept−

V0 =  − f  Vi
 R1  Apply node at A Apply node at B
V R 400 × 103 0 − Vi Vi − V2 V1 − Vi Vi
So, A v = 0 = − f = − = =
V1 R1 40 × 103 2 7 10 5
Av = –10 −7Vi = 2Vi − 2V2 V1 − Vi = 2Vi
105. Consider the non-inverting amplifier circuit of −9Vi = −2V2 V1 = 3Vi
figure given below. The closed loop voltage gain V
is 9Vi = 2V2 ...... (i) Vi = 1 .........(ii)
3
from equation (i) and (ii)
V
9 × 1 = 2V2
3
3V1 = 2V2
(a) 16 (b) –14 V2
(c) 15 (d) 14 = 3 / 2 = 1.5
V1
UPPSC AE 13.12.2020, Paper-I
Ans. (a) : Rf = 30 KΩ 107. Determine the input impendence of the
Ri = 2 kΩ amplifiers if the data sheet gives Zin = 2 MΩ,
Zout = 75Ω and open loop gain AOL = 200000.

This figure is non inverting amplifier-

 R 
So Av = 1 + f 
 Ri  (a) 100 G ohm (b) 46 M ohm
 30  (c) 250 M ohm (d) 400 G ohm
Av =  1 +  (e) 100 ohm
 2 
RSEB JE 2013
A V = 16
Ans. (d) : ZinF = Zino (1 + Aβ )
106. The ratio of V2/V1 for the network shown below
is = 2 × 106 (1 + 2 × 105 )
= 2×2×1011
= 4×1011 Ω
Zinf = 400 G Ω
108. Active load is primarily used in the collector of
the differential amplifier of an OPAMP.
(a) To increase the output resistance
(b) To increase the differential gain A
(a) 3.5 (b) 5 (c) To handle large signals
(c) 3 (d) 1.5 (d) To provide symmetry
TSPSC Manager (Engg.) HMWSSB 2020 ESE-2014
Electronics-II 927 YCT
Ans. (b) : Active load is used to increases differential 111. The op-amp circuit shown below is a filter. the
gain Ad. type of filter and its cut off frequency are
respectively

(a) High pass and 1000 rad/sec

(b) Low pass and 1000 rad/sec
(c) Low pass and 1000 rad/sec
The collector resistors of differential amplifier can be (d) High pass and 10000 rad/sec
replaced by a current mirror, whose output acts as an RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
active load. Ans. (a) : A high pass filter is designed to pass all
Thus the differential collector current signal is frequency above its cut off frequency ωc.
converted to a single ended voltage signal without 1 1
intrinsic losses and the gain is extremely increased. ωc = =
RC 1×10 × 10−6
3
109. Which of the following is the characteristic of
an ideal op-amp? ωc = 1000 rad / sec
(a) Zero voltage gain 112. Which of the following statements about the
(b) Zero input resistance
Wien Bridge Oscillator is CORRECT?
(c) Infinite bandwidth
(d) Infinite output resistance (a) Op-amp circuit is introduced in 180°
LMRC (SCTO) 17.04.2021 phase shift.
PGCIL SR- II, 22.08.2021 (b) The amplifier gain condition is |A|≥29.
Ans. (c) : Infinite bandwidth- (c) Op-amp is used in inverting mode.
Parameters Ideal value Practical value (d) Feedback network is lead-lag network.
Voltage gain ∞ 106
PGCIL NR- I, 13.08.2021
Input resistance ∞ 10 Ω to 1 MΩ
6

Output resistance 0 10Ω to 100 Ω Ans. (d) : Wien Bridge oscillator uses a feedback
B.W. ∞ 106 Hz network which is same as lead-lag network.
6
CMRR ∞ 10 or 120 dB 113. In an ideal operational amplifier, the non-
Slew rate ∞ 80V/µ sec inverting terminal is grounded and the
110. The circuit shown below is: inverting terminal is connected to the output
through a capacitor of capacitance 1000µF. A
dc input voltage source of 15V is connected to
the inverting terminal through a resistor of
1kΩ. The op-amp supply is from +/-15V. Initial
voltage at the output is zero. What happens to
the output as time progresses?
(a) Clamper (b) Clipper (a) Saturates at +15V (b) Saturates at –15V
(c) Log amplifier (d) Anti-log amplifier (c) Remains zero (d) None of the above
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II ISRO VSSC (TA) 14.07.2021
Ans. (d) : An anti log amplifier is an electronic circuit Ans. (b) : Integrator op-amp-
that produces an output that is proportional to the anti
logarithm of the applied input.

 V  If , Vin = 15V
 
ηV
V0 = –Rf Is e T  C = 1000 µF

Electronics-II 928 YCT

 Rin = 1Ω 117. In an op-amp, the differential mode gain is
Then, _______________.
1 t (a) always zero (b) very low
R in C ∫0
V0 = − Vin dt (c) always unity (d) very high
UPPCL JE- 08.09.2021, Shift-II
1 1
−6 ∫0
=− 15 dt Ans. (d) : op-amp has high input impedance &
1× 10 ×1000 × 10
3
differential gain
V0 = –15V
114. Find the value of R in figure below to keep Vo=
0V
Vout
Ad = ⇒ (V1–V2) is very less, so Ad is high
V1 − V2
118. An instrumentation amplifier exhibits;
(a) High impedance between input terminals.
(b) Low impedance between input terminals.
(c) High offset and drift.
(d) Low common mode rejection and high
(a) 7.273K (b) 2K effective output impedance.
(c) 5.375K (d) 6.667K HPPSC PWD AE 24.08.2021
ISRO VSSC (TA) 14.07.2021
Ans. (a) :
Ans. (a) :
An instrumentation amplifier is usually employed to
amplify low level signals, rejecting noise and
interference signals.
A good instrumentation amplifier has to meet the
following specification.
(i) Finite accurate and Stable Gain
(ii) Easier Gain Adjustment
From virtual ground Va = Vb (iii) High input impedance
Apply nodal- (iv) Low output impedance
2 − Va 2 − Va Va − 0 (v) High CMRR
+ = (vi) High Slew Rate
2 2 4
Va = 8/5 119. Schmitt trigger is also known as:
6× R (a) squaring circuit
Vb =
R + 20 (b) blocking oscillator
8 6× R (c) sweep circuit
= (∵ Va = Vb ) (d) astable multivibrator
5 R + 20
80 BSNL TTA (JE) 27.09.2016, 10 AM
R= = 7.273 kΩ Ans. (a) A Schmitt trigger is a comparator circuit with
11
115. An op-amp based integrator converts the DC hysteresis implemented by applying positive feedback
level into a ________ output. to the non-inverting input of a comparator and it is also
(a) triangular known as squaring circuit.
(b) linearly increasing ramp
(c) square wave X. Integrated Circuits
(d) saw-tooth
UPPCL JE- 08.09.2021, Shift-II 1. Which of the following is the fastest of all
Ans. (b) : An op-amp integrator is an operational saturated logic families ? It is also used in SSI
amplifier circuit that performs the mathematical and MSI ICs.
operation of integration. An op-amp integrator converts (a) RTL (b) I2L
the DC level into a linearly increasing ramp. (c) TTL (d) DCTL
116. What is the unit of measurement for slew rate UPPCL JE- 08.09.2021, Shift-I
of an op-amp? Ans. (c) : TTL (transistor-transistor logic) is the fastest
(a) V/µs (b) dB logic family. It is build up from bipolar junction
(c) nA (d) Ampere transistor (BJT).
UPPCL JE- 08.09.2021, Shift-II 2. The other name for thick film deposition
Ans. (a) : The slew rate of an op-amp or any amplifier technology is:
circuit is the rate of change in the output voltage caused (a) film printing (b) name printing
by a step change on the input. It is measured as V/µs or (c) screen printing (d) diode printing
V/ms EESL Engineer (Technical) 2020
Electronics-II 929 YCT
Ans. (c) : Thick Film Technology:- Thick Film (more 7.
SSI refers to ICs with
correctly printed & fired) technology uses conductive (a) Less than 12 gates on same chip
resistive and insulating pastes containing glass frit, (b) Less than 8 gates on same chip
deposited in patterns defined by screen printing and (c) Less than 6 gates on same chip
fused at high temperature onto a ceramic substrate. (d) Less than 3 gates on same chip
• Also known as screen printing technology. HPSSC JE 2017 (Code-579)
3. Ans. (a) : SSI(small scale integration) refers voltage
Which among the following is the remedy for
ICS with less than 12 gate on same chip.
an integrated circuit to improve reliability?
(a) Reducing number of interconnections 8. The figure of merit of a digital IC is defined as
(b) All of these (a) the amount of heat dissipation in a second.
(c) Reduce component size (b) the product of cross-sectional area of the IC
(d) Advanced testing and average power dissipation.
NMRC JE 2019 (c) the ratio of propagation delay to average
Ans. (b) : An integrated circuit to improve reliability- power dissipation.
Reducing number of inter connections (d) the product of propagation delay and average
Reduce component size power dissipation.
Advanced testing BSPHCL JE 30.01.2019, Shift-II
4. Silicon has a preference in IC technology because?
Ans. (d) : The figure of merit of digital IC circuit is
(a) of the availability of nature oxide SiO2
defined as the product of speed and power. The speed is
(b) it is an elemental semiconductor specified in terms of propagation delay time expressed
(c) it is an indirect semiconductor in nanoseconds that means figure of merit is defined as
(d) it is a covalent semiconductor the product of propagation delay and average power
SSC JE 2015
dissipation.
Ans. : (a) 9. CMOS circuits are extensively used for IC-
1. Si is plenty available on the surface of earth. chips fabrication, mainly because of their
2. Leakage in Si is very less as compared to Ge. extremely:
3. Formation of SiO2 layer. (a) low power dissipation
4. Si is cheaper than Ge. (b) large packing density
5. Si has high power handling capability
(c) high noise immunity
6. Temperature handling capability of Si is more than
(d) low cost
Ge.
BSNL TTA (JE) 27.09.2016, 10 AM
For Si → up to 175ºC
For Ge → up to 75º C Ans. (b) CMOS circuits are extensively used for IC chip
fabrication, mainly because of their extremely Large
5. IC 741 and IC 555 timer output pin number:
(a) 6, 6 (b) 6, 3 packing density.
(c) 3, 3 (d) 3, 6 Operative voltage range of CMOS is in between +3V to
+15V supply. CMOS is easily fabricated on IC chips.
UJVNL JE 2016
10. IC LM7815 is a-
Ans. (b) : IC 741 this contain 6 output pin. The voltage
at this pin depends on the signal at the input pins and (a) Voltage regulator with a +5V output voltage
the feedback mechanism used. (b) Voltage regulator with a –5V output voltage
output high i.e. +ve the voltage supplied. (c) Voltage regulator with a +15V output voltage
output low i.e. -ve voltage supplied (d) Voltage regulator with a –15V output voltage
IC 555 this contain 3 output pin. There are two ways in BSNL TTA 26.09.2016, 10 AM
which a load can be connected to the output terminal.
Ans. (c) : IC LM7815 is a voltage regulator with a
+15V output voltage and IC LM7915 is a voltage
regulator with a –15 V output voltage.
78XX represents positive output voltage and 79XX
represents negative output voltage.
11. An astable 555 timer has the following number
of stable states
6. Which IC is a decade counter? (a) 0 (b) 1
(a) 7476 (b) 7486 (c) 2 (d) 3
(c) 7404 (d) 7490 BSNL TTA 28.09.2016, 10 AM
UKPSC JE 2013, PAPER-I Ans. (a) : An astable 555 timer has the zero number of
Ans. (d) : 7490 – decade counter stable states. IC 555 is a timer device. It operates both
7404 – Hex inverter as mono-stable and astable multivibrator. It is simple to
7486 – Quad Exclusive OR gate use and requires very few components for assembly in
7476 – Master–slave J–k flip–flop the circuit.
Electronics-II 930 YCT
12. In the process of fabricating monolithic XI. Communication Engineering
integrated circuits :
(a) Only passive components are fabricated on 1. The maximum peak to peak voltage of an AM
the same chip wave is 20 mV and the minimum peak to peak
(b) Active and passive components are fabricated voltage is 4 mV. The modulation factor is:
on the separate chips (a) 0.06 (b) 5
(c) The active and passive components are (c) 0.66 (d) 2
fabricated on the same chip DSSSB JE 19.03.2021, Shift-I
(d) Only active components are fabricated on the
V − Vmin 20 − 4
chip Ans. (c) : Modulation factor = max =
KVS WET 2017 Vmax + Vmin 20 + 4
Ans. (c) : The monolithic fabrication process consist of 16 2
m= =
wafer preparation, epitaxial growth, diffused isolation, 24 3
base and emitter diffusion, pre-ohmic etch, and final m = 0.67
testing. 2. It is assumed that quantization error, e(n) is a
All the active and passive components require for the sequence of random variables where
circuit are fabricated on same chip. 1. The statistics do not change with time.
13. Normal timer Circuit has 2. It is sequence of uncorrelated random
(a) Resistor, Inductor and Capacitor variables.
(b) Inductor and Capacitor 3. It is uncorrelated with the quantizer input
(c) Resistor and Inductor x(n).
(d) Resistor and Capacitor 4. The probability density function is uniformly
BSNL TTA 29.09.2016, 10 AM distributed over the range of values of
Ans : (d) The timer circuits are used to produce time quantization error.
delay intervals for triggering a load. This time delay is Which of the above statements are correct?
set by the user. Normal timer circuit has resistor and (a) 1, 2 and 3 only (b) 1, 2 and 4 only
capacitor e.g. IC 555 timer circuit. (c) 3 and 4 only (d) 1, 2, 3 and 4
ESE (Pre) 18.07.2021
14. As compared to voltage regulators made up of ESE 2020
discrete components, IC regulators have the
Ans. (b) : Quantization error is the difference between
inherent advantages of the analog signal and the closest available digital value
(a) self protection against over temperature at each sampling instant from the A/D converters.
(b) remote control The probability density function does not uniformly
(c) current limiting distributed over the range of values of quantization error.
(d) All of these
3. In a super heterodyne receiver, the IF is 455
BSNL TTA 29.09.2016, 10 AM kHz. If it tuned to 1200 kHz, the image
Ans : (d) IC regulators have inherent superiority of frequency will be
more temperature self protection, remote control and (a) 1655 kHz (b) 2110 kHz
current control when compared to voltage regulators (c) 745 kHz (d) 910 kHz
manufactured from separate components. JPSC AE 10.04.2021, Paper-I
15. Which of the following are the basic elements Mizoram PSC IOF 2019, Paper-III
in a 555 timer IC? Ans. (b) : A signal (image) can interfere with a super
(1) Two comparators heterodyne receiver if its equation
(2) A flip-flop fimage = Signal frequency +2IF
(3) A discharge transistor Which says that a signal has the capacity to interfere
(4) A resistive voltage divider with a super heterodyne receiver if frequency is equal to
(a) 1, 2 and 4 (b) Only 1, 2 and 3 the signal frequency plus or minus twice the IF.
(c) Only 2, 3 and 4 (d) Only 1, 2, 3 and 4 So one possible image frequency = fs + 2IF
RPSC Lect. (Tech. Edu. Dept.) 09.01.2016 = 1200 + 2 × 455 = 2110 KHz
Ans. (d) : The single 555 timer chip consist of 4. What is the maximum bit rate of a noiseless
channel with a bandwidth of 1000 Hz
transistors, 2 diodes in comparators and a flip-flop and transmitting a signal with two signal levels?
various resistors as voltage divider. (a) 2000 bps (b) 3000 bps
16. Integrated Circuits (ICs) were used in– (c) 4000 bps (d) 6000 bps
(a) First-generation computing devices ESE (Pre) 18.07.2021
(b) Second-generation computing devices Ans. (a) : According to question
(c) Third-generation computing devices Bandwidth B = 1000 Hz
(d) Fourth-generation computing devices Signal level µ = 2
(RRB JE (Shift-II), 04.09.2015) ∴ Maximum bit rate of a noiseless channel
Ans : (c) Integrated Circuits (ICs) were used in third- C = 2B log2µ
generation computing devices. = 2×1000 log 2 2 = 2000 bps

Electronics-II 931 YCT

5. A signal has eight data levels with a pulse 9. Aliasing refers to
duration of 1 ms. What is the bit rate? (a) Sampling of signals greater than Nyquist rate
(a) 1000 bps (b) 2000 bps (b) Sampling of signals less than Nyquist rate
(c) 3000 bps (d) 4000 bps (c) Sampling of signals at Nyquist rate
ESE (Pre) 18.07.2021 (d) None of the above
Ans. (c) : According to question JPSC AE 10.04.2021, Paper-I
Data levels ℓ = 8 Ans. (b) : In signal processing and related disciplines,
pulse duration Ts = 1 ms aliasing is an effect that causes different signals to
then bit duration become indistinguishable when sampled. Aliasing refers
T 1 1 to sampling of signals less than Nyquist rate.
Tb = s = ms = s 10. The modulation index of an AM wave is
3 3 3000
1 1 changed from 0 to 1. The transmitted power is
∴ bit rate rb = = = 3000 bps (a) halved (b) increased by 50%
Tb 1/ 3000 (c) quadrupled (d) unchanged
6. The function of an AM detector is to Mizoram PSC IOF 2019, Paper-III
demodulate the AM signal and recover JUVNL JE 2017
(a) the original source information with same BSNL TTA 29.09.2016, 3:00 PM
frequencies and same relative amplitude KPTCL JE 2016
characteristics. BSNL TTA JE 14.07.2013
(b) the original source information with up- ESE 2001
converted frequencies.
(c) The original signal with amplified output  m2 
voltage. Ans. (b) : Pt = Pc 1 + 
 2 
(d) the original source information with various
frequencies and different amplitude  02 
characteristics. When m = 0 Pt1 = PC 1 + 
ESE (Pre) 18.07.2021  2 
Ans. (a) : The function of an AM detector is to Pt1 = PC
demodulate the AM signal and recover the original
source information with same frequencies and same  (1)2 
relative amplitude characteristics. m= 1 Pt 2 = PC  1 + 
 2 
7. Which one of the following statements is 
correct for full amplitude modulation?
 1
(a) The spectrum consists of two sidebands (one = PC 1 + 
termed the upper sideband and the other  2
termed the lower sideband). 3
(b) The spectrum consists of one sideband = PC
(termed the upper sideband). 2
(c) The spectrum consists of one sideband Pt − Pt1
% increase Pt = 2 × 100
(termed the lower sideband). Pt1
(d) The spectrum consists of three sidebands (one
termed the upper sideband, the second termed 3 / 2PC − PC
= × 100
the lower sideband, and the third termed the PC
lowest sideband).
1
ESE (Pre) 18.07.2021 = × 100
Ans. (a) : Full amplitude modulation consists of two 2
side bands one termed as the upper side band and the = 50%
other termed as lower side band. 11. A sinusoidal voltage of amplitude 1 kV is
8. The highest frequency component of a speech amplitude modulated by another sinusoid
signal needed for telephonic communications is voltage to produce 30% modulation. The
about 3.1 kHz. What is the suitable value for amplitude of each sideband term is
the sampling rate? (a) 300 volts (b) 150 volts
(a) 1 kHz (b) 2 kHz
(c) 500 volts (d) 250 volts
(c) 4 kHz (d) 8 kHz
ESE (Pre) 18.07.2021 MPPKVVCL JE 2018
Ans. (d) : Given that, BSNL TTA 28.09.2016, 10:00 AM
fm = 3.1 kHz KSEB Sub Engineer 2015
as we know 30
Ans. (b) : Modulation Index (m) = 30% = = 0.3
sampling rate ( fs ) ≥ 2f m 100
fs = 2×3.1 VC = 1 kV = 1000 V
f s = 6.2kHz mVc 0.3 ×1000
Voltage at each side band = = = 150V
So, fs should be greater than 6.2 kHz. 2 2
Electronics-II 932 YCT
12. A carrier is modulated simultaneously by two 17. PPM signal is
sine waves with modulation indices of 0.3 and (a) Differentiation of PWM
0.4, the total modulation index is- (b) Integration of PWM
(a) 1 (b) Can not be calculated (c) Differentiation
(c) 0.5 (d) 0.7 (d) Not related to PWM or PAM
BSNL TTA 26.09.2016, 10 AM ESE-2011
BSNL TTA 28.09.2016, 3:00 PM Ans. (a) : PPM is equivalent to differentiation of PWM.
Ans. (c) : Given that, m1 = 0.3, m2 = 0.4 In PPM (Pulse Position Modulation) the position of the
pulse of the carrier is varied with reference to the
Total modulation index ( m ) = m12 + m 22
position of a reference pulse. The position varied in
= ( 0.3) + ( 0.4 ) accordance with the sampled modulating signal.
2 2

18. To produce sound waves of different pitch,

= 0.09 + 0.16 objects of different sizes and conditions are
= 0.25 made to vibrate at different-
m = 0.5 (a) Quality (b) Frequencies
13. An FM signal with a modulation index mf is (c) Time (d) Type
passed through a frequency Tripler. The wave RRB JE 01.09.2019 Shift-I
in the output of the Tripler will have a Ans. (b) : To produce sound waves of different pitch,
modulation index of: objects of different sizes and conditions are made to
(a) mf (b) 9 mf vibrate at different frequencies.
(c) 3 mf (d) mf/3 19. In differential PCM, each word indicates:
JUVNL JE-2017 (a) Difference between a sample amplitude and a
Ans. (c) : Modulation index reference signal
∆f (b) Difference in amplitude between a sample
mf = …….(i) and the previous sample
fm (c) Addition of a sample amplitude and a
when it passes through tripler reference signal
3∆f (d) Addition of amplitude of a sample and the
m′f = previous sample
fm
ESE-2011
from (i)
Ans. (b) : DPCM- Differential pulse code modulation
m′f = 3m f (DPCM) is a procedure of converting an analog into a
14. Following is not the purpose of modulation : digital signal in which an analog signal is sampled and
(a) Multiplexing then the difference between the actual sample value and
(b) Effective radiation its predicted value (predicted value is based on previous
(c) Narrow banding sample or samples) is quantized and then encoded
(d) Increase in signal power forming a digital value..
KPTCL JE 2016 20. In a frequency modulation system, maximum
Ans. (d) : Increase in signal power is not the purpose of frequency deviation allowed is 1000 and
modulation. modulating frequency is 1 kHz. Determine
In modulation technique we are mixing message signal modulation index β.
with very low frequency to carrier signal at high (a) 2 (b) 2000
frequency on transmitter end. Same message signal (c) 1 (d) 1000
obtained at receiving end by demodulation method. ESE-2013
15. A PAM signal can be detected by using Ans. (c) : Modulation index can be given as
(a) an integrator (b) a band pass filter ∆f
(c) a high pass filter (d) a low pass filter β=
KPTCL JE 2016 fm
Ans. (d) : The demodulation of PAM signal can be Where, ∆ f = maximum frequency deviation
done by using a low pass filter. In PAM, detector, low f m = modulating frequency
pass filter eliminates high frequency ripples and Given that,
generate the demodulated signal which has its ∆f = 1000 and fm = 1 kHz
amplitude portion to PAM signal at all time instant. 1000
Then, β= =1
16. The following is not an advantage of FM over 1kHz
AM :
21. In communication system, noise is most likely
(a) Sputtering effect (b) Capture effect
(c) Fidelity (d) Noise immunity to affect the signal -
KPTCL JE 2016 (a) At the destination
Ans. (a) : Sputtering effect is not an advantage of FM (b) At the transmitter
over AM. Frequency Modulation has many advantages (c) In the channel
over Amplitude Modulation such as noise immune (d) In the information source
(high S/N ratio), require less modulation power. RSMSSB JEN (Degree) 29.11.2020
ESE 2005
Electronics-II 933 YCT
Ans. (c) : In communication system, noise is most Ans. (b) : Audio frequency 20 Hz to 20,000 Hz
likely to affect the signal in the channel. Channel is Infrared frequency less than 20 Hz
connection or link between transmitting end to Ultrasonic range above 20,000 Hz
receiving end (Transmitter to Receiver) channel may be 25. In commercial FM broadcasting the maximum
wired or wireless. If wired then medium may be- frequency deviation is normally
(i) Coaxial cable (a) 200 kHz (b) 75 kHz
(ii) Twisted pair cable (c) 5 kHz (d) 15 kHz
(iii) Transmission line RSMSSB JEN (PHED)Degree 26.12.2020
Noise is always introduced at the channel. Ans. (b) : Maximum frequency deviation allowed for
22. What is the disadvantage of FM over AM? commercial F.M broadcost is 75 kHz. Therefore
(a) High noise is produced approximate bandwidth is 150 kHz.
(b) High modulating power is needed 26. Which one of the following statement is not
(c) Requires high output power correct?
(d) Large bandwidth required (a) FM has infinite number of side-bands
RSMSSB JEN (Degree) 29.11.2020 (b) Modulation index for FM is always greater
Ans. (d) : The bandwidth of the F.M signal is higher than one
than the AM signal. Where the bandwidth of AM signal (c) As modulation depth increases the BW
is twice the highest modulating frequency. increase
B.W = 2 fm (d) As modulation depth increases the sideband
In FM the bandwidth is equal to two times the sum of power increases
the frequency and frequency deviation of the ESE-2014
modulating signal. B.W = 2 (fm + ∆f) Ans. (b) : Modulation index-
23. In the sinusoidal pulse-width modulation For wideband FM = about above 0.5
scheme, if the zero of the triangular wave For narrow band FM = less than 0.5
coincides with the zero of the reference So, this statement is not correct i.e. modulation index
sinusoidal, then the number of pulse per half for FM is always greater than 1.
cycle is 27. Consider an analog signal x(t) = 5 sin
f f (6000πt)+10 cos (12000πt). What is the Nyquist
(a) c (b) c + 1
2f 2f rate for this signal?
2f c f (a) 12000 Hz (b) 24000 Hz
(c) (d) c − 1 (c) 18000 Hz (d) 6000 Hz
f 2f DGVCL JE 06.01.2021, Shift-I
ESE-2016
Ans. (a) : Given, an analog signal
Ans. (d) : In sinusoidal pulse width modulation zero of
a carrier signal coincides with zero of the reference x ( t ) =5 sin ( 6000 πt ) + 10 cos (12000 πt )
wave is a sinusoidal wave and the carrier wave is a ω1 = 6000π, ω2 = 12000π
triangular wave. ω2( max ) = 12000π
2πf max = 12000π
f max = 6000 Hz
Nyquist rate = 2f max = 2 × 6000
=12000 Hz
28. In an AM signal when the modulation index is
one, the maximum power Pt, (where Pc is the
carrier power) is equal to
(a) Pc (b) 1.5 Pc
(c) 2 Pc (d) 2.5 Pc
ESE-2001
In the above waveform, we have given the carrier wave Ans. (b) : Maximum power or total power -
of 4 pulses in a half cycle i.e. m = 4 and we are getting
(m-1) pulses i.e. 3 pulses at the output.  m2 
Pt = Pc 1 + 
fc  2 
Number of pulses per half cycle = −1
2f Pt = total power
Where, fc = frequency of carrier triangular wave Pc = carrier power
f = frequency of the sinusoidal wave. m = modulation index = 1
24. What is the frequency range of audio  1
amplifier? Pt = Pc 1 + 
(a) 0 to 20 Hz (b) 20 Hz to 20 kHz  2
(c) 20 to 200kHz (d) Above 20 kHz P t = Pc × 1.5
(e) 100 to 500 kHz Pt = 1.5 Pc
RSEB JE 2011
Electronics-II 934 YCT
29. The sampling frequency of analog signal x(t)= 4 Ans : (b) Generally fLO > fs
sin 300 π t + 2 cos50π t should be : Given fs = 1455 kHz
(a) Greater than 50Hz (b) Greater than 300Hz We know that for AM,
(c) Less than 300Hz (d) Less than 50Hz f IF = 455 kHz
NLC GET 17.11.2020 f LO = fS + f IF
Ans. (b) : x(t) = 4 sin 300πt + 2 cos 50πt Then, fLO = 1455 + 455 = 1910 kHz
ω1 = 300π, ω2 = 50πt 34. Power spectral density of a signal is
ω1( max ) = 300π (a) Complex, even and nonnegative
(b) Real, even and nonnegative
fm = 150 Hz (c) Real, even and negative
f s ≥ 2f m (d) Complex, odd and negative
f s ≥ 2 ×150 ESE-2003
Ans. (b) : Power spectral density (PSD)
f s ≥ 300 Hz ∞
Sx ( f ) = F{Rx(T)}= ∫ R x (T) e −2 jπfτdτ
30. Modulation has a number of advantages. −∞
Which of one of the following in not correct? Where, j = −1
(a) Efficient transmission Power spectral density of the signal describe the power
(b) Reduction in noise and interference present in the signal as a function of frequency, per unit
(c) Overcomes hardware limitations frequency.
(d) Requires higher power transmitter Since power of a signal is real quantity and can never be
ESE-2014 negative. So, power spectral density can also even, real
and non negative.
Ans. (c) : Modulation does not overcome hardware
limitations. 35. Fosters Seeley discriminator uses a
(a) Double tuned circuit in which primary and
31. From bandwidth point of view, narrow band secondary are tuned to same frequency
FM is equivalent to ................... (b) Double tuned circuit in which primary and
(a) AM secondary are tuned to different frequencies
(b) PM (c) Single tuned circuit
(c) SSB (d) Three diodes in series
(d) DSB suppressed carrier BSNL TTA 25.09.2016, Shift-I
BSNL TTA 29.09.2016, 3 pm BSNL TTA 29.09.2016, 3 pm
Ans : (a) From bandwidth point of view narrow band Ans : (a) Fosters Seeley discriminator uses a double tuned
FM is equivalent to AM. In which its side band circuit in which primary and secondary are tuned to same
component is at (fc±fm), so it needs only 2fm frequency. The Foster Seeley discriminator is also known
transmission bandwidth. It's spectrum is different from as the phase shift discriminator. It used as double-tuned RF
AM in two ways. First modulate two side bands are transformer to convert frequency variations in the received
FM signal to amplitude variations.
180º out of phase.
36. An AM superheterodyne receiver with IF of
32. A DSB suppressed carrier reception is shown 455 kHz is tuned to the carrier frequency of
in the below figure. If (SNR)i is the S/N ratio 1000 kHz. The image frequency is
for direct (incoherent) detection and (SNR)s is (a) 545 kHz (b) 1 MHz
that for (coherent) synchronous detection, then (c) 1455 kHz (d) 1910 kHz
ESE-2001
Ans. (d) : We know that -
Image frequency (fsi) = fs + 2fi
Where,
fs = signal frequency or carrier frequency = 1000 kHz
(a) (SNR)s = 2(SNR)i (b) (SNR)s = (SNR)i fi = intermediate frequency = 455 kHz
(c) (SNE)s = 4(SNR)i (d) (SNR)s = 1/2(SNR)i f(si) = 1000 + 2 × 455 = 1910 kHz
ESE-2001 37. The data rate for PRI in ISDN is
Ans. (b) : SNR remains in case of direct (in coherent) (a) Same as that of E1 (b) 64 kbps
and coherent detection (c) 10Mbps (d) 100Mbps
(SNR ) s = ( SNR ) i BSNL TTA 29.09.2016, 3 pm
But, SNR decreases as compare to a incoherent and Ans : (a) The data rate for PRI in ISDN is same as that
of E1. PRI (Primary Rate Interface) is a
coherent in case of non coherent detection.
telecommunication standard. Which is used for telecast
33. In case a station is tuned to 1455 kHz, the local of DS0 voice and data between network and user on
oscillator frequency will be .................. integrated services digital network (ISDN). It is based
(a) 1000 kHz (b) 1910 kHz on T-carrier (T1) transmission in Japan, America &
(c) 1455 kHz (d) 2100 kHz Canada while E- carrier (E1) is common in Europe and
BSNL TTA 29.09.2016, 3 pm Australia.
Electronics-II 935 YCT
38. In phase modulation, the frequency deviation is 42. For practical purpose, the signal to noise ratio
(a) Independent of the modulating signal for acceptable quality transmission of analog
frequency signals and digital signals respectively are
(b) Increasingly proportional to the modulating (a) 10 - 30 dB and 05 - 80 dB
signal frequency (b) 40 - 60 dB and 10 - 12 dB
(c) Directly proportional to the modulating signal (c) 60 - 80 dB and 20 - 24 dB
frequency (d) 70 - 90 dB and 30 - 36 dB
(d) Inversely proportional to the square root of ESE 2019
the modulating signal frequency Ans. (b) : SNR-
ESE-2014 • In analog and digital communications signals to
Ans. (c) : We know that, noise ratio is a measure of the strength of the desired
PM0 = Ac cos ωct + kp m(t) signal relative to undesired signal (background
m(t) = message signal = Am sinωmt noise).
∴ PM = Ac cosωct + kp Am sinωmt • SNR is typically expressed in dB (decibels).
∴ m = kp Am • SNR can be zero, positive or a negative number.
and ∆f = mfm • For practical purpose, SNR for transmission of
∴ ∆f = kp Am fm analog signals and digital signals respectively are
& ∆f ∝ f m in PM 40-60 dB and 10-12 dB.
So, in phase modulation, the frequency deviation is 43. A signal m(t) = 2 cos 6000 πt + 4 cos 8000 πt + 6
directly proportional to the modulating signal cos 10000 πt is to be truthfully represented by
frequency. its samples. The minimum sampling rate using
Where, band pass consideration will be
fm = Modulating signal frequency (a) 5,000 Hz (b) 10,000 Hz
m = Modulation index (c) 15,000 Hz (d) 20,000 Hz
39. Attenuator have applications..................... ESE 2019
(a) In d.c. circuits only Ans. (a) : Given signal is
(b) In a.c. circuits only m(t) = 2 cos 6000πt + 4cos8000πt + 6cos10000πt
(c) In d.c. and a.c. circuits ω1 = 6000π, ω2 = 8000π , ω3 = 10000π
(d) In 10 Hz frequency circuits only f1 = 3000Hz, f 2 = 4000Hz, f 3 = 5000Hz
BSNL TTA 29.09.2016, 3 pm
Ans : (c) Attenuator have applications in dc and ac fL = 3000Hz , fH = 5000 Hz
circuits. Attenuator is an electrical equipment which Bandwidth = fH–fL = 5000–3000
weakness the power of a wave without deforming the =2000 Hz
waveform. For band pass sampling
40. When an information signal is multiplied by an 2× Highest frequency component ( f A )
f s( min ) =
auxiliary sinusoidal signal to translate its Greatest integer value ( K )
frequency, the modulation is called
(a) Phase modulation Highest frequency component ( f H )
K≤
(b) Frequency modulation Bandwidth ( BW )
(c) Amplitude modulation
5000
(d) Quadrature amplitude modulation ≤
ESE 2019 2000
Ans. (c) : Information (message) signal is multiplied K ≤ 2.5, k ≃ 2
with auxiliary (carrier) signal in amplitude modulation 2 × 5000
to translate baseband frequency to higher frequencies. f s( min ) =
2
41. The transmission power efficiency for a tone = 5000 Hz
modulated signal with modulated index of 0.5
will be nearly 44. Consider the analog signal
(a) 6.7% (b) 11.1% xa(t) = 3 cos100πt
(c) 16.7% (d) 21.1% The minimum sampling rate FS required to
ESE 2019 avoid aliasing will be
Ans. (b) : Given = 0.5, (a) 100 Hz (b) 200 Hz
Transmission power efficiency (c) 300 Hz (d) 400 Hz
ESE 2019
µ2
η= Ans. (a) : Xa (t) = 3 cos 100πt
2 + µ2 2πfm = 100π ⇒ fm = 50 Hz
( 0.5)
2
Minimum sampling frequency
η= = 0.111 fS ≥ 2 fm
2 + ( 0.5 )
2
fS ≥ 2 × 50
η = 11.1% fS ≥ 100 Hz

Electronics-II 936 YCT

45. The modulating index of an AM-signal is Hence, maximum upper side frequency-
reduced from 0.8 to 0.5. The ratio of the total Rb 10
power in the new modulated signal to that of USF( max ) = f c + = 70 + = 75 MHz
the original signal will nearly be 2 2
Minimum lower side frequency-
(a) 0.39 (b) 0.63
(c) 0.85 (d) 1.25 R 10
LSF( min ) = f c − b = 70 − = 65MHz
ESE 2018 2 2
Ans. (c) : It is given that :- 48. In modulation system, the energy per bit-to-
µ1= 0.8, µ2 = 0.5 E
PT2/PT1 = ? noise power density ratio b is
N
Pc (1 + µ 22 / 2 )
o
PT2 C fb N B
= × ×
Pc (1 + µ21 / 2 )
(a) (b)
PT1 N B C fb
 ( 0.5 )2  C B N fb
(c) × (d) ×
1 +  25 N fb C B
PT2  2  1 +
= = 200 ESE 2020
PT1  ( 0.8 )2  1 + 64 Ans. (c) : Carrier to noise ratio of received signal,
1 +  200 C Eb fb
 2  = ×
N N0 B
PT2 = PT1 × 0.85
Eb C B
46. In AM modulation, the equation of the = ×
No N f b
modulating signal is given by f(t) = Am cos ωm t.
If the amplitude of the carrier wave is A and Where, f b = bit rate
there is no over-modulation, the modulation B = received noise bandwidth
efficiency will be 49. Which one of the following is not a
(a) 33.3% (b) 38.6% transmission parameter of a private line data
(c) 43.3% (d) 48.6% circuit that utilizes public telephone network?
ESE 2020 (a) Geographical parameter
Ans. (a) : For AM signal, (b) Bandwidth parameter
µ2 (c) Interface parameter
Modulation efficiency ( η ) = (d) Facility parameter
2 + µ2 ESE 2020
No over modulation ( µ ≤ 1) Ans. (a) : There are three broad categories of
So, for maximum efficiency µ = 1 transmission parameters–
Bandwidth parameter
1 100
η% = ×100 = Interface parameter
2 +1 3 Facility parameter
η = 33.3% Geographical parameter is not transmission parameter.
47. For a binary phase-shift keying modulator with 50. The Shannon limit for information capacity I is
a carrier frequency of 70 MHz and input bit  S  S
rate of 10 Mbps, the maximum Upper Side (a) Blog 2  1 −  (b) Blog 2  1 + 
Frequency (USF) and minimum Lower Side  N   N 
Frequency (LSF) are respectively  S  S
(c) Blog10 1 −  (d) Blog10 1 + 
(a) 85 MHz and 65 MHz  N  N
(b) 75 MHz and 65 MHz Where:
(c) 55 MHz and 45 MHz N = Noise power (W)
(d) 75 MHz and 45 MHz B = Bandwidth (Hz)
ESE 2020 S = Signal power (W)
Ans. (b) : Given, carrier frequency fc = 70 MHz ESE 2020
Input bit rate Rb = 10 mbps Ans. (b) : Shannon limit for information capacity of a
BPSK spectrum- communication channel refers to the maximum rate of
error-free data that can theoretically be transferred over
the channel
 S
I = Blog 2 1 + 
 N
Where, N = The total channel noise power across
bandwidth B
B = Bandwidth for data transmission
S = Received signal power
Electronics-II 937 YCT
51. A signal is said to be Ans. (d)
1. Deterministic if there is no uncertainty over Advantages of FM over AM -
the signal at any instant of time. FM AM
2. Deterministic if it is expressible through a FM receivers are AM receivers are not
mathematical equation. immune to noise immune to noise
3. Random or non-deterministic if there is Bandwidth is higher Bandwidth is lower
uncertainty over the signal at the instant of and depends on and Independent of
time. modulation index modulation index
4. Random or non-deterministic if it is not
Noise can be This feature is absent
expressible through a mathematical equation.
Which of the above statements are correct? decreased by in AM
(a) 1, 2 and 3 only (b) 1, 2 and 4 only increasing deviation
(c) 3 and 4 only (d) 1, 2, 3 and 4 55. In order to recover the original signal from the
ESE 2020 Sampled one, what is the condition to be
Ans. (d) : A signal is said to be deterministic if there is satisfied for sampling frequency ωs and highest
no uncertainty over the signal at any instant of time and frequency component ωm?
can be expressed through a mathematical equation. (a) ωm < ωs ≤ 2 ωm (b) ωs ≥ 2 ωm
Signal is said to be random or non-deterministic if there (c) ωs < ωm (d) ωs = ωm
is uncertainty over the signal and non-expressable JKSSB JE 2014
through mathematical equation. Ans. (b) : In order to recover the original signal from
52. The Nyquist rate for the signal the sampled one for sampling frequency ωs and highest
1 frequency component ωm the condition ωs ≥ 2 ωm
x(t) = cos (4000 πt) cos (1000 πt) will be
2π Should be satisfied.
(a) 5 kHz (b) 10 kHz 56. If large amount of information is to be
(c) 15 kHz (d) 20 kHz transmitted in a small amount of time, we
ESE 2020 require
Ans. (a) : To evaluate the Nyquist rate of signal (a) Low-frequency signals
1 (b) Narrow-band signals
x(t) = .cos(4000πt).cos(1000πt)
2π (c) Wide-band signals
1 (d) High-frequency signals
x(t) = .[ 2cos(4000πt).cos(1000πt) ] ESE-2003
4π
1 Ans. (d) : If large amount of information is to be
x(t) = .[ cos(3000πt).cos(5000πt)] transmitted in a small amount of time, we require high-
4π
using cos (A – B) + cos (A + B) = 2 cos A. cos B) frequency signals.
ωm = 5000 π 57. A modulator is a system to
(a) separate two frequencies
 5000 π 
⇒ fm =   = 2500 Hz (b) impress the information on to a radio
 2π  frequency carrier
So, by low pass sampling theorem Nyquist rate ≥ 2fm (c) extract information from the carrier
for fs = 2(2500) (d) amplify the audio frequency signal
fs = 5000 Hz Mizoram PSC Nov. 2015, Paper-III
fs = 5 KHz Ans. (b) : Modulator control the an input audio signal.
53. A radio transmitter is an equipment : The modulator does not make a sound instead it
(a) For receiving R.F. signals changes the original carrier sound wave. Hence
(b) For generating modulated radio frequency modulator is a system to impress the information on to a
waves radio frequency carrier .
(c) For amplifying R.F. signals 58. In a frequency division multiplexed (FDM)
(d) For generating carrier waves system, cross talk occurs due to
DMRC JE 03.08.2014 (a) Imperfect time synchronization between
Ans. (b) : A radio transmitter is an equipment for transmitter and receiver
generating modulated radio frequency waves. (b) Imperfect filtering at the receiver front-end
54. Which of the following are the advantages of (c) Imperfect carrier recovery at the receiver
FM over AM? (d) Channel noise
1. Better noise immunity is provided ESE-2014
2. Lower bandwidth is required Ans. (b) : In FDM system cross talk occurs due to two
3. Transmitted power is more useful given reason-
4. Less modulating pore is required i. The imperfect filtering of the receiver end. When
(a) 1, 2 and 3 (b) 1, 2 and 4 multiples signals are available at a time.
(c) 2, 3 and 4 (d) 1, 3 and 4 ii. The closeness of signals using different frequency
ESE-2014 bands in a signal communication channel.
Electronics-II 938 YCT
59. The main purpose of modulation is to 64. When a radio receiver is tuned to 555 kHz, its
(a) combine two waves of different frequencies local oscillator provides the mixer with an
(b) achieve wave-shaping of the carrier wave input at 1010 kHz. At the output, another
(c) transmit low-frequency information over long signal is also received along with the desired
distances efficiently signal. What is the frequency of the other
(d) produce sidebands station?
Mizoram PSC Nov. 2015, Paper-III What is the frequency of the other station?
Ans. (c) : The main purpose of modulation is to (a) 910 kHz (b) 355 kHz
transmit low frequency information over long distance (c) 455 kHz (d) 1465 kHz
efficiently. The primary purpose of modulation in a ESE-2005
communication system to generate a modulated signal Ans. (d) : Given, Tuned frequency fs = 555 kHz
suited to the characteristics of a transmission channel. Local oscillator frequency fLO= 1010 kHz
In radio communications, modulation is needed in the We know,
transmission systems to transfer the message into the
available high frequency radio channel. f LO = f s + fi
60. A modulator is a device to Then, f i = f LO − f s
(a) Separate two frequencies = 1010 − 555 = 455 kHz
(b) Impress the information on to a radio Now,
frequency carrier
(c) Extract information from the carrier Frequency of other station f os = fs + 2fi
(d) Amplify the audio frequency signal = 555 + 2 × 455
ESE-2003 f os = 1465 kHz
Ans. (b) : Modulator : (in electronics and 65. An FM wave uses a 2-5 V, 500 Hz modulating
telecommunications) a device that produces modulation frequency and has a modulation index of 50.
(control of the parameters of a high-frequency The deviation is
electromagnetic information carrier in accordance with (a) 500 Hz (b) 100 Hz
electrical signals of the transmitted message). A
(c) 1250 Hz (d) 25000 Hz
modulator is mainly a component of transmitting
apparatus for electrical communication and radio Mizoram PSC Nov. 2015, Paper-III
broadcasting. Ans. (d) : Frequency deviation,
61. The most useful modulation technique for high ∆f = f m × m f
fidelity audio broadcasting on radio in current = 500 × 50
practice is = 25,000 Hz
(a) amplitude modulation 66. Which of the following desirable features are
(b) frequency modulation possessed by SSB in comparison to AM?
(c) pulse amplitude modulation 1. Less power is required
(d) pulse code modulation 2. Bandwidth required is less
Mizoram PSC Nov. 2015, Paper-III 3. Antenna size can be reduced
Ans. (b) : Frequency modulation is the most useful 4. Lower frequency can be used
modulation technique for high fidelity audio Select the correct answer using the codes given
broadcasting on radio in current practice. Frequency below:
modulation is the encoding of information in the carrier (a) 3 and 4 (b) 2, 3 and 4
wave by varying the instantaneous frequency of wave. (c) 1 and 2 (d) 1, 2 and 4
62. In FM modulation, when the modulation index ESE-2003
increases, the transmitted power is Ans. (c) :
(a) Increased (b) Decreased
(c) Unchanged (d) Non related • In SSB-SC, the carrier and one sideband are
ESE-2015 suppressed only one sideband is transmitted.
Ans. (c) : Total power in frequency modulation can be • Power is saved.
given as- • Modulation and demodulation are complex.
• Less Bandwidth require.
A2
PT = C • Used - point to point communication, military
2 communication etc.
From above formula transmitted power is independent
67. In AM, the carrier is changed by a modulating
of modulation index.
signal. What parameter of the carrier is
63. Which of the following modulation techniques changed?
has got maximum SNR? (a) amplitude (b) frequency
(a) AM-SSB (b) AM-DSB
(c) pulse width (d) phase
(c) FM (d) AM-SC
Mizoram PSC Nov. 2015, Paper-III Mizoram PSC Nov. 2015, Paper-III
Ans. (c) : Frequency modulation technique has Ans. (a) : In AM (amplitude modulation) technique
maximum signal to noise ration Because harmonic amplitude of carrier signal is changed according to
occurs in the FM. message signal.

Electronics-II 939 YCT

68. A filter, circuit is included in the radio receiver 72. An FM wave is given as v = 12 sin (6 × 108 t + 5
set to sin 1250 t). Its carrier frequency is
(a) Enhance the strength of the signal (a) 60.0 MHz (b) 95.5 MHz
(b) Ensure that the required signal is not (c) 125.0 MHz (d) 276.3 MHz
attenuated ESE-2016
(c) To pick up the signal of the desired frequency UKPSC JE 2013, PAPER-I
and block out the signal of other frequencies Ans. (b) : Given, FM wave equation–
(d) All of the above v = 12 sin (6 × 108 t + 5 sin 1250 t) .....(i)
WBPSC SAE 2002 v = A C cos ( ωc t + m f sin ωm t ) .....(ii)
Ans. (c) : Filter is use in radio receiver to choice desired By comparing equation (i) with (ii) we get–
frequency and block/ attenuate other frequency.
ωC = 2πf C
69. The detection-gain for coherent DSB
demodulator is ω
fC = C
(a) 2 (b) 4 2π
(c) 8 (d) 16 ωC = 6 ×108 rad / sec
ESE-2003
6 ×108
Ans. (a) : Coherent detector- The same carrier signal fC =
(which is used for generating DSBSC signal) is used to 2π
detect s(t) the message signal. Hence, this process of = 95.5 MHz
detection is called as coherent or synchronous detection. 73. Which one of the following statements is
For coherent DSB detector, the detection gain is = 2. correct? The type of modulation used generally
in TV transmission for video and audio signals,
respectively, are
(a) FM and AM (b) FM and FM
(c) AM and AM (d) AM and FM
ESE-2004
Ans. (d) : In TV transmission AM is used for video and
FM is used for audio transmission. Total bandwidth of 4
70. A balanced modulator is used for generation of MHz is used to deliver the video information and 2
which of the following? MHz is used to deliver the audio information. Hence the
(a) DSB-SC signal (b) FM signal total bandwidth of 6 MHz is used for TV transmission.
(c) PM signal (d) PAM signal 74. Which one of the following statements is
UKPSC JE 2013, PAPER-I correct?
Ans. (a) : Generation of DSB – SC Wave – The capacitor charging time in the AM envelope
(i) Balanced modulator demodulator is based on the time for one
(ii) Ring modulator (a) Half cycle of the carrier frequency
Detection of DSB – SC Wave – (b) Quarter cycle of the carrier frequency
(i) Coherent detection or synchronous detector (c) Half cycle of the lowest audio frequency
(ii) Costa Receiver (d) Quarter cycle of the highest audio frequency
(iii) Squaring loop ESE-2004
71. In amplitude modulation, the modulation Ans. (d) : In the positive half cycle of the RF input
envelope has a peak value which is double the signal, the diode is forward biased and the capacitor c
gets charged up to the peak value of the input signal.
unmodulated carrier value. What is the value
When the input drops below its peak value, the diode
of the modulation index?
becomes reverse biased and the capacitor C becomes
(a) 25% (b) 50%
unchanged by the load RL. This discharging process
(c) 75% (d) 100%
continues till the next positive peak.
ESE-2004 So, the charging time of capacitor corresponds to rise of
Ans. (d) : We know that, standard form of AM signal is carrier signal which is quarter of the carrier frequency
s ( t ) = A C (1 + µ sin 2πf m t ) cos 2πf c t cycle.
Here, envelope = AC (1 + µ sin 2πf m t ) 75. Which of the following is correct about the gain
in dB of a cascade amplifier?
Peak value of envelope = A C (1 + µ × 1) (a) Total gain is a sum of individual gains
(b) Total gain is a product of voltage and current
(∴ maximum of sin 2πf m t = 1) gains
Now, AC = 2AC (c) Total gain is a product of individual gains
2A C = A C (1 + µ ) (d) Total gain is a ratio of individual gains
UPPCL JE 11.02.2018, Shift-I
µ =1
Ans : (a) In cascade amplifier, total gain is equal to sum
Hence, modulation index µ = 100% of individual gain when gain is given in dB.

Electronics-II 940 YCT

76. In a communication system, a process for Given, A m = 0.8V
which statistical averages and time-averages Total distributed power in AM,
equal, is called
(a) Stationary (b) Ergodic
(c) Gaussian (d) BIBO stable
ESE-2003
Ans. (b) : This is definition of Ergodic processes. A
random process is said to be ergodic if the time
averages of the process tend to the appropriate ensemble A C2 A C2 A 2m
PT = +
averages for a process to be ergodic, it has to 2R 4R
necessarily be stationary But not all stationary processes A 2C  A 2m 
are ergodic. = 1 + 
2R  2 
77. What do we call an externally introduced
( 500 )
 ( 0.8 )2 
2
signal which affects the controlled output?
= 1 +  = 2500 × 1.32
(a) Stimulus (b) Signal 2 × 50  2 
(c) Feedback (d) Gain control
DFCCIL JE 17.04.2016 Power = 3300W = 3.3kW
Ans. (a) : Stimulus is something that cause a reaction in 81. A telephone exchange has 9000 subscribers. If
a plant or part of body. It create a need to the number of calls originating at peak time is
communication and hence there must be stimulus for 10,000 in one hour, the calling rate is
communication. (a) 0.9 (b) 10/9
78. When the modulation frequency is doubled the (c) 0.81 (d) 0.1
modulation index is halved and the modulating BSNL TTA (JE) 25.09.2016, Shift-I
index is halved and the modulation voltage Ans. (b) : Let, for one subscriber the calling rate is x.
remains constant. This happens when the for 9000 subscriber calling rate = 9000x
modulating system ∴ 9000x = 10000
(a) AM (b) PM 10000
(c) FM (d) Delta Modulation Then x =
ESE-2016 9000
10
∆f x=
Ans. (c) : Modulation index of FM µ = 9
fm 82. The operating point of RF amplifier in an AM
If fm is twice µ will be halved and in case of PM by receiver is normally biased in
changing frequency modulation index does not change. (a) Class-A (b) Class-B
So the given process happens when the modulating (c) Class-C (d) Class BC condition
system is FM. ESE-2006
79. A band-limited signal with bandwidth ‘B’ may Ans. (c) : The class -C amplifier design has the greatest
be reconstructed perfectly from its samples, if efficiency but the poorest linearity in the classes of
the signal is sampled at a rate _______. amplifiers.
(a) less than ‘2B’ (b) equal to ‘B’ Applications of class- C amplifier.
(c) greater than ‘2B’ (d) equal to ‘B/2’ RF oscillator
DGVCL JE 06.01.2021, Shift-III RF amplifier
FM transmitter
Ans. (c) : A band-limited signal with bandwidth ‘B’ Booster amplifier
may be reconstructed perfectly from its samples, if the High frequency repeaters
signal is sampled at a rate greater than ‘2B’. tuned amplifiers.
80. An AM voltage signal s(t), with a carrier 83. The synchronous modems as more costly than
frequency of 1.15 GHz has a complex envelope the asynchronous modems because
g(t) = AC [1+m(t)], AC = 500 V, and the (a) They produce large volume of data
modulation is a 1 kHz sinusoidal test tone (b) They contain clock recovery circuit
described by m(t) = 0.8 sin (2π × 103t), appears (c) They transmit the data with stop and start bits
across a 50 Ω resistive load. What is the actual (d) They operate with a larger bandwidth
power dissipated in the load? BSNL TTA (JE) 25.09.2016, Shift-I
(a) 165 kW (b) 82.5 kW Ans. (b) : The synchronous modems as more costly than
(c) 3.3 kW (d) 6.6 kW the asynchronous modems because they contain clock
ESE-2005 recovery circuit. Initially one or two synchronization
Ans. (c) : Standard form of AM signal is characters are sent n synchronous serial transmission.
s ( t ) = A c 1 + K a m ( t )  cos 2πf c t Synchronization characters are sent to ensure the
beginning of a clock of data. Then data character is sent
Given that, Ac= 500V, fc = 1.15 GHz without any external bit continuous. Data is sent to detect
We know modulating signal some error at the end. A clock recovery circuit will be
m ( t ) = A m sin 2πf m t required so that synchronization is possible.
Electronics-II 941 YCT
84. V = A sin (ωct + m sin ωmt) is the expression for Pc = 2watt
(a) Amplitude modulated signal
(b) Frequency modulated signal m2
(c) Phase modulated signal Side Band Power = PC
2
(d) Carrier signal used for modulation
( )
2
ESE-2016 0.3
= 2×
Ans. (c) : The equation of phase modulated signal is 2
Spm ( t ) = A sin ( ωc t + k p m ( t ) ) each side band power =
0.09
= 0.045 watt.
2
= A sin ( ωc t + kp A m sin ωm t )
87. The demodulation of a delta modulated signal
Spm ( t ) = A sin ( ωc t + msin ωm t ) is achieved by
(a) Integration (b) Differentiation
Hence, V = A sin ( ωc t + msin ωm t ) is the expression for (c) Sampling (d) Band-pass filtering
phase modulated signal. ESE-2011
85. Which of the following modulated signals can Ans. (a) :
be detected by an envelope detector?
(a) DSB-suppressed carrier
(b) DSB-full carrier
(c) Frequency modulated signal
(d) SSB-suppressed carrier
ESE-2005
Ans. (b) : Diode Envelope Detector - Diode envelope
detector is the main circuit used in AM demodulation. It
is a simple but high efficiency circuit.
Demodulation of DM (delta modulator) is achieved by a
integrator.
88. Over modulation of transmitter signal is
corrected by the adjustment of the –––––––––
(a) speech amplifier (b) power amplifier
(c) RF oscillator (d) frequency doubler
BSNL TTA (JE) 25.09.2016, Shift-I
Ans. (a) : Over modulation of transmitter signal is
corrected by the adjustment of the speech amplifier.
89. A broadcast AM radio transmitter radiates 125
kW when the modulation percentage is 70.
How much of this is carrier power?
(a) ≈ 25 kW (b) ≈ 50 kW
(c) ≈ 75 kW (d) ≈ 100 kW
ESE-2005
Ans. (d) : We know that-
Merit of AM detector -  µ2 
Total transmitted power Pt = Pc 1 + 
(i) High power Handling capacity  2 
(ii) Less distortion 
86. A transmitter puts out a total power of 2.09 Where, µ = Modulation index
Watts of 30% AM signal. How much power is Pc = Carrier power
contained in each of the sidebands? Pt = 125 kw, µ = 0.7, Pc = ?
(a) 2.09 watts (b) 2 Watts
 ( 0.7 )2 
(c) 0.09 Watts (d) 0.045 Watts
125 = Pc 1 + 
BSNL TTA (JE) 25.09.2016, Shift-I  2 
Ans. (d) Given,  
m = 0.30  0.49 
Pt = 2.09 watt 125 = PC  1 + 
 2 
 m  2
2.49
Pt = Pc  1 +  125 = PC
 2  2
 0.09  125 × 2
2.09 = Pc  1 +  PC = kW
 2  2.49
Pc = 100.40
 2.09 
2.09 = Pc   Pc ≃ 100 kW
 2 
Electronics-II 942 YCT
90. MODEM can be classified as equipment of Ans. : (b) Advantage of a fiber optic link over a
(a) DCE (data MB_Communication equipment) conventional copper wire link:
(b) DTE (DATA terminal equipment) • Greater Bandwidth
(c) both • Faster speed
(d) None of these • Better reliability
BSNL TTA (JE) 25.09.2016, Shift-I • Immune to cross link.
Ans. (a) : MODEM can be classified as equipment of 95. In a frequency modulated (FM) system, when
DCE (Data MB-Communication equipment) the audio frequency is 500 Hz and audio
91. The four basic elements in a PLL are loop frequency voltage is 2.4 V, the frequency
filter, loop amplifier, VCO and deviation δ is 4.8 kHz. If the audio frequency
(a) Up converter (b) Down converter voltage is now increased to 7.2 V then what is
(c) Phase detector (d) Frequency multiplier the new value of deviation?
ESE-2016 (a) 0.6 kHz (b) 3.6 kHz
Ans. (c) : The four basic elements in a PLL are loop (c) 12.4 kHz (d) 14.4 kHz
filter, loop amplifier, VCO and phase detector. ESE-2016
92. The Q of a radio coil Ans. (d) :We know that
(a) is independent of frequency ∆f ∝ V
(b) increases monotonically as frequency Then,
increases ∆f 2 V2 δ 2
(c) decreases monotonically as frequency = =
∆f1 V1 δ1
increases
(d) increases up to a certain frequency and Given that
decreases beyond that frequency δ1 = 4.8 kHz
BSNL TTA (JE) 25.09.2016, Shift-I V1 = 2.4 V
Ans. (d) : The Q of a radio coil increases up to a V2 = 7.2 V
certain frequency and decreases beyond that frequency, 7.2
So, δ 2 = × 4.8 = 14.4 kHz
the bandwidth of the tuned circuit filter decreases. 2.4
93. For a given AM broadcast station transmits an 96. The IF amplifier in a super heterodyne
average carrier power output of 40 kW and receiver is
uses a modulation index of 0.707 for sine wave (a) Single-stage single tuned amplifier
modulation. What is the maximum (peak) (b) Two stages of single tuned amplifier
amplitude of the output if the antenna is (c) double-tuned amplifier
represented by a 50 Ω resistive load? (d) Class-C amplifier
(a) 50 kV (b) 50 V BSNL TTA (JE) 2013
(c) 3.414 kV (d) 28.28V Ans. : (b) IF amplifier in a super heterodyne receiver is
ESE-2005 two stages of single tuned amplifier.
Ans. (c) : Given R = 50 Ω 97. Which one of the following statement is
µ = 0.707 correct?
Pc = 40 × 103 W The threshold effect in demodulators is
According to given formula (a) Exhibited by all receivers when the input
SNR is low
A2
Pc = c (b) Exhibited only by correlation receivers
2R (c) The rapid fall in the output SNR when input
A c2 = 2 × 50 × 40 SNR falls below a particular value
Αc = 2 × 103 V = 2 kV (d) The exponential rise in the output SNR when
input SNR is increased above a particular
mp = µAc = (0.707) × 2×103 = 1.414 kV
value
∴ Peak amplitude of the output ESE-2009
= Ac + mp = 2 + 1.414 = 3.414 kV
Ans. (c) : The threshold relates to the quality (signal to
94. Which of the following are the advantages of a noise ratio) of the demodulator output as a function of
fiber optic link over a conventional copper wire
the quality of the received signal (demodulator input).
link?
Below threshold quality of the input, the output quality
1. A fiber optic link has greater bandwidth
deteriorates rapidly.
2. A fiber optic link has lower cost.
3. A fiber optic link is immune to cross link 98. A system has a receiver noise resistance of
4. A fiber optic link is easy to split. 100Ω. It is connected to an antenna with an
Select the correct answer using the code given input resistance of 50 Ω. The noise figure of the
below: system is-
(a) 1 and 2 (b) 1 and 3 (a) 1 (b) 2
(c) 2 and 3 (d) 1 and 4 (c) 3 (d) 50
BSNL TTA (JE) 2013 BSNL TTA (JE) 2013
Electronics-II 943 YCT
 R eq 103. The original spectrum of a message contains
Ans. : (c) Noise figure = 1 + 100 Hz, 200 Hz frequency components. It is
R antenna amplitude modulated by a carrier of 0.9 kHz.
100 Which frequency components are contained in
= 1+
50 the amplitude modulated signal spectrum?
=3 (a) 900, 1000 and 1100 Hz
99. A DSB-SC signal is generated using the carrier (b) 700, 800 and 900 Hz
signal cos (ωct + θ) and modulating signal m(t). (c) 700, 800, 900, 1000 and 1100 Hz
What is the envelope detector output of this (d) 100, 200 and 900 Hz
DSB-SC signal? ESE-2006
(a) m(t) cosθ (b) | m(t)| Ans. (c) :By AM output frequency spectrum we get
(c) m(t) tanθ (d) m(t) sinθ three frequency i.e. fc, fc+fm and fc–fm.
ESE-2006
Ans. (b) : A DSB-SC signal will be,
S(t) = m(t) cos(ωct + θ)
Where, m(t) → envelope of SDSB(t)
So, at the output of envelope detector = | m(t) |
100. The correct sequence of subsystems in an FM
receiver is If fm1 and fm2 are two frequencies of AM then output
(a) mixer, RF amplifier, Limiter, IF amplifier, frequencies will be fc, fc+fm1, fc+fm2.
discriminator, audio amplifier. Fc–fm1 and fc–fm2
(b) RF amplifier, mixer, IF amplifier, limiter, Given that
discriminator, audio amplifier. fc = 0.9 kHz = 900 Hz, fm1 = 100Hz, fm2 = 200 Hz
(c) RF amplifier, mixer, limiter, discriminator, IF Now, output frequency are 700Hz, 800Hz, 900Hz, 1000
amplifier, audio amplifier Hz, 1100Hz.
(d) mixer, IF amplifier, limiter, audio amplifier, 104. Fading is
discriminator (a) Change in polarization only at receiver end
BSNL TTA (JE) 2013 (b) Change in frequency only at receiver end
Ans. : (b) Correct sequence of subsystem in an FM (c) Fluctuation in signal strength at receiver
receiver is- (d) Change in phase only at receiver end
RF amplifier, mixer, IF amplifier, limiter, discriminator, BSNL TTA (JE) 2013
audio amplifier. Ans. : (c) Fading refers to the attenuation of the
101. If the turn on and turn off energy losses in a transmitted signal. Fading is the fluctuation in signal
transmitter are 51 mJ and 76.8 mJ respectively strength at receiver end.
and the mean power loss is limited to 200 W, 105. Carson's rule is (with symbols having their
what is the maximum switching rate that can standard meaning)
be achieved? (a) B = 2 DW (b) B = 2 (D+1) W
(a) 15649 cycles/s (b) 156.49 cycles/s (c) B = 2 (D + 1)W (d) B = 2DW
(c) 1564.9 cycles/s (d) 15.649 cycles/s
ESE-2009 ESE-2016
Ans. (c) : Given that turn on and turn off energy losses Ans. (b) : Bandwidth = 2 ( )m
β + 1 f
are E = (51+76.8) mJ If we consider D = modulation index
= ( 51 + 76.8 ) × 10−3 J and W = modulating signal
Mean power loss P = 200W Then B = 2(D+1)W
200 106. An analog signal has significant spectral
Then frequency = components from 1 kHz to 5 kHz. What is the
( 51 + 76.8 ) × 10−3 Nyquist sampling rate for this signal?
= 1564.9 cycles / sec (a) 5 k samples/s (b) 4 k samples/s
(c) 8 k samples/s (d) 10 k samples/s
102. In a super heterodyne receiver, the IF is 550
BSNL TTA (JE) 2013
KHz, if it is tuned to 1210 KHz, the image
frequency will be- Ans. : (d) Nyquist sampling rate ( f N ) ≥ 2fS
(a) 2970 KHz (b) 660 KHz fN → Maximum frequency of measured signal
(c) 2310 KHz (d) 1210 KHz given,
BSNL TTA (JE) 2013 fS ≥ 5kHz
Ans. : (c) Image frequency = fs + 2fIF f N ≥ 2 × 5k
= 1210+2×(550)
f N ≥ 10kHz
= 1210+1100
= 2310 kHz f N ≥ 10k samples/s

Electronics-II 944 YCT

107. All types of linear modulation can be detected by 110. The disadvantage of FM over AM is that
(a) Product demodulator (b) Envelope detector (a) Noise is very high
(c) Filtering (d) Linear detector (b) Larger bandwidth required
ESE-2012 (c) High output power required
Ans. (a) : Product demodulator- The product (d) High modulating power required
demodulator can decode over modulated AM and AM BSNL TTA (JE) 14.07.2013
with suppressed carrier. A signal demodulated with a Ans. : (b) The main disadvantage of FM over AM is
product detect will have a higher signal to noise ratio that in frequency modulation large bandwidth is
then the same signal demodulated with an envelope required.
detector. By product demodulator we can be detect the Bandwidth of FM = 2 ( ∆f + f m )
all types of linear modulation.
111. One of the main functions of RF stage amplifier
in Super heterodyne Radio Receiver is to
(a) Provide improve tracking.
(b) Permit better adjacent channel rejection.
(c) Increase tuning range of the receiver.
(d) Improve rejection of image frequency.
ESE-2012
Ans. (d) : RF Amplifier Stage = The RF amplifier
108. An audio signal 15 sin 2π 1000 t amplitude stage. Uses a tuned parallel circuit L1C1 with a variable
modulates 60 sin 2π 106t. The modulation index capacitor C1. The ratio waves from varies broadcasting
will be stations are intercepted by the receiving aerial and are
(a) 20% (b) 25% coupled to this stage. This stage selects the desired radio
(c) 50% (d) 100% wave and raises the strength of the wave to the desired
BSNL TTA (JE) 14.07.2013 level.
Ans. : (b) Given, • One of the main function of the RF amplifier in a
Vm = 15 sin 2π 1000 t super-heterodyne receiver is to have sufficient
bandwidth for the rejection of the image frequency.
V = 60 sin 2π 106 t
c 112. What is the power contained in SSB
Vm = A m sin ( 2πf m t ) transmission when the carrier power is 1 kW
and the modulation index is 0.3?
Vc = A c sin ( 2πf c t ) (a) 22.5 W (b) 90 W
After comparing (c) 300 W (d) 1 kW
Am = 15, Ac = 60 ESE-2007
Am Ans. (a) : We know that,
Modulation Index ( m ) = Power contained in SSB
Ac
15 µ2
= = 0.25 × 100 = 25% PSSB = PC ×
60 4
Here, Pc = carrier power
109. If two signals modulated the same carrier with
different modulation depths of 0.3 and 0.9, the µ = Modulation index
( 0.3)
2
resulting modulation signal will
(a) Be over-modulated PSSB = 1000 × = 22.5W
(b) Have the resultant modulation limited to 1.0 4
(c) Have the resultant modulation index around 113. The details of channels in ISDN BRI is
0.82 (a) 30B + D (b) 2B + D
(d) Have the resultant modulation index around (c) 10B +D (d) 31B + D
0.95 BSNL TTA (JE) 14.07.2013
ESE-2006 Ans. : (b) The details of channels of ISDN BRI is 2B +
Ans. (d) : Given modulation depths- m a = 0.3 D. BRI stands for Basic Rate Interface and ISDN stands
1 for Integrate Services digital Network.
and m a 2 = 0.9 114. In Klystron, the velocity modulation takes
place in
m = ma21 + m a22 (a) Input cavity resonator
∵ 0 < m <1, (b) Drift tube
(c) Output cavity resonator
m = ( 0.3) + ( 0.9 )
2 2 (d) Collector
BSNL TTA (JE) 14.07.2013
= 0.948 Ans. : (a) In klystron, the velocity modulation takes
m ≃ 0.95 place in input cavity resonator. Klystron is a microwave
device that works on principle of velocity modulation in
The signal is not critically or over modulated. addition to current modulation.

Electronics-II 945 YCT

115. For which of the following system, the signal to Ans. (d) Pulse code modulation have inherent most
noise ratio is the highest? noise resistant. For linear quantization, quantization
(a) PAM (b) PWM error is again feed in the signal. This is called
(c) PPM (d) PAM & PWM quantization error and it represented by ε.
ESE-2011 119. A carrier is amplitude modulated by a 4 signals
Ans. (c) : Merits of PPM: In PPM, the width (i.e. of frequency 10 kHz, 15 kHz, 20 kHz and 25
duration) of each pulse is the same, so the transmitter kHz. What is the bandwidth of the modulated
power remain constant. The amplitude of the pulse is signal?
also constant, hence it is not affected by noise. (a) 25 kHz (b) 50 kHz
116. What is the percentage power saving when the (c) 70 kHz (d) 140 kHz
carrier and one of the sidebands are suppress ESE-2007
in an AM wave modulated to a depth of 50%? Ans. (b) : We know that,
(a) 66.6% (b) 50% Bandwidth = 2× fmax
(c) 33.3% (d) 94.4% fmax= maximum frequency
BSNL TTA (JE) 27.09.2016, 10 AM = 2×25
Ans. (d) Given, m = 50% = 0.5 = 50 kHz
 m2  120. If the lower sideband overlaps the basebands,
Pt = Pc  1 +  the distortion is called:
 2 
 (a) Cross-Over distortion
(b) Aliasing
 ( 0.5)2 
When, Pt = Pc  1 +  (c) Cross-talk
 2  (d) None of these
  BSNL TTA (JE) 27.09.2016, 10 AM
= 1.125 PC Ans. (b) If lower side band overlapped on baseband
( 0.5 )2 signal, then it produce distortion, and this distortion is
PSB = PC = 0.0625PC called aliasing.
4
1.125 − 0.0625 121. The ring modulator is generally used for
%Power Saving = ×100 generating:
1.125 (a) SSB/SC signal (b) ISI signal
1.0625 (c) wideband signal (d) DSB/SC signal
= × 100 = 94.4%
1.125 BSNL TTA (JE) 27.09.2016, 10 AM
117. For the A 3000 Hz bandwidth channel has a Ans. (d) Ring modulator, generally used is double side
capacity of 30 kbps. The signal-to-noise ratio of band suppressed carrier. In DSB/SC an broadcast system,
the channel is both sideband is transmitted with corner this is called
(a) 20 dB (b) 25 dB double sideband system. If corner is not transmitted in an
(c) 30 dB (d) 40 dB system then it is called DSB-SC system.
ESE-2010 DSB-SC ⇒ Double sideband suppressed carrier .
 S 122. A duplexer is used to:
Ans. (c) : Channel capacity (C) = Blog 2 1 +  (a) couple two antennas to a transmitter
 N (b) isolate the antenna from the local oscillator
Given that, (c) prevent interference between two antennas
B = 3000Hz connected to receiver
C = 30 kbp (d) uses same antenna for reception and
 S transmission without interference
30 × 103 = 3 × 103 log 2 1 +  BSNL TTA (JE) 27.09.2016, 10 AM
 N
Ans. (d) A duplexer is used to uses same antenna for
 S
2 = log 2  1 + 
10
reception and transmission without mutual interference.
 N Radio channel and satellite channel are wave
S transmitted channel, thus it channel transmitted
= 1024–1 = 1023 information is digital form, for this work digital
N
S modulator used.
in dB = 10log10 1023 = 30.09 dB 123. Consider the following statements about analog
N
≃ 30dB communication and multiplexing:
1. Noise problem for analog communication has
118. The modulation inherently most noise resistant the greatest effect on TDM system.
is: 2. Noise problem for analog communication has
(a) SSB suppressed carrier the least effect on SDM system.
(b) frequency modulation Which of these statements is/are correct?
(c) pulse position modulation (a) 1 only (b) 2 only
(d) pulse code modulation (c) Both 1 and 2 (d) Neither 1 nor 2
BSNL TTA (JE) 27.09.2016, 10 AM ESE-2008
Electronics-II 946 YCT
Ans. (c) : The desired signal is pressed for a small time (c) redundancy is essential
period in TDM system so, there is highest noise effect (d) only binary code may be used
chance in it. If noise corrupts the signal there is not BSNL TTA (JE) 27.09.2016, 10 AM
chance to recover it. Ans. (a) According to Hartley rule the maximum rate of
There are noise in SDM (Space Division Multiplexing ) information transmission depends on the channel
system only one or few users in most cases, because it bandwidth.
has separate link for each user. User can check receiver C = Blog 2 (1 + S / N )
value several times and take average value and reduced
Where, C = Capacity (in bit/s)
the effect of noise.
B = Bandwidth of channel (Hz)
124. AGC voltage is applied to the stages which S = Signal power (in W)
are_____: N = Noise power (in W)
(a) before the detector stage
127. The type of noise reduced by limiters in FM
(b) after the detector stage
(c) either before or after the detector stage receivers is
(a) Avalanche noise
(d) none of these
(b) Burst noise
BSNL TTA (JE) 27.09.2016, 10 AM
(c) Narrow band-pass noise
Ans. (a) AGC voltage is applied to the stage which are (d) Impulse noise
before the detector stage. ESE-2012
AGC (Automatic Gain Control)
Ans. (d) : Impulse noise are short lived but they can
AGC is a close loop feedback regulating circuit.
cause permanent damage.
Application of AGC is maintain a suitable signal
Limiter circuit is used in FM receiver to remove the
amplitude at its output despite variation of the signal
noise present in the peaks of the received signal and to
amplitude at the input.
remove any amplitude variation in the received signal.
The output of the limiter has constant amplitude.
128. VLF waves are used for some types of services
because:
(a) of the low power required
(b) they are very reliable
(c) the transmitting antennas are of convenient
size
(d) interleaves pulses belonging to different
transmission
125. Si and S0 denote the signal at input and output BSNL TTA (JE) 27.09.2016, 10 AM
of a linear network Ni and N0 are the Ans. (b) VLF (Very low frequency) waves are very
corresponding noises. Which one of the reliable and generally used for military communication
following is the correct expression for noises and submarines & the range of VLF is 3 to 30 kHz
figure of the network? Wavelength range = 10-100 km.
SiS0 SN 129. A microphone with inbuilt amplifier has an
(a) (b) i i
Ni N0 S0 N 0 output noise level in a very quit room of about
SN S N 30 µVrms. the maximum output level is about
(c) i 0 (d) 0 0 300 mVrms before severe distortion occurs.
S0 N i Si N i
What dynamic range does this represent in dB?
ESE-2004 (a) 4 dB (b) 36 dB
Ans. (c) : Noise figure is defined as input signal to (c) 40 dB (d) 80 dB
noise ratio (SNR)i and output signal to noise ratio ESE-2005
(SNR)0. Ans. (d) : Ouput dynamic range of amplifier is the
(SNR )Input range between the smallest and largest useful output
Noise figure =
( SNR )output levels.
Here given that
Si / N i Vmin = 30 µVrms = 30×10–6V
=
So / N o and Vmax = 300mVrms = 300 × 10 −3 V
SN
= i o V 
So N i ∴ Dynamic range = 20log  max 
 Vmin 
126. The Hartley law states that______:
(a) the maximum rate of information  300 × 10−3 
= 20log  −6 
transmission depends on the channel  30 × 10 
bandwidth
= 20log104
(b) the maximum rate of information depends on
the depth of modulation = 80 dB

Electronics-II 947 YCT

130. For ___________, the frequency range is Ans. (b) A voltage controlled oscillator (VCO) is an
limited to a maximum of about 5 kHz. electronic oscillator whose oscillation frequency is
(a) carbon microphones controlled by a voltage input
(b) piezoelectric microphones VCO is used from frequency modulation or phase
(c) capacitive microphones modulation by applying of modulating signal to the
(d) dynamic microphones controlled input.
UPPCL JE- 07.09.2021, Shift-II VCO is a important part a phase locked loop (PLL)
Ans. (a) : The frequency range of carbon microphones VCO is used for FM signal generation.
is used upto 5 kHz. It is defined as the interval between 135. For an AM signal, the bandwidth is 10 kHz and
its upper limiting frequency and its lower limiting the highest frequency component present is 705
frequency. kHz. What is the carrier frequency used for
Specification of carbon microphones- this AM signal?
Size - Small (a) 695 kHz (b) 700 kHz
Cost - Cheapest (c) 705 kHz (d) 710 kHz
Frequency range → 2 kHz – 5 kHz. ESE-2008, 2003
Distortion → Highest 10% Ans. (b) : Frequency spectrum of AM :-
Noise → Highest
Application → Cheap radio set, telephones.
131. The following is analog media:
(a) EM (b) cable PCM
(c) OFC system (d) digital micro-wave
BSNL TTA (JE) 27.09.2016, 10 AM
Ans. (a) EM or electro-magnetic waves are accepted to
be of analogous nature by virtue of their continuous or
repeating sine wave expression. A EM waves are
analog, meaning they are continuous signals capable of
smooth fluctuation.
132. In an AM system, for satisfactory operation,
carrier frequency must be N times the
bandwidth of message-signal. What is the value
of N? Given,
(a) > 2 (b) > 5 Bandwidth = 10 kHz
(c) > 10 (d) > 50 Highest frequency component = 70 kHz
ESE-2008 We know Bandwidth = 2 fm
Ans. (d) : In an AM system, ideally carrier frequency 10 = 2 fm
must be greater than 50 times the bandwidth of fm = 5 kHz
message-signal for satisfactory operation. Highest frequency component = fc + fm
133. Phase Modulation is generally not used for 705 = fc + 5
transmission because: Carrier frequency fc = 700 kHz
(a) It needs higher power 136. A communication channel with additive white
(b) It needs large Antenna size Gaussian noise, has bandwidth of 4kHz and
(c) It is complex for decoding SNR of 15. Its channel capacity is:
(d) It does not carry much information (a) 1.6 kbps (b) 16 kbps
BSNL TTA (JE) 27.09.2016, 10 AM (c) 32 kbps (d) 256 kbps
Ans. (c) Phase modulation technique generally not used BSNL TTA (JE) 27.09.2016, 10 AM
for transmission because its demodulation is very Ans. (b) Given that,
complex. Bandwidth = 4 kHz
e = E 0 sin ( ωc t + ∆φ sin ωm t ) SNR = 15
β = ∆φ = K p A m Channel capacity ( C ) = Blog 2 (1 + SNR )

∆f = ∆φf m = 4 × 103 log 2 (1 + 15 )

β = modulation index = 4 × 103 × 4 = 16000 = 16kbps

∆φ = phase deviation 137. In a super-heterodyne receiver, the frequency
134. Voltage Controlled Oscillator is used for: of local oscillator is
(a) Decoding FM Signal (a) Half that of incoming signal.
(b) Generating FM Signal (b) Slightly less than that of incoming signal.
(c) Decoding AM Signal (c) Higher than that of incoming signal.
(d) Generating AM Signal (d) Equal to that of incoming signal.
BSNL TTA (JE) 27.09.2016, 10 AM ESE-2012
Electronics-II 948 YCT
Ans. (c) : Super-Heterodyne Receiver : 140. The percentage power saving for Carrier of
fully modulated AM is suppressed before
transmission,
(a) 75% (b) 67%
(c) 11% (d) 200%
Nagaland PSC CTSE (Diploma) 2017, Paper-I
Image frequencies can be eliminated by sufficient Ans. (b) : For a fully modulated A.M. µ = 1
attenuation by super-heterodyne receiver. Local Pt  µ 2 
oscillator frequency is greater than signal frequency. = 1 + 
Pc  2 
fo > fi
Pt  1 
fo = oscillator frequency = 1 + 
Pc  2 
fi = signal frequency
Pt = 1.5 Pc
138. The total power in Amplitude Modulated signal P − Pc
if the carrier of an AM transmitter is 600 W change in carrier signal = t × 100
and it is 50% modulated Pt
(a) 300 W (b) 30000 W 1.5 − 1
= × 100
(c) 675 W (d) 1200 W 1.5
Nagaland PSC CTSE (Diploma) 2017, Paper-I = 33.3%
Ans. (c) : Given PC = 600 W Hence power saving = 100% – 33.3%
1 = 67.7%
m = 50% = 141. For a non-uniform quantizer more quantizing
2 steps are used for signals of
Total power in amplitude modulated signal- (a) Low frequency (b) High amplitude
 m2  (c) Low amplitude (d) High frequency
Pt = Pc 1 +  ESE-2010
 2 
Ans. (b) : We know that,

( )  ( step size )
2 2
1
 2  Quantization noise power =
= 600 1 +
2 
12
 Where amplitude of signal is large, the signal power is
  more.
 1  600 × 9 Hence, more quantization steps are used for signals of
= 600 1 +  =
 8 8 high amplitude in non-uniform quantization.
142. In FM modulating voltage remains constant
Pt = 675 W
when the modulating frequency is 2 times and
139. The antenna current of an A.M. transmitter is the modulation index
8 A when only carrier is sent, but it increases to (a) Doubled (b) Same
8.93 A when the carrier is modulated. Then (c) Half (d) zero.
what is the percentage modulation of the wave? Nagaland PSC CTSE (Diploma) 2017, Paper-I
(a) 43.00% (b) 70.14% Ans. (c) : As we know that modulation index in
(c) 75.00% (d) 100.00% frequency modulation is –
∆f
ESE-2009 mf =
Ans. (b) : Total transmitted current in AM 2f m
Since voltage remain constant then frequency deviation
µ2
I T= I c 1 + here, Ic = carrier current ‘δ’ is also remain constant, and modulating frequency
2 become 2 times then,
µ = modulation index ∆f
m′f =
given, IT = 8.93 A, 2f m
IC = 8 A µ=?
1
µ2 m′f = m f
8.93 = 8 1 + 2
2 143. In a radio receiver, AGC works by
2
 8.93  µ2 (a) Turning the local oscillator
 8  = 1+ 2 (b) Turning off the audio section in the absence
 
of a received signal
µ2 = 0.2459×2 (c) Adjusting the gain of RF and IF amplifiers
µ = 0.4917 = 0.7012 (d) Limiting the signal level using a clipper in the
Hence, the percentage of modulation index ≃ 70.12% audio section
ESE-2014
Electronics-II 949 YCT
Ans. (c) : Automatic gain control (AGC) or automatic 147. A scheme in which several channels are
volume control (AVC) is a circuit design which interleaved and then transmitted together is
maintains the same level of amplification for sound or known as
radio frequency. (a) Frequency division multiplexing
It increases or decreases the signal strength level (b) Time division multiplexing
according to requirement. (c) A group
144. Which one of the following is considered as an (d) A super group
A.M. signal? ESE-2014
(a) Binary phase shift keying (BPSK) Ans. (a) : In FDM each signal is transmitted with the
(b) Differential phase shift keying (DPSK) technique that several channels are interleaved and
(c) Differential encoded PSK modulated to different carrier frequency.
(d) Quadrature PSK 148. A carrier is modulated by two modulating
ESE-2009 waves A and B having modulation indices of
Ans. (d) : Quadrature phase shift keying is considered 0.6 and 0.8 respectively. The overall
as an AM signal. Quadrature amplitude modulation modulation index is-
utilizes both amplitude and phase components to (a) 1 (b) 0.7
provide a form of modulation that is able to provide (c) 0.2 (d) 1.4
high levels of spectrum usage efficiency. BSNL TTA 26.09.2016, 10 AM
145. If the radiated power of AM transmitter is 10 Ans. (a) : Given that, m1 = 0.6, m2 = 0.8
kW, the power in the carrier for modulation
index of 0.6 is nearly- Overall modulation index ( m ) = m12 + m 22
(a) 8.24 kW (b) 8.47 kW
( 0.6 ) + ( 0.8 )
2 2
(c) 9.26 kW (d) 9.6 kW =
BSNL TTA 26.09.2016, 10 AM
BSNL TTA JE 2013 = 0.36 + 0.64
Ans. (b) : Given that, = 1.00
Transmitted power (Pt) = 10kW= 10×103W =1
Carrier power (Pc) = ? 149. How much power will an AM transmitter,
Modulation index (µ)= 0.6 rated at 50 kW radiate if it is modulated to
 µ2  100%?
∵ Pt = Pc 1 +  (a) 25 kW (b) 50 kW
 2  (c) 75 kW (d) 100 kW
 ( ) 
2
0.6 ESE2009
10 × 103 = Pc  1 +  Ans. (c) : The rated power is equal to the power
 2 
 transmitted for transmitting unmodulated carrier.
 0.36  Given that,
10 × 103 = Pc 1 +  Carrier power PC = 50 kW
 2 
Then,
10 × 10 = 1.18Pc
3
 µ2 
Pc =
10 × 103 PT = PC  1 +  {∵ µ = 1}
 2 
1.18
Pc = 8.47 kW  1
= 50  1 + 
146. An AM modulator has output  2
S(t) = 20cos(300πt) + 6cos(332πt) + 6cos(280πt)
3
Then what is the modulation index of the wave? = 50   = 75kW
(a) More than 100% (b) 0.93 2
(c) 0.3 (d) 0.6 150. The difference between phase and frequency
ESE-2009 modulation-
Ans. (d) :As we know equation of AM signal (a) Is purely theoretical because they are same in
1 practice
S ( t ) = A C cos 2πf c t + µA C cos ( f c + f m ) t  (b) Is too great to make the two systems
Carrier 2
USB compatible
1 (c) Lies in the poorer audio response to phase
+ µA C cos ( f c − f m ) t  modulation
2 (d) Lies in the definitions of the modulation index
LSB BSNL TTA 26.09.2016, 10 AM
By comparing with given equation we get,
1 Ans. (a) : Frequency modulation (FM) and phase
µA C = 6 and AC = 20 modulation (PM) have much in common and they are
2 usually concluded as angle modulation i.e. it is
1 impossible to tell them a part without knowledge about
So, µ × 20 = 6
2 the modulation function. Thus we can say that
Modulation index µ = 0.6 practically they are same but theoretically they differ.

Electronics-II 950 YCT

151. Which one of the following is a disadvantage of Ans. (b) : As we know that, in FM-
digital transmission as compared to analog m p = k p A m = ∆P
transmission?
k f A m ∆f
(a) Digital signals cannot be multiplexed mf = =
efficiently fm fm
(b) Digital transmission is less immune to 1
channel noise mf ∝
fm
(c) Digital signals needs to be coded before
transmission mf= modulation index
(d) Digital transmission needs more bandwidth fm= modulating frequency
ESE-2009 So, when the modulation frequency is doubled, the
modulation index is halved and the modulation voltage
Ans. (d) : Digital transmission needs more bandwidth
remains constant in FM compare to PM.
as compared to Analog transmission. Apart from it
digital signal transmission develops quantization and 155. What are the three steps in generating PCM in
round off errors systems and processing is more the correct sequence?
(a) Sampling, quantizing and encoding
complex.
(b) Encoding, sampling and quantizing
152. To connect the output of a data source to a (c) Sampling, encoding and quantizing
telephone line, it is necessary to have –––––––– (d) Quantizing, sampling and encoding
(a) An FMVFT system (b) Modem ESE-2008
(c) A leased line (d) Phase shift key
Ans. (a) : There main sequence in PCM are given
BSNL TTA 26.09.2016, 10 AM
below-
Ans. (a) : To connect the output of a data source to a (1) Sampling – We sample the analog signal at a rate ≥
telephone line, it is necessary to have an FMVFT Nyquist rate.
(Frequency Modulation Voice Frequency Telegraph) then,
system. (2) Quantizing- Quantize the message signal using
Modem-It is the compressed form of modulation and quantizer.
demodulation. then,
153. For which one of the following modulated (3) Encoding – Encode the quantized values using
signals, the original message, up to a scaling encoder.
factor can be recovered using envelope 156. Image signal frequency in a superheterodyne
detection? receiver is given by-
(a) 20 cos(200πt) + 30 m(t) cos(200 πt) (a) fs + fi (b) fs + 2fi
(b) 20 cos(200πt) + 16 m(t) cos(200 πt) (c) fs – fi (d) fs – 2fi
(c) 10 m(t) cos(400 πt) BSNL TTA 26.09.2016, 10 AM
(d) 10 cos m(t) cos(400 πt) Ans. (b) : Image frequency, fsi = fs +2fi
ESE-2009 Local oscillator frequency, fLO = fs + fi
Ans. (b) : We know, the standard equation of AM Where,
signal is fi = input frequency
S ( t ) = A C 1 + k a m ( t )  cos ( 2πf c t ) fs = tuned frequency or signal frequency.
157. What is the assigned bandwidth of each of the
for envelope detector,
channels in the AM broadcast band?
Kam (t) must be less than 1 (a) 5 kHz (b) 10 kHz
Kam (t) < 1 (c) 15 kHz (d) 200 kHz
from option (b), ESE-2010
S(t) = 20 (cos (200 πt) + 16 m(t) cos (200 πt) Ans. (b) : The AM carrier frequencies are in the
= 20 cos (200 πt) [1 + 0.8 m(t) ] frequency range 535-1605 kHz. Carrier frequencies of
here, 0.8 m(t) <1 540 to 1600 KHz are assigned at 10 kHz intervals. 10
So, from this modulation signal original message can be kHz channel BW is assigned for AM broadcast. The FM
recovered using envelope detector. radio band is from 88 to 108 MHz between VHF
154. Sine wave of frequency, fm modulates carrier of television channels 6 and 7.
frequency fc, producing the same frequency 158. A communication channel disturbed by
deviation and the same modulation index in additive white gaussian noise has a bandwidth
both FM and PM. Next if the modulation of 4kHz and SNR of 15. The highest
frequency is doubled, the modulation index in transmission rate that such channel can
FM relative to that in PM will be- support (in k-bits/sec) is-
(a) The same (b) Halved (a) 16 (b) 1.6
(c) Doubled (d) Quadrupled (c) 3.2 (d) 60
BSNL TTA 26.09.2016, 10 AM BSNL TTA 26.09.2016, 10 AM
Electronics-II 951 YCT
Ans. (a) : Given that, BW = 4 kHz, SNR = 15 163. A sinusoidal signal with a random phase is
As we know that, given by x(t)=A sin [π/2–(2πft +θ)] with the
 S probability density function
C = Blog 2  1 +  = 4 × 103 log 2 (1 + 15 )
 N pθ ( θ ) { 1/2π, 0 ≤ θ≤ 2π
0, Otherwise
= 4 × 103 log 2 16 What is the maximum amplitude of the
= 4 ×103 × log 2 2 4 autocorrelation function of this signal?
(a) A (b) A/2
= 16 × 103 ( ∵ log 2 2 = 1) (c) A2 (d) A2/2
C = 16k bit/sec. ESE-2006
159. In an FM system, if modulating voltage is Ans. (d) : Given,
constant and modulation frequency is lowered– x(t) = A sin [π/2 -2πft + θ]
(a) Relative amplitude of distant sidebands Autocorrelation function,
increases
(b) Relative amplitude of distant sidebands A2
R(τ) = cos 2πft × τ
decreases 2
(c) frequency deviation increases The maximum amplitude of the autocorrelation function
(d) frequency deviation decreases of this signal is A2/2
BSNL TTA 28.09.2016, 10 AM Autocorrelation function (ACF) defines how much a
Ans. (a) : In an FM system, if modulating voltage is signal is similar to a time shifted version of itself. ACF
constant and modulation frequency is lowered relative is independent of phase for sinusoidal wave.
amplitude of distant sidebands increases. Because the 164. The intermediate frequency of a
frequency of the carrier wave is changed according to superheterodyne receiver in 450 kHz, If it is
the instantaneous amplitude of the modulating signal. tuned to 1200 kHz, the image frequency will be
160. Which one of the following statements is -----------
correct? (a) 750 kHz (b) 900 kHz
Noise has the greatest effect in a (c) 1650 kHz (d) 2100 kHz
communication system when it interferes with BSNL TTA 28.09.2016, 10 AM
the signal Ans. (d) : Given, fi = 450 kHz
(a) In the transmitter (b) In the channel fs = 1200 kHz
(c) In the receiver (d) In the transducer
image frequency (fsi) = fs + 2fi
ESE-2005
where, fs = superheterodyne frequency
Ans. (b) :
fi = intermediate frequency
• Noise has the greatest effect in channel when it
interferes with the signal. fsi = 1200 + 2 × 450
• Noise is mainly produced by active and passive = 1200 + 900
elements in the circuit. It effect every frequency fsi = 2100 kHz
component of the information signal. 165. Which one of the following is the available
161. Which one of the following modulation noise power produced by a noisy resistor R,?
techniques has got maximum SNR? k = Boltzmann constant, T = Temperature and
(a) AM-SSB (b) AM-JSV B = Bandwidth
(c) FM (d) AM-SC (a) kTB (b) 4 kBT
ESE-2010 (c) 4 kBTR (d) 2 kBTR
Ans. (c) : Frequency modulation techniques has got SES-2006
maximum signal to noise Ratio (SNR). Ans. (a) : Thermal noise is caused by the thermal
162. The number of channels available in MF band agitation of electrons in resistances. If R is a noisy
(300 kHz - 3 MHz) for AM modulating signal resistor then mean square value fo thermal nosie voltage
of 20 kHz is is given by-
(a) 135 (b) 67 E 2 = 4RkBT
(c) 150 (d) 15 Where, R = Resistance
BSNL TTA 28.09.2016, 10 AM k = Boltzmann constant
Ans. (b) : Given, fm = 20 kHz T = Temperature
In MF band, frequency space available B = bandwidth
= 3000 − 300 = 2700 kHz Noise power can be given as-
when AM is used bandwidth of each channel
Then, B.W. = 2 × fm = 2 × 20 = 40 kHz E 2 4RkBT
= =
frequencyspace 4R 4R
Number of channel = = kBT
Bandwidth
2700 166. In radio receivers tube EM 84 is used as–––––
= = 67.5 (a) magic eye (b) full wave rectifier
40 (c) audio amplifier (d) none of these
Number of channel ≃ 67
BSNL TTA 28.09.2016, 10 AM
Electronics-II 952 YCT
Ans. (a) : In radio receivers tube EM 84 is used as Ans. (c) Multiplexing is the process of transmission of
magic eye. Technical literature called the magic eye information from more than one source in to a single
tube is an electron ray inductor, a vacuum tube that signal over a shared medium, we can be able to
provides visual indication of the amplitude of the multiplex analog or digital signal. If analog signals are
electronic signal. multiplexed then this type of multiplexer is called analog
167. When zero mean Gaussian noise of variance N multiplexer. If digital signals are multiplexed then this type
is applied to an ideal half-wave rectifier, what of multiplexer is called digital multiplexer. The advantage
is the mean square value of the rectified noise? of multiplexing is that we can transmit a large number of
(a) N/4 (b) N/2 signals to a single medium.
(c) N (d) 2 N 170. If two resistors of values R1 and R2 (at
ESE-2008 temperatures T1 and T2) are connected in series
Ans. (b) : We know that, to form a white noise source, the equivalent
Variance = N noise temperature is
N = E x2 – (E x )2 R T + R 2 T2 R T − R 2T2
(a) 1 1 (b) 1 1
For DC power, Ex = 0 R1 + R 2 R1 + R 2
So N = Ex2
R R
if it as cosine without generality loss (c) T1 + T2 (d) T1. 1 + T2 . 2
A 2C R2 R1
=N ESE-2008
2
Ans. (a) :
AC = 2N
By half wave rectifier we get rms value at output
rectification.
AC 2N N
= = ( rms value ) Thermal noise voltage of R1 can be given as-
2 2 2 V12 = 4R1T1kB
Hence,
and V22 = 4R 2 T2 kB
N
AC power P = (ACrms)2 = Equivalent noise voltage source-
2
Vn2 = V12 + V22
N
Mean quare value = AC power = 4kTB (R1+R2) = 4R1T1kB + 4R2T2kB
2
4kTB ( R1 + R 2 ) = 4kB ( R1T1 + R 2 T2 )
168. Diode demodulator will ignore
(a) The amplitude modulation R1T1 + R 2 T2
(b) The frequency modulation T=
R1 + R 2
(c) PCM
(d) PWM 171. Indicate the wrong statement regarding
ESE-2011 modulation-
(a) Ensure that intelligence is transmitted over
Ans. (b) : Diode Detector (Demodulator) - The diode
long distance
detector or demodulator is the simplest and most basic
(b) Separate differing transmission
form of amplitude modulation. It defects the envelopes
(c) Reduce the bandwidth use
of the amplitude modulated signal not the variation of
(d) Allows the use of practical antenna
frequency.
BSNL TTA 28.09.2016, 3 PM
So, Diode demodulator will ignore the frequency
modulation. Ans. (c) Modulation- It is the process of changing the
parameters of the carrier signal, in according with the
instantaneous values of the modulating signal.
Modulation is used to-
• Allow the use of practical antenna
• Separate differing transmission
• Increase in bandwidth use
• Ensure that intelligence is transmitted over long
distance.
Hence, the wrong statement regarding modulation is
reduce the bandwidth use.
172. Consider the following statements:
169. Signals from 4 channel sources are to be The thermal noise power generated by a
transmitted through a single transmission resistor is proportional to
channel. The circuit that can be used is - 1. The value of the resistor.
(a) Code converter (b) Decoder 2. The absolute temperature.
(c) Multiplexer (d) All of these 3. The bandwidth over which it is measured.
BSNL TTA 28.09.2016, 3 PM 4. The Boltzmann's constant.
Electronics-II 953 YCT
 Which of these statements is/are correct? that for 'phase-reversal' to exist in the DSB-SC
(a) 1, 2 and 3 (b) 2 only modulation waveform, the zero-crossing of the message
(c) 2 and 3 only (d) 2, 3 and 4 has to be accompanied by the zero-crossing of the
ESE-2009 carrier.
Ans. (d) : Johnson noise voltage can be given as, Consequently, the envelope of a DSB-SC modulated
E 2 = 4kBTR signal is different from the message signal.
and noise power can be given as-
E 2 4kBTR
= =
4R 4R
= kBT
Hence, thermal noise power is proportional to-
k= Boltzmann’s constant
B= Bandwidth 177. The modulation index of a phase modulated
T= Absolute temperature wave is–––––––––
173. Which one of the following modulation (a) Same as in frequency modulation
techniques has got maximum SNR? (b) Proportional to the modulating frequency
(a) AM-SSB (b) AM-DSB (c) Proportional to the reciprocal of modulating
(c) FM (d) AM-SC frequency
BSNL TTA 28.09.2016, 3 PM (d) Proportional to the phase of modulating
Ans. (c) In frequency modulation technique has got signal
maximum SNR because in FM we observe that BSNL TTA 28.09.2016, 3 PM
interference output is inversely proportional to carrier Ans. (a) The modulation index of a phase modulated
amplitude so the long carrier amplitude result-small wave is same as in frequency modulation.
interference in FM. Let, m(t) = Am sin (2πfmt)
174. In the frequency modulation if fm is modulating (i) For phase modulation-
frequency, ∆f is maximum frequency deviation θi (t) =2πfct + kpm(t)
and B is bandwidth, then
θi (t) =2πfct + kp Am sin (2πfmt)
(a) B = ∆f + fm (b) B = ∆f – fm
(c) B = 2(∆f + fm) (d) B = 2(∆f – fm) ∆θ = k p A m sin (2πf m t)
ESE-2001
∆θ |max = k p A m
Ans. (c) : Given that modulating frequency = fm
Maximum frequency deviation = ∆f 1 d θi (t)
Bandwidth = B fi (t) =
2π dt
Bandwidth of FM is given by- 1
Bandwidth = 2 ( ∆F + f m ) =  2πf c + k p A m 2πf m cos (2πf m t) 
2π 
 ∆f  fi(t)=fc+kp Amfm cos((2πfmt)
= 2 + 1 f m ∆f |max =  k p A m f m cos(2πf m t) 
f
 m  max
175. During amplitude modulation, the phase angle ∆f |max = k p A m f m
of the modulation voltage changes––––––––
(a) 45 degree (b) 180 degree ∆f k p A m f m
(c) 90 degree (d) zero degree Phase modulation index (mp)= =
fm fm
BSNL TTA 28.09.2016, 3 PM
mp = k p Am
Ans. (d) During modulation, the phase angle of the
modulation voltage changes 0o. The modulation of wave so, m p = ∆θ ........(i)
by varying its amplitude and carrier signal but
frequency and phase angle will remains constant used (ii) For frequency modulation-:
specially as a means of broadcasting an audio signal by m(t) = A m cos(2πf m t)
combining it with a radio carrier wave. fi (t)=fc+kf m(t)
176. In double sideband suppressed carrier fi (t) = fc + k f A m cos(2πf m t)
modulation, the modulated wave undergoes ∆f |max = k f A m
phase reversal, whenever
(a) Modulating signal's amplitude decreases. ∆f k f A m
mf = =
(b) Modulating signal's amplitude increases fm fm
(c) Modulating signal crosses zero.
k A
(d) Carrier signal crosses zero. mf = f m
ESE-2012 fm
Ans. (c) : The DSB-SC wave-form is always t

accompanied by a 'phase-reversal'. Whenever the

modulating signal goes through zero. We demonstrate 0
∫
θi (t) = 2π f i (t)dt

Electronics-II 954 YCT

 t 180. The wave form A cos(ω1t + k cosω2t) is
∫
= 2π [ fc + k f m(t)] dt
0
(a) Amplitude modulated
(b) Frequency modulated
t (c) Phase modulated

∫
= 2π [ f c + k f A m cos(2πf m t)] dt (d) Frequency as well as phase modulated
ESE-2002
0
2π k f A m Ans. (d) : A cos ( ω1t + k cos ω2 t ) is the general equation
= 2πfc t + sin(2πf m t) of frequency modulation and phase modulation both.
2πf m
(Angle modulation).
k A
θi (t) = 2πfc t + f m sin(2πf m t) In angle modulation frequency or phase of the carrier
fm varies according to the information signal.
kf Am 181. The signals contaminated with large noise are
∆θ |max =
fm demodulated by ––––––––––––
(a) Envelop detector
So, mf = ∆θ ……..(ii) (b) Synchronous detector
Hence, in both case mp= mf = ∆θ (c) Envelop detector followed by low pass filter
178. A communication channel is to receive signal (d) Envelop detector followed by high pass filter
power S and the noise at the receiver input is BSNL TTA 28.09.2016, 3 PM
additive thermal noise, with uniform power Ans. (b) Demodulation of DSBSC signal synchronous
spectral density (psd). It is found that if the detection clearly an envelope detector can not be used
bandwidth is 1 MHz, the channel capacity is 10 to demodulate the DSBSC signal, because its envelope
Mbps. What would be the channel capacity for is a distorted version of the modulating signal's wave
the same signal power and same noise psd, if the form. Instead, the technique of synchronous detection is
bandwidth is unlimited (tends to be infinite)? used.
(a) Zero (b) Infinite
(c) 15 Mbps (d) 1.5 Gbps 182. Bandwidth occupied by 100 MHz carrier, AM
ESE-2009 modulated by signal frequency of 10 kHz is
(a) 100 MHz (b) 20 kHz
Ans. (d) : Given that, Bandwidth (B) = 1 Mhz
channel capacity (C) = 10 Mbps (c) 10 kHz (d) 110 MHz
ESE-2012
 S
We know, channel capacity (C) = B log2 1 +  Ans. (b) : We know that,
 N Bandwidth of AM signal
if B increase then C increase, BW = 2fm
when B → ∞ S/N → 0 and C → ∞ = 2 × 10 kHz
signal power (S) → ∞ value = 1.44 S/η = 20 kHz
C = B log2 (1 + S/N) 183. The beat frequency between 1500 KHz and
10 × 106 = 106 log2 (1 + S/N)
1955 KHz will be –––––––
S/N ≃ 210 (a) 455 KHz (b) 100 KHz
η (c) 150 KHz (d) 195.5 KHz
Noise power (N) = × 2B = ηB BSNL TTA 28.09.2016, 3 PM
2
η Ams. (a) Given, f1 = 1500 KHz, f2 = 1955 KHz
= 106 × 210 (∴ signal power is fixed) ∵ Beat frequency ( f b ) = f 2 − f1
2
If B →∞ Where, f1 and f 2 two wave frequencies
S
C = 1.44 = 1.44 × 106 × 210 f b = 1955 − 1500
η
fb = 455 KHz
C = 1 .474 56 × 106 bps
C = 1.5 Gbps 184. Which one of the following is the correct
179. Which of the following circuits transmits two statement?
messages simultaneously in the direction ? Time division multiplexing
(a) Duplex (b) Simplex (a) Stacks several channels in adjacent frequency
(c) Quadruplex (d) Diplex slots
BSNL TTA 28.09.2016, 3 PM (b) Interleaves pulses belonging to different
ESE-2001 transmissions
Ans. (d) A circuit or device that supports simultaneous (c) Combines groups into a signal super group
transmission or reception of two independent signals. (d) Can be used with PCM only
Diplex communications technology is a simple form of ESE-2007
multiplexing that was considered quite revolutionary in Ans. (b) : TDM – Time division multiplexing method
the early days of telegraphy, when a diplex circuit is one in which multiple information signals are
would support transmission of two independent signals transmitted by a transmission channel on the basis of
in one direction only. time sharing without mutual interface.
Electronics-II 955 YCT
185. A trimmer is basically, a ––––––––– of the public switched telephone network. The main
(a) Insulator (b) Inductor feature of ISDN is that it can integrate speech and data
(c) Capacitor (d) Variable resistor on the same lines, which were not available in the
BSNL TTA 28.09.2016, 3 PM classic telephone system.
Ans. (c) A trimmer is basically a capacitor but in 190. RF carrier 10 kV at 1 MHz is amplitude
special cases it's behave like variable resistor (In case of modulated and modulating index is 0.6 peak
potentiometer) variable inductor (In case of superhet voltage of the signal is
radio receiver). It is also known as pre-set capacitor (a) 600 kV (b) 1200 kV
186. Let x(t) = 5 cos (50t + sin 5t). Its instantaneous (c) 6 kV (d) 10 kV
frequency (in rad/s) at t=0 has the value ESE-2013
(a) 5 (b) 50 Ans. (c) : Given that Ac = 10 kV, fc = 1 MHz, ma = 0.6
(c) 55 (d) 250 A
ESE-2002 ∴ ma = m
Ac
Ans. (c) : Given that,
∴ Am = maAc = 0.6 × 10 = 6 kV
x ( t ) = 5cos ( 50t + sin 5t )
191. In a certain parallel resonant band-pass filter,
Phase θ(t) = (50t + sin5t) the resonant frequency is 14 kHz. If the
Then instantaneous frequency = bandwidth is 4 kHz, the lower frequency-
dθ(t) d ( 50t + sin 5t ) (a) Is 12 kHz
ωi = = (b) Is 7 kHz
dt dt
(c) Is 10 kHz
ωi = 50 + 5cos5t
(d) Can not be determined
At t = 0 BSNL TTA 28.09.2016, 3 PM
ωi = 50 + 5 = 55 rad / sec Ans. (a) Given, fr = 14 kHz, B.W = 4 kHz
187. The total information transmitted is B.W.
proportional to–––––– ∵ fL = fr − here, fL = Lower frequency
2
(a) Bandwidth-time product fR = Resonance frequency
(b) Channel capacity B.W = Bandwidth
(c) Bandwidth-capacity product
4
(d) None of these f L = 14 −
BSNL TTA 28.09.2016, 3 PM 2
Ans. (a) The total information transmitted is f L = 12 kHz
proportional to bandwidth time product which is 192. An FM wave uses a 2-5 V, 500 Hz modulating
transmitted and the time which is available for the frequency and has a modulation index of 50.
transmission. It is Hartley’s work. The deviation is
188. If ACF denoted the autocorrelation function (a) 500 Hz (b) 100 Hz
and PSD denoted the power spectral density, (c) 1250 Hz (d) 25000 Hz
then for white noise, ACF is ESE-2002
(a) A Gaussian while PSD is uniform Ans. (d) : Given fm = 500Hz
(b) A delta function will PSD is uniform We know that, Modulation index -
(c) A delta function while PSD is exponential ∆f
(d) An exponential while PSD is uniform β =
ESE-2011 fm
Ans. (b) : For white noise PSD is a constant. or ∆f = β× f m = 50 × 500
∴Fourier transform of ACF is PSD and Fourier = 25000 Hz
transform of delta function is constant, So, ACF will be 193. A system has a receiver noise resistance of 50
a delta function. Ω. It is connected to an antenna with an output
The random process X(t) is called a white noise process resistance of 50 Ω. The noise figure of the
if- system is
N (a) 1 (b) 2
Sx(f) = 0 for all f. (c) 50 (d) 101
2
189. ISDN facility is available in following switching ESE-2013
technologies- Ans. (b) : Noise figure can be given as,
(a) E-10B (b) Cross-bar R eq
(c) Strowger (d) OCB Noise figure = 1 +
Rs
BSNL TTA 28.09.2016, 3 PM
Ans. (c) Integrated Services Digital Network (ISDN) Where, Req= Equivalent noise resistance
:- It is available for Strowger switching technology. Ra = Antenna resistance
These are set of communication standards for Then,
simultaneous digital transmission of voice, video, data, 50
Noise figure = 1 + =2
and other network services over the traditional circuits 50
Electronics-II 956 YCT
194. The speed of the modems could be increased Ans. (b) : Pre-emphasis circuit is used before the
from 9.6 kbps to higher by- modulation of information signal to equalize drive
(a) Increasing the compression rate power of transmitting signal in terms of deviation ratio.
(b) Using high class decoding It provides extra noise immunity by amplifying the
(c) Use of parity bits for error check higher audio frequencies.
(d) Simultaneous transmission of signals
BSNL TTA 28.09.2016, 3 PM 199. The speed at which serial data is transmitted is
Ans. (c) The speed of the modems could be increased referred to?
from 9.6 kbps to higher by use of parity bits for error (a) Bps (b) Baud rate
check. Modems and dial-up telephone lines are (c) Either (a) or (b) (d) None
commonly used when the connection is described as BSNL TTA 21.02.2016
"Causal" that is, it is used for very low volumes of Ans : (c) Baud rate is the speed of transferring data
information transfer and for just a few minutes at a from the transmitter to a receiver in the form of bits per
time. Usual speeds are now 9.6 kbps to 28.8 kbps. second. Baud rate is same as bits per second (Bps). In
195. A carrier wave of frequency 2.5 GHz amplitude serial data transmission send data to long distance
is modulated with two modulating frequencies quickly and reliable. In this standard data are sent over
equal to 1 kHz and 2 kHz. The modulated wave a single line from a transmitting device to a receiving
will have the total bandwidth device in bit serial format at a pre specified speed, and
(a) 6 kHz (b) 2 kHz also known as baud rate or number of bit sent per
(c) 4 kHz (d) 3 kHz second.
ESE-2013
200. Which one of the following statements is
Ans. (c) : Given fc = 25 GHz
correct?
fm1 = 1kHz
fm2 = 2kHz One hundred percent modulation of the carrier
The modulated wave bandwidth will be twice the for the broadcast FM radio band is achieved
highest message signal frequency ( f m2 > f m1 ) when
(a) Carrier frequency changes by ± 100%
So, Bandwidth = 2fm2 = 2×2
= 4 kHz (b) Carrier envelope changes by ± 100%
196. In TV transmission, the modulation schemes (c) Carrier frequency change by ± 75kHz
for Video and Audio are, respectively (d) Audio frequency changes by ± 15kHz
(a) FM and AM (b) AM and FM ESE-2004
(c) AM and FM (d) AM and AM Ans. (c) : In case of FM radio broadcasting 100%
ESE-2003 modulation of carrier is assumed when carrier
Ans. (c) : For better audio signal at receiver → FM is frequency changes by ± 75 kHz i.e. maximum
used. For less complex receiver for video → AM is frequency deviation = 75 kHz.
used. In FM percentage modulation is given by-
AM= For video signal ∆f
FM = For audio signal %β = ×100
fm
197. Attenuator have ––––––––
(a) Attenuation constant In standard FM the maximum permitted frequency is 15
(b) Phase constant kHz.
(c) Gain and phase constant So, ± 15 kHz deviation in carrier will give 100%
(d) Attenuation and phase constant modulation. Deviation of ± 15kHz gives carrier
BSNL TTA 28.09.2016, 3 PM
frequency change by ± 75kHz.
Ans. (a) Attenuator - To simplify the design of the
attenuator (K) for constant value can be used. This 'K' 201. The data transfer rate of a modem is measured
value is the ratio of the voltage, current or power in-
corresponding to a given value of dB attenuation and is (a) Bytes per second (b) Baud rate
given as- (c) Bits per second (d) Hertz
 dB  dB / 20 BSNL TTA 26.09.2016, 3 PM
K = anti log   = 10 for voltage or current
 20  Ans : (c) The data transfer rate of a modem is typically
 dB  dB /10
measured in bits per seconds. MODEM stands for
K = anti log   = 10 for power modulator demodulator.
 10 
202. In an Amplitude Modulated (AM) wave with
198. A Pre-emphasis circuit provides extra noise
100% modulation (ma), the carrier is
immunity by
(a) Boosting the base frequencies suppressed. The percentage of power saving
(b) Amplifying the higher audio frequencies will be
(c) Pre-amplifying the whole audio band (a) 100% (b) 50%
(d) Converting the phase modulation to FM (c) 25% (d) 66.7%
ESE-2014 ESE-2013
Electronics-II 957 YCT
 Carrier power Ans. (d) : For (B+1) quantizer SNR,
Ans. (d) : % Power saving = ×100
Total power  3σ 
SNR = 6.02 B+ 10.8–20 log10  x 
=
Pc
× 100  σx 
 ma2  According to question,
Pc 1 +  SNR = 90dB
 2 
Then,
∴ 100% modulated means ma = 1 90 = 6.02B + 10.8 − 20log10 3
Pc 90 = 6.02B + 10.8 − 9.54
= ×100
 1 B = 14.74 ≅ 15
Pc 1 + 
 2 Then,
B +1 = 15 +1 = 16 bits
2
= = 66.7% 206. In a radio receiver, which of the following
3 stages does not need alignment ..............
203. Which of the following is not a component of (a) TRF stage
PLL? (b) IF stage
(a) Frequency multiplier (b) Phase detector (c) Antenna input stage
(c) VCO (d) Loop filter (d) Audio stage
BSNL TTA 26.09.2016, 3 PM
ESE-2005
Ans : (d) The input to the audio stage is a demodulated
Ans. (a) : message signal and does not require any alignment to
• PLL is a feedback control system that automatically receive the desired frequency.
adjusts the phase of a locally generated signal to match 207. Which of the following are the advantages of
the phase of an input signal. FM broadcasting over AM broadcasting
• PLLs are used to generate, stabilize, modulate, 1. Better S/N ratio
demodulate, filter or recover a signal from a noisy 2. Not subject to signal fading
communications channel where data has been 3. Power efficiency is superior
interrupted. 4. Demodulation is simpler
Select the correct answer from the code given
Block diagram of PLL- below.
(a) 1 and 2 (b) 1, 2 and 4
(c) 2, 3 and 4 (d) 1 and 3
ESE-2005
Ans. (d) : • In FM the information is in the frequency
of the signal not in the amplitude, whereas the effect of
noise is mainly on the amplitude of the signal.
• Amplitude limiter can be used in FM system.
• The effect of noise can be reduced by increasing the
deviation (ie. by increasing the value of modulation
Frequency multiplier is not a part of PLL (phase intake PM).
locked loop). • FM broadcast in the VHF and UHF ranges, where the
204. Intermediate frequency used in commercial impact of noise is minimum.
medium wave super heterodyne receiver is- 208. A 1000 W carrier is amplitude-modulated and
(a) 455 kHz (b) 10.7 MHz has side-band power of 300 W. the depth of
modulation is
(c) 38.9MHz (d) 1450 kHz
(a) 0.255 (b) 0.545
BSNL TTA 26.09.2016, 3 PM (c) 0.775 (d) 0.95
Ans : (a) Standard intermediate frequency used is ESE-2013
455kHz for medium wave super heterodyne receiver. Ans. (c) : Given Pc = 1000W, PSB = 300W
This receiver used the principle of non-linear mixing or We know that,
frequency multiplication. P m2
205. How many bits are required in an A/D Total sideband power PT(SB) = c a
2
converted with a B + 1 quantizer to get a
1000 ma2
signal-to-quantization noise ratio of at least 90 300 =
dB for a Gaussian signal with range of ±3σ x ? 2
1000 ma2 = 600
(a) B + 1 = 12 bits (b) B + 1 = 14 bits ma2 = 0.6
(c) B + 1 = 15 bits (d) B + 1 = 16 bits ma = 0.7745
ESE-2019 ≃ 0.775

Electronics-II 958 YCT

209. MODEM is used for- Ans. (c) :
(a) Modulator at transmitting side and detector at• In TDM, Several sampled signals is combined in a
the receiving side definite time sequence.
(b) Which deals with analog signals and show • TDM is used when the data to be transmitted has
digital information the small changing rate and small bandwidth.
(c) Modulator at receiving side and detector at
• In TDM, all signals have only one carrier frequency
the transmitting side
but different time sequence.
(d) A device which deals with digital signals only
BSNL TTA 26.09.2016, 3 PM 213. The pre–emphasis circuit is used :
Ans : (b) MODEM is used to take analog signal and (a) After modulation
show digital information. Modem stands for modulator- (b) Prior to modulation
demodulator. It is a hard-ware component of computer (c) to increase or emphasis the amplitude of low
to connect with the internet. It converts analog signal to frequency components of the signal
digital and vice-versa in computer. (d) None of these
BSNL TTA 25.09.2016, 3:00 P.M.
210. PLL demodulators are now used in commercial
receivers because of which of the following: Ans : (b) The pre-emphasis circuit used prior to
1. PLL demodulators do not exhibit threshold in modulation. Modulating signal is given to pre- emphasis
S/N performance, circuit network in transmitter. This stage emphasizes
2. No requirement of pre-emphasis and de- high frequency components of modulating signal. To
emphasis. improve signal to noise ratio components of high
3. Cheap PLL ICs are available. frequency signal is increased in its amplitude.
Select the correct answer using the code given 214. A 100 V carrier peak changes from 160 V to 40
below: V by a modulating signal. The modulating
(a) 1 and 2 (b) 2 and 3 factor is
(c) 1 and 3 (d) 1, 2 and 3 (a) 0.3 (b) 0.5
ESE-2007 (c) 0.6 (d) 0.7
Ans. (d) : PLL demodulator is reduced the noise very ESE-2014
much at receiver system. So to increase SNR at Ans. (c) : We know that,
receiver. There is no requirement of pre-emphasis and V − Vmin
de-emphasis circuit. PLL demodulators do not exhibit Modulating factor or modulation index = max
threshold in SNR performance. Vmax + Vmin
PLL ICs are available with very low cost. So,
211. A 1 mW signal having a bandwidth of 100 160 − 40 120
ma = = = 0.6
MHz is transmitted to a receiver through cable 160 + 40 200
that has 40 dB loss. If the effective one–side 215. What is the automatic frequency control
noise spectral density at the receiver is 10–20 voltage of the FM transmitter VCO?
Watt/Hz, then the signal to noise ratio at the (a) DC voltage (b) Sine wave voltage
receiver is : (c) Square wave voltage (d) Ramp voltage
(a) 50dB (b) 30dB ESE-2007
(c) 40dB (d) 60dB
BSNL TTA 25.09.2016, 3:00 P.M. Ans. (a) : • Automatic frequency control (AFC) voltage
of the FM transmitter VCO is a DC voltage.
Ans : (a) ∵ S =1×10−3 = Pin • AFC is a circuit to automatically keep a resonant
Pin circuit tuned to the frequency of on incoming radio
Loss = 40 dB = 10 log signal.
Pout
Pout at receiver = 10 –7 216. Boosting of higher audio frequencies in FM to
noise power N0 = η × BW improve noise immunity is called :
(a) De–Emphasis (b) Pre–emphasis
Given that
(c) Compression (d) Expansion
η = 10 , BW = 100MHz = 10
–20 8
BSNL TTA 25.09.2016, 3:00 P.M.
N0 = 10 × 10 = 10
–20 8 –12
Ans : (b) Boosting of higher audio frequencies in FM
S 10−7 to improve noise immunity is called pre-emphasis.
Then = =10 5

N 0 10−12 Modulating signal is given to a pre-emphasis network

firstly in transmitter and this network boosts high
S S frequency components. To improve signal to noise ratio
=10 log =10 log 10 = 50 dB
5

N 0 dB N0 high audible frequency amplitude is increase.

212. Time division multiplexing is used when the 217. Voice is digitized using an ADC with a
data to be transmitted is sampling period of 0.1 millisecond and 10
(a) Slow changing bit/sample. What is the bit rate in kbps
(b) Of small bandwidth generated by this system?
(c) Slow changing and has a small bandwidth (a) 100 kbps (b) 1000 kbps
(d) Fast changing and has a wide bandwidth (c) 9.9 kbps (d) 10.1 kbps
ESE-2001 ESE-2007
Electronics-II 959 YCT
Ans. (a) : Given that, number of bits/Sample = 10 fc
bits/sample (a) fc + 2fm (b) − 2f m
fm
Sampling period Ts = 0.1 m sec = 10-4sec. (c) fc + fm (d) fc – fm
So number of samples per second KVS WET 2017
1 Ans. (c) : Amplitude modulated waveform is -
=
sampling period ( TS )
1
= = 104 samples / sec
10−4
We know that, bit rate = Number of sample/sec ×
number of bits/sample
= 104 × 10 bps
Bit rate = 100 kbps
218. In an FM system, when the AF is 500Hz and
the AF voltage is 2.4 V, the deviation is 4.8
kHz. If the AF voltage is now increased to 7.2V,
the new deviation will be :
(a) 4.8 KHz (b) 9.6 KHz
(c) 14.4 KHz (d) 28.8 KHz
BSNL TTA 25.09.2016, 3:00 P.M.
Ans : (c) In FM frequency deviation is given-
as ∆F = K F A m So,
Upper side band =fc + fm
∆F1 A m1 2.4 1 Lower side band = fc - fm
= = =
∆F2 A m2 7.2 3 222. Consider the case that noise phase modulates
∆F2 = 3 × ∆F1 the FM wave. As the noise sideband frequency
approaches the carrier frequency, the noise
∆F2 = 3 ( 4.8 ) amplitude -
∆F2 = 14.4kHz (a) remains constant (b) is decreased
(c) is increase (d) is equalised
219. For a 10-bit PCM system, the signal to Mizoram PSC IOF 2019, Paper-III
quantization noise ratio is 62 dB. If the number Ans. (b) : As the noise sideband frequency approaches
of bits is increased by 2, then how would the the carrier frequency, the noise amplitude is decreased.
signal to quantization noise ratio change? 223. A broadcast AM transmitter radiates 50 kW of
(a) Increase by 6 dB (b) Decrease by 6 dB carrier power. The radiation power at 85% of
(c) Increase by 12 dB (d) Decrease by 12 dB modulation is
ESE-2007 (a) 68.1 kW (b) 60.8 kW
Ans. (c) : In PCM system- (c) 61.8 kW (d) 62.0 kW
(S / N )dB = 6n + 1.76 ESE-2014
Given n = 10 and ( S / N )dB = 62dB Ans. (a) : Given that
PC = 50 W, ma = 85% = 0.85
(S/N) = 61.76…………………..(i)
We know, Total transmitting power or radiation power
When n = 12 then
(S/N)dB = 73.76…………………(ii)  µ2 
PT = PC  1 + 
Comparison equation (i) and (ii)  2
(S/N)dB = 12 dB increase
 0.85 × 0.85 
220. The highest modulation frequency typically = 50  1 + 
used in AM broadcast is :  2 
(a) 5 KHz (b) 10 KHz = 68.0625 kW
(c) 15 KHz (d) 1 MHz 224. The range of super heterodyne receiver tuning
BSNL TTA 25.09.2016, 3:00 P.M. when fLO > fC with broadcast frequency ranges
Ans : (a) Highest frequency used in AM broadcast is 5 540 to 1600 kHz is -
KHz. Amplitude modulation (AM) has very low (a) 85 – 1145 kHz (b) 540 – 1600 kHz
bandwidth in comparison with FM. AM has large signal
(c) 995 – 2055 kHz (d) 1450 – 2510 kHz
power than unmodulated signal. AM has distortion also.
In AM modulation the maximum possible bandwidth is Mizoram PSC IOF 2019, Paper-III
10KHz. Ans. (c) :
221. If fc is the carrier wave frequency and fm is the Since fLO>fc fc = fs = 540 to 1600 kHz
modulation frequency, then in the resulting f0 = fLO = fs + fi fi = 455 kHz
amplitude modulated waveform the upperside = (540 to 1600)kHz +455 kHz
band consists of : f0 = 995 to 2055 kHz
Electronics-II 960 YCT
225. Which one of the following signals can be 229. Consider the following statements about analog
applied to a delta modulator whose step size is data-digital signal:
0.1 V and sampling frequency is 20π kHz so 1. Amplifiers used in repeaters produce additive
that no slope overload occurs? noise.
(a) 2sin (1200πt) (b) 1sin (2600πt) 2. FDM is used for digital signals whereas TDM
(c) 3sin (1000πt) (d) 4sin (400πt) is used for analog signals.
ESE-2006 3. With TDM there is no intermodulation noise
Ans. (d) : No overload condition is whereas this is a concern for FDM.
|mt|max = ωA > ∆.fS 4. Conversion to digital signalling allows the use
of efficient digital switching techniques.
∆.f
A< s Which of these statements are correct?
ω (a) 1 and 2 (b) 3 and 4
Here, (c) 1, 2 and 3 (d) 1, 2, 3 and 4
fs = sampling frequency ESE-2006
∆ = step size Ans. (b) : FDM – If multiple message signals are
Given, A = 4 V,ω = 400π rad/s combined on the basis of frequency sharing, that is
fs = 20 π kHz, ∆ = 0.1 V transmitted on different carrier frequencies on different
Hence, the applied signal = A sin ωt carrier frequencies but at the same time then it is called
= 4 sin 400 πt frequency division multiplexing.
226. In a low-level AM system, amplifiers following • FDM is used for analog signals.
the modulator stage must be - TDM- TDM is the process of utilizing the time scale
(a) linear devices (b) harmonic devices for simultaneous transmission of more than one base
(c) class C amplifiers (d) nonlinear devices band signal on the same carrier.
Mizoram PSC IOF 2019, Paper-III •TDM is used for digital signal.
Ans. (a) : A low level AM modulator would be one 230. The most commonly used filters in SSB
where the modulation is applied to low power stage of generation are -
the transmitter typically in the RF generation stage or (a) mechanical (b) RC
via digital signal processing area. The drawback of This (c) LC (d) low-pass
approach is that linear amplification is required. Mizoram PSC IOF 2019, Paper-III
227. In a typical AM receiver circuit, the oscillator Ans. (a) : The most commonly used filters in SSB
frequency is generation are mechanical.
(a) Same as signal frequency A mechanical filter is a signal processing filter at radio
(b) Always equal to 455 Hz frequencies. Its purpose is the same as that of a normal
(c) Lower than the signal frequency by 455 Hz electric filter such as to pass a range of signal
(d) Higher than the signal frequency by 455 kHz frequencies, but to block others. The filter acts on
ESE-2014 mechanical vibrations which are the analogous of the
Ans. (d) : We know that, electric signal.
Local oscillator frequency fLO= fS + fIF 231. An angle modulated signal is described by the
where, signal frequency fS = 455 kHz equation
fIF = intermediate frequency xc(t) = 10 cos [2πfct + 10 sin(4000πt) + 5sin
then, fLO = (455 kHz + fIf) 2000πt]
hence, in a typical AM receiver circuit, the oscillator What is the bandwidth of this modulated
signal?
frequency is higher than the signal frequency by 455
(a) 6 kHz (b) 45 kHz
kHz. (c) 54 kHz (d) 63 kHz
228. The noise temperature about 4306K. The noise ESE-2009
figure will be - Ans. (c) : Given that,
(a) 3 dB (b) 6 dB xc(t)= 10 cos [2πfct + 10 sin(4000πt)
(c) 12 dB (d) 24 dB + 5 sin (2000πt)]
Mizoram PSC IOF 2019, Paper-III φ(t) = 2πfct + 10 sin 4000πt
Ans. (c) : Given noise temperature + sin (2000πt)
Tnoise = 4306 K dφ ( t )
we know that noise figure ωi =
dt
T  dφ ( t )
NF = 10 log10  noise + 1 2πfi =
 Tref  dt
 4306  Then f i = fc + 20 × 103cos 4000πt
= 10log 10  + 1 + 5 × 103 cos 2000πt
 290  so maximum frequency deviation,
= 10 log10 (15.84827) = 10 × 1.19 ∆fmax = 20 × 103 + 5× 103
= 11.99 ≈ 12 dB = 25 kHz
Electronics-II 961 YCT
∴ Message signal has two significant frequency Ans. (d) : Given,
components one at 2 kHz ( sin 4000πt) and one at 1 kHz fmax = 100.01 MHz
(sin 2000πt). fmin = 99.97 MHz
So message signal fm = 2 kHz Total frequency deviation around carrier
Bandwidth ( BW ) = 2 ( ∆f + f m ) = fmax – fmin
= 100.01 – 99.97
= 2 ( 25 + 2 ) kHz = 0.04 MHz
= 54 kHz 0.04
∴ One side frequency deviation = = 20 kHz
232. Indicate which of the following circuits cannot 2
demodulate SSB - ∴ Deviation on either side is same = 20 kHz
(a) Balanced modulator 236. A 50.004 MHz carrier is to be frequency
(b) Product detector modulated by a 3 KHz audio tone resulting in a
(c) BFO narrow band FM signal. Determine the
(d) Phase discriminator bandwidth of the FM signal -
Mizoram PSC IOF 2019, Paper-III (a) 2 KHz (b) 4 KHz
(c) 6 KHz (d) 4 MHz
Ans. (d) : Phasor discriminator is also shown as Mizoram PSC IOF 2019, Paper-III
center tuned discriminator or foster seeley
Ans. (c) : For a narrow band frequency modulated
discriminator. It uses double tuned RF transformer to
current frequency to amplitude variation. These signal BW = 2f m
amplitude are rectified and filter to provide dc o/p. fm = 3kHz given
Balanced modulator, product detector BFO are the ∴ BW = 2 (3kHz) = 6 kHz
devices to demodulate SSB. 237. In TV, video signals are transmitted through
233. Multiplexing scheme which uses carrier phase (a) Amplitude modulation
shifting and synchronous detection to permit (b) Frequency modulation
two DSB signals to occupy the same frequency (c) Either amplitude or frequency modulation
band is called (d) Neither amplitude nor frequency modulation
(a) NBFM (b) CDMA ESE-2015
(c) QAM (d) FDMA Ans. (a) : In TV system, video signals are transmitted
ESE-2014 through amplitude modulation (AM) and audio signal
Ans. (c) : QAM (Quadrature Amplitude Modulation) is through frequency modulation (FM).
a signal in which two carriers shifted in phase by 90 VSB is used for video modulation in TV transmission.
degrees are modulated and combined. As a result of 900. 238. The maximum range of a transmitter depends on
phase difference they are in quadrature and this gives (a) Its frequency
rise to the name QAM. (b) Its power
(c) Both Frequency and Power
234. Indicate which of the following systems is (d) None of these
digital - BSNL TTA 29.09.2016, 10 AM
(a) Pulse-position modulation Ans : (c) The maximum range of a transmitter depends
(b) Pulse-code modulation on both frequency and power. As frequency increases,
(c) Pulse-width modulation the signal is absorbed more by physical objects
(d) Pulse-frequency modulation (atmospheric moisture, trees, buildings etc). Hence you
Mizoram PSC IOF 2019, Paper-III need more power to make up for the signal loss. For
Ans. (b) : Pulse code modulation is a pulse modulation constant power, the range decreases because the signal
technique in which analog signal is converted into losses increase with increasing frequency.
binary representation as series of pulse. 239. The function of de-emphasis circuit in an FM
Form of signal modulation in which M message bits are receiver is_______
encoded by a transmission single pulse in one of (a) to control the amplitude of FM wave
possible required time shift. (b) to restore the various frequency components
It is also called pulse duration modulation method of to their original levels
(c) to reduce the high frequency components
reducing average power by an electrical signal (d) none of these
effectively into discrete part. BSNL TTA 29.09.2016, 10 AM
235. An F.M. signal which is modulated by a 4 kHz Ans : (b) De-emphasis is the inverse process of pre-
sine wave reaches a maximum frequency of emphasis. Pre-emphasis is done for boosting the relative
100.01 MHz and minimum frequency of 99.97 amplitude of the modulating voltages at higher audio
MHz, then what is the one side frequency frequencies. In De-emphasis, the original signal power
deviation of the signal? is restored at the detector output of the receiver. Thus,
(a) 6.67 (b) 5.00 the function of de-emphasis circuit in an FM receiver is
(c) 10.0 (d) 20.0 to restore the various frequency components to their
ESE-2009 original levels.
Electronics-II 962 YCT
240. Which one of the following factor is limited in Ans : (d) The direct methods cannot be used for the
case of F.M.? broadcast application. Thus the alternative method i.e.
(a) Maximum frequency deviation indirect method called as the Armstrong method of FM
(b) Maximum permissible modulation index generation, is used.
(c) Signal to noise voltage ratio In this method the FM is obtained through phase
(d) Minimum permissible modulation index modulation. A crystal oscillator can be used hence the
ESE-2009 frequency stability is very high. Thus, Armstrong
modulator generates both FM signal & PM signal
Ans. (a) : The bandwidth for FM
244. Analog data having highest harmonic at 30
B.W = 2[ ∆f + f m ] –––(i) kHz generated by a sensor has been digitized
where, ∆f→ maximum frequency deviation using 6-level PCM. What will be the rate of
digital signal generated?
fm→ modulating frequency. (a) 120 kbps (b) 200 kbps
Hence, we can say that the maximum frequency (c) 240 kbps (d) 180 kbps
deviation should be limited. ESE-2005
Bandwidth requirement is proportional to the maximum
Ans. (d) : Nyquist rate = 2 × 30 k = 60k samples/sec
frequency deviation.
For 6- level, 2 n= 6
BW. ∝ ∆f (form equation (i))
n ≃3
241. A carrier voltage frequency is 1 MHz and Bit rate = n× Nyquist rate
modulating signal frequency is 5 KHz. = 3×60 k = 180 k
Calculate the frequency of lower side band and 245. Telephone traffic is measured______
upper side band in case of Amplitude (a) with echo cancellers
modulation. (b) by the relative congestion
(a) 990 KHz and 1005 KHz (c) In terms of the grade of service
(b) 995 KHz & 1110 KHz (d) in Erlangs
(c) 1000 KHz & 1005 KHz BSNL TTA 29.09.2016, 10 AM
(d) 995 KHz & 1005 KHz Ans : (d) Telephone traffic is measured in Erlangs. The
BSNL TTA 29.09.2016, 10 AM erlang (E) is a dimensionless unit that is used in
Ans : (d) Given, telephony as a measure of offered load or carried load
Carrier frequency, fc= 1 MHz or 1000 kHz on service-providing elements such as telephone circuits
or telephone switching equipment. A single curd circuit
modulating frequency, fm = 5 kHz has the capacity to be used for 60 minutes in one hour
Now, full utilization of that capacity 60 minutes of traffic,
The frequency of lower side band, fL constitutes 1 enlarge.
fL = fc –fm 246. For an m-derived high pass filter, the cut off
= 1000 – 5 = 995 kHz frequency is 4 kHz and the filter has an infinite
The frequency of upper side band, fU attenuation at 4 KHz, the value of m is
fU = fc +fm (a) 1 (b) zero
= 1000 + 5 (c) 2 (d) 0.5
= 1005 kHz BSNL TTA 29.09.2016, 10 AM
242. Consider the following types of modulation: Ans : (b) f ∞ = infinite attenuation frequency
1. Amplitude modulation fc = cut-off frequency
2. Frequency modulation 2
3. Pulse modulation f 
m = 1−  c 
4. Phase modulation
 f∞ 
Which of the above modulation are used for
telecasting TV programs? 16
m = 1− = 1 −1
(a) 2 and 3 (b) 3 and 4 16
(c) 1 and 2 (d) 1 and 4 m=0
ESE-2015 247. A PLL can be used to demodulate
Ans. (c) : For TV telecasting programs we use AM (a) PAM signals (b) PCM signals
modulation and FM modulation. (c) FM signals (d) DSB-SC signals
AM → for video signal telecast. BSNL TTA 29.09.2016, 10 AM
FM → for Audio signal telecast. Ans : (c)
243. Armstrong modulator generates
(a) AM Signal
(b) FM Signal
(c) PM Signal
(d) Both FM Signal & PM Signal
BSNL TTA 29.09.2016, 10 AM
Electronics-II 963 YCT
PLL or phase locked loop is used as a FM demodulator. 251The basic data rate of bearer channel in ISDN
It is a high performance FM detector due to its key is-
advantages such as linearity and low manufacturing (a) 8 kbps (b) 16 kbps
costs. (c) 64 kbps (d) 384 kbps
When designing a phase locked loop system for use as BSNL TTA 27.09.2016, 3 PM
an FM demodulator, one of the key considerations is the Ans : (c) Basic Rate Interface (BRI):- There are two
loop filter. This must be chosen to be sufficiently wide date bearing channels (B channels) and one signaling
channel (D channel) in BRI to initiate connections. The
that it is able to follow the anticipated variations of the
frequency modulated signal. B channels operate at a maximum of 64 kbps while D
248. Modulation is used to channel operates at a maximum of 16 kbps. The two
1. Separate different transmission channels are independent of each other. For example,
2. Reduce the bandwidth requirement one channel is used as a TCP/IP connection to a
3. Allow the use of practicable antennas location while the other channel is used to send a fax to
4. Ensure that intelligence may be transmitted a remote location.
over long distance 252. Consider the following features of FM vs AM;
Which of the above statements are correct? 1. Better noise immunity is provided
2. Lower bandwidth is required
(a) 1, 2 and 3 only (b) 1, 3 and 4 only
3. The transmitted power is better utilized
(c) 2 and 4 only (d) 1, 2, 3 and 4 4. Less modulating power is required
ESE-2016 Which of the above are advantages of FM over
Ans. (b) : Modulation is used to- AM?
1. Separate different transmission (a) 1, 2 and 3 only (b) 1, 3 and 4 only
2 Allow the use of practicable antennas (c) 2 and 4 only (d) 1, 2, 3 and 4
3. Ensure that intelligence may be transmitted over ESE-2016
long distance Ans. (b)
249. If the carrier of a 100% modulated AM wave is Comparison between FM and AM-
suppressed, the percentage power saving will FM AM
be- FM receivers are AM receivers are not
(a) 50 (b) 150 immune to noise immune to noise
(c) 100 (d) 66.66 Bandwidth is higher Bandwidth is lower
BSNL TTA 27.09.2016, 3 PM and depends on and Independent of
ESE 2016 modulation index modulation index
Noise can be This feature is absent
 m2  decreased by in AM
Ans : (d) Total power in full AM, Pt = Pc  1 + 
2  increasing deviation

253. Which of the following will carry the same
where m = 1 information as the AM wave itself?
 1 (a) SSB (b) VSB
Pt = Pc 1 +  (c) DSB (d) All of these
 2
BSNL TTA 27.09.2016, 3 PM
Pt = 1.5 PC
Ans : (d) Sideband:- A side band is a band of
Pc Pc frequencies, containing power, which are the lower and
Power saving % = =
Pt 1.5Pc higher frequencies of the carrier frequency. The sideband
= 66.66% (SSB, VSB, DSB) contain the same information.
254. Consider the following statements about FM.
250. If an FM wave is represented by the equation e 1. Modulation index determines the number of
=10 sin (9 × 108t + 4 sin 1500t), then what is the significant sideband components.
carrier frequency? 2. Theoretical bandwidth is infinite.
(a) 127.32 MHz (b) 150.00 MHz 3. Carrier suppression is not possible.
(c) 143.31 MHz (d) 208.00 MHZ 4. Sidebands are not symmetric about carrier.
ESE-2009 Which of these statements is/are correct?
Ans. (c) : Given that, (a) 1, 2, 3 and 4 (b) 1 and 2 only
e = 10 sin(9 × 108t + 4 sin 1500t) (c) 3 and 4 only (d) 3 only
Compare this with standard FM equation ESE-2010
s(t) = Ac sin (2πfct + βsin 2πfm t) Ans. (b) : In FM there are infinite number of sideband
Where, in theoretical condition.
fc- carrier frequency So, we can say there are infinite bandwidth of FM signal.
fm - message signal frequency Bandwidth of FM = 2 [ ∆f + f m ]
Comparing we have - Bandwidth = 2f m [ mf + 1]
2πfc = 9 × 108
mf = modulation index
9 × 108 Thus in FM modulation index determines the number of
fc = = 143.31MHz
2π significant sideband components.

Electronics-II 964 YCT

255. The disadvantage of FM over AM is that......... 259. The de-emphasis filter in an FM receiver comes
(a) The noise is very high for high frequency signal (a) Before FM demodulator
(b) High modulating power is required (b) After FM demodulator and before baseband
(c) Larger bandwidth is required filter
(d) High output power is required (c) After baseband filter
BSNL TTA 27.09.2016, 3 PM (d) Before RF amplifier
Ans : (c) FM systems have a much wider bandwidth ESE-2010
than AM systems and therefore more prone to selective Ans. (b) : De-emphasis is performed in the
fading. Frequency modulation requires much wider discriminator output in the receiver which is after the
channel (7 to 15 times) as compared to AM. FM demodulator and before baseband filter.
256. Which one of the following statement is 260. Which one of the following multiplexing
correct? techniques involves signals composed of light
In TDM, non-essential frequency components of beams?
the modulating signal are removed by (a) CDM (b) FDM
(a) Sampler (b) Attenuator (c) TDM (d) WDM
(c) Pre-alias filter (d) Modulator ESE-2003
ESE-2004 Ans. (d) : WDM (Wavelength Division
Ans. (c) : By using pre-alias filter before transmitter we Multiplexing)- WDM is a fiber-optic transmission
remove non-essential frequency in time division technique that enables the use of multiple light
multiplexing (TDM) system. wavelength to send data over the same medium.
Early fiber-optic transmission system put information
onto stands of glass through simple pulse of light.
261. Johnson noise is-
(a) Caused by thermal agitation of free electrons
carrying current therefore modulating the
current
(b) Noise carried into a circuit through conductors
(c) Noise of an electromagnetic origin that is
radiated into a circuit
(Pre or anti-alias filter) (d) Shot noise which results from emission of
Pre or anti-aliasing filter looks at the user-specified electrons across a p-n junction
sampling frequency and removes any under-sampled BSNL TTA 27.09.2016, 3 PM
frequencies that may appear in the signal.
Ans : (a) Johnson noise:- It is also known as thermal
257. In an amplitude modulated wave, the value of noise and Nyquist noise. It is the electronic noise
Emax is 10V and Emin is 5V, then percentage of generated by the thermal agitation of the charge carriers
modulation will be- (usually the electron) inside an electrical conductor at
(a) 2% (b) 33.3% equilibrium, which happens regardless of any applied
(c) 50% (d) 75% voltage. Thermal noise is present in all electrical
BSNL TTA 27.09.2016, 3 PM circuits, and in sensitive electronic equipment.
Ans : (b) Given, Emax = 10V, Emin = 5V 262. One disadvantage of adaptive delta modulation
Modulation index- over linear delta modulation is that it
E − E min (a) Requires more bandwidth
m a = max
E max + E min (b) Is more vulnerable to channel errors
(c) Requires a large number of comparators in
10 − 5 5
ma = = the encoder
10 + 5 15 (d) Is not suitable for signals with periodic
5 components
= ×100
15 ESE-2002
ma = 33.3% Ans. (d) : In linear delta modulation step size is fixed
258. Typical gain of a amplifier for the UHF for the whole signal, whereas in adaptive delta
channels is- modulation the step size varies depending upon the
(a) 0 dB (b) 2 dB input signal.
(c) –5 dB (d) 40 dB • Linear delta modulation has the slope overload and
BSNL TTA 27.09.2016, 3 PM granular noise errors but has not seen in adaptive
Ans : (b) delta modulation.
• UHF television broadcasting is the use of ultra high • The dynamic range of adaptive delta modulation is
frequency (UHF) radio for over the air transmission of wider than linear delta modulation.
television signals. • Adaptive delta modulation utilizes bandwidth more
• UHF frequencies are used for both analog and digital effectively than linear delta modulation.
television broadcast and typical gain of an amplifier for • SNR of adaptive delta modulation is better than
the UHF channels is 2dB. linear delta modulation.

Electronics-II 965 YCT

263. U interface in ISDN is the interface between- Ans. (a) : Armstrong modulator :
(a) PSTN and desktop • This is an indirect method of generating FM.
(b) TA and ISDN phone • In this method first phase modulation is done (from
(c) TA and non ISDN device which narrow band FM is obtained) and then
(d) TA and PSTN wideband FM is obtained using frequency
BSNL TTA 27.09.2016, 3 PM multiplier.
Ans : (d) ISDN-U interface:- U interface consist of • In this method crystal oscillator is used which has
two wires among the exchange and network terminating good frequency stability. Therefore, the center
unit and it interfaces between TA and PSTN in ISDN. frequency of the FM wave generated by this
264. The performance of the DPCM-Coder processes is extremely stable, which is not prone to
improves as the distortion.
(a) Input probability spectral density tends to be • The value of the modulation index less then 1.
white
(b) Input power spectral density tends to be white 267. In phase modulation, phase deviation is
(c) Input dynamic range increases proportional to
(d) Sample-to-sample correlation of the input (a) Carrier amplitude
increases (b) Carrier phase
ESE-2002 (c) Message signal
Ans. (d) : DPCM- Differential pulse code modulation (d) Message signal frequencies
is a signal encoder that uses the baseline of pulse-code ESE-2011
modulation but adds some functionalities based on the Ans. (c) : Phase of the carrier in phase modulation is
prediction of the samples of the signal the input can be proportional to message signal.
analog signal or a digital signal.
265. Find the correct match between group-1 and
group-2 So, phase deviation is proportional to message signal.
Group-1 Group-2 268. A carrier is frequency modulated with a
P. {1 + km ( t )} W. Phase Modulation sinusoidal signal of 2 kHz resulting in a
A sin(ωct) maximum frequency deviation of 5 kHz. What
Q. {k m(t)}.A X. Frequency is the bandwidth of the modulated signal?
sin(ωct) Modulation (a) 7 kHz (b) 5 kHz
R. A sin{ωct + km(t)} Y. Amplitude (c) 14 kHz (d) 4.5 kHz
Modulation JPSC AE 10.04.2021, Paper-I
S. A sin(ωct + Z. DSB-SC Ans. (c) : According to Carson's rule,
t Bandwidth of FM is given by 2 (∆f + fm) where, ∆f is
k ∫ m(t)dt) Modulation
∞

-
the deviation in frequency and fm is the frequency of
(a) P-Z, Q-Y, R-X, S-W sinusoidal signal.
(b) P-W, Q-X, R-Y, S-Z The required bandwidth = 2 ( ∆f + f m )
(c) P-X, Q-W, R-Z, S-Y = 2(5 + 2)
(d) P-Y, Q-Z, R-W, S-X = 14 KHz
JPSC AE 10.04.2021, Paper-I
269. Which one of the following PCM scheme is
Ans. (d) : Amplitude Modulation - depicted in the below figure?
VAM(t) = [Vc + kaVm cosωmt] cosωct
or
VAM(t) = vc [1+ ma cosωmt] cosωct
V
ma = k a m
Vc
Am-DSB/SC
1
VAM(t) = m a Vc cos ( ωc + ωm ) t + cos ( ωc − ωm ) t 
2 (a) Adaptive DM (b) Differential
Phase modulation (PM) (c) Companding (d) Delta Modulation
VPM(t) = Ac cos[(ωct + kp f(t)] ESE-2001
Where, fm = modulating signal Ans. (a) : Adaptive delta modulation- This
frequency modulation (FM) modulation is the refined form of delta modulation this
VFM (t) = A cos ωc t + k f ∫ f (t)dt  method was introduced to solve the granual noise and
  slop overload error caused during delta modulation.
266. An indirect way of generating FM, is The transmitter circuit consists of a summer, quantizer
(a) The Armstrong modulator delay circuit, and a logic circuit for step control. The
(b) The reactance FET modulator baseband signal X(nTs) is given as input to the circuit.
(c) The varactor diode modulator The feedback circuit present in the transmitter is an
(d) the reactance bipolar transistor modulator integrator. The integrator generates the stair case
ESE-2011 approximation of the previous sample.
Electronics-II 966 YCT
270. Which of the following analog modulation The pre-emphasis circuit increases the value of the high
scheme requires the minimum transmitted frequency modulating components before modulation.
power and minimum channel bandwidth? Thus the SNR (signal to noise ratio) of the high
(a) VSB (b) DSB-SC frequency components increases thus the effect of noise
(c) SSB (d) AM at the time of transmission on high frequency
JPSC AE 10.04.2021, Paper-I components is reduced.
Ans. (c) : In SSB transmission only one sideband is 274. When aliasing take place
transmitted while in other case more than one side- (a) Sampling signals less than Nyquist rate
band is transmitted, so minimum power is transmitted (b) Sampling signals more than Nyquist rate
for SSB. (c) Sampling signals equal to Nyquist rate
271. A 4 GHz carrier is amplitude-modulated by a (d) Sampling signals at a rate which is twice of
low- pass signal of maximum cut off frequency Nyquist rate
1 MHz. If this signal is to be ideally sampled, UPPSC AE 13.12.2020, Paper-II
the minimum sampling frequency should be Ans. (a) : In signal processing and related disciplines,
nearly aliasing is an effect that causes different signals to
(a) 4 MHz (b) 4 GHz become indistinguishable when sampled. Aliasing take
(c) 8 MHz (d) 8 GHz place when sampling signals less than Nyquist rate.
ESE-2001
275. "Slope overload" occurs in delta modulation
Ans. (a) : Given that,
fc = 4GHz when the
and fm = 1 MHz (a) Frequency of the clock pulses is too low
Then BW = 2 fm = 2 × 1 = 2 MHz (b) Rate of change of analog waveform is too
large
So, minimum sampling frequency ≥ 2 × BW (c) Step size is too small
= 2 × 2 = 4 MHz (d) Analog signal varies very slowly with time
272. A 400 W carrier is amplitude modulated with ESE-2001
m = 0.75. The total power in AM is Ans. (b) : Slope overload occurs in delta modulation if,
(a) 400 W (b) 512 W
rate of change of message signal greater than the slope
(c) 588 W (d) 650 W
at the o/p of delta modulator. So, if message is varying
UPPSC AE 13.12.2020, Paper-II
very fast then slop overload will occur.
Ans. (b) : Given: Carrier Power (Pc) = 400W
Modulation index (m) = 0.75 276. Consider sinusoidal modulation in an AM
Total power in AM (PT) = ? system. Assuming no over modulation the
modulation index (µ) when the maximum and
 ( m )2   ( 0.75 )2 
formula: PT = Pc  1 +  = 400  1 +  minimum values of the envelope, respectively
 2   2  are 3V and 1V is
  (a) 0.7 (b) 0.5
 2.5625  (c) 0.3 (d) 0.8
= 400  
 2  UPPSC AE 13.12.2020, Paper-II
PT = 512.5 Ans. (b) : Given,
PT ≅ 512W Vmax = 3V, Vmin = 1V
Vmax = VC (1 + µ)
273. The main advantage of pre-emphasis circuit in
Vmin = VC (1 – µ)
FM transmitter is
(a) To increase the carrier power Modulation index (µ) = ?
(b) To improve the signal to noise ratio at low V − Vmin
audio frequencies µ = max
Vmax + Vmin
(c) To increase the bandwidth of side band
(d) To improve the signal to noise ratio at high 3 −1
audio frequencies µ=
3 +1
ESE-2011
2
Ans. (d) : Pre-Emphasis Circuit : µ=
4
µ = 0.5
277. Which of the following component blocks is not
required in the FDM transmitter block
diagram?
(a) Filter cutting off lower and higher frequencies
(b) Filter cutting off higher frequencies
(c) Single sideband modulator
(d) Double sideband modulator
ESE-2011
Electronics-II 967 YCT
Ans. (d) : Double sideband modulator block is not 282. A binary channel with capacity of 36 k bits/sec
required in the FDM transmitter block diagram. Low is available for PCM voice transmission. If
pass filter is required for blocking the higher signal is band limited to 3.2 kHz, then the
frequencies and for passing the lower frequencies. appropriate values of quantizing level L and
FDM is a technique by which the total bandwidth the sampling frequency respectively are
available in a communication medium is divided into a (a) 32 and 3.6 kHz (b) 64 and 7.2 kHz
series of non-overlapping frequency bands, each of (c) 64 and 3.6 kHz (d) 32 and 7.2 kHz
which is used to carry a separate signal. ESE-2013
278. The phenomenon used in the optical fiber is- Ans. (d) : Given that message signal frequency
(a) Diffraction (b) Refraction fm = 3.2 kHz
(c) Total internal Reflection (d) Polarization Channel capacity = 36 kbits/sec = Rb
BSNL TTA 26.09.2016, 3 PM Sampling frequency,
Ans : (c) Total internal reflection phenomenon is used fs ≥ 2fm
in optical fiber. This phenomenon occurs at the fs ≥ 2 × 3.2 × 103
interface between the core is higher than the angle
fs ≥ 6400 Hz
called critical angle. The incident light get reflected
back to the core. and nfs ≤ (bit rate) = channel capacity
= 36000 bits/sec
279. DPCM is particularly suited for
(a) Radar signals transmission Rb
Hence, n ≤
(b) Radio signals transmission fs
(c) Speech signals transmission n ≤ 5.625 or n = 5
(d) Seismic signals transmission
∴ Quantization level,
ESE-2012
L = 25 = 32
Ans. (c) : The DPCM technique mainly used speech,
and sampling rate,
image and audio signal compression. The DPCM
36000
conducted on signals with the correlation between fs = = 7.2kHz
successive samples leads to good compression ratios. n
DPCM can use optimal Lloyd-max quantizer or an 283. Output data ratio of a 8-bit PCM-TDM system
adaptive quantizer than can select the quantization sampling 24 voice channels, comparing these
based on the local statics of the error signal. using µ-law at the rate of 8 kHz and with a I
280. A comparison of FDM and TDM systems frame alignment word, is
shows that (a) 1.2 × 106 bits/sec (b) 1.4 × 106 bits/sec
6
(a) FDM requires lower bandwidth, but TDM has (c) 1.6 × 10 bits/sec (d) 1.8 × 106 bits/sec
greater noise immunity. ESE-2013
(b) FDM has greater noise immunity and requires Ans. (c) : Given that,
lower bandwidth the TDM. Number of voice channels (N) = 24
(c) FDM requires channel synchronization while
Sample bits n = 8
TDM has greater noise immunity.
(d) FDM requires more multiplexing, while TDM Frame alignment word a =1
requires band-pass filter. 1
Sampling time Ts =
ESE-2012 8 kHz
Ans. (c) : One of the major difference between FDM A frame alignment consist of data as well as
and TDM is that in FDM multiple signals are synchronizing bit-
transmitted by occupying different frequency slots. As n(N + a)
against in TDM, the various signal gets transmitted in Rb =
Ts
multiple time slots.
8 ( 24 + 1)
281. In time division multiplexing cross talk may be Rb = = 8 ( 25 ) 8 × 103
avoided by 1/ 8kHz
(a) Proper base band filtering.
Rb = 1.6 × 106 bits/sec.
(b) Proper selection of time of sampling.
(c) Increasing the amplitude of signal. 284. 24 voice channels are sampled uniformly at a
(d) Proper quantization. rate of 8 kHz and then time division
ESE-2012 multiplexed. The sampling process uses flat-top
Ans. (a) : In electronics crosstalk is any phenomenon samples with 1 µs duration. The multiplexing
by which a signal transmitted on one circuit or channel operation includes provision of synchronization
of a transmission system creates an undesired effect in by adding an extra pulse of 1 µs duration. The
another circuit or channel cross talk is usually caused by spacing between successive pulses of the
undesired capacitive, inductive, or conductive coupling multiplexed signal is
from one circuit or channel to another. (a) 4 µs (b) 6 µs
In TDM cross talk may be avoided by proper base band (c) 7.2 µs (d) 8.4 µs
filtering. ESE-2013
Electronics-II 968 YCT
Ans. (a) : Since the sampling rate- Ans. (b) : Difference between PCM and DM-
fs = 8000 samples/sec. S.No PCM DM
1 1. PCM stands for pulse code DM stands for
Ts = = 125µs modulation Delta
8000 modulation
A sample of each of the 24 voice signal is sent over this 2. Feedback does not exist in Feedback
time period. transmitter or receivers exists in
Each of the sample process uses 1µs and synchronizing transmitter
pulse of 1µs. 3. Per sample 4,8 or 16 bits are Per sample
∴ To locate 25 pulses we can allocate used only one bit is
125 used
= 5 µs 4. PCM requires highest DM requires
25
Since the actual duration of each pulse is 1µs. transmitter bandwidth lowest
transmitter
∴ Spacing between successive pulse must be bandwidth
(5–1)µs = 4 µs 5. Has good signal to noise has poor signal
285. A signal is passed through a LPF with cut-off ratio to noise ratio
frequency 10 kHz. The minimum sampling 288. Which one of the following system gives the
frequency is highest figure-of-merit (a measure of the noise
(a) 5 kHz (b) 10 kHz performance)?
(c) 20 kHz (d) 30 kHz (a) WBFM (b) NBFM
ESE-2013 (c) AM (d) SSB
Ans. (c) : The minimum sampling frequency, ESE-2014
f s( min ) = 2f m Ans. (a) : When spectrum efficiency is important
narrow band FM (NBFM) is used but when better signal
Given that fm = 10 kHz quality is required wideband FM (WBFM) is used at the
Then expense of greater spectrum usage.
f s( min ) = 2 ×10 = 20kHz 289. If the number of bits per sample in a PCM
system is increased from 8 to 16, then the
286. The Nyquist sampling interval, for the signal bandwidth will be increased
sinc (700t) + sin(500t) is (a) 2 times (b) 4 times
1 π (c) 8 times (d) 16 times
(a) sec (b) sec
350 350 ESE-2015
π π Ans. (a) : The bandwidth of PCM system is given by
(c) sec (d) sec BW = nfs
700 175 n = number of bits to encode
ESE-2013 f = sampling frequency
s
Ans. (c) : Here signal is given that, Calculation-
Let, f ( t ) = sin ( 700t ) + sin ( 500t ) For n = 8, the bandwidth will be
Highest frequency component is (700t) BW = 8fs………….(i)
Similarly, for n = 16, the bandwidth will be
means ωm = 700 BW = 16 fs………….(ii)
or 2πf m = 700 So equation (i) and (ii) calculate-
700 Bandwidth is increased by 2 times.
fm = 290. In a PCM system, a five bit-encoder is used. If
2π the difference between two consecutive levels is
1 1 1 V, then the range of the encoder is
Nyquist interval T = =
2f m 2 × 700 (a) 0 - 31 V (b) 0 - 30 V
2π (c) 1 - 32 V (d) 1 - 30 V
ESE-2015
π
= sec Ans. (a) : For an ‘n’ bit encoder, the number of levels
700 will be-
287. Consider the following statements comparing L = 2 n
delta modulation (DM) with PCM system: The range of an encoder is volts can be calculated as-
DM requires 0 ≤ range ≤ ( 2n − 1) × step size
1. A lower sampling rate
Analysis for n = 5,
2. A higher sampling rate The number of levels will be: L = 25= 32
3. A higher bandwidth Given step size = 1V i.e. every successive levels has a
4. Simple hardware difference of 1V between them.
Which of the above statements are correct? ∴ The range of the encoder will be-
(a) 1 and 2 only (b) 2 and 4 only 0V ≤ range ≤ ( 32 − 1) ×1V
(c) 1, 3 and 4s (d) 2, 3 and 4
ESE-2014 0V ≤ range ≤ 31V
Electronics-II 969 YCT
291. The main units in a pulse code modulator are: Ans. (b) : As given BW = 10 kHz
1. Sampler 2. Quantizer BW = 2fm
3. Encoder 4. Comparator Then fm = 5kHz
(a) 1 and 2 only (b) 2 and 3 only Highest frequency = fc + fm = 705 kHz
(c) 1, 2 and 3 (d) 2 and 4 Put fm = 5kHz
ESE-2016 Then fc +5 = 705
Ans. (c) : There are three main units of PCM system- ∴ f c = 700 kHz
1. Sampler 2. Quantizer 3. Encoder 296. In an analog data acquisition unit, what is
292. For long distance communication which of the correct sequence of the blocks starting from the
following data transfer technique is used? input?
(a) Serial transfer (a) Transducer –Recorder –signal conditioner
(b) Parallel transfer (b) Transducer – signal conditioner – Recorder
(c) Serial-Parallel transfer (c) Signal conditioner – Transducer –Recorder
(d) Parallel-Serial transfer (d) signal conditioner – Recorder – Transducer
BSNL TTA 27.09.2016, 3 PM RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
Ans : (a) Serial transmission:- It is normally used for Ans. (b) : Data Acquisition system-
long distance data transfer. It is also used in cases where Physical system → Transducer sensor→ Signal
the amount of data being sent is relatively small. It conditioning → Analog-Digital conditioning →
ensures that data integrity is maintained as it transmits computer.
the data bits in a specific order, one after another, in this A data acquisition system is a collection of
way, data bits are received in sync with one another. measure or control physical characteristics of something
But as only a single data bits is transmitted per clock in the real world.
pulse thus the transmission of data is a quiet time taking 297. Consider the following
process. 1. Pulse-position modulation
2. Pulse code modulation
3. Pulse width modulation
Which of these communications are not
digital?
(a) 1 and 2 (b) 2 and 3
Fig: Serial Communication (c) 1 and 3 (d) 1, 2 and 3
293. Which of the following is considered as an BSNL TTA (JE) 2013
indirect method of generating FM? Ans. : (c) Pulse Code Modulation (PCM) is a digital
(a) Balanced modulator scheme for transferring analog data. In digital
(b) Varactor diode modulator communication, data transferred from point to point or
(c) Armstrong system point to multipoint channel. While pulse position
(d) Reactance modulator modulation (PPM) and pulse width modulation are
RPSC ACF & FRO 23.02.2021 analog in nature.
Ans. (c) : The indirect method called as the Armstrong 298. Which of the following stage has AGC bias?
method of FM generation. In this method, the FM is (a) Local oscillator
obtained through phase modulation. A crystal oscillator (b) Mixer
can be used hence, the frequency stability is very high (c) RF amplifier
and this method is widely used in practice. (d) AFT discriminator
294. Indicate which of the following system is BSNL TTA 27.09.2016, 3 PM
digital: Ans : (c) The AGC bias is a DC voltage proportional to
(a) PPM (b) PCM the input signal strength. It is obtained by rectifying the
(c) PWM (d) PFM video signal as available after the video detector. The
BSNL TTA 25.09.2016, 3:00 P.M. AGC bias is used to control the gain of RF and IF
stages in the receiver to keep the output at the video
Ans : (b) PCM system basic elements are transmitter,
detector almost constant despite changes in the input
transmission path and receiver. It is called digital
signal to the tuner.
system because signal is transmitted in the form of data
(0,1) binary codes. 299. A band-limited signal with bandwidth ‘B’ may
Example- PCM, DM, ADM, ASK, PSK, FSK be reconstructed perfectly from its samples, if
295. For an amplitude modulated signal, the the signal is sampled at a rate _______.
bandwidth is 10 kHz and the highest frequency (a) less than ‘2B’ (b) equal to ‘B’
component present is 705 kHz. The carrier (c) greater than ‘2B’ (d) equal to ‘B/2’
frequency used for this AM signal is DGVCL JE 06.01.2021 Shift-III
(a) 695 kHz (b) 700 kHz Ans. (c) : A band-limited signal with bandwidth ‘B’
(c) 705 kHz (d) 710 kHz may be reconstructed perfectly from its samples, if the
RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II signal is sampled at a rate greater than ‘2B’.
Electronics-II 970 YCT
300. The modulation index of an FM signal, having at m = 0.9
a carrier swing of 100 kHz with modulation 0.92
signal frequency is 8 kHz is I t = Ic 1 +
(a) 6.25 (b) 12.5 2
(c) 16.8 (d) 2.85 It = I c 1.405 .........(ii)
BSNL TTA 28.09.2016, 10 AM Dividing each (i) & (ii)
Ans. (a) : Given, carrier swing = 100 kHz, modulating
12 Ic 1.125
signal frequency (fm) = 8kHz =
Carrier swing = 2 × Frequency deviation I t Ic 1.405
100 = 2 × ∆f It = 13.4 Amp
∆f = 50kHz
∆f 50 XII. Modern Methods of
∵ Modulation index (Mf) = =
fm 8 Communication
Mf = 6.25
1. In a sinusoidal PWM, if the peak of the
301. A broadcast AM radio transmitter radiates 125 triangular carrier wave is coincident with zero
kW when the modulation percentage is 70. of the reference sinusoid, then the number of
How much of this is carrier power? pulses generated in each half cycle is_______
(a) ≈ 25 kW (b) ≈50 kW where 'fc' is the frequency of the carrier wave
(c) ≈75 kW (d) ≈100 kW and 'f' is the frequency of the reference
Mizoram PSC Nov. 2015, Paper-III sinusoid.
Ans. (d) : Given, f f
Total power (PT) = 125 kW, modulation index (a) c (b) c
(ma) = 70% = 0.7, carrier wave power (PC) = ? f 2f
fc fc
 m2  (c) (d)
PT = PC  1 + a  f 2f
 2 
 DGVCL JE 0.5.01.2021, Shift-II
 0.49  Ans. (b) : When the peak of the triangular carrier wave
125 = PC 1 +
2 
is coincident with zero of reference sinusoid wave then
 number of pulse generated in each of half cycle.
125 = PC (1 + 0.245)
125 f
PC = = 100.40kW N= c
1.245 2f
302. Microwave Communication uses ............ 2. Which of the following is NOT an advantage of
amplifier to obtain large gain over wide Pulse Duration Modulation (PDM) recording?
bandwidth : (a) It has a less complex electronic circuitry and
(a) Reflex Klystron therefore the reliability of such system is
(b) Pi–Mode Magnetron high.
(c) Travelling wave Tube (b) It has high S/N ratio.
(d) All of these (c) It has high accuracy due to the fact that it can
BSNL TTA 25.09.2016, 3:00 P.M. be self-calibrated.
Ans : (c) Microwave communication uses travelling (d) It has the ability to simultaneously record
wave tube amplifier to obtain large gain over wide information from a large number of channels.
bandwidth. UPPCL JE- 07.09.2021, Shift-II
303. When a broadcast AM transmitter is 50% Ans. (a) : Another kind of pulse modulation is pulse
modulated, its antenna current is 12A. What duration modulation. In which intelligence is
will be the current when the modulation depth represented by the length and order of regularly
is increased to 90%? recurring pulses.
(a) 13.4 A (b) 12.9 A A familiar example of PDM is - the international morse
(c) 16.6 A (d) 21.8 A code, amateur radio and certain other forms of radio
BSNL TTA 25.09.2016, 3:00 P.M. telegraphy.
Ans : (a)  Signal 
It has high reliability and high   ratio.
m2  Noise 
I t = Ic 1 + and it has the ability to simultaneously record
2 information from a large number of channels.
Where m = modulation index It has high accuracy but can not be self-calibrated.
m1 = 0.5 m2 = 0.9
3. In ____ the information from different
0.52 measuring points is transmitted serially one
I t = Ic 1 + after another on the same communication
2
channel.
12 = I c 1.125 .......(i) (a) time division multiplexing
Electronics-II 971 YCT
 (b) corresponding multiplexing = 125 ×10-6 sec
(c) frequency division multiplexing Ts = 125µsec
(d) rapid division multiplexing
UPPCL JE- 07.09.2021, Shift-II
Ans. (a) : In time division multiplexing the information
from different measuring points is transmitted serial one
after another on the same communication channel.
Time division multiplexing is a method of transmitting and
receiving independent signals over a common signal path
by means of synchronized switches at each end of the 5Tspace = 125µ sec
transmission line so that each signal appears on the line
only a fraction of time in an alternating pattern. 125
Tspace = = 25µ sec
4. Which of the following statements is 5
INCORRECT with regard to 'light'? 7. Which of the following systems is digital?
(a) Light can be of different colours, which depend (a) Pulse-position modulation
on the wavelength of the radiation causing it. (b) Pulse-code modulation
(b) It is a form of electromagnetic energy (c) Pulse-width modulation
radiated from a body which is capable of (d) Pulse-frequency modulation
being perceived by the human eye. NSCL Diploma Trainee 24.02.2021
(c) Light can be described as a vibratory motion, BSNL TTA (JE)- 14.07.2013
which is transmitted in the form of waves Ans. (b) : Modulation can be define as the process of
through space. changing the carrier signal’s parameters by the instant
(d) Light radiations form a very large part of the value of the message signal.
complete range of electromagnetic radiations. The classification of modulation techniques can be
UPPCL JE- 07.09.2021, Shift-II done based on the type of modulation used for instance
Ans. (d) : For light - the digital modulation used PCM or pulse code
* A light can be described as a vibratory motion, which modulation technique.
is transmitted in the form of waves through space. In PCM the message signal can be signified through a
* Light can be of different colours, which depends on series coded pulses so this message signal can be
the wavelength of the radiation causing it. attained through signifying the signals in the form of
* It is a form of electromagnetic energy radiated from a discrete in both time as well as amplitude.
body which is capable of being perceived by the 8. Vestigial side band is most commonly used
human eye. in___
5. __________ can be very small and are usually (a) radio transmission
associated with electronic circuitry such as (b) television transmission
preamplifier and a ADC, so that a single chip (c) telephony
can produce digital audio. (d) All of these
(a) Condenser microphones. JPSC AE 10.04.2021 Paper-I
(b) Carbon microphones. BSNL TTA 29.09.2016, 10 AM
(c) Dynamic microphones. Ans : (b) This VSB (Vestigial side band) modulation is
(d) Silicon microphones. mostly used in television transmission. The transmission
UPPCL JE- 08.09.2021, Shift-I bandwidth of VSB modulated, wave will be the total of
Ans. (d) : Silicon microphones can be very small and message bandwidth and the width of vestigial sideband.
are usually associated with electronic circuitry such as Two guard bands are laid on both the sides of this VSB
pre amplifier and a ADC so that a single chip can signal so as to avoid the interference of signal.
produce digital audio. 9. In PCM, if the number of quantization levels is
6. A Time Division Multiplexing system is used to increased from 4 to 64, then the bandwidth
multiplex four independent voice signals using requirement will approximately be increased––
pulse amplitude modulation. Each voice signal ––– times
is sampled at the rate of 8 kHz. The system (a) 8 (b) 16
incorporates a synchronizing pulse train for its (c) 32 (d) 3
proper operation. What is the timing between JPSC AE 10.04.2021, Paper-I
the synchronizing pulse trains and the impulse BSNL TTA 28.09.2016, 10 AM
trains used to sample the four voice signals? Ans. (d) : Bandwidth for PCM system
(a) 5µs (b) 10µs B = 2nNfm Hz for N >>1, n >>1
(c) 15µs (d) 25µs where, n = number of channel
ESE (Pre) 18.07.2021 N = number of bit
Ans. (d) : Given that, B1 = 2n N1fm
Sampling rate (fs) = 8×103Hz B2 = 2 n N2 fm
1 1 B1 N1
Frame time (Ts) = = =
fs 8 × 103 B2 N 2
Electronics-II 972 YCT
 2 N1 = 4 ⇒ N1 = log 2 2 ⇒ N1 = 2 14. According to the sampling theorem, the
sampling frequency should be
2 N2
= 64 ⇒ N 2 = log 2 , N 2 = 6
6
(a) Greater than twice the highest signal
B1 2 frequency
= ⇒ B2 = 3B1 (b) Less than half the lowest signal frequency
B2 6
(c) Greater than the lowest signal frequency
Therefore bandwidth requirement will approximately be (d) Less than half the highest signal frequency
increased three times. RPSC ACF & FRO 23.02.2021
10. Clamping circuits are employed in Ans. (a) : Sampling Theorem:- In order to recover the
(a) Television, Rectifiers original modulating signal from its sampled version the
(b) Rectifiers, Amplifiers signal must be having a sampling frequency of greater
(c) Amplifiers than or equal to twice of highest modulating frequency
(d) Television component contained in the given signal i.e.
APGCL AM 2021 f s ≥ 2f m : ωs ≥ 2ωm
Ans. (d) : Clamping circuit:- A clamping circuit is a Where, fs = sampling rate
circuit that adds a D.C level to an A.C signal. Actually 15. Which of the following is the correct
the positive and negative peaks of the signals can be statement?
placed at desired levels using the clamping circuit. A If the channel bandwidth doubles, the S/N ratio
clamping circuit are employed in television. becomes
11. In a DM system, the granular noise occurs (a) Double of the former S/N ratio
when modulating signal (b) Square root of the former S/N ratio
(a) increases rapidly (c) Half of the former S/N ratio
(b) decreases rapidly (d) None of these
(c) changes within the step size RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
(d) has high frequency component Ans. (b) : If the channel bandwidth doubles, the S/N
JPSC AE 10.04.2021, Paper-I ratio becomes square root of the former S/N ratio.
16. Which among the device that converts output
Ans. (c) : Granular noise - It can be seen that when the
into a form that can be transmitted over a
original analog input signal has a relatively constant telephone line?
amplitude, the reconstructed signal has variations that (a) Teleport (b) Multiplexer
were not present in the original signal. This is called (c) Concentrator (d) Modem
granular noise. Granular noise in delta modulation is RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
analogous to quantization noise in conventional PCM. Ans. (d) : A modulator-demodulator, or simply a
In a DM system, the granular noise occurs when modem, is a hardware device that converts data from a
modulating signal changes within the step size. digital format intended for communication directly
12. Analog data having highest harmonic at 30 between devices with specialized wiring into one
KHz generated by a sensor has been digitized suitable for a transmission medium such as telephone
using 3-bit PCM. What will be the rate of lines or radio.
digital signal generated? 17. Pulse code modulation is commonly used in
(a) 120 Kbps (b) 355 Kbps telemetry because
(c) 240 Kbps (d) 180 Kbps (a) It ensures immunity from noise during
JPSC AE 10.04.2021, Paper-I transmission
(b) The bandwidth requirement of the channel is
Ans. (d) : Sampling theorem reduced
fs ≥ 2fm : ωs =2ωm (c) It removes quantization error
Where, fs = sampling rate (d) It permits lower rate of sampling than what is
The Nyquist rate of sampling represents the minimum normally required under Shanon's theorem.
rate sampling so that the original signal can be RPSC Lect. (Tech. Edu. Dept.) 16.03.2021, Paper-II
recovered from its sampled version. Ans. (a) : Pulse code modulation (PCM) is one of the
Nyquist rate = 2fs = 2×30 = 60 kHz most widely utilized radio telemetry techniques for the
2n should be greater than or equal to 6. recovery of test data from aero-space vehicles.
Thus, n = 3, bit rate = 60 × 3 = 180 Kbps Synchronization of the receiver with the transmitted
13. The process of converting a discrete signal to data is perhaps the prime requisite of a PCM telemetry
digital form is known as system
(a) Linearization (b) Sampling 18. ..............is mostly preferred for telegraphy–
(c) Quantization (d) None of the above (a) Single tone modulation
JPSC AE 10.04.2021, Paper II (b) On–off keying
(c) Frequency shift keying
Ans. (c) : The process of converting a discrete signal to (d) Pulse code modulation
digital signal form is known as quantization. In this UPPCL JE 11.11.2016
process the value of each signal is represented by a Mizoram PSC IOF 2019 Paper-III
value selected from a finite set of possible. RSMSSB JEN (PHED) Degree 26.12.2020
Electronics-II 973 YCT
Ans : (c) Frequency-shift keying (FSK) is a frequency 22. Calculate the Nyquist rate for sampling when a
modulation scheme in which digital information is continuous time signal is given by:-
transmitted through discrete frequency changes of a x(t) = 5 cos 100πt +10 cos 200πt – 15 cos 300πt
carrier signal. (a) 100 Hz (b) 150 Hz
This technology is used for communication such as (c) 300 Hz (d) 600 Hz
telegraphy, caller ID and emergency broadcasts." UPPCL JE 2018, Shift-II
Ans. (c) : For the given signal-
100π 200π
f1 = = 50Hz , f2 = = 100Hz
2π 2π
300π
f3 = = 150Hz
2π
The highest frequency is 150 Hz. Therefore
fmax= 150 Hz
Nyquist rate = 2fmax
= 2×150=300Hz
23. A line trap in carrier current relaying tuned to
carrier frequency present
(a) Low impedance to both carrier and power
frequency
(b) High impedance to carrier frequency and low
impedance to power frequency
19. In PCM system, if the quantization levels are (c) High impedance to both carrier and power
increased from 2 to 8, the bandwidth frequency
requirement will : (d) Low impedance to carrier frequency and high
(a) remain same (b) be doubled impedance to power frequency
(c) be tripled (d) become four times UGVCL JE 2012
BSNL TTA (JE) 27.09.2016, 10 AM Ans. (b) : A line trap, also known as wave trap or high
BSNL TTA (JE) 2013 frequency stopper, is a maintenance free parallel
Ans. (c) Bandwidth B = log2 L resonant circuit, mounted in line on high voltage. It is a
L = quantization level parallel tuned circuit containing inductance and
B log 2 8 capacitance. It has low impedance for power frequency
n= 2 = and high impedance to carrier frequency.
B1 log 2 2
This unit prevents the high frequency carrier signal
=
( log 2 2 ) 3log 2 2
3

= =3
from entering the neighbouring line.
1 log 2 2 24. Flat top sampling leads to
n = 3 times (a) an aperture effect (b) aliasing
(c) loss of signal (d) None of these
20. At microwave frequencies, the size of the
antenna becomes KPTCL JE 2016
(a) Very large (b) Large Ans. (a) : Flat top sampling of low pass signal give rise
(c) Small (d) Very Small to aperture effect.
KSEB Sub Engineer 2015 In delta modulation system, granular noise occurs when
the modulating signal remain constant e.g. A PAM
Ans. (d) : Size of Antenna depends upon wavelength. signal can be detected by using Low Pass Filter.
C 25. The material used for making optic-fibre cable
λ ↓=
f↑ in general is-
Microwave frequency are beyond MHz or infact GHz (a) Steel (b) Copper
very high i.e. f ↑, λ↓ i.e. size of Antenna becomes (c) Aluminium (d) Transparent plastic
smaller. RRB JE 01.09.2019 Shift-I
Ans. (d) : The material used for making optic-fibre
21. Calculate the minimum sampling rate to avoid
cable in general is transparent plastic.
aliasing when a continuous time signal is given
by:- x(t) = 5 cos 400πt 26. In data communications, which of the following
(a) 100 Hz (b) 250 Hz methods convert digital data in the form of a
(c) 400 Hz (d) 20 Hz sequence of bits to a digital signal?
UPPCL JE 2018, Shift-II (a) Line coding (b) Convolution coding
Ans. (c) : In the given signal, the highest frequency is (c) Block coding (d) Nonlinear encoding
BSPHCL JE 31.01.2019 Shift-I
400π
given by f = = 200Hz Ans. (a) : A line code is the code used for data
2π transmission of a digital signal over transmission line.
The minimum sampling rate required to avoid aliasing This process of coding with a chosen so as to avoid
is given by Nyquist rate. The nyquist rate is = 2f overlap and distortion of signal such as inter-symbol-
= 2×200=400Hz interference.
Electronics-II 974 YCT
27. Which of the following allows data transmission 31. For a standard telephone circuit with a signal-
in both the directions simultaneously? to-noise power ratio of 1000 (30dB) and a
(a) Half-duplex transmission bandwidth of 2.7 kHz, the Shannon limit for
(b) Full-duplex transmission information capacity is
(c) Simplex transmission (a) 27 Mbps (b) 27 kbps
(d) Full-simplex transmission (c) 2.7kbps (d) 2.7 Mbps
BSPHCL JE 31.01.2019 Shift-I BSNL TTA 29.09.2016, 3 pm
Ans. (b) : In full-duplex transmission system, both S
parties can communicate with each other Ans : (b) Given, B = 2.7 kHz, =1000
simultaneously. There is a two way, communication N
channel between them. A duplex communication The Shannon limit for information capacity is as-
system is a point-to-point system composed of two or  S
C = B log2 1 + 
more connected parties or devices that can  N
communicate with one another in both directions. So, C = 2.7 × 103 log2 (1001) = 2.7×103 log2 210
28. Which of the following is not a standard Baud C ≃ 2.7 × 103 × 10 = 27 kbps
Rate?
(a) 2500 (b) 4800 32. Quantization noise occurs in
(c) 1200 (d) 9600 (a) Time division-multiplex
UPPCL JE 27.11.2019, Shift-II (b) Frequency division multiplex
(c) Pulse position modulation
Ans. (a) : Standard Baud Rates:- 110, 300, 600, (d) Pulse code modulation
1200, 2400, 4800, 9600, 14400, 19200, 38400, 57600,
BSNL TTA 29.09.2016, 3 pm
115200, 128000 and 256000 bits per second.
Ans : (d) Quantization noise occurs when an analog
29. The baud rate–
(a) Is always equal to the bit transfer rate signal is converted into its digital form, thus it occurs in
(b) Is equal to twice the bandwidth of an ideal pulse code modulation.
channel 33. (i) PCM is inherently most noise resistant (ii)
(c) Is not equal to the signaling rate PCM requires small BW. Indicate the right
(d) Is equal to one–half the bandwidth of an ideal answer :
channel (a) True, False (b) False, False
BSNL TTA 29.09.2016, 3 pm (c) False, True (d) True, True
Ans : (b) The baud rate of a data communication BSNL TTA 29.09.2016, 3 pm
system is the number of symbols per second transferred. Ans : (a) (i) PCM is inherently most noise resistant and
It is equal to twice the bandwidth of an ideal channel. it requires large bandwidth.
30. A 3000 Hz bandwidth channel has a capacity of 34. An online, real time data transmission system
30 kbps. The signal to noise ratio is is most likely to require a connection that is
(a) 20dB (b) 25dB (a) Duplex (b) Semiduplex
(c) 30dB (d) 40dB (c) Time shared (d) None of these
BSNL TTA 29.09.2016, 3 pm BSNL TTA 29.09.2016, 3 pm
Ans : (c) Channel capacity can be given as Ans : (b) An online, real time data transmission system is
 S most likely to require a connection that is semi duplex.
C = B log 2 1 +  Semi-duplex channel is a single physical channel in which
 N direction of transmission can be reversed.
S 35. In case of modems ADSL stands for
Where B = Bandwidth and is signal to noise ratio.
N (a) Asynchronous Digital Subscriber Line
Given, (b) Asymmetrical Dynamic Subscriber Link
B = 3000 Hz, C = 30 kbps (c) Asymmetric Digital Subscriber Line
then (d) Asynchronous Data Service Line
 S BSNL TTA 29.09.2016, 3 pm
30000 = 3000 log2 1 + 
 N  Ans : (c) In case of modems ADSL stands for
Asymmetric digital subscriber Line. It is a type of
 S
10 = log 2  1 +  digital subscriber line (DSL) technique which is a data
 N communication technology.
 S 36. CSMA/CD Stands for
210 = 1 + 
 N  (a) Collision sense multiple access .carrier
S Defection
= 2 − 1 = 1023 ≃ 103
10
(b) Carrier sense multiple access/collision detection
N (c) Collision sense media access/carrier detection
Signal to noise ratio in dB - (d) Carrier sense media access/collision detection
S S BSNL TTA 29.09.2016, 3 pm
= 10log10
N dB N Ans : (b) CSMA/CD Stands for carrier sense multiple
access/collision detection. To deal with collisions it is
= 10log10 103 = 30 dB
used in ethernet as the MAC protocol.

Electronics-II 975 YCT

37. How many bits are required in an A/D (a) 7 (b) 9
converter with a B+1 quantizer to get a signal- (c) 11 (d) 13
to quantization noise ratio of at least 90 dB for ESE 2019
a Gaussian signal with range of ± 3σx? Ans. (c) : Given accuracy = 0.1% of maximum value.
(a) B + 1 = 12 bits (b) B + 1 = 14 bits
∆ 0.1
(c) B + 1 = 15 bits (d) B + 1 = 16 bits Hence, = × A max
ESE 2019 2 100
Ans. (d) : Vp− p = 6σ x 2A max 0.1
= × A max
for Gaussian variable mean mx = 0 2 × 2n 100
Signal power = mean square value  2A max 
S = m 2x + σ 2x = σ2x ∵Step size, ∆ = 2n 
 
∆2 2 n ≤ 1000
Noise power =
12 2 n ≤ 210
Vp− p 6σ n ≃ 11
∆ = n = nx
2 2 40. If 'N' signal are multiplexed using PAM band
 36 σ2x  3σ2x limited to fM' the channel bandwidth need not
Noise power =  2n /12  = 2n be larger than
 2  2
f
(a) N. M (b) N.fM
σ2x 22n 2
SNR = =
 3 σ2x  3 (c) 2N.fM (d) N2.fM
 2n  ESE 2019
 2  Ans. (b) : Bit Rate = f × N
S
SNR in dB = 10 log10 2 2n − 10log10 3 = (6n – 4.8) dB Where fS = 2fm
Given, SNR ≥ 90 dB Bit Rate = 2Nfm
6n − 4.8 ≥ 90 B.W. = 2Nfm
n ≥ 15.8 So bandwidth need not be larger than Nfm.
n = 16 41. In a time division multiplexing, there are 8000
Number of bits required = 16 samples for a digital signal-0 channel that uses
38. The noise variance σε2 at the output of 8 kHz sample rate and 8 bit PCM code. The
0.5z line speed will be
H(z)= with respect to input will be nearly.
z - 0.6 (a) 56 kbps (b) 64 kbps
(a) 40% (b) 50% (c) 76 kbps (d) 84 kbps
(c) 60% (d) 70% ESE 2020
ESE 2019 Ans. (b) : Speed of communication in Time division
Ans. (a) : By considering the noise having zero mean, multiplexing (TDM) ⇒ Rb = Nnfs
Variance = power Number of signals multiplexed is not given, so that
Given, TDM is normal PCM only, where only one signal is
0.5z
H (z) = transmitted,
z − 0.6n Rb = nfs (∵ N = 1)
h(n) = 0.5(0.6) u(n) =8×8k
If input, x(n) = δ (n) = 64 kbps
then output, y(n) = h(n) = 0.5(0.6)n u (n)
42. For an 8-PSK system, operating with an
Input energy,
∞ ∞ information bit rate of 24 kbps, the band rate
∑
n =−∞
y 2
(n) = ∑
n =−∞
h 2
(n) will be
(a) 16,000 (b) 12,000
∞ (c) 8,000 (d) 6,000
= ∑ 0.25 × ( 0.36 )
n
ESE 2020
n =0
Ans. (c) : Given,
0.25 0.25
= = = 0.4 Rb = 24 kbps
1 − 0.36 0.64
output energy = 40% of input energy Rb
Band rate Br =
output power = 40% of input power log 2 M
39. The discrete samples of an analog signal are to M=8 (for 8-PSK)
be uniformly quantized for PCM system. If the 24 kbps
maximum value of the analog sample is to be Br =
log 2 8
represented within 0.1% accuracy, then
minimum number of binary digits required will = 8 kbps
be nearly Br = 8,000
Electronics-II 976 YCT
43. LASER stands for: 47.Which of the following gives maximum
(a) Light Amplification by Stimulated Emission probability of error
of Radiation (a) ASK (b) FSK
(b) Light Amplification by Saturation Emission (c) PSK (d) DPSK
of Radiation. BSNL TTA (JE) 25.09.2016, Shift-I
(c) Light Amplified by Stimulated Emission of Ans. (a) : ASK (Amplitude shift keying) gives maximum
Radiation errors probability and has high bandwidth and low noise.
(d) Light Amplified by Saturated Emission of The chances of errors in FSK and PSK are very low and
Radiation their bandwidth is high. PSK has low probability of error
DFCCIL 30.09.2021, 4:30 PM to 6:30 PM hence it is used in most of applications.
Ans. (a) : LASER stands for Light Amplification by 48. As compared to PPM, the disadvantage of
Stimulated Emission of Radiation. A LASER is a PDM is that it requires –––––––––
device that emits light through a process of optical (a) more samples per second
amplification based on the stimulated emission of (b) pulses of larger width
electromagnetic radiations. (c) powerful transmitter
44. One disadvantage of adaptive delta modulation (d) none of these
over linear delta modulation is that it BSNL TTA (JE) 25.09.2016, Shift-I
(a) requires more bandwidth Ans. (c) : As compared to PPM, the disadvantage of
(b) is more vulnerable to channel errors
PDM is that it requires powerful transmitter.
(c) requires a large number of comparators in the
Pulse-density modulation, or PDM, is a form of
encoder
modulation used to represent an analog signal with a
(d) is not suitable for signals with periodic
binary signal.
components
Pulse-position modulation (PPM) is a form of signal
Mizoram PSC Nov. 2015, Paper-III
modulation in which M message bits are encoded by
Ans. (c) : One disadvantage of adaptive delta transmitting a single pulse in one of possible required
modulation over linear delta modulation is that it time shifts.
requires a large number of comparator in the encoder.
49. The maximum speed at which the data can be
45. Which of the following modulation techniques transmitted on standard PCM stream is
is mostly used in inverters? (a) 64 kbps (b) 128 kbps
(a) Pulse width modulation (c) 2 Mbps (d) 4 Mbps
(b) Square wave output modulation BSNL TTA (JE) 25.09.2016, Shift-I
(c) Both (a) and (b)
(d) Neither (a) nor (b) Ans. (d) : The maximum speed at which the data can
UKPSC JE 2013, PAPER-II be transmitted on standard PCM stream is 4Mbps.
Ans. : (a) Pulse width modulation- In pulse width 50. Quadrature multiplexing
modulation the width of each pulse is proportional to (a) Same as FDM
the instantaneous value of the modulating signal. (b) Same as TDM
(c) A combination of FDM and TDM
(d) The scheme where same carrier frequency is
used for two different signal
BSNL TTA (JE) 2013
Ans. : (d) Quadrature multiplexing is the scheme where
same carrier frequency is used for two different signal.
51. The bandwidth of an n-bit binary coded PCM
signal for an original signal bandwidth of B Hz
is:
46. In delta modulation, the slope overload (a) B Hz (b) nB Hz
distortion can be minimised by- (c) (B/N) Hz (d) n2B Hz
(a) Decreasing the step size BSNL TTA (JE) 2013
(b) Keeping the step size constant Ans. : (b) Bit rate of a PCM signal can be calculated
(c) Keeping the step size zero form of bits per sample × the sampling rate
(d) Increasing the step size
BSPHCL JE 30.01.2019, Shift-II Bit rate = nb × f s
Ans. (d) : In delta modulation, the slope overload nb → no. of bit
distortion can be minimized by increasing the step size
but increase in step size increase granular noise. fs → frequency (2fm)
1
Bandwidth = × (Data Rate)
2
1
= × n × 2B
2
BW = nB Hz
Electronics-II 977 YCT
52. In a PCM system of telemetry, the quantization
noise depends on-
(a) The sampling rate and quantization levels
(b) The sampling rates only
(c) The number of quantization levels only
(d) Acoustics noise
BSNL TTA (JE) 2013
Ans. : (c) In a PCM system of telemetry , the
quantization noise depends on the number of
quantization levels only. 57. HART is a digital communication protocol for
∆ sending and receiving information. It uses
Maximum quantization error, q = which of the following current loop standards?
2
(a) 50 - 80 mA (b) 40 - 100 mA
Vmax − Vmin
∆ = step size = (c) 4 - 20 mA (d) 120 - 140 mA
L BSNL TTA (JE) 27.09.2016, 10 AM
Where, L= 2n Ans. (c) : HART is a digital communication protocol
V − Vmin for sending and receiving information. It uses 4-20 mA
q = max
2L current loop standards.
So, quantization error depend only number of level. HART means Highway Addressable remote transmitter.
53. In pulse code modulation (PCM), what is the 58. The main advantage of time division
correct sequence of steps before a PCM signal multiplexing (TDM) over frequency division
is generated: Filtering (F), Quantization (Q), multiplexing (FDM) is that it
and Sampling (S) (a) Requires less bandwidth
(a) FQS (b) FSQ (b) Requires less power
(c) QSF (d) SFQ (c) Requires simple circuitry
BSNL TTA (JE) 14.07.2013 (d) Provide better signal-to-noise ratio
Ans. : (b) In pulse code modulation (PCM) the correct ESE-2013
sequence is filtering(f) → Sampling (s) → Quantization Ans. (d) : The main advantage of time division
(Q), multiplexing (TDM) over frequency division multiplexing
before a PCM signal is generated. (FDM) is that it provide better signal-to-noise ratio.
54. Which of the following systems is most noise 59. In PCM system, if the code word length is
immune? increased from 6 to 8 bits, the signal to
(a) SSB (b) FM quantization noise ratio improves by the factor-
(c) PCM (d) PAM (a) 8/6 (b) 12
BSNL TTA (JE) 14.07.2013 (c) 16 (d) 8
Ans. : (c) PCM (pulse code modulation) is most noise BSNL TTA 26.09.2016, 10 AM
immune. PCM is digital scheme for transmitting analog Ans. (c) : Code word length (n1) = 6
data. It convert analog signal into digital signal then (n2) = 8
transmit. As we know that,
55. Quantization noise is produced in Signal to quantization noise ratio (SQNR) = 22n
(a) PAM (b) PM ( SQNR )1 22×6 212 1
∴ = = =
(c) PPM (d) PCM
BSNL TTA (JE) 14.07.2013
( SQNR )2 22×8 216 24
Ans. : (d) Quantization error is produced in PCM. (SQNR )2 = 16 ( SQNR )1
Quantization error is the difference between analog Thus we can say that the signal to quantization noise
signal to the closed available digital signal at each ratio (SQNR) improves by the factor 16.
sampling. 60. During the heterodyne process in reciever, the
56. Pulse Shaping in line coding is used for: modulation of the signal –––––––––
(a) Using Optimum Power Consumption (a) Decreases
(b) Using Optimum Bandwidth (b) Remains unaffected
(c) Maximize Inter symbol Interference (c) Increases
(d) Simplicity of Circuits (d) Is eliminated
BSNL TTA (JE) 27.09.2016, 10 AM BSNL TTA 26.09.2016, 10 AM
Ans. (b) Pulse shaping in line coding is used for Ans. (b) : Heterodyning is a signal processing technique
optimum bandwidth. that creates new frequencies by combining or mixing
In electronics and telecommunication, pulse shaping is two frequencies. It is used for shifting one frequency
the process of changing the waveform of transmitted range to another frequency.
pulses. Its purpose is to make the transmitted signal It is used in the process of modulation and
better suited to its purpose or the communication demodulation.
channel. Typically by limiting the effective bandwidth Thus during the heterodyne process in the receiver, the
of the transmission. modulation of the signal is not affected.

Electronics-II 978 YCT

61. The disadvantage of FSK is that ––––––––– sampling rate
(a) It does not provide sufficient S/N ratio f s ≥ 2f m
(b) It does not have low error probability fs ≥ 2 × 4 = 8 KHz
(c) It is not efficient in use of spectrum space transmission rate
(d) None of these r = Nfs
BSNL TTA 26.09.2016, 10 AM = 4 × 8kHz
Ans. (c) : Frequency shift keying (FSK) is a frequency r = 32Kbits/sec.
modulation scheme in which digital information is 65. The number of symbols in quadrature phase
transmitted through discrete frequency change of a
shift keying is-
carrier signal. FSK uses large bandwidth compare to
other modulation techniques such as ASK and PSK. (a) Two (b) Four
Hence it is not bandwidth efficient. (c) Eight (d) Sixteen
Bandwidth of FSK =(F1–F2)+2Rb BSNL TTA 28.09.2016, 3 PM
Where, Rb = bit rate Ans. (b)– One of the most common and simplest
BWASK < BWPSK<BWFSK modulation methods is known as QPSK (quadrature
62. If the synchronization between transmitter and phase shift keying) every two input bit will map to one
receiver fails which of the following pulse of four symbols.
systems would be affected? Constellation size and bit rate-
(a) PAM (b) PDM Modulation Possible number Bits per Transmitted
(c) PPM (d) None of these
BSNL TTA 26.09.2016, 10 AM Type of symbol Symbol bit Rate
Ans. (c) : In PPM (pulse position modulation) system as Q − PSK 22 = 4 2 2 × Symbol rate
the position of the PPM pulses is varied with respect to
8 − PSK 23 = 8 3 3 × Symbol rate
a reference pulse, a transmitter has to send
synchronizing pulse to operate the timing circuits in the 16 − QAM 24 = 16 4 4 × Symbol rate
receiver, without them, the demodulation would not be 64 − QAM 6 6 × Symbol rate
2 = 64 6
possible to achieve. Thus we can say that if the
synchronization between transmitter and receiver fails 256 − QAM 28 = 256 8 8 × Symbol rate
then PPM pulse systems would be affected.
66. PSK is ––––––––type of modulation.
63 . Pulse code modulation employing 4 bit code is (a) Analog (b) Digital
used to transmit a data signal having frequency (c) Amplitude (d) Angle
components from dc to 2 kHz. The minimum
bandwidth of the carrier channel should be- BSNL TTA 28.09.2016, 3 PM
(a) 2 kHz (b) 4 kHz Ans. (b) – Phase shift keying (PSK):- Although phase
(c) 8 kHz (d) 16 kHz modulation is used for some analog transmission, it is
BSNL TTA 26.09.2016, 10 AM more widely used as a digital form of modulation where
Ans. (c) :Given, Number of bit (n) = 4 it switches between different phases. This is known as
Modulating frequency (Fm) = 2 kHz phase shift keying.
Signal frequency (fs) = 2Fm, 67. Introduction of parity bit for error detection
fs = 2×2 = 4 kHz does not imply-
Signaling rate (R) = nfs = 4 × 4 (a) Increase in the lengths of the code
= 16 kHz (b) Increase in the hardware of system
So, (c) Automatic error correction
R (d) All the above
Minimum bandwidth ( B.W ) =
2 BSNL TTA 21.02.2016
16 kHz Ans : (c) Introduction of parity bit for error detection
= does not imply automatic error correction. The parity
2
B.W. = 8 kHz bit is only suitable for detecting errors, it can not
64. In a PCM system the number of quantization correct any errors.
levels are 16 and the maximum signal 68. Spread-spectrum multiplexing is also known
frequency is 4 kHz, the bit transmission rate is as-
(a) 64kbits/sec (b) 32kbits/sec (a) Time division multiplexing
(c) 16kbits/sec (d) 32 bits/sec (b) Frequency division multiplexing
BSNL TTA 28.09.2016, 10 AM (c) Code division multiplexing
MPPEB SUB. Engineer 08.07.2017 shift -I (d) All the above
Ans. (b) Given, L = 16, fm = 4 kHz BSNL TTA 21.02.2016
We know L = 2N
where, N = number of bit in codeword Ans : (c) Spread - spectrum multiplexing is also known
16 = 2N as code division multiplexing. Multiple users can
24 = 2N transmit simultaneously in the same frequency band as
N = 4 bits long as they use different spreading sequences.
Electronics-II 979 YCT
69. The bit rate of digital communication system is (a) Noise power (N0)
34 M bits/sec. The modulation scheme used is (b) Peak signal energy (Emax)
QPSK. The baud rate of the system is- (c) N 0
(a) 8.5 M bit/sec (b) 17 M bit/sec
(c) 34 M bit/sec (d) 68 M bit /sec (d) E max
BSNL TTA 21.02.2016 ESE-2004
Ans : (b) Given, Ans. (d) : We know that, the probability error for PCM
Bit rate = 34M bits / sec  1 E max 
1
system Pe = erf c 
Baud rate of QPSK =
Bit rate
2  2 N 
 0 
2
Hence, Probability error in PCM is proportional to
34
= M bit / sec E max .
2
= 17 M bit/sec 75. The maximum number of quantized amplitude
70. Companding is used in PCM to- levels, in a 3-digit ternary PCM system can be
(a) Reduce bandwidth used to represent is
(b) Reduce power (a) 8 (b) 9
(c) Increase S/N ratio (c) 27 (d) 81
(d) Get almost uniform S/N ratio ESE-2002
BSNL TTA 26.09.2016, 3 PM Ans. (a) : Number of quantization level in n-bit PCM
Ans : (d) For digital audio signals, companding is used = 2n
in pulse code modulation (PCM). The process involves n = number of bits = 3 = 23
decreasing the number of bits used to record the =8
strongest signals and to get almost uniform signal to 76. The impact of rains on microwave
noise (S/N) ratio. communication is higher in :
71. In PCM system encoder- (a) Lower Frequency Range
(a) Assignes quantized values (b) Medium Frequency Range
(c) No Impact at all
(b) Changes quantized value to binary value
(d) Higher Frequency Ranges
(c) Changes quantized value to numerical value
BSNL TTA 25.09.2016, 3:00 P.M.
(d) Changes numerical values to binary values
BSNL TTA 26.09.2016, 3 PM Ans : (d) High frequency signals travel quickly in dry
and clean weather. When rain comes it moistures the air
Ans : (b) In PCM system encoder changes quantized and air becomes humid and wet. This obstructs the path
value to binary value. The output of a PCM will of microwave signals. So high frequency signals will be
resemble a binary sequence. much effected than low frequency signals.
72. A scheme in which several channels are 77. Satellite used for intercontinental
interleaved and then transmitted together is communications are known as -
known as? (a) Comsat (b) Domsat
(a) Frequency division multiplexing (c) Marisat (d) Intelsat
(b) TDM Mizoram PSC IOF 2019, Paper-III
(c) A group
Ans. (d) : Intel sat-It is a kind of communication for
(d) a super group intercontinental services.
BSNL TTA 26.09.2016, 3 PM Comsat- A global telecommunication
Ans : (a) A scheme in which several channels are inter Marisat- The global satellite for telecommunication of
leaved and then transmitted together is known as marine transport.
frequency division multiplexing. In frequency division 78. Which of the following pulse modulation
multiplexing signals occupy a range of frequency and systems is analog?
two adjacent signals are separated by guard band to (a) PCM (b) Differential PCM
prevent mixing. All the multiplexed signals are then (c) PWM (d) Delta
transmitted simultaneously. Mizoram PSC IOF 2019, Paper-III
73. The maximum speed at which the data can be Ans. (c) : PWM is the powerful technique for
transmitted on each channel of a standard controlling analog circuit with microprogram digital
PCM stream is? output. PWM is employed in a wide variety of
(a) 64 kbps (b) 128 kbps application like measurement of communication,
(c) 2 Mbps (d) 4 Mbps conversion and process control.
BSNL TTA 26.09.2016, 3 PM
79. If the number of bits per sample in PCM
Ans : (a) In standard PCM stream, each channel system is increased from n to n+1, then the
transmits data at maximum speed of 64 kbps.
improvement in signal to quantization noise
74. Which one of the following statement is ratio will be-
correct? (a) 3 dB (b) 6 dB
In PCM, the conditional probability of error is
(c) 2n dB (d) 0 dB
proportional to
Mizoram PSC IOF 2019, Paper-III
Electronics-II 980 YCT
Ans. (b) : ( SQNR )dB = (1.78 + 6n ) dB 83. Quadrature amplitude modulation is a
combination of.................
Given that, PCM increase from = n to n + 1
(SQNR)1 = 1.76 + 6n ––––(i) (a) PSK & FSK (b) ASK & FSK
(SQNR)2 = 1.76 + 6 (n + 1) ––––(ii) (c) ASK & ICW (d) ASK & PSK
Subtract Equation from (ii) to (i) BSNL TTA 27.09.2016, 3 PM
(SQNR)2 – (SQNR) = 1.76 + 6n + 6 – 1.76 – 6n Ans : (d) Quadrature Amplitude Modulation
= 6dB (QAM):- It is possible to combine ASK, FSK and PSK.
80. In single pulse modulation of PWM inverters, One benefit of combining different modulation method
the pulse width is 1200. For an input voltage of is to increase the number of symbols available,
220 V dc, the r.m.s value of output voltage is - increasing the number of available symbols is a
(a) 179.63 V (b) 254.04 V standard way to increase the bit rate, because increasing
(c) 127.02 V (d) 185.04 V the number of symbols increase the number of bits per
Mizoram PSC IOF 2019, Paper-III
symbol. It is rare of all three methods to be combined,
Ans. (b) : Given to d = 2π/3 but very common for ASK and PSK to be combined to
VS = 220 V create QAM.
2d
V0 = Vs ×
π
 2 × 2π  4
= 220 ×   = 220×
 π×3  3
= 254.04 V
81. In a single phase modulation of PWM
inverters, third harmonics can be eliminated if
pulse width is equal to -
(a) 300 (b) 600 Fig: Basic QAM I-Q modulator circuit
0
(c) 120 (d) 1500 84. PSK and FSK are which type of modulation?
Mizoram PSC IOF 2019, Paper-III (a) Analog modulation
Ans. (c) : To eliminate nth harmonic nd = π (b) Digital modulation
π π (c) Both analog modulation and digital
∴d = = = 600
n 3 modulation
2d = 1200 (d) None of these
82. What is the difference of UART and USART BSNL TTA 27.09.2016, 3 PM
communication Ans : (b) Amplitude shift keying (ASK) frequency shift
(a) they are the names of the same particular keying (FSK) and phase shift keying (PSK) are digital
thing, just the difference of A and S is there modulation scheme
in it FSK -
(b) one uses asynchronous means of FSK refer to a type of frequency modulation that
communication and the other uses
assigns bit values to discrete frequency levels FSK is
synchronous means of communication
(c) one uses asynchronous means of divided into non coherent and coherent forms.
communication and the other uses PSK-
synchronous and asynchronous means of PSK is a digital transmission refers to a type of angle
communication modulation. In which phase of the carrier is descretely
(d) one uses angular means of communication and varied.
the other uses linear means of communication 85. Noise temperature of sun is more than ____K.
BSNL TTA 29.09.2016, 10 AM (a) 1000 (b) 5000
Ans : (c) UART v/s USART:- (c) 100000 (d) 500
UART:- UPPSC AE 13.12.2020, Paper-II
• The full name is Universal Asynchronous
Ans. (c) : Noise temperature of sun is more than
Receiver/Transmitter
100000 K.
• UART supports lower data rate.
• UART is simple protocols. 86. A speech signal is sampled at 8 kHz and
USART:- encoded in PCM format using 8-bit/sample
• The full name is Universal synchronous PCM data is transmitted through a baseband
/Asynchronous Receiver/transmitter. channel via 4-level PAM. Minimum bandwidth
• The synchronous data is transmitted block wise. required for transmission is
• USART can also generate data similar to UART. (a) 16 kHz (b) 8 kHz
Hence USART can be used as UART but reverse is (c) 24 kHz (d) 10 kHz
not possible. UPPSC AE 13.12.2020, Paper-II
Electronics-II 981 YCT
Ans. (a) : Given, Ans. (b) : Bandwidth required to transmit a baseband
Speech signal frequency of sampling(fs)= 8kHz binary signal with ideal Nyquist pulse shaping is
Number of levels (M) = 4 R
Number of bits (n) = 8 bit/sample BW = B0 = b Hz
Bit rate (Rb) = nfs 2
Rb = 8×8 = 64kb/sec 2048
Hence, B0 = = 1024kHz
R / 2 64 / 2 2
Minimum bandwidth = b = It is the minimum theoretical bandwidth required to
log 2 M log 2 4
transmit any baseband digital signal.
( B.W )min = 16kHz 91. The pulse width modulation control technique
87. Time division multiplexing requires in inverters is used for :
(a) Constant data transmission (a) Voltage control
(b) Transmission of data samples (b) Frequency control
(c) Transmission of data at random (c) Harmonic reduction
(d) Transmission of data of only one measured (d) Voltage control and harmonic reduction
BSNL TTA (JE) 2013
DMRC JE 2015
Ans. : (b) Time division multiplexing (TDM) is a
technique by which one data signal can be transmitted Ans. (d) : The pulse width modulation control
over a common communication channel in different technique in inverters is used for voltage control and
time slot. So TDM requires transmission of data harmonics reduction. A inverter is a power electronics
samples. device that change the direct current to alternating
88. FDM is an analog multiplexing technique used current. The input voltage, output voltage and frequency
to combine and overall power handling on inverter. Inverter is
(a) Analog signals single phases and three phase.
(b) Digital signals 92. Good voice reproduction via PCM requires 128
(c) Both analog and digital signals quantization levels. If bandwidth of voice
(d) Alternatively passes analog and digital signal channel is 4 kHz, then data rate is
UPPSC AE 13.12.2020, Paper-II (a) 250 kbps (b) 128 kbps
Ans. (a) : FDM is an analog multiplexing technique (c) 56 kbps (d) 28 kbps
used to combine analog signals. FDM is a technique by ESE-2012
which the total bandwidth available in a communication
medium is divided into a series of non-overlapping Ans. (c) : Given that,
frequency bands, each of which is used to carry a Quantization levels Q = 128
separate signal. Bandwidth (BW) = 4 kHz
89. Broad-band frequency over power line can be Q = 2n
obtained by using following modulation: Where Q is quantization levels and n is the number of
(a) Phase modulation. bits/sample.
(b) Orthogonal frequency division multiplexing ∴ 128 = 2n
(OFDM) n=7
(c) Amplitude modulation (AM). bit rate = 2 × bandwidth
(d) Frequency modulation (FM). ∴ bit rate= 2 × 4 = 8 kbps
HPPSC PWD AE 24.08.2021
Data Rate = n × bit rate
Ans. (b) :
Broad-band Frequency over power line can be Hence data rate = 7 × 8 = 56 kbps
obtained by using orthogonal frequency division 93. In high speed TDM, the channels are separated
multiplexing (OFDM). in the receiver employing
Orthogonal Frequency Division Multiplexing (a) OR gate (b) NAND gate
(OFDM) is a digital multi-carrier modulation (c) NOR gate (d) AND gate
scheme that extends the Concept of Single ESE-2011
Subcarrier modulation by using multiple subcarriers Ans. (d) : In high speed TDM, the channels are
within the same single channel.
separated in the receiver employing AND gate.
OFDM is based on the well known technique of
Frequency Division Multiplexing (FDM). 94. A binary channel with capacity 36 kbps is
90. A 20 channel PCM system has a bit rate of available for PCM transmission. If signal is
2048 kbps. What is the frequency band band limited to 3.2 kHz, then approximate
required for the PCM signal as per the first values of quantizing levels (L) and sampling
Nyquist criteria? frequency (fS) respectively are
(a) 512 kHz (b) 1024 kHz (a) 32 and 3.6 kHz (b) 64 and 7.2 kHz
(c) 2048 kHz (d) 4096 kHz (c) 64 and 3.6 kHz (d) 32 and 7.2 kHz
BSPHCL JE 31.01.2019 Shift-I ESE-2012
Electronics-II 982 YCT
Ans. (d) : Given channel capacity (C) = 36 kbps Ans. (a) : Data rate supported by standard Ethernet is
Bandwidth (B) = 3.2 kHz 10 Mbps. The most popular physical layer for Ethernet
We know that channel capacity use is LAN technology. It defines the number of
C = 2 B log2 L conductors that are required for the connection, the
36 ≥ 2 × 3.2 × log2 L performance pressures that can be expected, and
45 provides the frame network for data transmission.
log2 L ≤
8 99. The standard value of sampling rate of audio
L ≤ 49.35 frequency signal is.................
Hence from options (a) 4000 samples per second
L = 32 (b) 8000 samples per second
L = 2n = 32 (c) 10000 samples per second
n= 5 (d) 16000 samples per second
Sampling frequency BSNL TTA 26.09.2016, 3 PM
r 36 ×103 Ans : (b) The standard values of the sampling rate are 8
fs = b = = 7.2 kHz kHz for audio frequency signal (telephone
n 5
communications), 44.1 kHz for music CDs and 48 kHz
95. Quantizing noise occurs in
for audio tracks in movies.
(a) Pulse width modulation
(b) Frequency division multiplexing 100. Which one of the following statement is
(c) Pulse code modulation correct?
(d) Time division multiplexing Quantizing noise is produced in
ESE-2011, 2005(a) All pulse modulation systems
Ans. (c) : Quantizing noise occurs in PCM due to (b) PCM
quantization of sampled values to a certain fix levels. (c) All modulation systems
Quantization noise is a model of quantization error (d) FDM
introduced by quantization in the analog to digital ADC ESE-2004
Ans. (b) : In PCM, quantization noise results when a
or PCM. It is a rounding error between the analog input
continuous random variable is converted to a discrete
voltage to the PCM and the output digitized value.
96. The most noise immune system is one or when a discrete random variable is converted to
(a) SSB (b) PCM one with fewer levels.
(c) PDM (d) PWM 101. To overcome slope overload problem, which
ESE-2010type of the integrator is used in delta
Ans. (b) : PCM is most noise immune system. modulation?
Advantages of PCM are- (a) Fixed slope integrator
Robustness to channel noise. (b) Variable slope
Efficient regeneration of the coded signal along the(c) Linear slope integrator
channel path. (d) Bipolar integrator
Uniform format for different kind of base band ESE-2005
signals. Ans. (b) : A solution to this slope overload issue is an
97. Which one of the following adaptive delta modulation. In this implementation of an
pulse
communications systems is digital? ADM, slope overload is eliminated by using digital
(a) PAM (b) PCM logic to adjust the step size of the integrator used to
(c) PDM (d) PWM construct the reference voltage signal.
102. Which of the following is the modulating signal
ESE-2011
Ans. (b) : in SPWM?
(a) Sinusoidal (b) Square
(c) Triangular (d) Saw-tooth
UPRVUNL JE -21.10.2021,9 am-12 pm
Ans. (a) : Sinusoidal is the modulating signal in
SPWM.
103. Automatic meter reading can be done with:
(a) Automatic System for Mobile
Communication
(b) Global System for Mobile Communication
• PCM is digital communication technique. (c) Automatic System for Mobile Network
98. Data rate supported by Standard Ethernet is (d) Global System for Mobile Network
(a) 10 Mbps (b) 100 Mbps UPRVUNL JE -21.10.2021,9 am-12 pm
(c) 1000 Mbps (d) 10 Gbps Ans. (b) : Automatic meter reading can be done with
BSNL TTA 28.09.2016, 10 AM Global System for Mobile Communication.
Electronics-II 983 YCT