Microprocessor/Microcontroller
Architecture
Chapter 2
References
Computers as Components, Marilyn Wolf,
2012, The Morgan Kaufmann Series in
Computer Architecture and Design
Introduction to Embedded Systems, EA
Lee, SA Seshia, 2012, UC Berkeley
Real Time Embedded Systems, Sam Siewert,
2007, Charles River Media
Computers
General purpose computers
Mainly interacting with humans
Keyboard, Mouse, Display, Touch-screen, Audio
Wide range of software, often by third-parties
Special purpose computers
Limited or no interaction with humans
Limited resources (processing power, memory)
Sensors and actuators
Specialized software (usually no third party software)
Architecture wise, both types of computers are similar
Embedded systems are special purpose computers
Embedded Systems
➢ What is an embedded system?
– An embedded system is a special purpose computing system which is
completely encapsulated by the device it controls. It is a combination
of hardware and software and works in a reactive and time-
constrained environment as a part of a larger system.
➢ What are the major components of an embedded?
– Hardware
– Software: Application/Programming software
– RTOS: Real Time Operating System
– Mechanical components/Peripherals
Computer Architecture
Processor or the Central Processing Unit (CPU)
Memory
Main memory (Random Access Memory or RAM)
Read only memory (Basic System Software, BIOS)
Cache (memory inside the processor)
Peripherals (Input/Output devices)
Human interaction
Secondary storage (Hard Disks, Other storage devices)
Sensors, Actuators
Note: Processor Components
Arithmetic and Logic Unit (ALU)
Performs operations like add, subtract, compare, etc
General purpose registers (a.k.a. register file)
used for storing operands and results of the ALU operation
Special purpose registers
Program counter (PC) keeps track of the address of the next instruction
to be executed
Processor Status Register (PSR) records the current status of the register
Registers are memory-mapped: has an address in memory
space (can be referred by mnemonic name or its address)
Control unit
Issues signals to control the other units
Note: Processor Components …
Data path
ALU, Registers, Buses
Control path
Control unit and control signal lines going to various units in the data
path
Control signal examples
Output contents of register r1 onto Bus A
Output contents of register r2 onto Bus B
Perform ADD operation in the ALU
Store the ALU output into register r3
Note: Memory Organization
Memory consists of many
millions of cells (0 or 1)
A word is a group of n bits,
word length can be 16 to 64
bits
Memory is a collection of
consecutive words
of the size specified by the
word length
Each location in memory has
an address
No of bits in an address
defines address range, or
address space
Note: Memory Organization …
Address space may be
divided into several
segments
Some address range used for
ROM
Some for RAM
Some for I/O devices
Some processors have
multiple address spaces
Separate address spaces for
programs, data, I/O devices
Note: Memory Organization …
A common word length is
32 bits
Such a word can store a 32-bit
signed integer or four 8-bit
bytes (e.g., ASCII characters)
For 32-bit integer encoding,
bit b31 is sign bit
Words in memory may store
data or machine instructions
for a program
Each machine instruction
may require one or more
consecutive words for
encoding
Note: Memory/Processor Interaction
Read operation
Processor provides the address via the address bus
Processor indicates read operation using the R/W control line
Memory provides the data on the data bus, after some time (access
delay)
Write operation
Processor provides the address via the address bus and the data to be
written via the data bus
Processor indicates write operation using the R/W control line
After some time the specified data is written at the specified address
Memory is generally slower compared to the processor
Read/Write operations may need multiple processor clock cycles
Processor must hold address and or data on the respective buses for
long enough for the memory to complete the operation
Note: Memory/Processor Interconnection
Address bus
Data bus (bidirectional)
Read/Write control line
Read operation: memory retrieves
contents at address location
given by processor
Write operation: memory
overwrites contents at given
location with given data
Note: Memory Access Timing (READ)
Note: Memory Access Timing (WRITE)
Note: Stack Pointer
Stack Pointer (SP) is a special purpose register
Consider the following code segment
x=b+c
y = sin(x)
z=d+e
This would get translated into machine language and
loaded into memory
Evaluation of the function sin(x) would be done as a
subroutine
Program flow
Jump to subroutine
Evaluate function
Return from subroutine and continue the main program
Note: Stack Pointer …
We use a “Stack” to facilitate subroutine calls
Stack is a reserved section of memory
Before calling the subroutine/function
Push the current value of PC onto the stack
Also may push arguments for the subroutine
Within the subroutine
Pop the arguments out of the stack (if applicable)
May use the stack for further subroutine calls
Return from subroutine
Pop the saved value of PC onto the PC
Now the program can continue from where it stopped
Stack pointer always points to the top of the stack
Depending on the processor, the stack may grow towards increasing
addresses or decreasing addresses
Processor Architecture
Processor can be described at different levels
Circuit level (Transistors, Diodes, Resistors, ….)
Logic level (Logic gates, Flip-flops, ….)
Register Transfer Level (Registers, ALU, …)
Instruction Set Architecture (ISA)
A register transfer level description of the processor giving just
enough details to be able to write programs using the instruction set
of the processor
Serves as an interface between software and hardware
Provides a mechanism by which the software tells the hardware what
should be done
Von Neumann vs. Harvard Architectures
Von Neumann Harvard
Single address space for Separate address spaces for
program and data program and data
I/O devices also use the Two physically separate
same address space memories
Possible to access both
memories independently
In some cases, a third
separate address space for
I/O devices is used
Commonly used in Digital
Signal Processors (DSPs)
Better performance possible
(greater memory bandwidth)
CISC vs. RISC (Instructions/Execution)
CISC: Complex RISC - Reduced
Instruction Set Computer Instruction Set Computer
Many addressing modes Single instruction format of
(multiple instruction formats fixed length
of different lengths) Memory access is done only
Many operations by Load and Store
(add contents of memory All other instructions take
location X to content of operands from registers
memory location Y and store Large number of general
result in memory location Z) purpose registers
Complex instructions Pipelining of CPU is easier,
CPU logic becomes complex resulting in faster execution
times
Instruction Set Characteristics
The instruction set of the computer defines the interface
between software modules and the underlying hardware
Fixed versus variable length
Addressing modes
Numbers of operands
Types of operations supported
High level language code : C, C++, Java, Fortran,
compiler
Assembly language code: architecture specific statements
assembler
Machine language code: architecture specific bit patterns
software
instruction set
hardware
Word Length
The size of words that a processor is designed to operate
on (8-bit, 16-bit, 32-bit, 64-bit etc)
width of general purpose registers, and width of the
internal data buses is equal to processor word length
The operands for the ALU operations cannot be longer
than the word length
Memory word length need not be the same
e.g. It is possible to have a 32-bit processor (word length = 32 bits),
but memory organized as 8-bit memory words
Byte addressable
Assigns an address to each byte
Assuming a word length is 32 bits, word locations have addresses 0, 4,
8, …
Big- and Little-Endian Addressing
Two ways to assign byte address across words
Big-endian addressing assigns lower addresses to more
significant (left most) bytes of word
Little-endian addressing uses opposite order
Commercial computers use either approach, and some
can support both approaches
Addresses for 32-bit words are still 0, 4, 8, …
Bits in each byte labeled b7 … b0, left to right
Big- and Little-Endian Addressing …
Instructions and Sequencing
Instructions for a computer must support:
Data transfers to and from the memory
Arithmetic and logic operations on data
Program sequencing and control
Input/output transfers
Processor does nothing but executing instructions
Instruction Cycle
Instruction fetch: Bring the content of memory address
indicated by the Program Counter (PC) into the
Instruction Register (IR)
Instruction decode: Decode the instruction to
understand it
Operand fetch: If the instruction requires operands to be
fetched from memory, bring them into some registers
Execute: Feed the operands to the ALU and perform the
operation (only if the instruction involves an
arithmetic/logic operation)
Store the result: Save the result in the specified register
or the specified memory location
Instruction Formats
Instructions are stored in memory
As a collection of “1”s and “0”s
The processor must be capable of interpreting the 1s and
0s (decode the instruction)
It must know the instruction format
There may be more than one instruction format for a particular
processor
Instructions have a OP-CODE (operation code) and one
or more “operands”
Instruction Format Example
OPCODE (4 bits)
0100 means add, 0101 means subtract, …
Operand1, Operand2, Destination (4 bits each)
0000 means register0, 0001 means register1, ….
Add contents of r1 and r2 and save result in r3
0100 0001 0011 0010
Assembly Language
Processor understands binary instructions (Machine Language)
Difficult to write programs in binary
Use “Assembly Language” to represent binary instructions to
make it easier for humans to understand
0100 0001 0011 0010 in Machine Language
ADD r3, r1, r2 in Assembly Language
An assembler compiles programs written in assembly language
and converts it to machine language that the processor
understands
Commercial processors use mnemonics, usually abbreviations (e.g., LD, ST,
and ADD)
Mnemonics differ from processor to processor
Addressing Modes
Addressing modes provide compiler with different ways to
specify operand locations
Immediate: Operand value is given as part of the instruction
Register: Operand is to be taken from a register. The
instruction specifies the register(s)
Direct: Address of the operand is given in the instruction.
The instruction length must be sufficiently long to include
the operand address
Indexed: Address of the operand is the content of a
register (base register) plus a displacement. The displacement
can be an immediate value or given by another register
Useful in accessing array elements
Register Indirect: Operand address is given in the register
Addressing Modes …
Addressing Modes - General Examples
For the following fundamental addressing modes, we’ll show “pseudo” assembly language usage
Assume all addresses are 16-bits, and all memory and CPU registers are 16-bits wide.
Mode 1: Immediate—the operand itself (not the address of the operand) is part of the
instruction. This mode is useful for initializing registers with address or data constants in programs.
Memory Addr Addr Contents
Instruction
0x017A add
r0, #0xA39D 0x0178 ------
0x0179 ------
• Compile the example instruction into 0x017A opc r0 reg/imm one
the appropriate memory locations 0x017B 0xA39D instruction
Note that since the immediate operand is 0x017C ------
16-bits long, it is placed at memory 0x017D ------
location 0x017B, a “trailing word.”
Thus, this is a “two-word” instruction.
• What is the “address” of the operand that is added to R0?
• What is the “value” of the operand that is added to R0?
Ref: CSULB –Examples of Addressing Modes © 2014 -- R.W. Allison
Addressing Modes - General Examples
Mode 2: Direct—the instruction contains the address of the operand. Direct addressing may also
be referred to as "absolute" addressing. The address must be known at compile time.
Memory Addr Addr Contents
Instruction
0x017A add
r0, @0xA39D 0x0178 ------
0x0179 ------
• Compile the example instruction into 0x017A opc r0 reg/dir one
the appropriate memory locations 0x017B 0xA39D instruction
Note that since the direct address is 16-bits 0x017C ------
long, it is placed at memory location 0x017B, 0x017D ------
a “trailing word.”
Again, this is a “two-word” instruction. : :
0xA39C ------
• What is the “address” of the operand that is added to R0? 0xA39D 0xBC5F
• What is the “value” of the operand that is added to R0? 0xA39E ------
:
Ref: CSULB –Examples of Addressing Modes © 2014 -- R.W. Allison
Addressing Modes - General Examples
Mode 3: Register Indirect—specifies the register holding the address of the operand. This addressing
mode is used to access memory operands pointed to by “base pointers” that are stored in registers
Memory Addr Addr Contents
Instruction
0x017A add
r0, [r7] 0x0178 ------
0x0179 ------
• Compile the example instruction into 0x017A opc r0 r7 reg/regi
one
instruction
the appropriate memory locations 0x017B ------
Note that since the R7 contains the 16-bit 0x017C ------
address, there is no “trailing word.” 0x017D ------
Thus, this would be a “one-word” instruction.
: :
• What is the “address” of the operand that is added to R0? 0x875E ------
This can’t be answered without knowing the contents of R7. 0x875F 0x10D5
For this example, let’s assume R7 = 0x875F 0x8760 ------
• What is the “value” of the operand that is added to R0? :
Ref: CSULB –Examples of Addressing Modes © 2014 -- R.W. Allison
Addressing Modes - General Examples
Mode 4: Base (Indexed) — a variation of register indirect mode, where the effective address of the
operand is calculated by the addition of a "base" register and a offset (signed displacement) included as a
field in the instruction. We could name this mode as “Register Indirect with Offset.”
Addr Contents
Memory Addr
Instruction
0x017A add r0,
0x0178 ------
[r7+ 0xA39D]
0x0179 ------
• Compile the example instruction into 0x017A opc r0 r7 reg/base one
the appropriate memory locations 0x017B 0xA39D instruction
Although R7 contains the 16-bit “base address,” 0x017C ------
the 16-bit offset must be in a “trailing word.” 0x017D ------
Thus, this would be a “two-word” instruction.
: :
• What is the “address” of the operand that is added to R0? 0xBA9C ------
This can’t be answered without knowing the contents of R7. 0xBA9D 0x5A17
For this example, let’s assume R7 = 0x1700 0xBA9E ------
• What is the “value” of the operand that is added to R0? :
Ref: CSULB –Examples of Addressing Modes © 2014 -- R.W. Allison
Addressing Modes - General Examples
Mode 5: PC Relative — a variation of “base mode,” where the effective address of the operand
(typically an address to jump to) is calculated by the addition of the current PC and a offset (signed
displacement) included as a field in the instruction.
Addr Contents
Memory Addr
Instruction
0x017A jmp [PC 0x0178 ------
+ 0x439D] 0x0179 ------
• Compile the example instruction into 0x017A opc PC_rel one
the appropriate memory locations 0x017B 0x439D instruction
Although PC contains the 16-bit “base address,” 0x017C ------
the 16-bit offset must be in a “trailing word.” 0x017D ------
Again, this would be a “two-word” instruction.
: :
• What is the “address” to jump to? 0x4518 ------
Based on all the info given above, 0x4519 instr we’ll jmp to
you should be able to answer this 0x451A ------
PC 0x017C + 0x439D :
Ref: CSULB –Examples of Addressing Modes © 2014 -- R.W. Allison
Addressing Modes - General Examples
Mode 5: PC Relative — a variation of “base mode,” where the effective address of the operand
(typically an address to jump to) is calculated by the addition of the current PC and a offset (signed
displacement) included as a field in the instruction.
Addr Contents
Memory Addr
Instruction
0x017A jcs [PC 0x0178 ------
+ 0x439D] 0x0179 ------
• Compile the example instruction into 0x017A opc PC_rel
the appropriate memory locations 0x017B 0x439D
The difference between this example and the 0x017C ------
previous one is that the “jmp” here is conditional. If 0x017D ------
the C-flag is set, the PC changes; if the C-flag is clear,
the PC does not change. : :
• 0x4518 ------
What “address” does the PC get if C=1?
0x4519 instr we’ll jmp to
PC 0x017C + 0x439D 0x451A ------
• :
What “address” does the PC get if C=0?
PC 0x017C
Ref: CSULB -–Examples of Addressing Modes © 2014 -- R.W. Allison
PIC16F Architecture
PIC-Peripheral Interface Controller from Microchip Technology.
PIC processors include several different families
Varying capacities and data path sizes
PIC16F family is the mid range family
8 bit architecture (word size = 8 bits)
Instructions are 14 bits longs
Harvard architecture
Program memory word size is 14 bits
Up to 8192 words of instructions memory
Data memory word size is 8 bits
Byte addressable
368 bytes in SRAM
256 bytes in EEPROM data memory
PIC16F Instruction Space
Program Counter is 13 bits wide
Instruction space
2k, 4k or 8k instructions depending on the model
Lowest addresses hold the interrupt vectors
Rest of memory divided into 4 pages
Low end devices have only page 0
Mid range can access pages 0 and 1
High end have access to all pages
Stack
Implemented as a “hardware stack”, and does not occupy a portion of
the instruction address space
Stack pointer is not readable nor writable
Circular buffer of size 8 – when the stack overflows a previously
written value is overwritten
PIC16F Instruction Space …
PIC16F Data Space
Data space
Divided into 4 banks
Two bits of the status register RP<1:0> selects which bank is used
General Purpose Register means a data memory location
Special Purpose Registers + General Purpose Registers are collectively called the Register
File (file registers)
In other words, data memory = register file
Some of the data space unimplemented in some processors
Special Function Registers
Lowest 32 or 16 locations depending on the bank
Addresses 0x00 to 0x1F, ...
CPU Registers, registers related to the I/O devices
General Purpose Registers
All the remaining locations of each bank
Addresses 0x20 to 0x7F, ….
Last 16 of these locations (0x70 to 0x7F) common in all 4 banks
PIC16F Instruction Set
35 Instructions
18 byte oriented operations
4 bit oriented operations
13 control and literal operations
Operands and destinations
W refers to the accumulator
f refers to one of the file registers (7 bits, 0x00 to 0x7F)
b refers to a particular bit in a register (3 bits, bit 0 to 8)
k refers to a literal (immediate operand) – 8 bits for data instructions
and 11 bits for CALL / GOTO instructions
For instructions involving two operands, one operand always comes
from the W register (accumulator)
Other operand comes from a file register, or as a part of the
instruction (literal, or immediate operand)
PIC16F Addressing Modes
Immediate (literal)
Direct Address
When f is any value other than 0x00 (f - register file)
Can access a special function register as well as a general purpose
register
Indirect Address
When f has value 0x00
Uses INDF and FSR registers
INDF is not an actual register
Accessing INDF register means accessing the memory location (a
register in PIC terminology) pointed to by FSR register
PIC16F Addressing Modes …
PIC16F Program Counter
The low byte PC<7:0> comes from the PCL register,
which is a readable and writable register.
The high byte (PC<12:8>) is not directly readable or
writable and comes from PCLATH
On any reset, the PC is cleared
Modifying PC
During a write to PCL, (executing any instruction with f=
0x02), all 13 bits of the PC will change
PCLATH<4:0> → PCH
ALU Output → PCL
During a CALL or GOTO instruction
PCLATH<4:3> → PCH<4:3>
IR<10:0> → PCH<2:0>,PCL
PIC16F Program Counter …
PIC16F Instructions
Most instructions take only one instruction cycle to
complete
One instruction cycle = 4 Q cycles
Q1: Instruction Decode Cycle or forced No Operation
Q2: Instruction Read Cycle or No Operation
Q3: Process the Data
Q4: Instruction Write Cycle or No Operation
Please refer the PIC16F Instruction Set document
