Buses Protocols
Buses Protocols
The basic building block of most bus protocols is the four-cycle handshake, illustrated in
Figure 2.1. The handshake ensures that when two devices want to communicate, one is
ready to transmit and the other is ready to receive.
The handshake uses a pair of wires dedicated to the handshake: enq (meaning enquiry) and
ack (meaning acknowledge). Extra wires are used for the data transmitted during the
handshake. The four cycles are described below.
Device 1 raises its output to signal an enquiry, which tells device 2 that it should get
ready to listen for data.
When device 2 is ready to receive, it raises its output to signal an acknowledgment. At
this point, devices 1 and 2 can transmit or receive.
Once the data transfer is complete, device 2 lowers its output, signaling that it has
received the data.
After seeing that ack has been released, device 1 lowers its output.
At the end of the handshake, both handshaking signals are low, just as they were at the start
of the handshake. The system has thus returned to its original state in readiness for another
handshake-enabled data transfer.
Microprocessor buses build on the handshake for communication between the CPU and
other system components. The term bus is used in two ways.
The most basic use is as a set of related wires, such as address wires. However, the term may
also mean a protocol for communicating between components.
To avoid confusion, we will use the term bundle to refer to a set of related signals. The
fundamental bus operations are reading and writing. Figure 2.2 shows the structure of a
typical bus that supports reads and writes.