Microprocessor :8086 and

6 Modern Microprocessor
Unit-IV

Syllabus :
Evolution of Microprocessor and type, 16 bit Microprocessor - 8086, Features of 8086, pin diagram and architecture
timing
of 8086, Flag register and segment registers of 8086, Minimum mode and maximum mode of operation,
Pentium Family
diagram, concept of memory segmentation and pipelining, physical address generation. Overview of
length, addressing
and Processors, Characteristics of RISC processor, CISC with RISC in terms of Instruction set,
modes.

The 4004 processor, used in a hand-held calculator built by

Syllabus Topic : Evolution of Microprocessor
Busicom of Japan, was part of a four chip set called the 4000
Family :
$.1 Evolution of Microprocessor 4001 -2,048-bit ROM memory
4002 - 320-bit RAM memory
The first microprocessor was the Intel 4004, produced in
1971, 4003 - 10-bit l/O shift register
Originally developed for a calculatorand revolutionary for its 4004 -4-bit central processor
time, it contained 2,300 transistors on a 4-bit microprocessor
Intel 8008 (1972) :
that couid perform only 60,000 operations per second.
The first 8-bitmicroprocessor was the Intel 8008, developed. The 8008 increased the 4004's word length from four to eight..
in 1972 to un computer terminals. bits, and doubled the volume of information that could be
The Intel 8008 contained 3300 transistors. processed.

The first truly general-purpose microprocessor, developed in It was still an invention in search of a market however, as the
1974, was the 8-bit Intel 8080, which contained 4,500 technology world was just beginning to view the
transistors and could execute 200,000 instructions per second. microprocessor as a solution to many needs.
By 1989, 32- bit microprocessors containing 1.2 milion 8080 (1974) :
transistors and capable of executing 20 million instructions
per second had been introduced. The 8080 were 20 times as fast as the 4004 and contained
Microprocessors are fabricated using techniques similar to twice as many transistors.
those used for other integrated circuits, such as memory This 8-bit chip represented a technological milestone as
chips. engineers recognized its value and used it in a wide variety of
Microprocessors generally have a more complex structure products.
than do other chips, and their manufacture requires extremely It was perhaps most notable as the prOcessor in the first kit
precise techniques. computer, the Altair, which ignited the personal computing
The first step in producing a microprocessor is the creation of phenomenon.
an ultrapure silicon substrate, a silicon slice in the shape of a
round wafer that is polished to a mirror-like smoothness. 8088 (1979) :
At present, the largest wafers used in industry are 300mm Created as a cheaper version of Intel's 8086, the 8088 was a
(12 in) in diameter. 16-bit processor with an 8-bit external bus.
Intel 4004 (1970) : This chip became the most ubiquitous in the computer
industry when IBM chose it for its first PC.
Intel's Ted Hoff and Federico Faggin designed and The success of the IBM PC and its clones gave Intel a
implemented (respectively) the first general-purpose dominant position in the semiconductor industry.
microprocessor.
2 Digi. Tech. and Microprocessor (TISem 3/MSBTE) 6-2 Microprocessor : 8086 &Modern Microprocessor
It provides consumers great performance at an exceptional
80286 (1982) : value, and it delivers excellent performance for uses such as
With 16 MB of addressable memory and 1GB of virtual gaming and educational software
memory, this 16-bit chip is referred to as the first "modem"
microprocessor.
Pentium ll(1999) :
Many noices were introduced to desktop computing with a The Pentium IIprocessor features 70 new instructions.
"286 machine" and it became the dominant chip of its time. It was designed to significantly enhance Internet experiences,
It contained 130,000 transistorsS and packed serious compute allowing users to do such things as browse through realistic
power (12 MHz) into a tiny footprint. online museums and stores and download high-quality video.
The processor incorporates 9.5 million transistors using 0.25
80386 (1985), 80486 (1989): micron technology.
climb with
The pricelperformance cçrve continued its steep
that broughtreal Pentium llI Xeon(1999):
the 386 and later the 486 --32-bit processors
computing to the masses.
The Pentium IIXeon processor extends Intel's offerings to
The 386, which became the best-selling microprocessSor in the workstation and server market segments, providing
than a
history, featured 275S,000 transistors; the 486 had more additional performance for e-Commerce applications and
million. advanced business computing.
The processors incorporate the Pentium II processor's 70
Pentium (1993) : SIMD instructions, which enhance multimedia and streaming
Adding systems-level characteristics to enormous raw video applications.
compute power, the Pentium supports demanding VO, The Pentium II Xeon processor's advance cache technology
speeds information from the system bus to the processor,
graphics and communications intensive applications with
more than 3 million transistos. significantly boosting performance.
It is designed for systems with multiprocessor configurations.
Pentium Pro (1995) :
Intel's Pentium-4 processor :
The newest Pentium has dynamic instruction execution and
The Pentium-4 is fabricated in Intel's 0.18-micron CMOS
other performance-enhancing features such as a large L2
cache in the chip package, in addition to its more than 5.5 process.
million transistors. Its die size is 217 mm2 and power consumption is 50W.
The Pentium 4is available in 1.4GHz and 1.5Hz bins.
Pentium Il (1997) : At 1.5GHz, the microprocessor delivers 535 SPECint2000
The 7.5 million-transistor Pentium I processor incorporates and 558 SPECfp2000 of performance.
Intel MMXTM technology, which is designed specifically to Currently it is the second-performing general-purpose
process video, audio and graphics data efficiently. microprocessor.
The world champion is Compag/Digital Alpha 21264B CPU
Pentium lIl Xeon (1998): delivering 544 SPECint2000 and 658SPECfp2000 at
The Pentium II Xeon processors are designed to meet the 833 MHZ.
performance requirements of mid-range and higher servers The previous Intel chip, Pentium-II "Coppermine", had 442
and workstations. SPECint2000 and 335 SPECfp2000 results at 1GHZ.
Consistent with Intel's strategy to deliver unique processor Pentium-4 is the first completely new x86-processor design
products targeted for specific markets segments, the Pentium from Intel since the Pentium PRO processor, with its P6
II Xeon processors feature technical innovations specifically micro-architecture, was introduced in 1995. Pentium-4'
designed for workstations and servers that utilize demanding micro-architecture is known as NetBurst. It has many

business applications such as Internet services, corporate data interesting features.

warehousing, digital content creation, and electronic and Compared to the Intel Pentium-III processor, Intel's NetBurst
mechanical design automation. micro-archiecture doubles the pipeline depth to 20 stages.
Systems based on the processor can be configured to scale to In addition to the LI 8 KB data cache, the Pentium 4
four or eight processors and beyond. processor includes an Execution Trace Cache that stores up to
12 Kdecoded micro-ops in the order of program execution.
Celeron (1999) : The on-die 256KB L2-cache non-blocking, 8- way set
associative.
Continuing Intel's strategy of developing processors for
specific market segments, the Intsl Celeron processer is It employs 256-bit interface that delivers datatransfer rate of
designed for the value PC market segment. 48 GB/s at 1.5 GHz.
 Microprocessor: 8086 &Modern
Digi. Tech. and Microprocessor (|T/Sem 3/MSBTE)
The Pentium 4 processor expands the floating point registers
6-3

2
MicroproceSSOr
Reduced Instruction Set Computer (RISC):
to a full 128-bit and adds an additional register for data
movement. Pentium-4 NetBurst micro-architecture RISC is a type of microprocessor architecture which to
introduces Internet Streaming SIMD Extensions 2(SSE2). highly-optimized set of instructions. RISC reduces the cycl
This extends the SIMD capabilities that MMX technology per instruction at the cost of the number of instructione
and SSE technology delivered by adding 144 new program.
instructions. Pipelining is one of the cxclusive feature of RISC which i
These instructions include 128-bit SIMD integer arithmetic done by overlapping the execution of several instructions in .
and 128-bit SIMD double-precision floating-point operations.
pipeline style. It has a high-performance advantage over
Pentium 4 processor's 400 MHz (100 MHz "quad pumped") CISC.
system bus provides up to3.2 GB/s of bandwidth.
The bus is fed by dual PC800 Rambus channel. This 3 Superscalar Processors :
compares to 1.06 GB/s delivered on the Pentium-II
processor's 133-MHz system bus. A superscalar processor can execute more than one
Two Arithmetic Logic Units (ALUs) on the Pentium 4 instruction per clock cycle. As processing speeds are
measured in clock cycles persecond (megahertz), a
processor are clocked at twice the core processor frequency. superscalar processor will be faster than a scalar processor
This allows basic integer instructions such as Add, Subtract, rated at the same megahertz.
Logical AND, Logical OR, etc. to execute in a half clock
cycle. A superscalar architecture contains parallel execution units.
which can execute instructions símultaneously. Pentiüm
The integer register file runs also runs at the double
processors are the example of superscalar processor.
frequency.
Interesting is that this method was firstly introduced by 4. Application SpecificIntegrated Circuit (ASIC):
Elbrus team in their E2K processor design.
This type of processors are designed and used for specific
application such as automotive emissions control,
Syllabus Topic : Types of Microprocessor environmental monitoring, and personal digital assistants
computers (PDACS). ASICs can be very cost effective for
6.1.1 Types of Microprocessor various applications where volumes are high.

There are five types of microprocessors as described below : ’ 5. Digital Signal Processors (DSP) :

Types of Microprocessor Digital Signal Processors are microprocessors specially

designed to tackle Digital Signal Processing tasks such as
high-speed data manipulations, and is used in audio,
1. Complex Instruction Set Computer (CISC) communicatíons, image manipulation, and other data
acquisition and data-control applications.
2. Reduced instruction Set Computer (RISC) A digital signal processor is designed to perform
3. Superscalar Processors mathematical functions rapidly. The signals are handled so
the information contained in them can be displayed or
4. Application Specific Integrated Circuit (ASIC) converted to another type of signal. A Digital Signal
Processor (DSP) can process data in real time, creating them
5. Digital Signal Processors(DSP) perfect for applications that can't bear delays.
Fig. 6.1.1 : Types of Microprocessor
Syllabus Topic: 16 bit Microprocessor-8086
1, Complex Instruction Set Computer (CISC) :
This type of architecture is used for microprocessor design. 6.1.2 16 bit Microprocessor- 8086
The CISC architecture comprises a large set of computer The 8086 is the first 16-bit microprocessor developed in 1978
instrkctions that range from very simple to very complexX and by an Intel Corporation.
dedicated sacrificing the number of cycles per instruction The 8086
required for execution. microprocessor has a much more powerful
instruction set along with the architecture developments,
Microprocessors based on the CISC architecture are designed which provides programming flexibility and improves the
to minimize the memory cost as the big speed of operation as compare to 8-bit microprocessor.
programs need more
memory, thus increasing the memory cost and large memory The 8086 is a 16-bit HMOS microprocessor. It is available in
becomes more expensive. To resolve these difficulties, the a 40pin IC and operates at 5 volts DC supply.
Dumber of instructions per program can be reduced by Its electronic circuitry consists of 29000 transistos. It is
embedding the number of operations in a single instruction, implemented in N-channel, silicon gate technology and
hence it makes the instructions more complex available in three version i.e. 8086(5 MHz), 8086-2(8 MHz)
and 8086-1(10 MHz).
( Digi. Tech. and Microprocessor (T/Sem 3/MSBTE) 6-4
Microprocessor : 8086 &Moden Microprocessor
The 8086 microprocessor is no longer used, but the concept
of its principles and structure is very much
useful for the Syllabus Toplc Pin Diagram
understanding of other advanced Intel microprocessors.
The 8086 have 20 address lines using which
we can interface 6.2.1 Pin Diagram and Description of 8086
address up to 1 MB
n20= 1MB of memory mean it can
S-11, S-12, S-14
memory.
lines are multiplexed with MSBTE Questions
Outof 20 address lincs, 16 address 0.1 List all the signals of 8086 in minimum mode and
AD-AD.
data line and named as maximum modes.
multiplexed with status (S-11)
Remaining four address lines are also
Q. 2 Draw a neat labeled pin diagram of 8086. Explain
signals. the functions of minimum mode pins of 8086.
Syllabus Topic : Features of 8086 (S-11, S-14)
Q.3 State the function of 1ollowing pins of 8086.

6.2 Salient Feature of 8086 () TEST (ü) READY (ii) BHE

Microprocessor (iv) ALE (v) DT/R (vi) RD
W-08, S-09, W-11, S-12, W-12, S-13 (vi) INTA (ix) NMI
(vi) DEN
MSBTE Questions (W-11, S-14, S-15)
microprocessor. S1
0.1 List any four features of 8086 Q.4 State all the control signals generated by S0,
(W-08) and S2 with their functions. (W-14)
8086
Q. 2 List any four advantages of 8086
microprocessor. Q.5 State the function of following pins of
(S-09, S-12) microprocessor.
memory which can be (ü) DT/R
Q.3 State the maximum size of ALE
interface to 8086. Give reason for it. (W-11)
(ii) MIO (iv) HOLD (W-14)
Q.4 State any eight features of 8086. (W-11)
(W-12,S-13) Q. 6 State the functions of pins of 8086: MN (S-15)
Q.5 List any eight features of 8086.
Provides 20 address lines so, IMbytes of memory can be Q.7 Explain maskable and non-maskable interrupt used
in 8086. (S-15)
addressed.
Multiplexed 16 bit address and data bus AD, - ¨D, to The Fig. 6.2.1 shows the pin diagram of 8086 microprocessor.
minimize numbers of pin on IC.
Operating clock frequencies are 5MHz, 8MHz, 10 MHz. GND
16 bit 9 ADis Multiplexed Address /Data pin
Arithmetic operation can be performed on 8bit AD,
signed and unsigned data incluing muitipication and AD;s
division. ADp
Can operate in single processor and multiprocessor AD,,
configuration i.e. operating modes. ADn 6 5 AgSs
AD, 7
The instruction set is powerful, flexible and can be
language. AD 8 33 MNMX Select minimum/ maximum mode
programmed in high level language like C Mutiplexed
Provides 256 types of vectored software interrupts. Adoress and AD 32RD
data bus AD, 10 31 RQGT, (HOLD)
8086
Provide 6 byte instruction queue for pipelining of instructions 11 CPU 30 AO/GT, (HLDA)
UUUUUTUTUU AD.
execution.
AD, 12 29 LOCK (WA)
Generate 8 bit of 16 bit I/O address so it can access maximum
AD, 13 28 S, (MIÖ)
64 k I/O devices. AD 14 27 (DTIR)
Operaie in maximum and minimum mode to achieve high AD 15 2 (DEN)
performance level. AD 16 (ALE)
Supports 24 operands addressing modes. Intemupt NMI 17 2 (INTA)
Snpports multiprogramming. pins INTR 18 Tes -Minimum Mode signals
Provides separate instructions for string manipulation. CLK 19 2 Rady Maximum Mode sgnals
GNO 20 21 Rese!

Fig. 6.2.1: Pindiagram of 808 Mlicroprocessor

 Dy

Ao MicroprocOssor: 8086 &Modern

Digi. Tech. and I Microprocessor (IT/Sem 3/MSBTE) 6-5
MicroprocesS0
ADAD1s RD (Read)
W-11.S-14. S-13
Inese lincs are time-multiplexed bi-directional address/data read signal issued by the
It is an active low processor o
bus, performing read
indicate that the processor is operation
During T, clock cycle of the bus cycle, they cary lower order memory or /O depending on the status of M/IO Signal.
16-bit addres. This signal is used to read devices, which are connected to
During T), Tand T, they carry 16-bit data. remain tri-stated
the 8086 local bus and during 'hold
So, ADy-AD, lines cary lowcr order byte of data and
acknowlcdge'
AD-ADs carry high order byte of data.
AjS, AjSs, AS, AS READY
W-09, W-11. S-14, S.15
These are time multiplexed address and status ines. MSBTE Question
During T, clock cycle, these lines cary upper four-bit a.1 How is an 8086 entered into.
a wait state ?
address and during V0operation, these lines are low..
This is an acknowledgement from the slower /0 device ot
(W-9)
During T;,T, and T, S, and S, carry status signal and these
status line are used to identify memory segments as shown in memory.
Table 6.2.1. It is an active high input signal.
Ss is an interupt enable status signal and is updated at the When high, it indicates that the peripheral device is ready to
beginning of each clock cycle. transfer data.
READY pin can be used to add wait state. When this pin ic
State Table 6.2.1
high, the 8086 is "READY" and operates normally.
S, S, Segment register If the READY input is made low at the right time in a
machine cycle, the 8086 will insert one or more wait state
0 ES between T, and T, in that machine cycle.
0 1 SS An external hardware device is set up to pulse READY low
before the rising edge of the clock in T,.
CS or none After the 8086 finishes T, of the machine cycle, it enters the
wait state.
1 1 DS
During a WAIT state, the signals on the buses remaining the
same as they at the start of the WAIT state.
BHE /S, (Bus High Enable / Status) The address of the addressed memory location is held on the
W-11,S-14,5-15 output of latches, so it does not change, the control bus signal
The bus high signal is used indicate the transfer of data MI0 and RD, also do not change DURING the WAIT state.
over higher order (D1sD) data bus shown in Table 6.2.2. TwAT
It goes low for the data transfer over D-Das and is used to The memory or port device then has at least one more clock
drive chip selects of odd addres memory bank or peripherals. cycle to gets its data output.
If the READY input is made high again during T, or during
BHE in coajunction with Ap determines whether a byte or the WAIT state, then after one WAIT state, the 8086 will go
word will be transferred from / to memory locations. on with the regular T, of the machine cycle.
The BHE/S, is a time-multiplexed line, so during T, to T, the If the 8086 READY input is still low at the end of a WAIT
status signal S, is transmitted on this line. state, then the 8086 will insert another WAIT state.
It remains always high. The 8086 will continue inserting WAIT states until the
Table 6.2.2
READY input is made high again.
A Word / Byte Access RESET
BHE
It is a system reset.
Whole word from even address
When this signal goes high, processor enter into reset state
Upper byte fronvto odd address
and terminate the current activity and start execution from
Lower byte from/to even address FFFFO H.
1 None This signal is an active high signal and must be active for at
least four clock cycles.
 Digi. Tech. and Microprocessor (IT/Sem 3/MSBTE) 6-6 Microprocssor : 8086 &Moderm Microprocessor

For minimum mode of operation, the pin MNMX is

Maskable and Non-maskable interrupt
S-15 kept high. The pins 24- 31 have unique function for
and the minimum mode.of operation as given below.
Maskable hardware interrupts can be mask or unmask
interrupting device
8-bit vector type must be provided by an acknowledge bus Pin 24 : INTA (Interrupt acknowledge)
interrupt
to the processor during an W-11. S-14. S-15
sequence.
maskable interrupt. It is an active low output signal.
In 8086, INTR is an
predefined internally When processor receive INTR signal, the processor complete
Non-maskable hardware interrupts use a
masked or avoided, processor cufrent" machine cyce and acknowledge the interrupt by
supplied vector and cannot be generating this signal.
interrupts.
has to service these maskable.
software interrupt are non
In 8086. NMIand all Pin 25: ALE (Address latch enable)
W-11. S-14. W-14. S-15
INTA (interrupt Request)
checked It is an active high pulse issued by the processor during T,
interrupt request input and is address
This is a level triggered state of bus cycle to indicate the availability of valid
instruction to determine
during the last clock cycle of each on the ADo-AD1s.
latches 8282-or
the availability of the request. This pin is connected to latch enable pin of
occurred, the processor enters the
If any interrupt request is 74LS373.
interrupt acknowledgecycle.
NMI(Non-maskable Interrupt) Pin 26: DEN (Data enable) W-11.S-14. S-15
W-11. S-14. S-15
by the processor during
request which causes It is an active low signal issued
This is an edge triggered input interrupt middle of T, until the middle of T,
to indicate the availability
a Type-2 interrupt of valid data over ADg-ADs.
The NMI is not maskable by software. transceivers (bi-directional
This signal is used to enable the
separate the data from the
buffers) 8286 o; 74LS245 to
TEST
W-11. $-14.S-15 multiplexed address / data signals.
math co-processor
This signal is used to test the status of Pin 27:DTR (Data transmit Ireceive)
8087. W-11. S-14. W-14. S-15
to this pin of 8086. direction of data flow
The BUSY pin of 8087 is connected This output signal is used to decide the
'WAIT" instruction. buffers) 8286 /
Thisinput signal is examined by a through the transceivers (bi-directional
execution will continue, else, 74LS245.
If the TEST s0gnal goes low, and
the processor remains in an idle
state. When the processor sends data out, this signal is high
signal is low.
when the processor receives data, then this
CLK (Clock input)
processor
This clock input provides the basic timing for Pin 28: M/IO (status signal)
W-14
operation and bus control activity.
cycle.
Itis symmetric square wave with 33% duty This signal is issued by the processor to distinguish memory
versions is from 5
The range of frequency for different 8086 access from an VO access.
When this signal is high, memory is accessed and when this
MHz to 10 MHz.
internal circuit.
Va +5 V power supply for the operation of signal is low, an I/0 device is accessed.
GND - Ground for the internal circuit.
Pin 29: WR (Write)
MN/MX data
S-15 It is an active low signal issued by the processor to write
M/IO
This pin indicates the operating mode of 8086. to memory or I/O device depending on the status of
There are two operating node of 8086 i.e. minimum mode
and maximum mode.
signal.
Pin 30 : HLDA (Hold acknowledge)
When this pin is connected to Vc, the processor operates in
This is an active high output signal generatcd by the
minimum mode and when this pin is connected to. ground,
processor operates in maximum mode. processor after receiving the HOLD signal.
 MicroprOcessor: 8086 & Modem
Digi. Tech. and Microprocessor (IT/Sem 3/MSBIE)
Pin 31: HOLD W-14
6-7

Pin 30, 31 : RQ / GT,,RQ / GT, (Request /| Grant)

MicroprocSOr
other local bus master
When_another master device needs the use of the address, These pins are used by in
data and control bus, it sends a HOLD request to the mode to gain the control of local buses at the
end of the maximum
processor through this line. processor's current buscycte.
It is an active high input signal.
The pins RQ/ GT, and RQ /GT, are
Max bi-directional and
For maximum mode of operation, the pin MN/MX 0is RÌ / GT, have higher priority than RQ /GT,.
kept low. The pins 24 - 31 have unique function for After receiving request on these lines, the
Raximum mode of operation as given below acknowledge signal on same lines.
CPU sends
Pin 24, 25 : QS,, QS, (Queue Status)
These lines provide information about the status of Syllabus Topic : Architecture of 8086
instruction queue during the clock cycle after which the
queue operation is performed. 6.2.2 Architecture of 8086
The Table 6.2.3 shows the status of QOS, and QS,. S-09, S-11, W-12, S-13, W-14, S-6
Table 6.2.3 MSBTE Questions
Status a. 1 Draw 8086 architecture block diagram. (S09)
NoOperation Q. 2 What are the main blocks in BIUand EU? Descrhe
BIUand EU elaborately. (S-11)
1byte of op-code from queue
Empty queue Q.3 Write in brief about the memory pointer registers,
1 1 Subsequent byte from queue queue and segnentation in 8086 microprocessor.
(S11)
Pin 26, 27,28 :S, S, S, (Status signal) Q. 4 Draw the functional block diagram of 8086
W-14 microprocessor and describe in detail. (W-12)
These status signals reflect the type of operation, being Q.5 Draw the register organization of 8086 and mention
the function each register. (S-13)
caried out by thc processor and required by the bus
controller Intel 8288 to generate all memory or IO access Q.6 Wite any four important functions of any two units
control signals. of 8086 microprocessor. (W-14)
These become active during T4 of previous cycle and remain Q.7 Draw architecture of 8086 and label it. (S-15)
active during TËand T, of the current cycle. Memory interface
These status lines are encoded as given in Table 6.2.4.
Table 6.2,4 C- BUS

S, S Status
0 Interrupt acknowledge hTA 6 byte
Instruction
0 1 JO Read 3-BUS queue

0 JO Write Bus
interface 2:
0 Halt unit
(BIU) DS
1 0 0 Op-code Fetch
1 0 Memory Read Erecution unt
NTC Contral syste
Memory Write A-BUS
Passive

Pin 29 : LOCK

This is an active low output signal used to prevent other 2AH. AL *

BH BL
SVsiem bus nmaster from gaining the system bus, while the Exeaution
unít
CH Athmetic logic unit
DH
(EU)
IOCK signal is low and generated by LOCK prefix SP
RE
nstruction.

When i goes low, all interrupts are masked and HOLD FLAGS
rgnest is not granted. Fig. 6.2.2: Architecture or functional block diagramnof808%
 Tech. and Microprocessor (IT/Sem 3/MSBTE) 6-8 Microprocessor : 8086 &Moderm Microprocessor
is divided into two Q.6 Draw the flag register structure of 8086 and
As shown in Fig. 6.2.2, the 8086 CPU describe the operation of each lag. (W-10)
independent functional parts i.e. a.7 Staté the significance of following flags of 8086.
Functional parts
() TF ()F (i) DF (v) CF (W-11)
of 8086 CPU Q. 8 Draw the flag register format of 8086
microprocesSor and explain any two flags. (S-14)
1. Execution Unit [EU] Q.9 Draw the neat labeled architecture of flag register
of 8086 microprocessor. (W-14)
Q. 10 Write the function of EU. (S-15)
2.Bus Intertace Unit [BIU]
The functions of execution unit are :
Fig.6.2.3 :Functional parts of 8086CPU
Organization of 8086 To tell BIU where to fetch the instructions or data from.
G Register Structure or 2 To decode the instructions...
18-Bit Register 3 To execute the instructions.
register functions
name
7 07 The EU contains the control circuitry to perform various
AX AH AL Multiply/Divide internal operations.
fetched from
Adecoder in EU decodes the instruction
WO instructions
Byte DL
addressable DX DH
or external contro!
(8-8it
Loop/ Shif/ Repeat memory to generate different internal
signals required to perform the operation.
CH CL Count
register
names
B perform arithmetic and
shown) BX BH >Base registers EU has 16-bit ALU, which can
well as 16-bit data,
RP logical operations on 8-bit as
and shown in Fig. 6.2.6.
S >Index registers Flag register in EU is of 16-bit
flags.
These registers contain nine active
this register are similar to 8085
Five flags in the lower byte of
Stack pointer
SP

15 General flag register.

registers divided into two parts i.e.
So, the flag register of 8086 is
( machine control flags.
Code segment base address condition code or status flags and
including overflow flag of
The condition code flag register
CS
the
result of the operation performed by
Data segment base address

Stack segment base address

8086 reflects the
ALU.
Extra segment base address Direction Flag DF, Interrupt
ES The machine control flags are
Flag IF and Trap Flag TE.
Segment
registers
G Status flags
15

Flags
Status flags
Instruction
IP pointer

Fig. 6.2.4:Registers of 8086 1. Carry Flag (CF)

2. Auxiliary Carry (AF)

Syllabus Topic : Flag Register
3. Parity Flag (PF)
6.2.2(A) Execution Unit [ EU ] 4. Zero Fag (ZF)
S-08, W-08, S-09, W-09, S-10, W-10, S-11.
W-11, S-12, S-14, W-14, S-15 5. Sign Flag (SF)
MSBTE Questions
(S-08, S-12) 6. Overtlow Flag (OF)
Q.1 List all16bit registers of 8086.
8086 and describe
Q.2 Draw fag register structure of Fig. 6.2.5: Status Flags
operation of each flag. (W-08)
Carry Flag (CF)
Q.3 Comment of various flags and their use in 8086
system. (S-09) It is set to 1 if there is carry out of the MSB position i.e.
at MSB
Q. 4 Name the general purpose registers of 8086 giving resulting from an addition or if a barrOW 0s needed
brief description of each. (W-09, W-10, S-12) during subtraction.
result, the CF
Q. 5 List and explain control flags of 8086 ii there is no carry/barrow out of MSB bit of
microprocessor. List instructions related to control flag is reset.
flag. (S-10, S-12)
 Digi. Tech. andI Microprocessor : 8086 &
Microprocessor(T/Sem 3/MSBTE) 6-9
Carry flag
Modern
Parity flag
Auxiliary carry flag
Zero flag
Sign flag
Overflow flag
Dy5 D4 Dys D12 Di1 Do D D D Ds Ds D. D D DD,
OF DF IF TF SF ZF AF PF

Trap flag
Interrupt flag
’ Direction flag
Fig. 6.2.6: Flag register format
2.
Auxiliary Carry (AF)
If an Control flags
operation perfomed in ALUgenerates a
from lower nibble (i.e. D-D) to upper carry/baTOW
the AF flag is seti.e. carry given by D, nibble (i.e. D4-D), S-10, W-11.5
bit to D, is AF flag. The three control flags are
This is not general-purpose flag; it is used
processor to perform binary to BCD conversion. internally by the
Three control flags
3.
Parity Flag (PF)
This flag is used to indicate the 1. Trap Flag (TF)
If lower order 8-bits of the
parity of
result.
result of an operation contains
even number if 1, the parity flag is set and 2. Interrupt Flag (IF)
for odd number
of 1, the parity flag is reset.
4
3. Direction Flag (DF)
Zero Flag (ZF)
It is set, if the result of
arithmetic or logical Fig. 6.2.7 :Three control flags
else it willbe reset. operation is zero
Trap Flag (TF)
5. Sign Flag (SF) It is used for single step
control.
In sign magnitude format the sign of number is indicated by It allows user to execute
one instruction of a programli
MSB bit. time for debugging.
If the result of operation is
negative, sign flag is set. When trap flag is set, the program can be
mode. run in single se)
The sign flag is replica of MSB bit of result..
2
6. Overflow Flag (OF) Interrupt Flag (IF)
In case of the signed arithmetic It is an interrupt enable /
operation, the overflow flag is disable flag.
set,if the result is too large to fit inthe numbers bits If it is set, the maskable
available interrupt INTR of 8086 is enablal
to accommodate it. and if it is reset, the
interrupt is isabled.
The overflow flag has no It can be set by executing
operation.
significance in unsigned arithmetic by executing CLI instruction STI and can be Cleu
instruction.
3
Difference between Carry and Overflow Flags Direction Flag (DF)
Carry Flag The DF (Direction flag) is used in
Overflow Flag string operation.
II DF is set, string bytes are read or write from nig
Generated during the arithmetic Generated during the memory address to lower memory address.
and logical operation on arithmetic and logical If DF is reset, the string bytes are read or write fromlower
unsigned numbers operation on signed numbers
memory address to higher memory address.
Generated by D7 or Dl5 bit of 8 Generated by D6 or Dl4 bi The DF can be set by executing
or 16 bit number of 8or l6 bit STD instruction and ca
number reset by executing CLD
instruction.
Sfrip!
tata
 Digi. Tech. and Microprocessor(T/Sem 3/MSBTE) 6-10 Microprocessor : 8086 &Modern Microprocessor
The memory pointers are used to point or address particular
8086
G General purpose registers of memory locationin memory
W-09. W-10, S-12 Following register acts as the memory pointers register in
8086.
bit general purpose
Execution Unit (EU) contains eight 16
DX, SP, BP, SI and DI as The Code Segment CS register is used to address a
registers named as AX, BX, CX,
memorylocationin the code segment of the memory,
shown in Fig. 6.2.4. used where the op-code of program is stored.
BX, CX and DX can be
Out of these registers, AX, CL, CH. The Data Segment DS register points to the data
i.e. AL, AH, BL, BH,
either as eight 8-bit registers
16-bit i.e. AX, BX, CX and segment of the memory, where the datg is stored.
DL. DHor can be used as four The Extra Segment BS register is used to address the
DX. and AX is segment, which is additional data segment, used to
as 8 bit accumulator
The AL register is called store data.
accumulator..
called as 16 bit The Stack Segment. SS-egister is used to points stack
purpose job, some register have
In addition to the general can location in stack segment of the memory and used to
nomally used as a counter, BX
special task such as CX is hold store data temporarily on the stack such as the contents
used for /O addressing to
be used as a pointer and DX is instructions of the 8086 of the CPU registers, which will be required later stage
the VO address in some beead of execution.
microprocessor. offct and BP The Default Segment base and offset pair registers
are(CS:IP
The other registers in EU are SP, BP, S( and DI. SP
holds 16-bit offset within the and/SS:SP.)
are pointer register, which registers.
particular segment. SI and Dl are the index G Instruction queue IQ (Queue)
instructions, register SI
During the execution of string related To increase the execution speed, BIU
fetches as many as six
data or string in data
is used to store the offset of source instruction bytes ahead to time from
memory.
used to store the offset of
segment while the register DI is first-in-first-out 6-byte
destination in data or extra segment. All the six bytes are then held in
register called instruction queue IQ.
6.2.2(B) Bus Interface Unit [BIU] Then all bytes have to be given to EU
one-by-one
S-08, W-09. W-11:S-12, W-14, S-15 may be in parallel with
This pre-fetching operation of BIU speed o
MSBTE Questions execution operation of EU, which improves the
execution of the instructions.
Q.1 List all 16 bit registers of 8086. (S-08, S-12)
BIU of 8086. State their
Q.2 List out various blocks of
(W-11) 6.2.3 Operating Modes of 8086
functions. Microprocessor
interface unit of
Q.3 Describe the functioning of bus W-08. W-12
intel's 8086 microprocessor. (W-09, S-12)
in 8086 MSBTE Question
Q.4 State the names of segment register
microprosessor. (W-14) Q.1 Describe under what situation maximum mode
wite their operation is useful. (W-08, W-12)
Q.5 List all 16 bit register in 8086 and
instructions. (S-15) The microprocessor 8086 operates in two modes i.e.
Q.6 Wite the function of BIU. (S-15) 1 Minimum mode (Single master Mode)
The function of BIUis to send address to: 2. Minimum mode (Two master mode)
(a) Fetch the instruction or data from memory. In minimum mode, all control signals are generated by the
microprocessor 8086 itself.
(b) Write the data to memory.
So, it can be used in single microprocessor based system.
(c) Write the data to the port.
In maximum mode, all control signals are generated by bus
(d) Read data from the port.
controller 8288 not by microprocessor 8086.
Various sections of the BIU are given below.
So, it can be used in multiprocessor system, when
microprocessor based system contains external math co
Syllabus Topic : Segment Registers of 8086 processor like 8087.

G Segment Registers The pin no. 33 i.e. MN MX is used to set either minimum or
maximum mode of microprocessor 8086 and also the
BIU has 4 segment registers of 16-bit each i.e. CS, DS, SS function of pin no. from 24 to 31 will also be changed which
and ES as shown in Fig. 6.2.4. are been already discussed in section 6.2. 1.
 Microprocessor: 8086 &Modern
DIgi. Tech. and Microprocessor ((T/Sem 3/MSBIE)
6-11 MicroprocesSor
The CLK is the system clock for the microprocessor,
controller of. 33% duty cycle.
6.2.3(A) 8284 Clock Generator coprocessor and bus
The frequency off the signalis one third [1/31 the frequency
W-14
signal at EFI
or external input
MSBTE Question ofcrystal at X,, X,
Q.1 Draw the interfacing of 8284 cock generator wth whether crystal input or EFI signal should
The F/ Cdecides
8086 microprocessor. List and explain interfacing the CLK output signal.
signals. (W-14) be taken for generating
is used to generate CLK
When F/C is high. the
EFI
three.
signal ie.
Feature frequency divided by
8086and 8088 CLK frequency = EFI
(a) Generates the Systemclock for
signal
to generate CLK
When F/C is low, the crystal 1S USed
microprocessor. frequency divided by three.
(b) Uses crystal or TTL for frequency source. i.e. CLK frequency =crystal
whose frequency is half ot
(c) Provide local READY and multitbus READY The PCLK is a TTL clock signal
affected by F/C signal
synchronization. theCLK signal frequency and not
which synchronizes
(d) Generate system RESET output from schmite trigger input The CSYNC is a synchronization signal PC we have only
(e) Capable of clock synchronization with other 8084 8284s in a system but normally in
multiple
grounded in PC.
() Requires single +5 Volt one 8284. So, CSYNC pin is
crystal is an overtone
The TANK input is used only if the
Description mode crystal is used
type crystal. Normally in PC, simple
The 828-4 is not only clock generator, also it perform three hence this pin is grounded.
different functions as given below.
(b) Ready logic
low for the
Three diferent functions of 8284 This logic generates READY signal
8088 bus cvcle
microprocessor to add wait state in the 8086 /
(a) Generating system clock for the 8086. otherwise the READY signal is made high by 8284.
There are two pairs of input signals which can make READY
(b)Generating READY signal for the 8086. low.
(a) RDYl and AENI.
(c) Generating RESET signal for the 8086. (b) RDY2 and AEN2.
RDYT and RDY2 are the input signals available from the
Fig. 6.2.8: Three different functions of 8284
external devices.
Functionally the 8284 is divided into three different sections Whenever the external devices wants to add wait state in bus
iLe. clock logic, Reset logic and Ready logic. cycle of the 8086 during the data transfer, the external device
The Fig. 6.2.9 shows the block diagram and pin diagram of activate either RDY1 or RDY2 where it is connected.
8284 IC.
Then the 8284 generates synchronized READY signal for
F/O CSYNC 8086. Thus 8086 adds wait state in processor's bus cycle.
cSYNC 18 Voc
X Clock
17 X1
(c) RESET logic
Clock loglc OSC
PCLK 2
X2
EF1 -PCLK AENT 3 8 16] X2 This logic generates RESET signal for 8086 microprocessor.
RDY1 T4 4 15 TANK
RDY1
READY C5 14]EFI When the RES input pin is made low., the reset logic
AEN1
RDY2 Ready logic READY ADY2 6 13F/C generates high active RESET signal for 8086.
AEN2 C7 12 osC
AEN2 CLK 11 RES In PCs, the RES input is connected to either 'Power Good
Reset logic -RESET GND 9 10 Reset signal from SMPS or Power on Reset' from R-C low pass
RES
filter circuit.

Fig. 6.2.9: Block diagram and pin diagram of 8284 G Interfacing 8284 with 8086
(a) Clock logic description W-14
The clock logic generates three different output signals The interfacing of 8284 with the 8086 microprocessor
ie. CLK. OSC and PCLK. shown in Fig. 6.2.10
 3/MSBTE) 6-12 Microprocessor : 8086 &Modem Microprocessor
Digi. Tech. and Microprocessor(IT/Sem
+5V 50 Signal Description

18
Input Signals
Voc Voc |STATUS INPUT PINS: These pins arc the input pins
CLK S, S,S, from the 8086 processors and the 8288 decodes these
Lo
Cysta CLK

310 pF 18
RESET
READY
2AESET
ZREADY
inputs to generate command and control signals at the
appropriate time.
45V
8080 CLK CLOCK: This is a CMOS compatible input which
Extemal RCR
inlegrator for
120sc 8284
receives aclock signal from the 8284 clock generator
and serves to establish when command/control signals
power on 11RES
are generated.
AENI Clock to the peripherals
RDYI PCLK ADDRESS ENABLE: AEN enables command
AEN
AENZ
EFi44 outputs of the 82C88 Bus Controller a minimum of
ADY2
110ns (250ns maximum) after it becomes active
GND
(LOW). AEN going inactive immediately three-states
9
the command output drivers.
with the 8086 microprocessor COMMAND ENABLE: When this signal is LOW all
Fig. 6.2.10 : Interfacing of 8284 CEN
DEN and PDEN
82C88 command outputs and the
Inactive state. When
controloutputs are forced to their
6.2.3(B) 8288 Bus Controller this signal is HIGH, these same
outputs enabled.
are

used to generate different INPUT/OUTPUT BUS MODE: When the IOB pinis
The 8288 is a bus controller IC IOB
functions in the VO Bus
interfacing memory and I/O strapped HIGH, the 82C88
control signals necessary for the 82C88 functions
of8086. mode. When it is strapped LOW,
devices in maximum mode
in the System Bus mode
The functions of this IC are: Output Signals
control address latch 74LS373
(a) Generate ALE signal to ADDRESS LATCH ENABLE: This signal serves
to
ALE
latches.
or 8282. strobe an address into the address
signals to control data bus DATA ENABLE: This signal serves
to enable data
(b) Generate DT/R and DEN DEN
or system data bus.
transceiver 74LS245 or 8286. transceivers onto either the local
This signal is active HIGH.
control signals on the behalf of
(cy Generate the read/write
8086/ 8088 in maximum mode. Output Signals
different sections signal sets the
Functionaly, the 8288 consists of two DATA TRANSMITRECEIVE: This
DTIR transceivers. A
signal logic. |direction of data flow through the
namely bus command logic and control I/O or
pindiagram of 8288 HIGH on this line indicates Transmit (write to
Fig. 6.2.11 shows the block diagram and |memory) and a LOW indicates Receive (read
from I/0
bus controller.
or memory).
The
|ADVANCED VO WRITE COMMAND:
|AIOWC earlier the
in
MRDC AIOWC issues an VO Write Command
IOB 1 20 Vcc indication
machine cycle to give I/0 devices an carly
Bus +AMWC CLK O 191 0 of a write instruction.
2 Command IORC
kogic ST3 18 $2 line
+AOWC 17 MCEPDEN |UO WRITE COMMAND: This command
INTA 8 IOWC the data bus.
ALE 16 DEN instructs an I/O device to read the data on
AEN 6 15JCEN |The signal is active LOW.
8
MRDC 14 0NTA |VO READ COMMAND: This command
line
CEN Control +DT/R AMWC 13 TORC IORD onto the data
Signals +DEN
instructs an /O device to drive its data
CLK MWTG C9 12 AOVWC bus. This signal is active LOWN.
Logic +ALE
OB +MCEPDEN' GND C]10 11 OWc
|ADVANCED MEMORY WRITE COMMAND:
AMWC command earlier
8288 Block Diagram Pin Diagram of 8288 The AMWC issues a memory write
carly
|in the machine cycle to give memory devices an
Fig. 6.2.11: Block and pin diagram of 8288 bus controller |indication of a write instruction. AMWC is
active

|LOW.
 Digi. Tech. and
Microprocessor (IT/Sem 3/MSBTE) Microprocessor : 8086 & Moderm
Input Signals
6-13

The bus command signals generated by the 8288 MicroproceSSor

for

MWTC MEMORY WRITE COMMAND: This comnmand

line instructs the memory to
combination of the bus status signals are
Table 6.2.5. showndif erenint
the data bus, This signal is record the data present on Allthe command signals are active low.
active LOW.
MEMORY READ COMMAND: This When there is no bus cycle bythe 8086. the
MRDC
Instructs the memory to drive its data command line are inactive i.e. active high.
command signals
bus,MRDC is active LOW. onto the data
When the 8086 perform a bus cycle, the appropriale
command signal from 8288 becomes active low in T. an4
INTA |INTERRUPT ACKNOWLEDGE: This command remains low tillthe bus cycle is completed.
|line tells an interrupting device that its
been acknowledged and that it interrupt has All the command outputs become inactive (high) if the CEN
should drive vectoring input is low.
information onto the data bus. This signal is
active
|LOW. When the CEN is high, the bus command logic section of
8288 is enabled.
Control Signals
AIOWC ADVANCED VO WRITE COMMAND: The The AEN input is used to tri-state all command signals.
AIOWCissues an I/O Write Command
machine cycle to give /O devices an earlyearlier in the If AEN is low, the command outputs are enabled and if the
of a write instruction. indication AEN is high, the command output is disabled.
VO WRITE
IOWC COMMAND: This command line
instructs an I/O device to read the data If IOB signal is high, AEN has no effect over command
on the data
bus. The signal is active LOW. outputs. So, in a PC, the IOB is always kept low.
VO READ Table 6.2.5
IORD COMMAND: This
instructs an I'O device to drive its datacommand line
onto the data Bus status 8086 state
bus. This signal is active LOW. Command signals
AMWC ADVANCED MEMORY WRITE S S, S, Signal name Pin No.
The AMWC is_ues a memory write COMMAND:
in the machine cycle to give command earlier 0 Interrupt 14
memory
early indication of a write instruction. devices an INTA
AMWC is Acknowledge
active LOW. 0 0 1 Read I/O Port 13
MEMORY WRITE COMMAND: This command IORD
MWTC 0
line instructs the memory to record the data 1 0 Write JO Port
on the data bus. This signal is active LOW. present IOWC
|2
MEMORY READ COMMAND: This command and AIOWC
MRDC line instructs the memory to drive its data onto
the 1 Halt None
data bus. MRDC is active LOW.
0 Instruction fetch
DEN DATA ENABLE: This signal serves to enable data 7
MRDC
transceivers onto either the local or system data bus. 1
This signai is active HIGH. Read Memory 7
MRDC
DÁTA TRANSMIT/RECEIVE: This signal 1 1 0 Write Memory
DT/R 9
establishes the direction of data flow through the MWTC
transceivers. A HIGH on this line indicates Transmit 8
(write to IO or memory) and a LOW indicates AMWC
Receive (read from LOor memory). Passive None
Bus control logic
Control signal logic
The bus control logic is responsible for generating bus
command signals in T, T-state of every bus cycle of the CPU. The control signal logic is responsible for generating signals
for controlling the hardware connected to 8086s address bus
It accepts the bus staus signal s on S, S,, S, and decode these and data bus.
status signals to generate different control signals. The DT/R signal is used to set the direction of data through
This bus status signals are available from T, of previous bus the data bus transceiver like 74LS245 or 8286.
cycle of 8086, hence the 8288 has sufficient time to generate
appropriate bus command signals in T, of current bus cycle When DTR is high, the direction of data transfer is from
of 8086. 8086 to external device and when DT/R is low, the direction
of data transfer is from external device to 8086.
 Digi. Tech. and Microprocessor(T/Sem 3/MSBTE) 6-14
Microprocessor: 8086 &Modern Microprocessor
The DEN signal indicates when the data bus has to be active. 6,2.3(D) 74LS373 Octal Latch
When DEN is high, the data bus transceiver is enabled and
when DEN is low, the data bus transceiver is disabled andits Description
outputs are tri-stated. The Fig. 6.2.13 shows the internal
configuration of 74LS373.
The ALE signal is used to enable address latch during T, of The eight latches are Dtype latches
enable G is high, the Q outputs willindicating
that when the
every bus cycle of 8086. follow the Dinputs and
when enable G is low, the output will be
The ALE is used to de-multiplex address/data bus along with of data what it was at the input.
latched at the level
address/status bus during T, of 8086 bus cycle.
The latch is controlled by CLK and buffer is controlled by
The MCE/ PDEN is a dual function signal and called as
Master Cascade Enable if 1OB is kept low.
This signal is used if more than one interrupt controller
0C pin.
iiiiii!T!!!!!!.
(8259A) is connected in cascade.
CLK
Enable
If1OB is high, this pin will act as a Peripheral Data 00
DEN performs
and perform same function for the I/Obus that
I1 -’01
12 ’02
during I/O instructions.
03

6,2.3(C) 74LS245 Bidirectional Buffer

’04
’05
I6 06
Description I7 7

Bidirectional Bus is used to inçrease the driving capability of

the data bus and also called as octal bus transceivers.

Fig. 6.2.12 shows the logic diagram of 74LS245 bidirectional Fig. 6.2.13: Internal Block diagram of 74LS373
buffer.
The bidirectional buffer consists of sixteen non inverting Syllabus Topic : Minimum Mode of 8086
buffers, eight for each direction with tri-state outputs.
The direction of the data flow is controlled by DIR pin. 6.2.3(E) Minimum Mode of 8086
·S-08.S-15
When DIR pin is high, the data flow from A bus to B bus and
MSBTE Questions
when DIR pin is lows, the data flow from B bus to A bus.
Q.1 Draw neat interfacing diagram in mirnimum mode of
The active low enable signal G and the DIR signals are 8086. Explain the function of contrcd signals used.
ANDed to active the bus lines. (S-08)
Each buffer can sink 24 mA and source 15 mÀ of current.
Q. 2 Explain the minimum mode configuration of 8086
Voc GND microprocessor. (S-15)
DIR Voc The general 8086 bases system in minimum mode is shown
B1 A12 G in following Fig. 6.2.14.
A1 -
Crystal
’ B2 A2 3 B
A2
A B A34 4 17 B2 284 AGock
B Deneralor
A4 A45 16 B3 Gerebe
AS + B5 15B4 READY
A56 NIA
A B6 RESET Control
A67 14 B5 RDY bus
A7 -’B7 5 WR
A7 8 13B6 GND
HOLD
A8
A8 9 12 87 8006CPU HLDA
GND 10 11 B8 Wat
DTÄ Lateh
stale DEN
DIR generato
Fig.6.2.12: Internal block and pin diagram of 74LS24S ALE
GND
2obit
Address
74S373
Table 6.2.6 indicates the function of 74LS245.
alch
Table 6.2.6 AgA9
BHES, (20r3)
Enabie pin Direction control DIR Direction of data
pin flow
Databus

L B bus to A bus TONS74L$245

D,- Dis
Transcever
L H A bus to B bus
X Isolation
Fig. 6.2.14 :System configuration in inimun1 mode of 8086
 Digi. Tech. and Microprocessor (T/Sem 3/MSBTE) '6-15 Microprocessor : 8086& Modem
The working of minimum mode configuration can describe in
the terms of timing diagram which show how and when
The read bus cycle begins in T with the
and MI0 ignals.
MicroproceRSOr
assertion of ALE
different signals are generated by the 8086 while
During the falling edge of ALE signal, the valid address is
reading/writing data from to memory or J/O devices. latched on the local address bus Ag-Aj.
Hence, the timing diagram can be classified into two part
Ae. read bus cycle and write bus cycle. The BHE and Ag signals address low, high or both
In minimum mode 8086 based system, the microprocessor From T, to T,, the MM0 signal indicate a byes.
related operation.
memory or Vo
8086 is operated minimum mode by strapping its MN/MX
At T, the address signals are removed from the
pin to logic high i.e. +5V. address
and send to the output to the latches which latches addrese
In. this mode, all control signals are generated by the Ap- Ag lines. The bus is then tri-stated.
microprocessor 8086 itself.
So, in minimum mode, the remaining components are latches, The control signal RD is activeted in T; causes addreted
trans-receiver, clock generator, memory and J/O device. device to enable its data bus.
The latchs are generaly buffered output Dtypé flip-flop like After RD goes low, the valid data is available on the data bue
74LS373or 8282.
These latches are used to separate address signals from data 6.2.3(E).2 Timing Diagram of Write Cycle of
8086 in Minimum Mode
and status signals using ALE signal generated by 8086.
Trans-receiver is bi-directional buffer and sometime they are The Fig. 6.2. 16 shows, the write cycle of 8086 in minimum
called as data amplifier and are required to separate valid data mode.
from the time multiplexed address/data signals. The write bus cycle begins in T; with the assertion of ALE
These bi-directional buffers are controlled by two signals. i.e.
and M/10signals.
DEN and DT/R. The DEN signal indicates that the valid data During the falling edge of ALESignal, the valid address is
is available on the data bus and DT/R indicates the direction latched on the local address bus A-Ay.
Of data i.e. from or to the microprocessor.
The BHE and Ap signals is activated to read or write lower
The clock generator generates the clock from the crystal
byte, higher byte er both bytes.
oscillator and then shapes it and divide to makes it more
precious so that it e§n be used as an accurate timing reference The MIO signal is used to distinguish between a memory or
for the system. VOreiated operation from T, to T, clock cycle.
The clock generator also synchronizes some external signals During T) clock cycle, the address signals are removed from
with the system clock. the address bus and sends to the latches which latches
address
on Ap- A)g lines.
6.2.3(E).1 Timing Diagram of Read Cycle of
8086 in Minimum Mode The control signal WR is activated in T causes addressed
device to enable its data bus.
The Fig. 6.2.15 shows read cycle of 8086in minimum mode. After WR goes low, the valid data is available on the data bus
from which it is written to the memory of IO device.
CLK

CLK
AgSg-AyeS,
AND BHES,
AqgS_-A1eS Ajg-As
AND BHE/S, SgS3
(2) ADgs-AD Do-Dis
ADs-AD, Do-Dy5
ALE
an
ALE
Low = Oread, high = memory read
MIC
X
MIO
RD
wnle
DT/R RAreo R
DEN DTIR

DEN

Fiz. 6.2.15: Minim:m mode read bus cycle of 8086

Fig. 6.2.16: Minimum mode write bus cycle
 (T/Sem 3/MSBTE) 6-16 Microprocessor :8086 &Modern Microprocessor
Digi. Tech. and Microprocessor
Mode of 8086 JORCand IOWC are used to read data from I/O device and
Syllabus Topic :Maximum write data to I/O device respectivcly.
These signals enable an IO interface to read or write the data
of 8086
6.2.3(F) Maximum Mode
S-10, S-11,S-14, W.14| from or to the addressed port.

The MRDC and MWTC are used as memory read and write
MSBTE Questions
maximum
interfacing diagram in signals.
0.1 Draw the neat (S-10)
mode of 8086. Beside these signals, AlOWC and AMWCadvance control
maximum mode diagram of 8086.
Q. 2 Describe the (S-11, S-14) signals are available to serve same purpose but are activated
maximum mode one clock pulse earlier th¡n IOWC and MWTC.
With neat diagram, describe the
Q.3 describe functions of The general 8086 bases system in minimum mode is shown
operation of 8086. List and
of 8086. (W-14)
signals of maximum mode inFig. 6.2.17.
Crystal
Maximum mode W
G Importance of MNAMXGND
8284 MWI
Used in multiprocessor
environment clock CLK AMWC
1 multiproce_sor generato 8288
IORC Control
for bus control in AEAOY buA TOWC
8288 Bus Controller is used
bus
2 AESET 0ontrol AIOWC
C
environment AOY DEN INTA
generated in maximum mode for GNC
Advance control signals are ALE
LOCK NC
slower devices
masters i.e. DMA controller
Along with 8086, another twO
8086
4 CPU
interfaced LSTB
and 8087 FPUcan be GND 20 bi
8086 is operated by connecting Address
In maximum mode, the AD-AD15
Ag-A_g
MN/MX pin to groun. B¾S,

In this mode, the processor

derives the status signals S, S,
16 bit
aNData bus
74LS245 Do-Dis
and S Transcever
another chip called as bus
These status signals ae used by
controller 8288.
maximum mode of 8086
In maximum mode, more than one
processor may be in the Fig. 6.2.17:System configuration in
system configuration.
mode are same as that 6.2.3(F).1 Timing Diagram of Read Cycle in
Other IC's required in maximum Maximum Mode of 8086
minimum mode of 8086.
32 will change and
The functions of pins from 24 to The Fig. 6.2.18shows timing diagram of the read cycle of
remaining willremain as it is. 8086 in maximum mode.
is to generate
The basic function of bus controller 8288
different control signals for memory and IO
devices such as AD-AD)s. Ay|S;-Ay/S, and BHE/S, are generated by the
information microprocessor during T, of read cycle.
RD/ WR and DEN, DT/R, ALE etc. using
avaiable on the status line.
But DT/R, ALE, DEN and control signals IORCIMRDC are
The bus controller has input lines S,S, S, and CLK. generated by 8288 bus controller after receiving status signal_

the outputs ALE, DEN, DTR on status lines So. S, and S, in T, and T,.
It generates
bus
MRDC, MWTC, AMWC, IROC, MRDC, I0WC and The ALE is generated by 8288 during T, state of the read
cycle.
AIOWC.
The AEN, IOB and CEN pins are especially useful for DT/R, DEN and MRDC or IORC are generated during T;
the
multiprocessor systems. state by bus controller 8288 and make data available on
data bus D,-D,s.
The INTA pin is used to generate two interrupt active low
açknowledge pulses to the inerrupt contruller or to an
interrupting de vice.
 YDigi. Tech, and
Microprocessor (IT/Sem 3/MSEIE Microprocessor : 8086 & Moderm

Micro procasen
6-17

6.2.4 Differences between

CLK
Minimofum8086
Maximum Mode Operation and
S-08. W-08, W-09.
SSActve S, S Inactive W-10, W-1
S-12.W-12, S-13. S-14.
AgSg-AeS
AND BHES, A1g-A16
S-B
MSBTE Questions
ADs AD, Q.1 Differentiate between minimum and
(S-08, W-09,maxiW-m1um0.
Do-Ds
mode operations of 8086.
ALE
W-11,S-12, S-13, S-14, S-15)
MDRCIORC Ne O.2 List significant diferences between minimum anA
DTR maximum mode operation of 8086.
AeceeNe (W-08, W-12)
DEN Sr. Minimum mode
No.
Maximum mode
Fig,6.2.18: Maximum mode read cycle 1
MN/ MX pin is connected MN /MX pin is
6.2.3(F).2 Timing Diagram of Write Cycle in tto Vcc. grounded.
Maximum Mode of 8086
2.loseparate bus controller is Separate bus controller (828R
The Fig. 6.2.19 shows the timing
of 8086 in diagram of the write cycle required. is required.
maximum mode.
In this mode, the control Control signals M/ IO, RD Control signals M/10. RD
signal MWTC or
generated by 8288 bus controller to write data to theIOWC
is
WR are available on 8086 WR are not available on 8086
or I/O device during T, state of memory
write bus cycle. | directly. directly but status of the
ADo-ADs. Aj|S3-Aj|S; and BHE /S, are generated control signals are available
by the
microprocessor during T, of read cycle. on status pins S, ,S, and S,
But DTR, ALE, DEN and control 4
signals MWTC \ IOWC Control signals such as IOR, Control signals such as,
are generated by 8288 bus controller after
receiving status
signals on status lines So, S, and S,. LOW, MEMW, MEMR can MRDC, MWTC, AMWC,
be generated using control
IORC, LOWC. AIOWC, arc
signals MIO, RD , WR are generated by bus controller
CLK
available on 8086 directly. 8288 using status signals S,
Sz-S5inactve
S, and S,
AygS AteS
AND BHE/S, Sg-S
ALE, DEN, DT/ R and ALE DEN.
DT/R and INI
ADsADo Data out D1s-Do INTA signals are directly |signals are not directly
available. available and are generated by
ALE
bus controller 8288.
6
AMWC &AIOWC HOLD and HLDA signals
MWTC &IOWC
areavailable to interface RQ/GT, and RQ/GT
available o
another master in system signals are
such as DMA interface another master
DEN
controller. DMA
system such as

controller and Co-processo

Fig.6.2.19: Maximum mode write cycle 8087.
7
The ALE is generated by 8288 during TË state of the read bus Status of the
instruction
queue is not available
Status of the instruction que
cycle. IS available on pins QS, and
DTR DEN and MWTC or JWC e generated during T. QS
state by bus controller 8288 and make data available on he
data bus D,-Ds.
 (IT/Sem 3/MSBTE) 6-18 Microprocessor: 8086 &Modern Microprocessor
Microprocessor
2 Digi. Tech. and
The segments register contain the higher order 16 hbits of the
Segmentation
Syllabus Topic : Concept of Memory starting addresses for four memory segments i.e. Data
segment, Code segment, Stack segment, Extra segment that
Concept of Memory Segmentation S-15 the 8086 CPU works with at a particular time.
6.2.5 W-10, S-12. W-12,
S-13, As shown in Fig. 6.2.20, the base address is nothing but the
S-08, W-08, S-09, W-09, starting addresses of each segment, for example, the starting
MSBTE Questions base address_of data segment is 10000H, 2000OH for code
8086.
memory segmentation in
segment etc.
Describe
0.1 S-12, W-12, S-15) The 16-bits offset or displacement is added to the 16-bits
(S-08, W-09, W-10,
memory? (W-08) segment base register after shifting the contain of it toward
youmean by segmentedachieved in 8086
Q.2 What do is left by one digit to get 20-bits physical address.
memory segmentation (S-09, S-13)
Q.3 How
system ?
organized as 6.2.5(A) Advantages of Segmentation
8086 based system is
The memory in an
memory management
technique S-08. W-08, S-09, W-09. W-10, S-12, W-12, S-13, S-15
segmented memory and this MSBTE Questions
is called as segmentation. of
number of segrmentation.
complete physically memory is divided into a Q. 1 List any four advantages
The segmentation. (S-08,W-09, W-10, S-12, W-12, S-15)
logical segments in and addressed by one
of (W-08)
Size of each segment is
64 Kbytes Q. 2 List two advantages of segmented memory.
i.e. CS. DS, ES or SS. What are the advantages of segmented
memory
the segment register Q.3 and
segment register holds the starting memory segmentation? (S-09, S-13)
The 16-bitcontent of the
address of a particular segment. to address a The address associated with any
instruction or data is only
address or displacement 1
So, we need an offset physical address.
segment. 16-bits though the 8086 has 20-bits
specific memory location within a time shared system.
so the maximum offset
value will Segmentation can be used in multi-user
The offset address is 16-bit
2
maximum size of any segment_is separately from each pther
be FFFF H and hence the 3. Programs and data can be stored
2l6= 64k locations. in segmentation.
address 1 Mbytes of physical than 64 kbytes or d¡ta more
The CPU8086 is able to 4. We can have program of more
or data segments.
memory than 64 kbytes by using more than one code
memory can be divided into 16 which are
The complete 1 Mbytes Segmentation makes it possible to Write programs
shown in Fig. 6.2.20. 5.
segments, each of 64 kbytes size as re-locatable.
be assigned as 000OH to position independent or dynamically
The address of the segments may Segmentation allows two processes to share data.
6.
FO00H respectively. addressability of a
The offset address values are
from 0000H to FFFFH so that 7 Segmentation allows you to extend the
00000H to FFFFFH.
the physical addresses range from procesSOr.

Physical Address Byte Syllabus Topic : Physical Address Generation

FFFFF H Highest Address
8FFFF H Extra ES 8000 H 6.2.6 Physical Memory Address
segment 64 k Generation in Segmentation
80000 H S-08, W-08, S-09, W-09, S-10, W-11,S-12,
8FFFF H Stack SS = 6000 H. S-13, S-14, W-14, S-15
segment 64 k

60000 H
MSBTE Questions
2FFFF H CS = 2000 H Q.1 Describe physical address generation steps with
Code (S-08)
segment 64 k suitable example.
20000 H Q.2 Define logical and effective addresses. Describe
physicaladdress generation process in 8086.
1FFFF H Data DS.=1000H (W-08)
segment 64 k
generated in 8086
10000 H 0000H .3 How 20 bit physical address is
processor ? (S-09)
Q. 4 Describe how 20 bit physical address is formed in
8086 microprocessor with one suitable example.
Fig. 6.2.20 : Memory segmentation (W-09, S-12, S-15)
 Microprocessor : 8086 & Modern
Digi. Tech. and Microprocessor (T/Sem 3/MSBTE)
O.5
Define logical and efective address, Describe
6-19

Physical Address Byte

Microprocet
Physical address generation process in 8086. Inserted z
Galculate the physical address by taking suitable 3FFFF H
DS, CS and IP. (S-10, S-12) Next instruction byte 3*
Q. 6 Define physical and logical address. How 20 bit to be fetch IP
physical address is generated ? (W-11)
Q.7 Describe how 20 bit physical address is generated oksgo123 H Physical
Address
8086 microprocessor. (S-13)
a.8 State the maximum size of memory that can be Start of code > 30000 H
segmenit
interfaced with 8086 microprocessor. Why? (S-14)
Q. 9 Describe the physical address generation process I
8086 microprocessor. (W-14) Fig. 6.2.22 : Physical address generation for Code Segme
One Mbyte (1024 Kbyte) of physical memory can be
Now CS contains 3000 H, when shifted left' by
interface with the 8086 microprocessor because 8086 has 20 four bx
address lines i.e. 2 = 1024 Kbyte or 1Mbyte positions, it gives 30000 H, which is base áddress of the cod
segment i.e. start address.
The segment registers are used to hold 16-bit of the starting
address of four memory segments. When we add offset 0123 H, the 30123 H becomes the 0 L
physical address of the next instruction byte to be fetchet
But 8086 has 20-bit address bus, so it can address any of 2
=1 Mbytes in memory. 20-bitphysical address is normally represented as CS:IP.
The address associated with any instruction or data byte is Stack pointer SP
only 16-bitcalled as effective address or offset or
displacement or logical address. The 8086 allows us to set aside an entire 64 kbytes segment
as a stack.
The logical addresses are used to calculate physical address
However the address outputted by BIU is 20-bit -called as The upper 16-bit of the starting address of this segment is
loaded in the stack segment SS register.
physical address; Fig. 6.2.21 shows how 8086 calculates
physical address from the effective address. The stack pointer SP register holds the 16-bit offset from tke
Addsec.
2ssouted starting address of the segment where the word was most
15 15
Offset
recently stored on the stack i.e. top of the stack.
Efective address Segment address 0000 Segment
Address Register The physical address of the stack is generated by adding the
contents of the stack pointer SP to the stack segment base
register SS during read or write operation with stack.
ADDER So, the content of SS stack base segment register is Sind
left by four bits and then the content of SP register is added to
it. For example, if SS contains 6000 H and SP contans
FFEO H.
20 bit Physical Address
The SS is shifted left four bit position to give 60000 H.
After adaing SP ie. offset in to it. the resultant physiea
Fig. 6.2.21: Physical address generation address for the top of the stack will be 6FFE0 H
as show
Other registers in this section are given as follows: Fig. 6.2.23. This can be represented as SS:SP.
G Instruction Pointer IP
Physical Address Byte Top of stack
InsertedZero
The instruction pointer register holds the 16-bit address of the
next code byte within the code segment. 6FFEO H doloo9
The value stored in IP is called as offset or displacement.
SP =FFEO H
This offset is added to the code segment registr after SP FFEO
shifting Offset
it by four bits, which include base address_of the- code Physical
Address
segment. For example, let us take CS = 3000 H and Start of-60000 H
IP= 0123H. stack SS = 6000 H
segment
Fig, 6.2.22 shows the calculation of physical address from
CS and P.
Before adding the content of CS and IP, the content of CS is
Fig. 6.2.23: Physical address
shifted left by four bits position. generation of stacs
 Digi. Tech. and Microprocessor (ITISem3/MSBTE) 6-20
MicroproceSsor : 8086 &Modem Microprocessor
Ex. 6.2.1: If BX=0158H, DI = 10ASH, DS =2100H and Zero is inserted
displacement is 1B57H and DS is used as
3 4 5 A 0
segment register then calculate physical DS
address produced for different memory | 3 D C SI
addressing mode. S-08, 6 Marks P.A.=

Soln. : Ex. 6.2.3: What is

210OH displacement? How does it
Given: BX = 0158H, DI = 10ASH and DS = determine memory address in a MOV
Displacement = IBS7H (2000H), CL instruction.
Soln.: Assume DS= A000H, Memory address in MOV 2000H.
addressing mode
MOV AX, [BX]- Register Indirect CL is given below
register is DS
In above instruction the default base address Zero is inserted

and offset registerBX, the physical address is calculated as A 0 0 00 DS

given below 2 0 0 0 Displacement
Zero is inserted P.A.= A2 000
2 1 0 0 0 DS
Ex. 6.2.4 : State the default segment base and offset
(0 1 5 8 BA pair register. IF CS = 1000H and IP = 2000H.
PA= |2 11 58 then from which memory location 8086 reads
an instruction.

MOV AX, [BX+DI]- Base Indexed Addressing mode Soln.:

The default segment best and offset pair register are CS:IP
In above instruction the default base address register is DS
and SS:SP.
and offset is calculated by adding register BX with DI, so the
Zero is inserted
physical address is calculated as given below
| 0 0 0 0 CS
Zero is inserted
2 0 0 0 IP
2 1 0 0 0 DS
0 1 5 8 BX
PA.=12000
1 0 A 5 D After calculating physical address, then 8086 reads an
instruction from memory address 12000H in a code segment:
PA.=221 E D
MOV AX, [1B57]- Direct addressing mode Ex 6.2.5: Calculate the physical address generated by
) 4370: 561E (i) 7A32: 0028
In above instruction the defauit base address register is DS S-13, 4 Marks
and offset is given directly in instruction, so the physical address is
calculated as given below Soln. :
Zero is inserted (i)
2 1 0 0 0 DS. Zero is inserted
Base a d s s
1B S 7 16bit offset 4 3 7 0 0

PA.=22 B57 5 6 1 E Offset

P.A.= 48 D E
Ex. 6.2.2: If DS=345AH and SI=13DCH, calculate
physical address. W-08, 4 Marks
Soln.: Zero is inserted

7 A 3 2 0 Base
Suppose instruction using SI as aoffset register is MOV AX,
[SI] in Register Indirect addresing mode 0 0 2 8 Offset
In above instruction the default base address register is DS
and offset register SI, so the physical address iscalculated as given
below
P.A.= -a
 Digi. Tech. and
Microprocessor (T/Sem 3/MSBIE 6-21 Microprocessor : 8086 &
Moderm
Ex. 6.2.6:
Soln. :
IF DS = C239H and SI =
Calculate physical address. 8ABCH, then a.3 Describe pipelined architecture
helps in improving thoughput.
a. 4 Define pipeline
MiicroprocAR
Concept and how
Zero is inserted Q. 5 Explain the pipeliningin 8086
C 2

8
3

A B C IP
9 CS
is queuing useful in speeding up
8086 microprocessor. the
The technique used to enable an instruction
microprocopees roarti,on Ho

each clock cycle is called as pipelining. to complete vith

P.A.=
A44 Normally, on a non-pipelined processor, nine
Ex. 6.2.7: Calculate the physical address in the
required for fetch, decode and execute
cycles for the z clock cydes
instructions as shown in Fig.6.2.24(a). thrt
following cases. But, on a pipelined processor, the fetch, decode and a
(a) CS (b) DS S-14. 4 Marks
Soln.: operation are performed in parallel, only five
clock
(a) CS: 1200H and IP DE0OH the
are required to execute the same three
instructions a8 t cycde
physical address is calculated Fig. 6.2.24(b).
below D E D F

Zero is inserted Clock -

2 4 5 67
Cycle 8 9
2
0 SS (a)
DE SP

P.A.=1 FE F 1 F-Fetch
(b) DS: 1F0OH and BX : D
1A00H for MOVAX, (BX] D-Decode
Zero is inserted
E
1 F0 0 SS Clock
E-Execute
Cycle> 1 2 3 4 5
1 A 0 0 SP
(b)
P.A.=2 0 A Fig. 6.2.24: Pipelined execution of three
instructions
Ex. 6.2.8 : First_ instruction requires three cycles to_
If CS=69FAH and IP = 834CH, calculate the execution. complete te
physical address generated. W-14. 4 Marks Next instructions then complete at a rate of one instructok
Soln. : per cycle.
During the clock cycle 5 we have Ia
decoded and I, being fetched as shown incompleting,
Zero is inserted I, being
Fig. 6.2.24(6).
6 9 F A 0 CS Stack is a reserved area of the memory in the
RAM, wei
8 3 4 C IP temporary information may be stored.
Stack operates on the principle of Last In First Out (LO.
P.A.=7 2|2 EC Aqueue is an ordered collection of iitems where the addition
of new items happens at one end, called the "rear," andthe
Syllabus Topic : Concept of the Pipelining removal of existing items occurs at the other end.
The queue operates on the principle of first in fistou!
6.2.7 Concept of the Pipelining (FIFO).
W-09. S-10, W-10, W-12. So that the execution unit gets the instruction for executionin

S-13.S-14. W-14. S-15 the order they fetched.

Feature of fetching the next instruction while the curren!
MSBFE Questions
What is Queue? How does queue speeds up the instruction is executing is called pipelining which willreduct
Q. 1 the execution time.
processing of the 8086 microprocessor ? So, pipelining improve the execution speed of the processor.
(W-09, W-10, S-10, S-13) In 8086, pipelining is implemented by providing
Q.2 Explain the concept of pipelining. (S-10, S-14) 6 byte queue where as long as 6 one byte Instructions can e
stord well in aadvance and then one by one INsuctiongo
for decoding and
execution.
loche
3/MSEBTE) 6-22 Microprocessor :8086 &Modem Microprocessor
Digi. Tech. and Microprocassor(T/Sem
in a queue, processor Pentlum M(1997) :
So, while executing first instruction
fetches 8 instruction from
decodes second instruction and The 7.5 million-transistor Pentium II processor incorporates
the memory. Intel MMXMechnology, which is desighed spëcifically to
fetch, docode and execute
In this way, 8086 perform in process video, audio and graphics data efficiently.
single clock cycle as shown
operation in parallel i.e. in The Pentium Il used a66 or 100 MHz system bus.
Fig. 6.2.24(b). Desktop models had 7.5 million transistors, 512KB L2 cache
Pipelining
6.2.7(A) Advantages of Pentium Il Xeon (1998) :
W-09, S-11. S-12
The Pentium II Xeon processors are designed to meet the
pipelined architecture. performance requirements of mid-rarnge and higher servers
a.1 Slate the advantages of (W-09, S-11, S12) and workstations.
Systems based on the processor can be configured to scale to
instructions to be executed at the
Pipelining enables many four or eight processors and beyond.
same time.
Typically used in high-end and 2-way and 4- way servers,
in fewer cycles.
It allows execution to be done Xeon specs were like Pentium II with L2 cache from 512KB
Speed up the execution speed of the processor to 2MB and 100 MHz system bus.
More efficient use of processor
Celeron (1999) :
Pentium Family
Syllabus Topic : Overview of Continuing Intel's strategy of developing
processors for
Processor Intel Celeron processor is
specific market segments, the
designed for the value PC market segment.
6.3 Overview of Perntium Family It provides consumers great
performance at an exceptional
performance for uses such as
ProcesSor value, and it delivers excellent
gaming and educational software.
Intel Corp. in
Pentium family of processors developed by FistCelerons had no L2cache, but 128KB
on-die cache was
microprocessor.
1993 as the successor to Intel's 80486 additional in 1999.
a single chip and about system buses with 400
The Pentium contained two ALUon Celerons started with 66 and 100 MAz
3.3 million transistors.
MHz.
set computer)
Using a CISC (complex instruction address bus, a
32-bit
architecture, thePentium processor has a Pentium lI (1999) :
64-bit data bus, built-in floating-point and memory
new instructions.
management units, and two 8KB
caches with processor The Pentium II processor features 70
experiences,
speeds ranging from 60 megahertz
(MHz) to 200 MHz. It was designed to significantly enhance Internet
realistic
allowing users to do such things as browse through
high-quality video.
Pentium (1993) : online museums and stores and download
transistors using 0.25
The processor incorporates 9.5 million
Ci

to enormous raw
Adding systems-level characteristics
demanding IO, micron technology.
compute power, the Pentium supports and
graphics and communications intensive
applications with The Pentium II used a 100 or 133 MHz system bus
Transfer
more than 3 million transistors. either a 512KB L2 cache or a 256KB L2 Advanced
256KB to 1MB, used a Cache.
The Pentium had an L2 cache from
contained trom 3.1 to 3.3
50, 60 or 66 MHz system bus and Pentium lI Xeon (1999) :
milliontransistors
offerings to
The Pentium III Xeon processor extends Intel's
Pentium Pro (1995) : the workstation and server market segments, providng
The newest Pentium has dynamic instruction
execution and additional performance for e-Comnerce applications and.
L2
other performance-enhancing features such as a large advanced business computing.
cache in the chip package, in addition to its more than 5.5 processor's 70
The processors incorporate the Pentium III
million transistors. SIMD instructions, which enhance multimedia and streaming
Typically used in high-end desktops and servers, the Pentium video applications.
were
Pro improved memory from 4GB to 64GB. Typically used in 2-way to 8-way servers, Xeon specs
The Pentium Pro had L2 cache from 512KB to IMB, used a like Pentium IIwith L2cache up to 2MB.
configurations.
60 or 66 MHz system bus. It is designed for systems with multiprocessor
 geCooe code ntmohine code bto pde.
R aMicroprocessor (|T/Sem 3/MSBTE) ) 6-3Q.4e Microprocessor:8086 &Modern
Digi. Tech. and
Intel's Pentium-4 processor : 6.4 CISCand RISC Processor
MicroproCes
The Pentium-4 is fabricated in Intel's 0.18-mnicron CMOS
Central Processing Unit Architecture designed .
process.
"Instruçtion Set Architecture" ie. RISC
Its die size is 217 mm2 and power consumption is 50W. (Reduced
instructinisotrnuci
set computing) and CISC (Complex
The Pentium 4 is available in l.4GHz and 1.5Hz bins.
computing).
At 1.5GHz, the microprocessor delivers 535 SPECint2000
and 558 SPECfp2000 of performance. 6.4.1 CISC Processor Architecture
Currentlyit is the second-performing general-purpose The CISC or Complex
microprocessor. Instruction Set Computer is R
based processor architecture, which is designed
The worldchampion is Compaq/Digital Alpha 21264B CPU of
with ahuil.
instructions that were intended to
delivering $44 SPECint2000 and 658SPECfp2000 at
833 MHz.
capabilities in the most efficient way. provide..nede
The CISC processor architecture is designed to
The previous Intel chip, Pentium-III "Coppermine", had 442 simnlk
SPECint2000 and 335 SPECfp2000 results at 1GHZ. compilers and to improve performance under constraint ud
as small and slow memories.
Pentium-4 is the first completely new x86-processor design
from Intel since the Pentium PRO processor, with its P6 CISCprocessor is easy to program and make efficient use a
micro-architecture, was introduced in 1995. Pentium-4' memory.
micro-architecture is known as NetBurst. It has many CISC processor has variable length instructions where t
interesting features. length often varies according the addressing mode
heng
Compared to the Intel Pentium-Ill processor, Intel's NetBurst instructions require multiple clock cycles to exccute.
micro -architecture doubles the pipeline depth to 20 stages. It is easy for micro-coding new instuctions, which allo
In addition to the L1 8 KB data cache,
the Pentium 4
designers to make CISC processor upwardly compatibk
processor includes an Execution Trace Cache that stores up to means a new processor could run the same programs
12 Kdecoded micro-ops in the order of earlier processors because the new processor would contain :
program execution.
The on-die 256KB L2-cache is superset of the instructions of the earlier processors.
associative.
non-blocking, 8- way set In CISC architecture which has software
control unit consists
It employs 256-bit of micro-programmed control memory.
interface that delivers data transfer rate of
48 GB/s at 1.5 GHz. Fig. 6.4.1 shows the CISC
architecture with micro
The Pentium 4 processor expands the programmed control memory and unified cache.
floating point registers Most CISC architectures have a
to a full 128-bit and adds an Complex
movement. Pentium-4'
additional register for data
NetBurst
decoding logic for a single instruction to supportinstrctior
multiple
micro-architecture addressing modes.
introduces Internet Streaming SIMD Extensions 2 (SSE2).
This extends the SIMD capabilities that
MMX technology
and SSE technology delivered by Instrucion
adding 144 new Microprogrammed
control memory and
instructions.
data path
These instruction_ include 128-bit SIMD integer
and 128-bit SIMD arithmetjc
double-precision floating-point operations.
Pentium 4 processor's 400 MHz (100 MHz "quad Control unit
system bus provides up to 3.2 GB/s of bandwidth.. pumped") Cache
The bus is fed by dual
PC800 Rambus
compares to 1.06 GB/s delivered on thechannel. This
processor's 133-MHz system bus. Pentium-III Main memory
Two Arithmetic Logic Units
(ALUs) on the Pentium 4
processor are clocked at twice the core
This allows basic integer processor frequency. Fig.6.4.1: CISC Architecture
instructions such as Add, Subtract, Common characteristic of most CISC hardware architectures
Logical AND, Logical OR, ctc. to execute in a are a small number of general purpose registers result
half clock
cycle. having instructions, which can operate directly on memory.
The integer register ile runs also runs at tlag register also called as condition register, several special
the double
frequency. purpose egisters such as stack pointer, interrupt handling.
and so on.
2 Digi. Tech. and Microprocessor (IT/Sem 3/MSBTE) 6-24 Microprocessor : 8086 &Modern Microprocessor
The examples of CISC processor are
(a) IBM 370/168 ie. 32 bit processor ith 4 general Syllabus Topic : Characteristics of RISC Processor
purpose and 4 64-bit floating point registers)
6.4.3 Characteristics of RISC Processor
(b) VAX 11/780 i.e. 32-bit processor from DEC with large
number of addressing modes and machine instructions, 1 RISCProcessors have a lower number of instructions.
(c) Intel 80486 with instructions with variable length from 2 The addressing modes in RISC processor are also lower.
1to 11 and had 235 instructions and finally Pentium as 3. Allthe operations that are required to be performed take
amodern CISCprocessor. place within the CPU.

6.4.2 RISC Processor Architecture 4 All instruction are executed in a single cycle hence have a
faster execution time.
RISC or Reduced Instruction Set Computer is a hardwired 5 RISC architecture, the processors have a large number of
highly.
processor architecture which utilizes a small, registers and a much more efficient instruction pipeline.
optimized instructions set rather than a more specialized set The instruction formats are of fixed length and can be casily
of instructions normally found in other types of architectures. 6.

Hence, each instruction that a computer must perform, decoded.

requires additional transistors and circuitry, a larger set of 7 Load-and-store architecture i.e. only LOAD and STORE
other
computer instructions makes the microprocessor more instructions reference data in memory and alI
complicated and slower in operation. instructions operate only with registers.
The RISCprocessor has hardwired control unit. 8 Only a few simple addressing modes are used for example
Fig. 6.4.2 shows the RISC architecture with hardwired register, direct, register indirect, displacement.
control unit with split cache.
6.4.4 Advantages of RISCProcessor
S-15
Hardwired Data path
control unit MSBTE Ouestion
Q.1 Write any four advantages of RISC processor.
(S-15)
tested more
A new microprocessor can be developed and
Instrucion Data cache 1.
quickly which can take advantage of other technological
cache

developments leading to greater leaps in performance

between generations.
(Unstruction) (Data)
Main memory 2. To develop code with a smaller instruction set, it is easier to
use microprocessor' s instructions by operating system and
Fig. 6.4.2: RISC Architecture application programmers.
use
higher speed i.e. 3. The RISC processor gives more freedomto deçide_how to
The RISC processor can operate at a
second, or MIPS. the scope of a microprocessor.
perform more millions of instructions per
Register-to-register operations support only load and
store 4 Higher-level language compilers are used to generate more
operations to access memory and rest of the
operations on a efficient code as used the smaller set of instructíons which is
register-to-register basis. found in a RISC computer.
addressing modes i.e. 1 Superscalar RISC processor gives 2 to 4 times the
better
RISC processor have simple and few 5.
same
or 2. performance. as compare to CISC processors with the
registers, which are clock rates as a simplified instruction set allows a pipelined.
Ihe RISC processor has large number of
operations minimize
required to support register-to-register 6 The instruction set of a RISCprocessor requires much
less
the procedure call and return overhead. chip space for additional functions, such
as memory
instructions facilitates
The RISC processor has fixed-length managenment units or floating point arithmetic units.
efficient instruction execution and easyto pipelne. integrate
smaller instruction set for Smaller chips size gives a processor manufacturer to
It easier to develop code with a more functional parts on a single silicon chip,
which will
Operating system and Application. lower the per-chip cost.
per instruction) of one
RISC processors have a CPI (clock All instruction are executed in a single cycle
hence have a
each instruction on the CPU. 8
cycie due to the optimization of faster execution time.
 Digi. Tech. and Microprocessor (|T/Sem 3/MSBTE) 6-25 Microprocessor :8086 &Moderm Microprocessor

Syllabus Topic : CISC with RISC in the term of Sr. Parameter RISC (Reduced CISC (Complex
Instruction Set, Length, Addressing Mode No. Instruction Set Instruction Set
Computer) Computer)
6.5 4 Registers Large number Small number of
Compare CISC with RISC
General Purpose general purpose
S-15
Registers registers and
MSBTE Question Several special
Q.1 Compare RISCand CISC architecture. (S-15) purpose registers
Architecture Load/Store No load/store
Sr. Parameter 5
RISC (Reduced CISC (Complex architecture
No. Instruction Set Instruction Set
type architecture
Computer) Operation Single-cycle Multi-cycle
Computer) 6.
Instruction operation operation
Few Instructions in More instructions
Set instruction set in instruction set 7. Design Hardwired control micro-coded
2.
Data Types Few Data types control
More data types
Addressing Instruction Fixed length
3.
Mode
Few
Modes
Addressing More addressing 8.
Format instruction format
Variable-length
modes instruction format