Dhaka University of Engineering and Technology, Gazipur

Department of Electrical and Electronic Engineering

Course No: EEE-4202
Course Title: Telecommunication-I Sessional
4th year 1st semester
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Experiment No.: 02
Performance analysis of an input message signal after implementing Pulse Code Modulation and
Pulse Code Demodulation technique using TIMS module.
Objective:
(i) To understand the process of making an analog signal in to digital one.
(ii) To learn about the signal digitization enhanced advantages and few drawbacks.
Learning outcome:
Student can make difference between an analog signal and a digital one. They can also learn that
how an analog signal can be made or converted in to a digital signal.

Theory:
Pulse-code modulation (PCM) is a method used to digitally represent sampled analog signals. It
is the standard form of digital audio in computers, Compact Discs, digital telephony and other
digital audio applications. In a PCM stream, the amplitude of the analog signal is sampled
regularly at uniform intervals, and each sample is quantized to the nearest value within a range of
digital steps.

Fig.

Block diagram of Pulse code Modulation

TIMS PCM Encoder
An audio frequency analog-to-digital converter which outputs the digitised data in serial TTL-
level PCM format. Both linear and non-linear (logarithmic) digitising schemes are provided.
Frame synchronisation is implemented by both separate output synchronisation signal and also
an embedded code within the serial data stream. A variable frequency sinuous-type message is
provided, which is always synchronised to the input bit clock.

INPUT SIGNALS
Two input signals are required for correct operation: the analog signal to be digitised, Vin, and
the sampling "bit" clock, CLK. Vin will accept TIMS-level, bipolar signals ranging from DC up
to several kilohertz. Note that the Vin input is not band limited, so that aliasing may be observed
if desired. The bit clock, CLK, must be a TTL-level signal, such as the TIMS MASTER
SIGNALS 8.33kHz SAMPLING CLOCK output.
Note that careful consideration must be given regarding the sampling theorem, when selecting
the relative frequencies of both Vin and CLK.

PCM DATA
The TTL-level digitised data is output serially. TIMS PCM code words are in standard offset
binary format, with the first 7 bits allocated for data/coding and the least significant bit allocated
for the frame synchronisation code.
Three digitising schemes are provided for comparison purposes. Selection is made via front
panel switch:
(a) 7-bit linear,
(b) 4-bit linear, and
(c) 4-bit companded, either TIMS A4-Law or TIMS µ4-Law
Note that selection between TIMS A4-Law or TIMS µ4-Law is made via jumper selector on the
PCM ENCODER module’s PCB.

FRAME SYNCHRONISATION
Two methods are used to indicate frame synchronisation: a separate TTL-level output signal, FS,
and an embedded code within the digitised serial data. The frame synchronisation signal, FS, is
normally low and only goes high for one bit period, at the time of the least significant bit of the
PCM code word, bit 0. The frame synchronisation signal is also embedded within the digitised
code word, as the least significant bit, bit 0. The code selected is a repeating "0 - 1 - 0 - 1 ...."
sequence. This is a unique sequence which corresponds to the Nyquist frequency of the sampled
signal and so is otherwise considered a "disallowed" state.

PCM DECODER
ANALOG OUTPUT
Vout provides a bipolar, standard TIMS-level analog signal, derived from the input digital data at
PCM DATA. Note that Vout is taken directly from the converter without reconstruction filtering
so that individual steps in the conversion process may be observed if desired.
FRAME SYNCHRONISATION Two methods are used to recover frame synchronisation:
"EXTERNAL" makes use of a separate TTL level input signal connected to EXTERNAL FS,
and "EMBEDDED" extracts the embedded code within the digitised serial data. The method
required is selected by front panel switch, EXTERNAL or EMBEDDED.
(i) EXTERNAL Mode
In EXTERNAL mode, the separate frame synchronisation input signal, EXTERNAL FS, must
normally be low and should only go high for one bit period, at the time of the least significant bit
of the PCM code word, bit 0. Note that FS OUT is not active in this mode.
(ii) EMBEDDED Mode
In EMBEDDED mode, the TIMS PCM DECODER module will "search" and "extract" the
embedded code from the incoming serial data. In this mode, the PCM DECODER module will
also output the resulting extracted frame synchronisation signal at FS OUT. Note that the TIMS
PCM ENCODER module embeds a uniquely defined "0 - 1 - 0 - 1" repeating sequence within
the digitised code words.

INPUT SIGNALS
Two TTL-level digital signals are required for correct operation: PCM DATA, the serial digital
data to be converted to an analog signal and, CLK, a synchronised and in-phase bit clock. Both
these signals must be "clean", squared digital signals. Note that the TIMS DECISION MAKER
module may be required to "clean-up" digital signals that have undergone any kind of distortion.

PCM DATA
The format of the serial data expected at the PCM DATA input is exactly as generated by the
TIMS PCM ENCODER module: TIMS PCM code words in standard offset binary, with the first
7 bits allocated for data/coding and the least significant bit allocated for the frame
synchronization code

Experiment:
1. Select the TIMS companding A4-law with the on-board COMP jumper (in preparation
for a later part of the experiment).
2. Locate the on-board switch SW2. Put the LEFT HAND toggle DOWN and the RIGHT
HAND toggle UP. This sets the frequency of a message from the module at SYNC.
MESSAGE. This message is synchronized to a sub-multiple of the MASTER CLOCK
frequency. For more detail see the TIMS Advanced Modules User Manual
3. Use the 8.333 kHz TTL SAMPLE CLOCK as the PCM CLK
4. Select the 4-bit encoding scheme
 5. Switch the front panel toggle switch to 4-BIT LINEAR (ie., no companding).
6. Connect the Vin input socket to ground of the variable DC module.
7. Connect the frame synchronization signal FS to the oscilloscope ext. synch. input.
8. Start with a DC message. This gives stable displays and enables easy identification of
the quantizing levels.
9. On CH1-A display the frame synchronization signal FS. Adjust the sweep speed to
show three frame markers. These mark the end of each frame.
10. On CH2-A display the CLK signal.
11. Record the number of clock periods per frame.
Currently the analog input signal is zero volts (Vin is grounded). Before checking with the
oscilloscope, consider what the PCM output signal might look like when the DC input level
is changed. Make a sketch of this signal, fully annotated. Then:
12. On CH2-B display the PCM DATA from the PCM DATA output socket.
Except for the alternating pattern of ‘1’ and ‘0’ in the frame marker slot, you might have
expected nothing else in the frame (all zeros), because the input analog signal is at zero
volts. But you do not know the coding scheme.
There is an analog input signal to the encoder. It is of zero volts. This will have been coded
into a 4-bit binary output number, which will appear in each frame. It need not be ‘0000’.
The same number appears in each frame because the analog input is constant.
The display should be similar to that of Figure 3 below, except that this shows five frames
(too many frames on the oscilloscope display makes bit identification more difficult).

Report:
1. Attach the output wave shape of PCM encoding experiment. Analyze what are the
limitations of this experiment.
2. What is the necessity of pulse code modulation and why we call it the main step of signal
digitization-explain?
3. From measurements made of quantizing levels for 4-bit linear encoding using DC supply
answer the following:
• what is the sampling rate ?
• what is the frame width ?
• what is the width of a data bit ?
• what is the width of a data word ?
• how many quantizing levels are there ?
• are the quantizing levels uniformly (linearly) spaced ?