Unit 4
Unit 4
Processor communication
Exchange of data between the CPU and I/O module over the
data bus.
1
Device communication
Data buffering
Data transfer rates of peripheral devices are quite high than that of
CPU and memory .The data coming from memory or cpu are sent to
an I/O module , buffered and then sent to the peripheral device at its
data rate.
Also data are buffered in I/O module so as not to tie up the memory
in a slow transfer operation.
Thus the I/O module must be able to operate at both peripheral and
memory speeds
Error detection
I/O module is also responsible for error detection and for reporting
errors to the CPU. The different types of errors are mechanical and
electrical malfunctions reported by the CPU.
In this technique, the total memory address space is partitioned and part
of this space is devoted to I/O addressing.
Here the advantage is that the full memory address space is available.
The memory related instructions do not work.
Therefore, processor can only use this mode if it has special instructions
for I/O related operations such as I/O read, I/O write .
4
Types of data transfer techniques
5
I/O control by handshake signals
The handshake signals are used to ensure the readiness of the I/O
device and to synchronize the timing of the data transfer.
This method provides an external asynchronous input that would inform the
processor that it should complete whatever instruction that is currently
being executed and fetch a new routine (Interrupt Service Routine) that will
service the requesting device.
Once this servicing is completed, the processor would resume exactly where
it left off.
This event that causes this interruption is called interrupt and the special
routine executed to service the interrupt is called Interrupt Service Routine
( ISR).
An interrupt caused by an external signal is referred as hardware interrupt.
Conditional interrupts or interrupts caused by special instructions are called
software interrupts.
6
Response to interrupt
1. The CPU recognizes the interrupt when the external asynchronous input is
asserted by an I/O device.
2. In response to an interrupt a special sequence of actions are performed.
3. These are as follows :
a. The processor completes its current instruction.
b. The PC current contents are stored on the stack.
c. The PC is loaded with the address of ISR.
d. Program execution continues with the instruction taken from the
memory location pointed by the new PC contents.
e. The interrupt program continues to execute until a return instruction
is executed (RET).
f. After execution of the RET instruction processor gets the old address of
the PC from the stack and puts it back into the PC.
g. This allows the interrupted program to continue executing at the
instruction following the one where it was interrupted.
Enabling and Disabling interrupts
7
When masked , processor does not respond to the interrupt even if the
interrupt is activated.
Vectored Interrupts
8
Interrupt Priority
The processor takes the decision with the help of interrupt priorities.