GRAPHICAL

AUTOMATIC PROGRAMMING
A. Kossiakoff

Summary type Data Flow Circuit representing the data

HE DEVELOPMENT, PROOFING, AND MAINTE-
processing desired, as if they were equivalent
T NANCE of computer programs for complex data-
processing systems represents a difficult and in-
hardware functional elements. The designer can
also assemble and define special circuit elements
creasingly costly aspect of modern systems design, for his own use.
especially for those systems requiring real-time The correspondence between the individual
processing. The problem is aggravated by the ab- Data Circuit Elements and actual computer in-
sence of a lucid means of representing the opera- structions makes it possible for the designer to
tions performed by the program or its internal and assess the approximate time for executing each
external interfaces and the associated communica- circuit path and the total core required to store
tion gap between engineers and programmers. the instructions. This permits him to balance the
A major step toward the solution to this prob- performance requirements for accuracy and ca-
lem is believed to have been achieved. It consists pacity against the "cost" in terms of memory and
of an entirely new approach devised to provide execution time during the initial design of the
systems engineers with the capability of designing circuit. This capability can be of utmost impor-
entire complex data-processing programs by direct tance in programming high-data-rate real-time sys-
use of a modern computer graphics terminal. The tems, especially those having limited memory
name "Graphical Automatic Programming" capacity.
(GAP) has been suggested for this technique. Its 2. Application of Computer Graphics-Each
four principal features are summarized below. Data Circuit is designed by the engineer with the
1. Data Flow Circuit Language-The essential aid of a graphics terminal, operated by a time-
basis for the Graphical Automatic Programming shared computer such as the IBM 360/ 91. The
technique is the configuration of the program into circuit elements are selected, arranged, and con-
"Data Flow Circuits," which represent the pro- nected using a light pen and keyboard and dis-
cessing to be done in a form directly analogous played in a manner similar to that used in compu-
to the diagrammatic representation of hardware ter design of electronic circuits.
circuits. Data Flow Circuits represent a "universal The display program stores the circuit descrip-
language" with a form intimately familiar to engi- tion in an Element Interconnection Matrix and a
neers and at the same time directly translatable data "Dictionary." This is checked automatically,
into computer programs. The Data Flow language and any inconsistencies in structure are immedi-
consists of a "vocabulary" of some 30 basic data- ately drawn to the designer's attention.
processing "elements," each of which represents 3. Trans/ormation 0/ Graphical into Logical
an operation equivalent to the execution of a Form-The computer then executes a transforma-
specific set of instructions in a general-purpose tion program, which converts the Data Flow
computer. These "Data Circuit Elements" are Circuit automatically into an operational sequence,
configured by the designer into an engineering- representing the sequential action of the circuit

2 :\PL T ech n ical D igest

 elements as they would be serially processed by ular set of data. This capability is being exploited
the computer. In the next step, the computer in major libraries and in almost every business.
converts the operational sequence into computer A third type of application of enormous impor-
assembly code for the computer driving the tance has been in the automation of operating sys-
graphics terminal. The program logic is checked tems. The Whirlwind computer, developed to
out by using sample inputs and examining the automate the handling of radar information in
outputs. Errors or omissions can be corrected im- the SAGE continental air-defense system, was one
mediately by the designer by modifying the faulty of the historic landmarks in the evolution of very-
connections or input conditions in the circuit. high-speed high-capacity digital computers.
4. Integration and Testing of Complex Pro- The problems associated with these three appli-
grams-When checked out, the circuit is assem- cations of general-purpose digital computers are
bled by the computer with other blocks of the fundamentally very different. The application as
total program. The result is checked for proper a high-speed mathematical calculator involves the
operation. At any desired stage, the individual transformation of a set of given parameters by
circuits or their assemblies can be translated into a sequence of specific mathematical transforma-
the machine assembly code of the particular com- tions into one or a set of solutions. The storage
puter on which the operational program is to run, and retrieval of data involves the organization of
which can be fed directly into the assembler of a filing system with suitable indexing to facilitate
the operational computer. Subsequent modifica- rapid location of the data to be retrieved. The
tions to the program can be made by calling up use of a computer to automate portions of a com-
the circuit to be altered, making the changes with plex system generally does not require involved
the display terminal, and invoking a program to computations or elaborate data retrieval. In this
find and change other affected sections. application, the primary processes are the correla-
In this wayan entire complex computer pro- tion and classification of data inputs, recognition
gram can be designed, documented, and managed of significant events or changes in input conditions
through the use of Data Circuit language by direct to the system, and translation of these into con-
interaction between the systems engi,neer and the cise information outputs or actual control signals
graphics terminal. It is hoped that this technique to external devices.
will be capable of producing system software at
The design of computer programs for using
a fraction of the time and cost achievable by cur-
digital computers in automating real-time operat-
rent methods.
ing systems has turned out to be quite different
Introduction and much more difficult than designing programs
The general-purpose digital computer found its for the computing and data-handling applications.
first practical application in the forties in calcu- Thus the enormOllS potential impact of the use of
lating more extensive tables of mathematical func- modern digital computers in automating such sys-
tions than had been practicable to produce by tems has been impeded by the very large ex-
mechanical calculating machines. Few viewed the penditure of manpower, and hence of time and
appearance of these devices as a breakthrough in money, in the design of satisfactory large-scale
technology. In fact, there was considerable specu- computer programs. In many instances the devel-
lation as to what would be left for them to do opment of the so-called "software" (in contrast to
after the computation of function tables had satis- the "hardware," or equipment) is widely regarded
fied all reasonable requirements. as the limiting factor in both time and cost of
As things have turned out, the digital computer system development.
did not run out of work when the most important Operation and Programming of a General-
mathematical tables were finished. Computers Purpose Digital Computer-For those with
were applied with great success to problems in only general familiarity with the problem of de-
scientific and engineering analysis requiring highly signing computer programs, a brief discussion of
complex mathematical calculations. They were how a general-purpose computer operates and
also found to be extremely useful for economically of aids available to programming is necessary to
storing large masses of data sorted in a way that provide a background for the description of the
permits almost instantaneous retrieval of a partic- Graphical Automatic Programming techniques.

September - October 1969 3

 The general-purpose digital computer consists sembler" which automatically translates the assem-
of a central processing unit (CPU), a random bly language program into machine instructions.
access memory unit (Core), and peripheral "in- Since the program in assembly code requires
put-output" (I/ O) devices. The central processing a separate instruction for each elementary machine
unit contains a set of circuits, each designed to instruction, it is very laborious to use in designing
execute a specific operation on one or more digital complex programs. For this reason several "pro-
"words" which represent numbers or characters gramming languages" have been developed which
making up the data. The execution of each opera- enable the programmer to write concise "higher
tion is called for by a coded word called an "in- level" instructions. This involves development of
struction." A sequence of instructions calling for a program called a "compiler," which translates
a series of operations is called a "program." The the high-level instructions into the assembly code
instructions are stored in part of the random- for a given computer. Since much of the detailed
access memory, along with data words in various housekeeping is done by the compiler, the pro-
states of processing. Data are entered into the grammer's task is greatly facilitated.
computer by means of punched cards, tape, or The most widely used computer language has
disk. Control signals are usually entered through been "FORTRAN," which was developed by IBM
special interrupt connections. Results are read for programming mathematical calculations. "AL-
out in the same form as data inputs, or as printed GOL" is a more sophisticated algebraic language.
copy, plots, or graphic displays. They may also For programming data storage and retrieval opera-
be used to control various devices directly. tions, such as those used predominantly in busi-
The main task in effectively using a general- ness applications, "COBOL" is widely used. More
purpose computer in a given application is the recently mM combined the best features of FOR-
development of a satisfactory computer program. TRAN and COBOL into "PL/ I" (Programming
Since the individual operations of the central Language One) to handle both types of program.
processing unit are very elementary, a relatively In addition to these general-purpose languages, a
long sequence of instructions must be written to variety of higher level programming aids have
accomplish most data-processing tasks. Care must been developed to handle special applications.
be taken to insure that adequate space is reserved Problems in Design of Real-Time Pro-
in memory to hold data inputs and partially pro- grams-Unfortunately, while these higher level
cessed information. Where the process involves languages are very helpful in programming com-
decision points and "branches" into alternative puters for use in mathematical analysis and busi-
paths, it is not unusual to make mistakes in the ness applications, they do not lend themselves to
proper sequencing of instructions. Sequencing er- the design of real-time programs for complex auto-
rors are inherently difficult to locate, so that "de- mated systems. In such applications, the program
bugging" of the program is usually the most time- has to provide for accessing and outputting data at
consuming part of the job. times required by the system timing, often in
The actual instructions stored in the computer a period of a millisecond or less, and it must have
to execute a given program are made up of binary a system of priorities which interrupts lengthy
code. The lowest language readily intelligible to operations in favor of those requiring immediate
a programmer is called "assembly language." This action. It must be subject to external commands
is a direct representation of machine code for each by operators, to adapt tc.e processing priorities or
instruction, in characters which convey meaning, modes to changes in the operational environment.
as for example "LDA(M)" which means "Load The higher level languages obscure the relation
the contents of memory location M into die A between the operation called for and the time re-
register." The assembly language can use names to quired for its execution, and hence can inadvert-
refer to memory addresses and labels for instruc- ently produce a program which later proves to
tion locations. This notation makes it possible to require unacceptably long processIng times. "Tim-
write a program without assigning particular loca- ing" in scientific or business programs generally
tions in memory for data files (or arrays) and the only affects cost. In high-data-rate real-time sys-
instructions themselves. Each computer model has tems timing may control success or failure.
its own assembly code notation and its own "as- Automated systems must often accommodate

4 APL Technical Digest

 large variations in the volume and rate of data to "jump" instructions in the digital program. The
inputs, and in their quality or noise content. The term "Data Flow Circuit" will be used in referring
use of a higher level language obscures the mem- to this representation.
ory requirement for storing the program code and The development of the Data Flow Circuit
data. The resulting inefficient use of the memory is representation has required the definition of a
often a limiting factor on data-handling capacity. set of "elements" which constitute the building
In such systems the use of assembly language, in blocks of the circuit. Each element has a dual
which the execution time and memory required meaning: to the engineer it represents a transfer
for each instruction is immediately apparent, is function and to the programmer it represents a
more satisfactory in insuring that the program set of computer operations. Before describing
meets all system requirements, -aespite the in- these building blocks, it is illuminating to compare
creased labor involved in the detailed coding. the general form of a typical computer program
These characteristics make the design of computer with its equivalent Data Flow Circuit.
programs for real-time systems vastly more diffi- A computer program representative of a practi-
cult and tedious than the preparation of programs cal example of real-time programming is illus-
for batch-type computational tasks. trated in Fig. 1. It lists the code of one of the
An even more basic difficulty in the preparation processes used in a program for automatic track-
of effective programs for computers which serve ing of target returns from a three-dimensional
as permanent elements in complex automated sys- search radar. This program is written for the
tems is the "communication gap" between the Honeywell DDP-516 computer-a small modem
engineers and the programmers. The design speci- high-speed machine, with a relatively simple but
fications on the program are prepared by engineers versatile set of instructions.
to fit the characteristics of the data inputs and the
The figure shows both the DDP-516 machine
rate and accuracy requirements of the processed code and the corresponding assembly code for
outputs. Capacity is often dictated by operational
each instruction. The machine code is listed in
factors. At the time he has to make these specifica-
the columns of numbers on the left side of the
tions, the system engineer does not have effective
figure, and the equivalent assembly code is listed
means to estimate reliably the complexity of the in the middle columns of characters. The same
program that will result. The programmer, in tum,
code will be used in examples described in later
has little discretion in altering the specifications
sections of this paper. The text at the right lists
to meet the limitations on computer capacity and comments written by the programmer for his own
processing times. Accordingly, the development reference in "debugging" or modifying the pro-
of the system computer program is effectively an
gram. The program consists of some 100 instruc-
open-loop process, and often results in an over- tions. Since it does not have an obvious form or
sized and unbalanced product after an inordinate structure, a typical program such as this is difficult
expenditure of effort and time. to follow by anyone except the programmer who
Data Flow Circuit Language wrote it.
The fundamental new concept which constitutes The representation of the same process in the
the essential basis of the techniques of Graphical form of a Data Flow Circuit is shown in Fig. 2.
Automatic Programming is the representation of The solid (red) lines represent the flow of data
a computer program in a "language" consisting of in the form of digital words, and thus trace the
circuit networks in a form directly analogous to successive operations on a given data input. The
diagrams used by engineers to layout electronic dashed (blue) lines represent control signals trans-
circuits. This representation focuses attention on mitted to gates which activate particular opera-
the "flow" of identifiable data inputs, quantized tions or data paths, and thus effect branching in
in the form of digital words, through alternative the operational sequence.
paths or "branches" making up the total data- The polygons in Fig. 2 represent the 12 main
processing network. The switching of data flow functional elements in the circuit. The shape of
at the branch points of the network is done by the element and the number and types of signal
control signals generated in accordance with the inputs and outputs indicate the general type of
required logic. These control signals are equivalent function it performs, while the characters inside

September - Octob er 1969 5

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ability of following the operations performed on
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Perhaps of equal significance is the fact that
each circuit element, when used in a given com-
Fig. I-Target Coordinate Computation Circuit Program. puter, has associated with it a definite set of in-
structions, except for minor variations depending
defin e its specific operation. Thus, the visual con- on the form of the inputs, and hence the number
figuration of the circuit is descriptive of its general of words in Core, and time to execute, can be
operational function. estimated quite closely at the outset. For example,
The routing of data and control signals among it will be seen later that the COMPARE element,

6 APL T echnical Digest

 designated in Fig. 2 by a hexagon marked by the each Data Circuit Element was designed to meet
characters "CP ," requires four instructions for the following criteria:
the DDP-516 computer. In general, each signal 1. It must be sufficiently basic as to have wide
routing element requires an average of one instruc- application in data-processing systems.
tion, while the main functional elements require 2. It must be sufficiently powerful to save the
an average of six instructions counting the prep- designer from excessive detailing of secondary
aration of data inputs. This knowledge gives the processes.
designer a measure of the size of the program 3. It must have a symbolic form which is simple
equivalent to the circuit and the approximate to represent, which is meaningful in terms of its
transit time through any of the possible circuit characteristic function, but which is not readily
paths. If either the size or time of the equivalent confused with existing component notation.
program appears excessive, the designer can seek The choice and definition of the basic GAP
to simplify the processing operations at the very data circuit elements is in an early stage and will
outset so as to achieve a well balanced program. evolve as experience is gained in applying the
A Data Flow Circuit is conceptually equivalent language to practical problems. At present five
to an actual circuit constructed from a multiplicity classes of circuit element have been defined. The
of special-purpose digital circuit elements. This first four perform direct signal transformations,
equivalence was in fact the origin of the idea, and the last routes data and control signals
when it was realized that special-purpose digital through the circuit. These classes are defined as
operational elements are becoming so inexpensive follows:
that they could be used to advantage in high-data- SENSE elements test a particular characteristic
rate real-time data processing to complement the of a data word and produce one of two control
general-purpose computer. outputs according to whether the result of the
Digital circuits differ from analog circuits by test was positive (Yes) or negative (No).
virtue of the fact that in the former the signals OPERATOR elements perform arithmetic or
are "quantized" in the form of digital "words." logical operations on a pair of data inputs and
This means that signal transformation and "flow" produce a data word.
occur by a series of steps rather than continuously. COMP ARISON elements combine several
A Data Flow Circuit differs from an ordinary sensing and operator functions in a single element
digital circuit in that the steps are further restricted to accomplish frequently used data classification
to take place one at a time to correspond to the operations.
sequence of operations by the computer. Thus, TRANSFER elements bring data in and out of
while data will flow in parallel paths in a circuit the circuit from files in memory and from external
network such as that shown in Fig. 2, at any given devices.
instant signals will be flowing in only one of the ROUTING elements combine, split, and gate
paths. This characteristic does not detract from the flow of data and control signals in the circuit.
the high visibility of all of the interactions in the Some routing elements do not themselves produce
process inherent in the diagrammatic representa- program instructions, but rather modify those
tion. produced by the functional elements to which they
Data Circuit Elements-As stated previously, are connected.
in a Data Flow Circuit each functional element Table 1 lists the elements presently defined for
has a dual meaning. In the engineering represen- initial use of GAP. These include 2 SENSE ele-
tation it can be considered to be exactly equiva- ments, 11 OPERATOR elements, 4 COMP ARI-
lent to a hardware building block, which trans- SON elements, 6 TRANSFER elements, and 9
forms the indicated digital inputs into a uniquely ROUTING elements. Others found to be widely
defined set of output signals. In its represen- applicable may be added to the basic vocabulary
tation of a sequence of operations performed by for general use. Facility will be provided for each
a general-purpose digital computer, it corresponds designer to define for his own use special-purpose
to a definable set of instructions in computer as- functions as auxiliary elements. Most of these can
sembly language. be built up from combinations of the basic ele-
In selecting the building blocks to be used as ments, as is true of the COMPARISON elements
the functional elements of Data Flow Circuits, already defined.

S ep tem ber - O ct ob er 1969 7

 TABLE 1 elements it is four. Connections are numbered
OAT A FLOW CIRCUIT ELEMENTS clockwise with # 1 at 12 o'clock.
SENSE ELEMENTS TRANSFER ELEMENTS Operation of Data Circuit Elements-The
SENSE ZERO READ FILE characteristics of Data Circuit Elements can
SENSE SIGN WRITE FILE best be described by examples. Five of the ele-
INPUT DATA
OPERATOR ELEMENTS OUTPUT DATA ments shown in Fig. 3 will later be used in a sim-
ADD FUNCTION TABLE ple circuit to illustrate the automatic translation
SUBTRACT SHIFT REGISTER of a Data Circuit into a computer program. The
MULTIPLY
DIVIDE ROUTING ELEMENTS detailed operation and equivalent code of these
AVERAGE DATA SPLIT five elements are described below.
EXPONENTIATE DATA JUNCTION The function of the COMPARE element is to
MAXIMUM DATA GATE
MINIMUM DATA PACK emit a control signal from one of its three output
LOGICAL AND DATA LOOP connections in accordance with the relative magni-
EXCLUSIVE OR CONTROL SPLIT tude of the two data inputs, x and y. As the signals
INCLUSIVE OR CONTROL
JUNCTION in a Data Circuit flow from an output of one ele-
COMPARISON ELEMENTS CONTROL GATE ment to an input of another, one link at a time,
COMPARE SIGNAL SPLIT the step when a given Data Element performs its
THRESHOLD
CORRELATE
function and generates an output occurs when the
RANGE GATE final input necessary for its operation arrives. In
the case of the COMPARE element in its basic
Figure 3 illustrates the symbolic representation ungated form, two data inputs are required. When
of typical circuit elements. The top rows picture the first arrives it is put in a temporary memory
one element of each of the four main functional location. When the second arrives, usually several
groups, while the bottom rows illustrate four steps later, the element functions and generates
ROUTING elements. As noted previously, solid the appropriate output, which in tHis instance is a
lines are used for data signals and dashed lines control output from connection #3, #4, or #5.
for control signals. In translating the functioning of the element
In Fig. 3 the sample elements are seen to have into computer assembly code, th~ conditions at
the following types and numbers of connections: the time of functioning must be noted. When the

Data Control Data Control

Element Type Name Inputs Inputs Outputs Outputs
SENSE SENSE ZERO 1 0 1 2
OPERATOR ADD 2 1 1 0
COMPARISON COMPARE 2 1 0 2-3
TRANSFER READ FILE 1 2 1 1
ROUTING DATA SPLIT 1 0 2-5 0
DATA GATE 1 1 1 0
CONTROL JUNCTION 0 2-5 0 1
DATA LOOP 2 1 0

OPERATOR, COMPARISON, and TRANS- COMP ARE element is activated by the arrival of
FER elements are provided with an optional con- the input at connection # 2, the corresponding
trol input to serve as a gate for delaying the func- data word is in a general register AR, while the
tioning of the element until the receipt of a control other data input is in a temporary memory loca-
signal from elsewhere in the circuit. The READ tion, M6. The resulting code would have the form
FILE and DATA LOOP elements have a con- listed below for computers having a specific
trol input which serves a different purpose, namely "Compare" instruction. The instructions in word
to initiate the next cycle of the loop. form are listed in the left column and the equiva-
The maximum number of connections for any lent instructions in DDP-516 assembly code are
element is six, and for SENSE and OPERATOR listed at the right.

8 APL Technical Digest

 1. Compare AR with M6 CAS CP6 memory locations containing data, as M6 or CP6,
2. Jump to M3 (if AR > M6) JMP CP3 or instructions, as M3, M4, M5 or CP3, CP4,
3. Jump to M4 (if AR = M6) JMP CP4 CP5. In the rest of the paper it will be convenient
4. Jump to M5 (if AR < M6) JMP CP5 to relate these labels, which are entirely arbitrary,
In the above, code labels are used to designate to the notation of the corresponding element input
or output connections.
Like most functional elements, the COMPARE
SENSE OPERATOR element has a connection (# 1) that can be used
X X as a control gate when it is desired to make the
operation conditional on a particular control out-
put from another element. This connection saves
V the use of a separate gating element on one of the
4
data inputs. When gating is used, the second data
input is also temporarily stored in memory (M2)
and operation of the element occurs when the
X X+V gating input arrives. The. code for the gated form
SENSE ZERO ADD of the COMPARE element begins with the in-
struction
COMPARISON TRANSFER M1: Load M2 into AR CP1: LDA CP2
1 followed by the same code as the ungated form.
The "M 1 :" (or CP 1 :) preceding the instruction
is a label used in assembly language to indicate
the destination of a jump instruction.
The COMPARE element also has another form
in which either control output # 3 or # 5 is de-
signed as "unconnected." Output # 4 then be-
X(n) comes a "greater than or equal to" output. In this
COMPARE READ FILE form an output at #4 will be produced when
M2 ::::::,. M6. Since such simple variants of an ele-
ment are distinguishable in the diagram by the
ROUTING status of specific optional connections, the same
basic element can be used for several closely re-
lated functions without ambiguity.
The READ FILE element has the function of
extracting one or a series of data words from an
array or file in memory. In its fully connected form
X
it is designed to operate in a circuit "loop," ex-
X
tracting one word of a sequence at each turn until
DATA DATA
SPLIT GATE the file is empty. If the stepping control input at
connection # 5 is designated as unconnected, the
READ FILE element will extract a single data
IC

Loopr
I word from the file location designated by the input
I at connection #2.
I
r-- In the fully connected form of the READ FILE
'1 C element, the input required to generate the code is
'V the control input at connection # 6. When this
J X OR V input arrives, the element reads out the data word
CONTROL DATA located at the address indicated by the initial
JUNCTION LOOP
value, n, of the index, i.e. the number of items in
the file to be read out, which has been stored
Fig. 3-Examples of Data Circuit elements. previously at the data input at connection # 2.

September - October 1969 9

 After the extracted word has been processed, The CONTROL JUNCTION routes several
a "stepping" control pulse is received at connec- different control outputs to a single element input.
tion # 5. This input causes the index to step to While it does not in general produce code, it does
the next word on the list. If the incremented value change the labels of jump instructions on the con-
of the index shows that no words remain, a con- nected elements.
trol output appears at connection # 3. If not, the Data PreparatioD-The word length in most
next word is read out at connection # 4, initiating general-purpose computers varies between 16 and
the next cycle of the loop. 36 bits. The accuracy with which a given variable
The translation of the READ FILE element is known is seldom greater than one part in 2000,
into assembly language is written in a single which requires 11 bits plus 1 bit to designate sign.
sequence of instructions as soon as the first word Often the accuracy of the data requires 8 bits or
is read out. The differentiation between the initial less. Since memory capacity is often a limiting fac-
and stepping modes is done by the use of labels tor in the performance of a computer as a system
which indicate the entry points for the two modes. element, it is frequently necessary to combine or
The code for the READ FILE element is shown "pack" two or more variables into a single data
below in its generalized form on the left and in word to economize on memory storage and access
DDP-516 assembly code on the right. The "IRS" time. When an operation must be performed on a
instruction in the 516 code stands for "increment, given variable, the latter must first be extracted
replace, and skip" and has the function of incre- from the data word and manipulated to adjust its
menting the contents of the indicated memory sign bit and location to put it into proper form
location by one and skipping the next instruction for the ensuing operation. The data preparation
if the result is zero. "SKP" is an unconditional usually involves several mask, shift, and comple-
skip instruction. The significance of the other in- ment instructions.
structions is obvious.
In the Data Flow Circuit notation, such prep-
1. M5: Increment M2 RF5: IRS RF2 aration is specified as a preliminary to the opera-
SKP tion performed by each element. The format of
2. Jump to M3 if M2 = 0 JMP RF3 each variable is also specified as part of the circuit
3. M6: Load M2 into XR RF6: LDX RF2 definition. The manipulations involved in data
4. Load Ml , X into AR LDA RFl, 1 preparation, which represent a major portion of
M5 is the label of the jump instruction which the "housekeeping" labor in programming, are
provides the gating input to connection # 5. M6 thereafter accomplished automatically along with
is the label corresponding to the readout of the the translation of the functional operations of the
first word on the list. Thus an instruction calling elements in the Data Circuit.
for a jump to M6 would result in the execution of
instructions 3 and 4, and eventual return to the Application of Computer Graphics to
loop at instruction 1. Ml, X stands for the X'th the Design of Data Flow Circuits
entry in the file whose base address is in Ml, and The second key element in the technique of
where X is the contents of the index register. Graphical Automatic Programming is the utilization
The DATA SPLIT element routes a data signal of the newly available computer-driven displays
from one element to as many as five other circuit to help the designer layout a satisfactory Data
elements. The data input is temporarily stored by Flow Circuit, and at the same time store in the
the code: computer a complete description of the circuit as
1. Store AR in Ml STA DSI drawn. This latter step lays the necessary founda-
tion for automating the transformation of the
The DATA GATE is used to inhibit the flow
Data Circuit directly into computer code. The net
of a data signal until a control signal is received.
result is an enormous saving in time in the overall
At that time the data input, which had been stored
process of Data Flow circuit design, checkout, and
in a temporary memory location, Ml, is reloaded
translation.
into the general register for subsequent processing.
The development of computer graphics termi-
The corresponding code is:
nals enables the engineer to use the computer
1. M2: Load Ml in AR DG2: LDA DGI without writing a computer program. An example

10 APL Techn ical Digest

 of a modern graphics terminal is the mM 2250, above for conventional electronic circuits. The
which can be driven by most of the IBM 360 symbols used are those defined in Fig. 3 for the
computers. The display has a 10-in. x 10-in. Data Circuit elements, with the appropriate char-
cathode-ray-tube screen, a typewriter keyboard, a acter code specifying the member of the element
set of special control keys, and a light pen for class. Figure 4 shows the display of the circuit of
direct interaction between the display and the op- Fig. 2 on the IBM 2250 terminal.
erator. The operator uses the light pen to indicate
the point at which he wishes a line or -other symbol
to appear, or the symbol which he wishes to select,
erase, or otherwise operate on as he may direct
by the keyboard.
Graphics terminals have greatly broadened the
utility of computers as direct aids to many human
tasks. By enabling the operator to "talk" with
pointers and English words rather than through an
elaborate code, they are revolutionizing many
tasks. For example, a computer program called
"ECAP ," together with a graphics terminal, en-
ables an engineer to "draw" an electronic circuit
on the face of the display, punch in the component
values he wishes to try, and in a few moments it
gives him the salient characteristics of the circuit.
If these characteristics are outside the desired
limits, the engineer can adjust component values,
alter connections, insert or delete components,
and get essentially instantaneous feedback of the
effects on performance. This technique promises Fig. 4-Graphic display of circuit of Fig. 2.
to shorten the time for circuit design drastically.
In the graphic display program for the design The GAP graphic display program is designed
of electronic circuits, the available components to fulfill the following functions:
are first displayed at the bottom of the screen.
1. To display the element symbols located by
They are then located in the circuit by pointing in
the designer, storing the location of all element
tum to the desired component and then to the
connections.
desired location on the screen with the light pen.
2. To display the data and control connections
The scanning beam in the display recognizes the
between the elements, and any special notation
location of the light pen, associates it with the
entered by the designer, including data prepara-
component, and positions it accordingly. Elements
tion.
are connected by simply pointing the pen at each
3. To associate the linked elements into an
of the terminals to be joined.
"Interconnection Matrix."
The successful development of such a powerful 4. To check for any obvious errors in the dia-
technique for the design of electronic circuits sug- gram and to signal them to the designer.
gested that computer graphics might equally help 5. To interact with the designer in the later
accomplish direct and real-time transformation stages of program generation by displaying anom-
of Data Circuits into computer routines. The alies or altering the circuit as directed.
programming of the computer to accomplish this
is, of course, quite different from "ECAP ," but Example of the Graphical Design of a Data
the property of communication between the engi- Flow Circuit-The following elementary process
neer and computer by means of symbols and light illustrates how a simple Data Flow Circuit would
pen is the same. be designed.
The display of a Data Circuit is accomplished Data Inputs:
in the same general manner as that described 1. A number of potential target returns or

S eptem ber - O cto ber 1969 11

"hits" have been received by a radar during sev- The representation of this data process in Data
eral dwells. Flow Circuit language can be accomplished by
2. The Amplitude, A, and Range, R, of each the use of three functional elements.
hit have been encoded into a single word A, R. 1. READ FILE, to extract each hit from the
3. The hits have been listed sequentially in a hit entry file.
file. 2. COMP ARE, to select hits whose amplitude
Data Processing: equals or exceeds the threshold.
1. All hits whose amplitude equals or exceeds 3. WRITE FILE, to enter the selected hits into
a certain threshold are to be retained and stored another file for retention.
in another file for further processing.
The designer selects the READ FILE (RF)
2. Other hits are to be rejected.
and WRITE FILE (WF) from the TRANSFER
The representation (If this process in a con- elements and positions them on the screen with
vential programffier's Logic Flow Diagram is the aid of a ~ -in. grid used during circuit assem-
shown in Fig. 5. In the figure, a potential target bly. He positions the COMPARE (CP) element
return is called a "HIT," and a return exceeding to qne side to provide the path for the hit selection
the threshold is called a "TRK·," a mnemonic for logic. He then selects and locates the signal
"track." The diagram shows the steps required in ROUTING elements and connects the element
indexing and the three decision branch points inputs and outputs with data (solid) or control
which occur when the amplitude is below the ( dashed) lines. The ROUTING elements required
threshold or when either file is exhausted. are a DATA SPLIT (DS) to route the extracted
hit to both the COMP ARE element and the
WRITE FILE element, and a DATA GATE
(DG) to pass the hit for entry only if the com-
parison shows that its amplitude passes the thresh-
old. The partially completed circuit diagram is
shown in Fig. 6a.
The next step is to enter the arrows marking the
input end of each connection, as well as other
auxiliary labels and symbols (Fig. 6b). Where
data inputs are to be stored in permanent memory
locations, the input is indicated by a diamond with
a symbol denoting the variable. Where a data
input requires preparation, such as extracting the
amplitude A from the hit word (R, A), the input
arrow is closed into a triangle.
In order to help him remember the data and
control inputs to the different elements, the de-
signer may type in appropriate symbols on the
keyboard and place them on the diagram by
means of the light pen. In Fig. 6b the file names
"HIT" and "TRK" are indicated on the RF and
WF elements, the number of hits "NHT" and the
number of empty spaces in the TRK file "JTK"
are indicated by the abbreviations "N" and "J,"
respectively, and the threshold and amplitude con-
nections 09- the CP element are indicated by the
symbols "T" and "A."
Figure 6b includes a CONTROL JUNCTION
(CJ) element and a connecting link from it to the
WF element that are not shown in Fig. 6a. Figure
Fig. ~Hit Sorting logic flow diagram. 6b also shows connections marked "EX" (Exit)

12 APL Techn ical Digest

 The data tables stored in the computer to gen-
erate the above circuit design on the 2250 could
be converted by an automatic program into a table
of logical connections represented by the circuit.
A simpler approach, however, is to use the graphic
routine initially for the sole purpose of remember-
ing graphical elements, and not their logical con-
nections. A connection within the circuit can then
be entered by the designer after he is satisfied
with the display by simply touching the light pen
to each end of a link. This avoids the housekeep-
ing overhead associated with remembering
"bends" in lines representing links, and circum-
vents the necessity of encoding logic to handle
deletions and additions of line segments.
Element Interconnection Matrix-The infor-
mation concerning the configuration of the
(a) Partially completed circuit. Data Flow Circuit entered by the designer is or-
ganized by the graphics display program into a
table which will be called the Element Intercon-
nection Matrix. The matrix for the circuit de-
scribed in Figs. 6a and 6b is shown in Table 2.
The first three columns contain the element name,
reference number in the circuit, and code. The
next six numbered columns are the labels of the
terminations of each respective connection. Each
connection which is linked to another element in
the circuit is labeled with the code and connection
number of that element. For example, the entry
"DS 1" in column 4 of row 1 means that connec-
tion # 4 of RF is linked to connection # 1 of DS.
Since there may be several elements of a given
type in a single circuit, in actual practice the labels
would use the reference numbers instead of the
element code letters.
(b) Completed circuit.
In the above example, the reference number
"4" of the DS element would be used instead of
Fig. 6-Sample circuit displayed on the IBM 2250
the code letters "DS" in labeling the link. The
terminal.
matrix entries also indicate when "Data Prepare"
to the RF and WF elements. The appearance of operations are to be performed on data inputs or
these features illustrates how the GAP graphics outputs, referring to a separate list where each
program would discover formal errors or omis- operation is specifically defined. Such an entry is
sions by the designer in connecting the circuit made in column 2 of row 2, and defined in the
elements. The computer examines each connec- note below the matrix.
tion to see whether it has been assigned its proper Each connection in the matrix which is linked
function, i.e., data or control, input or output, to an input and output from the circuit is desig-
and indicates omissions or incompatibilities by nated by a label representing the respective file,
flashing or otherwise marking the connections in- variable, or control instruction. For example, the
volved. The designer would correct such errors entry "NHT" in column 2 of row 1 stands for
before initiating the transformation of the circuit the data entry for the number of hits to be read
into computer code. out of the file named "HIT." These designations

S ep tem ber - O ct ob er 1969 13

 TABLE 2
ELEMENT INTERCONNECTION MATRIX

Elements Linkages Connections

Ref·
Name No. Code 1 2 3 4 5 6 1 2 3 4 5 6
READ RF HIT NHT EXH DSI CJ1 ENT D J 0 C C
1 D
FILE
COMPARE 2 CP - DS3-P - DG3 CJ2 THR U D U J J D
WRITE 3 WF DG2 JTK EXT TRK - CJ3 D D J D U J
FILE
DATA 4 DS RF4 DGI CP2 - - - D 0 0 U U U
SPLIT
DATA 5 DG DS2 WFI CP4 - -
- D 0 C U U U
GATE
CONTROL 6 CJ RF5 CP5 WF6 - -
- J C C U U U
JUNCTION
P PREPARE: MASK A

are separately identified by the designer and opposed to an ordinary digital circuit, signals flow
recorded in a "Dictionary" accompanying the in a succession of steps, each representing the
set of Data Circuits which will be combined into transfer of a signal from an output of one element
the total program. to an input of an adjoining element. The trans-
The last column of the matrix designated "Con- formation of a Data Flow Circuit into an opera-
nections" indicates the type of each connection, tional sequence involves putting these steps into
namely: an order which can be performed efficiently by
D Data Input a general-purpose computer. A remarkably sim-
o Data Output ple set of rules produces a program that has high
C Control Input efficiency and is free from any evident pitfalls.
J Control Output These rules are listed in Table 3. They are divided
U Unconnected
TABLE 3
The data in this column enable the program to
CIRCUIT TRANSFORMATION RULES
make sure that an output always goes to an input
and that each element has the appropriate type of Output Sequence Priority
connections. 1. Last Data Output
2. Last Control Output
Transformation of Graphical into Input Handling
Logical Form
The third key feature of Graphical Automatic Element Initial Data Final Data or
Programming is the automatic transformation of Type Input Control Input
the Element Interconnection Matrix, generated by 1. FUNCTIONAL Put in Write
the graphics terminal from the Data Flow Circuit, Temporary Function
Store Code
into the desired computer program. This requires
2. DATA Jump to
the translation of the designated process repre- JUNCTION Termination
sented by a two-dimensional circuit diagram into _ 3. CONTROL Change
a one-dimensional sequence of computer instruc- JUNCTION Termination
tions. The noteworthy facts are that this trans- of Inputs
to that of
formation can be done entirely automatically and Output
that the resulting program is highly efficient in 4. DATA Write
execution time and Core usage. LOOP Function
Code
It will be recalled that in a Data Flow Circuit, as

14 APL T echnical D igest

 into "Output Sequence Priority" rules and "Input tion of the DL element in the Operational Se-
Handling" rules. quence at the point where the direct input arrives.
The logic behind the Sequence Priority rules The function code is written to include both the
is the following: direct and feedback mode with a label to identify
the address of the "Jump" instruction from the
1. When an element produces a data output,
feedback path.
this output is in a general register of the computer.
It is more efficient to operate on this output while Transformation of a Data Flow Circuit-
it is in a general register than to go to another The application of most of the above rules to the
operation, since this saves the steps of temporarily translation of a Data Circuit into computer in-
storing the output and later reloading it in a structions can be illustrated by going step by step
general register. Therefore, the element to which through the process on the very simple circuit de-
the output is connected is first examined to see if scribed in the previous section. This is shown in
it is ready to operate. Figs. 7 a, b, and c.
2. When no data outputs remain, selecting the Figure 7 a shows the first step in the transforma-
latest control output insures that any internal loop tion process. The process begins by tabulating
in the circuit will be closed inside of any larger and labeling the inputs and outputs connecting
loop. Entry inputs to the circuit are listed at the the circuit block to other blocks in the overall
beginning of the program as control outputs of program. The external data inputs are: two con-
external circuit blocks. nections to files-HIT and TRK, and three data
word inputs-the file indices NHT and JTK, and
The Input Handling rules are the following:
the threshold THR. There are three external con-
1. For the four types of functional element trol inputs and outputs: one enter, ENT, and
the rules for handling inputs were described two exits, EXH and EXT.
earlier. They state that an element is activated to It is helpful to assign a section of the computer
function by the arrival of the last input, whether program to the definition of the labels used in the
a data or control signal, and that data inputs instruction code. This section, usually called the
arriving previously are stored until needed. "Linkage" or "Assembly" area, defines the labels
2. The DATA JUNCTION element is equiva- used in referring to each external connection. The
lent to an "or" gate combining several alternative resulting assembly code, in DDP-516 language,
data signal inputs into a single output. This is is given in the top block at the right side of Fig.
effected in computer code by a "Jump" instruc- 7a. The instruction "DAC" stands for "Declare
tion to the point in the program to which the DJ Address Constant" and serves to define the labels
element is connected, thereby joining the input used in the assembly code for the circuit in terms
paths. of labels for variables and files defined for the
3. The CONTROL JUNCTION element per- overall program. The labels used for all memory
forms the same function for control signals. Since locations are defined in terms of the element con-
a control output is already a "Jump" instruction, nections, as used in the Element Interconnection
this element does not require writing additional Matrix.
code, and is translated simply by changing the The Linkage section will later be used to con-
termination of each junction input to the termina- nect the circuit block to others in the program.
tion of the junction output. Other circuit blocks may be in a different section
4. The DATA LOOP element has two data of the computer memory, and in the DDP-516
inputs-one direct and the other a feedback from have to be addressed by the "indirect" memory
the processed direct signal. Its function is to out- address mode. An asterisk is used to indicate in-
put the direct signal upon its arrival, and to hold direct addressing.
the feedback signal until the arrival of a control The listing of the external connections in the
feedback gating signal for processing the feedback Linkage section produces one control output,
signal through another cycle of the loop. It is namely from the Enter symbol to RF6. This and
translated into code in a similar manner as the other outputs are listed in Fig. 7a at the right of
READ FILE element, which also has a direct and the instruction block.
feedback mode. This is done by placing the execu- The first link to be made in the circuit is the

Sep tem ber - O cto ber 19 69 15

 ENT~~Hl
:-------~$~ EXH
LABEL
RFl
WF4
INSTRUCTION
DAC
DAC
HIT
TRK
OUTPUTS

: THR A RF2 DAC NHT

1 WF2 DAC JTK
1 CP6 DAC THR
A RF3 DAC EXH
CJ :--- WF3 DAC EXT
1 RF6 DAC ENT
I
1 RF5 IRS * RF2
1 SKP
I JMP * RF3
1
L________ _ RF6 LDX
LDA
*RF2
*RFl
WF
-~EXT
a LINK 1
TRK

HIT
LABEL INSTRUCTION OUTPUTS
RF5 IRS * RF2
SKP
,..---------- 5
I
3 -{> EXH
RF6
JMP * RF3
LDX *RF2
~ :. EI}
I
LDA *RFl ~ CD
: THR
I CD I I STA DSl I ~ CD
D - DS3 CD
I

~
CJ ~ -- 5 3
CD ANA CP2
CAS *CP6
12 CD 4 JMP DG3
I JMP DG3
I
I JMP CJ2
I
I CD I DG3 I LDA
I
L_________ _ JTK CD LDX *WF2
STA *WF4
WF IRS *WF2
3 JMP * CJ2
tEXT
b LINKS 2 to 7 JMP WF3
TRK

HIT

ENT ~- LABEL I NSTRUCTI ON OUTPUTS

RF5 IRS *RF2
SKP
,..---------
1
5
RF6
JMP * RF3
LDX * RF2
1 LDA * RFl

@
: I THR
STA DSl
ANA CP2

~
CAS CP6
JMP DG3
CJ 1- - -
JMP
31
DG3
I ® JMP RF5
1 DG3 LDA DSl
I LDX *WF2
I STA *WF4
I JTK IRS *WF2
L _________ 6
® JMP RF5 £. :.~i CD
CD WF JMP *WF3 ~ :.'{!F.HD
3 -~ EXT CP2 DEC MKA I ~ :.Bf2. ®
C LINKS 8 to 11 TRK CD

16 APL Technical Digest

 connection of the above output to the READ DS 1 into the input of the DG element, and hence
FILE element. Since the index data input is al- the operation:
ready available in the Linkage, the RF element 4. Change label on DGI to DSI.
functions when the control input RF6 arrives.
This step results in the following set of operations At this point we note the distinction between a
which transforms the circuit into computer code: true electronic circuit and a GAP circuit. In an
1. Write code for RF element in its gated form. electronic circuit, signals in lines emanating from
List data output RF4. a branch are processed in parallel, whereas in
List control output RF3. most computers only one branch can be executed
at a time. In GAP, a DATA SPLIT automatically
In accordance with the priority rules, the last stores the input as it arrives, then processes one
data output, RF4, is chosen as link 2, the next branch, and later processes the other branches.
step in the transformation. This and the subse- The order of execution of elements connected to
quent five steps in the transformation of the circuit the branches of a DATA SPLIT is controlled by
are illustrated in Fig. 7b. The number of each use of gates either on the elements themselves or,
output selected, the corresponding link formed as in the sample circuit, by the use of the DATA
in the circuit, and the resulting block of code are GATE routing element. This element is used here
shown by a circled number. The Linkage section so that the code for the COMPARE function will
of code is not repeated, for the sake of brevity. be written before the code for the WRITE FILE
The arrival of the data input to the DATA element.
SPLIT element in this step is sufficient to cause it The next output in priority is the last control
to function. This stores the input temporarily output, CP5, and hence initiates Step 5. This out-
and produces two data outputs. The transforma- put provides one of the two necessary inputs to
tion results in the following operations: the CONTROL JUNCTION element and results
in no code.
2. Write code for DS element.
Output CP4, Step 6, completes the required
List data output DS2.
inputs to the DATA GATE. This step results in
List data output DS3.
the operations:
The last data output from Step 2 is DS3, and it
6. Write code for DG element.
is chosen as Step 3 in the transformation. This
List data output DG2.
completes the inputs required for the COMPARE
element to function, and results in the operations: Step 7 is to link data output DG2 to WFl,
which causes the WF element to function. This
3. Prepare input CP2.
results in the operations shown in the last block
Write code for CP element.
in Fig. 7b:
List control output CP4.
List control output CP5. 7. Write code for WF element.
List control output WF3.
The data input to CP has to be prepared by ex-
List control output WF6.
tracting the amplitude, A. This is accomplished
by a logical "and" (ANA) masking operation, The final figure of the series, 7 c, shows the
which is included in the first instruction of the completion of the last four links in the circuit.
block of code written for the CP element. Output WF6 causes the CJ element to function.
According to the priority rules, the remaining The functioning of the CJ element completes the
data output, DS2, is operated on before the con- link to RF and simply changes the labels on the
trol outputs are. This becomes Step 4 in the trans- control outputs CP5 and WF6 from CJ2 and
formation sequence. In order to function, the CJ3 to RF5. The remaining links do not write
DATA GATE element requires the presence of additional code since the exit connections were
the control input as well as the data input. Since already included in the linkage section.
the former has not yet arrived and the latter is The last step is to define the label CP2 in the
already stored in a temporary location, DS 1, the code for the CP element as the mask for extracting
completion of link 4 does not result in any code the amplitude A. This is done in the final assembly
but merely the entry of the temporary store label instruction in Fig. 7c. The notation DEC stands

September - October 1969 17

for a decimal number. MKA stands for a number the memory location of a data-input or of the in-
which, when translated into binary code, forms struction for a jump. The status or location of
the mask for extracting A. each input (in memory or in a register) is desig-
Element Operational Sequence-In Fig. 7 nated by code letters defined below the table. This
the Data Circuit was transformed directly into information, together with the basic definitions of
computer assembly code. In actual practice it is each element in terms of the code for a particular
useful to divide this process into two steps. computer, is sufficient to translate the Operational
Sequence into computer assembly code.
1. Transformation of the Element Interconnec-
The Element Operational Sequence has a form
tion Matrix into an Operational Sequence.
entirely independent of the computer for which
2. Compilation of the Operational Sequence
the program is to be written. Thus it represents
into Computer Code.
a set of high level or "macro" instructions, which
The first step is the really fundamental one, can now be translated into the assembly code of
since it converts the two-dimensional matrix into any desired computer by a "compiler." This
a one-dimensional sequence. This is done by process involves a mechanical substitution of the
following the priority order of the circuit trans- code for each element in the operational sequence,
formation rules. During this process some of the with due regard for the mechanics of storing and
signal routing elements effectively disappear after retrieving data from temporary stores as indicated
establishing the sequence of operation of the func- by the notation in the connection field, and the
tional elements and making direct interconnections conversion of label notation to suit the format of
among the functional elements themselves. the specific computer code being written.
The result of this first step for the example dis- The compact and universal form of the Element
cussed above is shown in Table 4. Comparing Operational Sequence means that this intermediate
this table with Table 2 shows that the control junc- step in program design can be used to check the
tion has disappeared, and the connections are program logic using any computer code, including
made directly between the functional elements to the one which drives the graphics terminal, such
which it had been connected. The sequence of as the IBM 360. Thus, compilation of the IBM
operations is given by the numbers in the third 360 version of the code enables the immediate
column. on-line test of the entire logical design of the
The significance of the entries under each con- circuit and of its transformation into the sequence
nection in the Operation Sequence is the following. of operations. If this is successful, the program
The characters at the left designate the label of logic can be considered "debugged" for all practi-

TABLE 4
ELEMENT OPERATIONAL SEQUENCE

Linkage/ Status
Ref
No. Code Seq. 1 2 3 4 5 6
1 RF 1 RFI/* RF2/* RF3/* DSI/O RF5/L RF6/*L
2 CP 3 /U RF4/AMP /U DG3/J RF5 / J CP6/*
3 WF 5 DG2/ AM WF2/* WF3/* WF4/* /U RF5 / J
4 DS 2 RF4/A DGI/O CP2/0 /U /U /U
5 DG 4 RF4/ M WFI/O DG3/L /U /U /U

Status:
* Stored in Linkage Location P Data to be prepared o Data Output
A Data in general register L Labelled Instruction J Control Output
M Stored in Memory C Control Input U Unconnected

18 APL T echnical D igest

 cal purposes, inasmuch as the conversion to the HIT HIT
code for another computer involves no change in FILE NUMBER
operational logic. This on-line debugging capa- lHIT lNHT
bility is an enormous advantage inherent in the ENTER ~~~8 1

use of the graphics terminal to effect direct inter- HIT EXH

FILE EMPTY ~ - - 6 HSP 5~THRESHOLD
action with the computer.
TRACK EXT
FILE FULLf"--7 2 4
Integration and Testing of Complex
lTRK jJTK
Programs TRACK FILE
A large data-processing program for a large- FILE INDEX
scale system can be represented as a Data Flow
Block Diagram, in which each block is an indi- Fig. 8-Hit Sorting Program block.
vidual Data Flow Circuit. Each Circuit Block can
be regarded as a special "Macro" Circuit element, 2 control outputs. By reference to Fig. 7 a it can
with data and control signal inputs and outputs also be seen that all of these connections are em-
connecting it to other blocks which comprise the bodied in the Linkage Section of the code for the
total program. The integration of Data Flow block. This section is equivalent to a terminal
Circuits is readily accomplished by the use of the strip in a piece of electronic equipment.
graphics terminal and a special Integration Pro- The integration of program blocks into the total
gram in a manner similar to that used in con- program is simply done by drawing the program
structing the Data Flow Circuits. This program Block Diagram on the graphics display and mak-
serves the purpose of a "Linkage Editor" in com- ing proper connections between the individual
puter terminology. blocks. In such a diagram, it is important to keep
The representation of a Data Flow Circuit as a all files external to the processing circuits.
Program Block is shown in Fig. 8, using the Hit An example of such a diagram is shown in Fig.
Sorting Program as a simple example. It is seen 9, which represents the Track Prediction module
that the block has 8 connections, namely 4 of the 3D Radar Automatic Tracking Program.
data inputs, 1 data output, 1 control input, and The program blocks are represented by rectangles

RADAR TRIGGERS .--_ _ ___

1
1 DWELl
EXEC.

EL SCAN TARGET COORDINATE

EXEC. COMPUTATION

- --I
--- 1
'--_~ I I

TARGET TRACK
PREDICTION

Fig. 9-Track Prediction module.

S ep tem ber - O ctober 1969 19

 and the data files by squares. The block illustrated 3. Circuit Blocks
in Fig. 2 is near the center of the diagram. 4. Modules
The very important function of synchronizing
In addition, areas of memory must be allotted
the operations of the program with the real-time
to store each of the above.
schedule of radar transmission, elevation scanning,
Once the above terms have been defined, their
and rotation is accomplished by three "Executive"
subsequent use requires only reference by code
blocks supervised by a master Executive block.
name. The computer automatically looks up the
The Data Flow representation is ideally suited to
necessary characteristics in the Program Diction-
visualize the detailed interactions between the
ary. This saves a great deal of housekeeping by the
high-priority, real-time functions and the support-
system designer, and should eliminate a major
ing functions which may be accomplished with
source of error.
loose scheduling.
The transformation of the Block Diagram into Program Checkout-The most laborious and
computer assembly code involves only the proper time-consuming part of programming is the elimi-
correlation of the block linkage labels, where all nation of errors, or "debugging." It is in this area
inputs and outputs are listed. Since the module that Graphical Automatic Programming is likely
is itself a "block," as seen in Fig. 10, the next to produce the greatest benefit in program design.
higher level of program integration is done in The power of this technique to facilitate the pro-
terms of entire modules rather than blocks. In duction of a correct program stems from the fol-
this wayan orderly and flexible format for the lowing sources:
total program can be achieved. 1. The Data Flow Circuit representation ren-
ders the pattern of data and logic flow highly
visible and hence eliminates many errors at the
RADAR
COORD. GATED HITS
source.
l_ l 2. The entry of the Data Flow Circuit into the
computer enables a virtually instantaneous check
DWELL I ~-":-_-7, GATE
NO.
of any inconsistencies in the design by checking
B~~~~ +-(- -of TRACK the Element Interconnection Matrix and monitor-
SCANI(:.-:.":_~
PREDICTION ing its transformation into computer code.
EL MODULE
3. The display of the circuit by the graphics
SECTOR I;:'-:"~ terminal enables the designer to correct errors

r
BEARING
ELEVATION
IT
RANGE
immediately by altering the circuit and verifying
that the errors have been eliminated.
4. The GAP technique is ideally suited to rapid
and thorough testing of the program at any desired
Fig. lo--Program module. level of realism. Thus, upon completion of a con-
stituent circuit, the designer can test it by entering
Program Dictionary-The efficient manage- sample inputs and reading out the resulting out-
ment of the process of program design requires puts. He can also quickly design a test program
careful definition , organization, and maintenance in the form of another Data Circuit which would
of all terms used in the program. The list of these perform a realistic simulation of the program in-
properties has to be assembled during the design put and automatically compare the results with
process and, when complete, constitutes a basis requirements.
for fully documenting the program and facilitating
A particularly important type of test that may
future changes.
be performed automatically is that of compatibility
The data required for this list include the code
with real-time operation. Since the functioning of
names, definitions, format, constituent parts, and
each element corresponds to a definite execution
cross-references of all of the following in a Pro-
time in the computer to be employed, it is readily
gram Dictionary:
possible to have the test program simulate the
1. Variables and constants execution time and monitor it against specified
2. Data Files events.

20 APL Tech nical Digest

 Design of Data Flow Circuits (WF) elements to read out data on new hits,
The representation of data-processing opera- previous entry, and to store updated coordinates.
tions in the Data Flow Circuit form has turned out 2. CORRELATE (CR) element to check
to have all of the characteristics which were range correlation.
sought for in a basic language for the program- 3. COMPARE (CP) element to compare
ming of real-time systems. For those interested amplitude of new and previous hit.
in how a given problem is translated by the de- 4. ADD (+) elements to increment the num-
signer into a Data Flow Circuit, the paragraphs be- ber of hits.
low illustrate how one might design the circuit 5. AVERAGE (AV) elements to combine
illustrated in Fig. 2. bearing and elevation for hits of equal amplitude.
The design of a particular Data Flow Circuit is The table also helps to arrange these operations
best approached by constructing a "cause-effect in an efficient order in the circuit. It is evident,
table"-similar to a "truth table" or "decision for example, that the range correlation check
matrix" in mathematical logic. This lists the possi- should be made before amplitude comparison.
ble combinations of input conditions and the cor- With the aid of this type of logical organization,
responding outputs. For its application to the the layout of a Data Circuit such as the one shown
Target Coordinate Computation Circuit illustrated in Fig. 2 follows quite readily. The representation
in the figure, the logic is as follows: is intuitively easy to use by engineers, and makes
it relatively simple to configure the routing ele-
1. If no prior hit exists in the target data file ments to minimize the total number of instruc-
(TD4), set number of hits = 1 and store coor- tions. For example, convergence of the data paths
dinates of new hit in target data files (TD4, TD5). before storage of the updated coordinates is an
2. If previous hit exists, but does not coincide obvious saving in code. This type of optimization
in range with new hit, exit to multiple target is made much more visible by the Data Circuit
routine. representation than by the conventional sequential
3. If previous hit correlates in range, increment logic approach.
number of hits, store target coordinates of strong- The Data Circuit language thus makes it possi-
est hit. ble for an engineer to design the data flow process,
This leads to the following cause-effect table in a form with which he is intuitively familiar, to
in which A is amplitude, 6R is range increment achieve the best balance between operational re-
within the gate, B is bearing, E is elevation. quirements on accuracy, capacity, and timing
within the limitations of available computer speed
From the cause-effect table it is evident that
and size. The language is also directly interpretable
the following functional elements will be required.
by a programmer, so that even without the auto-
1. READ FILE (RF) and WRITE FILE matic features it bridges the communication gap

Conditions (Cause)
Previous entry in TD4,
(A, ~R) None Yes Yes Yes Yes
~R of hit correlates with
previous entry No Yes Yes Yes
Amplitude of hit compared
to previous entry Greater Equal Less

Actions (Effect)
Number of hits Set = 1 Add 1 Add 1 Add 1
Store in file TD4,
(N, A, ~R) New hit New hit Previous Previous
hit hit
Store in file TD5,
(B, E) New hit New hit Average
Other Exit

September - October 1969 21

which currently represents one of the greatest have developed a program for displaying GAP
impediments to the economical design of system circuits on the IBM 2250 terminal.
"software. "
I should like most particularly to acknowledge
Acknowledgment the very significant contribution of Lee Hoevel to
In seeking to make the subject of this paper the development of the Graphical Automatic Pro-
clear to all readers with a possible interest in its gramming concept. This very appropriate name
application, I obtained many valuable suggestions and its acronym, GAP, are his ideas. As an expert
from R. P . Rich, W. H. Guier, W. N. Sweet, and programmer, he provided the first authoritative
J. R. Austin, which I gratefully acknowledge. confirmation that the transformation of a Data
R. R. Newton was particularly helpful in this regard. Circuit to a computer program could in fact . be
I wish also to acknowledge the help of D. M. carried out unambiguously and could produce
White, who has been the first to actually use Data efficient code. He has given much time after work-
Circuits for designing SIMFAR-a major radar ing hours to critical discussions of every aspect of
simulation program, and therefore has been iri a the design of the language and to its presentation
position to demonstrate the utility of this concept. in this paper. Working with him has been a most
W. T. Pullin contributed his expert knowledge of enjoyable experience, and I look forward to col-
computer graphics to the design of GAP symbols, laborating with him in the further development
with the result that they are both visually clear and and implementation of the Graphical Automatic
easy to generate. W. T. Pullin and S. E. Anderson Programming technique.

WITH THE AUTHOR

A. KossiakofJ, author of "Graphi- siakoff has been awarded the Pres-

cal Automatic Programming," is the idential Certificate of Merit and the
Director of the Applied Physics Navy's Distinguished Public Service
Laboratory. Dr. Kossiakoff received Award.
a B.S. degree in chemistry from Dr. Kossiakoff has been involved
California Institute of Technology in systems engineering for many
in 1936, a Ph. D. degree in chemis- years. About two years ago he de-
try from The Johns Hopkins Uni- cided to learn the details of com-
versity in 1938, and then spent a puter programming in order to get
year as a post doctoral fellow at a better assessment of the problems
California Institute of Technology. involved in their rapidly growing
He taught at The Catholic University applications to the automation of
of America (1939-42) , then served complex systems. He found this fiel d
with O.S.R.D., and was Deputy Di- so interesting that he devoted a
rector of Research at the Allegany good deal of his spare time to the
Ballistics Laboratory, Cumberland, design of a computer program fo r
Maryland from 1944 to 1946. the automatic detection and tracking
Dr. Kossiakoff joined the Applied of aircraft by a three-dimensional
Physics Laboratory in 1946, and radar. The ideas discussed in this
served as head of the Launching paper stemmed from his experience
Group until 1948, when he was ap- with the difficulties of using exist-
pointed Assistant Director. He be- for the U .S. Navy, particularly in ing techniques for the application of
came Associate Director in 1961 , the design and implementation of computers to complex real-time
Deputy Director in 1966, and was guided-missile defenses for the fleet. systems.
appointed Director on July 1, 1969, From 1948 to 1951 he served as Dr. Kossiakoff is a member of the
when Dr. R. E. Gibson retired as Chairman of the Panel on Launch- American Chemical Society, Ameri-
Director of the Laboratory. ing and Handling of the Department can Association for the Advance-
Dr. Kossiakoff has made impor- of Defense Research and Develop- ment of Science, The Philosophical
tant contributions to the develop- ment Board. In recognition of his Society of Washington , and the
ment of advanced weapons systems work on national defense, Dr. Kos- Cosmos Club.

22 .-\PL T ech nical Digest