Experiment 7

Interrupts and ISR Programming

Interrupt Control in Cortex M4

TM4C123GH6PM implements Nested Vectored Interrupt Controller to handle the interrupts.

All the exceptions and interrupts are processed in handler mode. The processor returns to the
thread mode when it is finished with all exception processing. The processor automatically
saves its current state to the stack when it accepts an interrupt to be serviced. The state is
automatically restored from the stack upon the exit from the interrupt service routine (ISR).
When an interrupt occurs, state saving and vector fetch are performed in parallel reducing
interrupt latency and enabling effcient interrupt entry.
Software can set eight priority levels (0 to 7: a higher level corresponds to a lower priority, i.e.,
level 0 is the highest interrupt priority) on seven exceptions (such as, reset, software interrupt,
hardware interrupt, bus fault, etc.) and 65 interrupts.
When an interrupt occurs and it is accepted by processor core, the corresponding interrupt
service routine is executed. Starting address of each interrupt is loaded from the vector table
which is an array of word-sized data. Each entry in the vector table points to the starting ad-
dress of one exception or interrupt handler. The vector table is located at address 0x0000.0000
after reset.
Every exception/interrupt handler is located at the address obtained by multiplying the corre-
sponding exception/interrupt number with 4. For example, if the reset is exception type 1, the
address of the reset vector is 1 times 4 (each word is 4 bytes), which equals 0x00000004, and
NMI vector (type 2) is located in 2 × 4 = 0x00000008. Consult table 2-8 and 2-9 for the entries
of the vector table from article 2.5.2 The Cortex-M4F Processor - Exception Types of
the datasheet.

Processor Interrupt Configuration

Global level configurations of interrupts are handled at processor level. These are handled by
PRIMASK, FAULTMASK and BASEPRI registers. The default values of these registers are
such that all interrupts are enabled. However, in case of critical code execution, that should not
be interrupted, global interrupt enabling and disabling can be performed. For that purpose,
either the PRIMASK or FAULTMASK register can be used. The PRIMASK register prevents
activation of all exceptions with configurable priority. The FAULTMASK register prevents
activation of all exceptions except for Non-Maskable Interrupt (NMI).

Copyright © 2023 Department of Electrical Engineering, University of Engineering and Technology Lahore,
Pakistan. Permission is granted to copy and distribute for educational purpose. However, any commercial use
of the material, in any form, is not allowed.
Base Priority Register
The flexibility in masking the interrupts is introduced by the BASEPRI register. The interrupt
masking by the BASEPRI is performed depending on the current priority level configuration.
Since the number of priority levels in TM4C123GH6PM is 8, it requires 3 bits to be used by
the BASEPRI register (Figure 7.1).

Figure 7.1: 3-bit implementation for the BASEPRI register

When BASEPRI is set to a non-zero value, it blocks all the interrupts of the same and lower
priority, while it allows the processor to accept the interrupts of higher priority for process-
ing. When BASEPRI is set to 0, it is disabled. These interrupt masking registers are accessed
through special register access instructions. Move to special register from general-purpose regis-
ter (MSR) and move special register to general-purpose register (MRS) assembly programming
instructions are used for this purpose. Add the following lines of code before the Re-
set Handler in your startup file.

EXPORT DisableInterrupts
EXPORT EnableInterrupts
EXPORT EnablePriorityInterrupts
EXPORT WaitForInterrupt

DisableInterrupts
CPSID I ; s e t PRIMASK t o d i s a b l e interrupts
BX LR

EnableInterrupts
CPSIE I ; c l e a r PRIMASK t o e n a b l e i n t e r r u p t s
BX LR

EnablePriorityInterrupts
MOV R0 , #0 x 4 0 ; s e t b a s e p r i o r i t y 2
MSR BASEPRI , R0
BX LR

WaitForInterrupt
WFI
BX LR

NVIC Configuration
Note: The register map for NVIC is to be consulted from article 3.2 - Cortex-M4 Periph-
erals - Register Map of the controller datasheet.

Copyright © 2023 Department of Electrical Engineering, University of Engineering and Technology Lahore,
Pakistan. Permission is granted to copy and distribute for educational purpose. However, any commercial use
of the material, in any form, is not allowed.
To activate an interrupt source, following two steps must be followed:

1. Enable the source from the corresponding NVIC enable register.

2. Set the priority for that interrupt.

For better understanding, we discuss the example of enabling the interrupt for Port F. Follow
the following steps to activate the interrupt for port F.

1. Find the interrupt number (i.e., bit position in interrupt register) from Table 2-9 (2nd
column) corresponding to GPIO Port F (Figure 7.2).

Interrupt Number

2. Find the interrupt register that is needed to enable IRQ30 from Table 3-8. It is NVIC EN0 R.
So, it tells you that you need to set bit 30 of NVIC EN0 R to 1 to enable interrupt on
Port F (Figure 7.3).

Interrupt Enable

3. From Table 3-8, find the register needed to set the priority of IRQ 30. It is NVIC PRI7 R
(Figure 7.4).

Interrupt Priority

To set a priority value, say 5, you may use the following statement in C:
NVIC_PRI7_R = ( NVIC_PRI7_R & 0 xFF00FFFF ) | 0 x00A00000 ;

Copyright © 2023 Department of Electrical Engineering, University of Engineering and Technology Lahore,
Pakistan. Permission is granted to copy and distribute for educational purpose. However, any commercial use
of the material, in any form, is not allowed.
Configuring GPIO (Device) as Interrupt
Note: The register map for GPIO is to be consulted from article 10.4 - General-Purpose
Input/Outputs (GPIOs) - Register Map of the controller datasheet.

To configure GPIO pin as interrupt and select the source of the interrupt, its polarity and edge
properties following steps must be followed:

1. Disable the interrupts before writing to the control registers from GPIO Interrupt Mask
register (GPIOIM) Figure 7.5.

GPIO Interrupt Mask Register

2. Select whether the source of interrupt is edge-sensitive or level sensitive using GPIO
Interrupt Sense register (GPIOIS) Figure 7.6.

GPIO Interrupt Sense Register

3. To enable interrupts for both edges write the appropriate value in the GPIO Interrupt

Copyright © 2023 Department of Electrical Engineering, University of Engineering and Technology Lahore,
Pakistan. Permission is granted to copy and distribute for educational purpose. However, any commercial use
of the material, in any form, is not allowed.
 Both Edges register(GPIOIBE) Figure 7.7.

GPIO Interrupt Both Edges Register

4. Write the appropriate value in GPIO Interrupt Event register (GPIOIEV) to configure
the corresponding pin to detect rising (high level) or falling (low level) edges depending
on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register Figure 7.8.

GPIO Interrupt Event Register

5. Clear the interrupt flag for the corresponding pin by asserting the appropriate bit in the
GPIO Interrupt Clear Register (GPIOICR) Figure 7.9.

6. Enable the interrupts by asserting the corresponding bits in GPIO Interrupt Mask register
(GPIOIM) Figure 7.5.

Copyright © 2023 Department of Electrical Engineering, University of Engineering and Technology Lahore,
Pakistan. Permission is granted to copy and distribute for educational purpose. However, any commercial use
of the material, in any form, is not allowed.
 GPIO Interrupt Clear Register

Exercise
Configure an interrupt on SW1 (PF4) that is falling edge triggered and has a priority 5. Write
a code that blinks LEDs of different colours on switch1 press. Template is provided on piazza.
Complete the missing portions. Consult the datasheet where needed.

Copyright © 2023 Department of Electrical Engineering, University of Engineering and Technology Lahore,
Pakistan. Permission is granted to copy and distribute for educational purpose. However, any commercial use
of the material, in any form, is not allowed.