Department of

Electronics and Telecommunication Engineering

Final Year UG Project 2022-2023

Design of CMOS Low Noise Amplifier (LNA)

operating at 4.9-8.9GHz

SUBMITTED BY :
• Amit Bar (302010701004)
• Abhishek Kayal (302010701006)

UNDER THE SUPERVISION OF: Dr. Sayan Chatterjee

 CERTIFICATE

This is to certify that the project report entitled – “Design of CMOS Low Noise
Amplifier (LNA) operating at 4.9-8.9GHz” submitted by Amit Bar and Abhishek
Kayal for the partial fulfillment of the degree of Bachelor of Electronics and
Telecommunication Engineering at Jadavpur University is based on their assigned
project work during the session 2022-2023 under the guidance of Prof. Dr. Sayan
Chatterjee of Electronics and Telecommunication Engineering Department of Jadavpur
University, Kolkata, West Bengal, India.

Project Guide Signature of Student

Signature of Student
 ACKNOWLEDGEMENT
We intend to acknowledge all those who have helped us to prepare this report over its
duration. We would like to express our most sincere gratitude and respect to our
project supervisor Prof. Dr. Sayan Chatterjee, Department of Electronics and
Telecommunication Engineering, Jadavpur University for his constant support, new
ideas, encouragement, valuable guidance and tireless efforts to help us in every
manner during the entire course of the project.We also express our gratitude and thanks
to PhD Research scholar, Shrabanti Das for her support and guidance during our
project work, so that we can bring the best out of our works.

We would also like to thank Prof. Manotosh Biswas, the HOD of Electronics and
Telecommunication Engineering for his initiatives throughout the entire course.

Signature of Student

Signature of Student
 INDEX

Topic Page No
• Abstract 1

Chapter-1:Introduction

1.1 LNA
1.2 Application of LNA 2-6
1.3 Importance of LNA
1.4 LNA as first stage of RF receiver
1.5 Types of LNA
1.6 Advantages and Disadvantages

Chapter-2: Literature Survey 7-23

Chapter-3: Basic Theory of LNA

3.1 Two port Network

3.2 Matching 24-49
3.3 CMOS LNA
3.4 Working of LNA
3.5 Block Diagram
3.6 LNA parameters
3.7 LNA Topology

Chapter-4: Circuit Design 50-55

4.1 Body Floating Technique

4.2 Self Biased Technique
4.3 Flow Chart
4.4 Specifications

Chapter-5: Result and Discussion 56-59

Chapter-6: Conclusion 60-62

• References 63-65
 ABSTRACT

A low noise amplifier (LNA) is an electronic circuit that amplifies a very weak
input signal while adding very low noise to it. LNAs are used in a wide range of
applications, including radio and microwave communications, medical imaging, and
scientific research. The design of an LNA typically involves the selection of a suitable
amplifier topology (such as CS,CG etc.), the careful matching of input and output
impedances to minimize signal loss, and the use of noise-reduction techniques such
as feedback and filtering. Additionally, LNA design must take into account the trade-
off between gain, noise figure, and power consumption.

A Low Noise Amplifier Circuit using CMOS technology has been designed and
simulated its various characteristics parameters with the help of Cadence Virtuoso
Tool.The results (Gain,Noise Figure etc.) are very promising such that it can be sued in
5G wireless communication .
 Chapter-1

INTRODUCTION
1.1 Low Noise Amplifier
A low noise amplifier (LNA) is one kind of amplifier that is specifically
designed to amplify very low-level signals with a high degree of accuracy and very
little noise. LNAs are used in a variety of applications where it is necessary to
amplify small signals with a high signal-to-noise ratio (SNR), such as in radio
telescopes, satellite communication systems, and wireless communication
systems. LNAs are typically designed to have a high gain and a low noise
figure. The gain of an amplifier is a measure of how much it amplifies the input
signal, and the noise figure is a measure of how much noise is introduced by the
amplifier. A low noise amplifier is one that has a low noise figure, which
means that it introduces very little noise into the amplified signal. LNAs can be
designed using a variety of different topologies, like CS,CG etc. The specific
design of an LNA will depend on the specific application it is being used for. A
low noise amplifier (LNA) is a type of amplifier that is designed to amplify
weak signals in the presence of noise. It is typically used in radio frequency
(RF) and microwave systems to amplify small signals that have been received
from an antenna. The primary function of an LNA is to amplify the signal while
adding as little noise as possible. This is accomplished through the use of low
noise amplifier design techniques and high quality components. LNAs are an
important component in many RF and microwave systems, such as satellite
communication systems, radar systems, and radio telescopes. They are also used
in other applications where low noise amplification is required, such as in
medical imaging and instrumentation.

Fig.1.1- Block Diagram of RF Receiver[7]

1.2Application of LNA
▪ In communications receivers such as in telephones, GPS receivers,
wireless LANs (WiFi), and satellite communications.[1]
▪ It is a key component at the front-end of a radio receiver circuit to help reduce
unwanted noise in particular.[2]
▪ It can enhance the performance of software-defined radio (SDR) receiver
systems. SDRs are typically designed to be general purpose and therefore
the noise figure is not optimized for any one particular application. With
performance is improved over a range of frequencies.[3]
Basically LNA is the main part of the RF receiver Circuit and it is the first stage of
RF Receiver. Range of RF signal is about 3KHz-300MHz. LNAs are used in
communications receivers such as in cellular telephones, GPS receivers, wireless
LANs (WiFi), and satellite communications.

Fig1.2- Low Noise Amplifier, Practical Convenient LNA Amplifier for Home for Electronic
Component for Factory for Office[1]
Features-
• The high-quality PCB adopts 1.6mm thick double-sided board, which is durable
and practical.
• Full tinning process ensures good passing performance of large and small
currents.
• The integral molding has no burrs, the surface is smooth, and the installation is
smooth.
• The heat dissipation area is large, and the service life is better improved.
• The working frequency is 50-4000MHz, the amplification gain is 21.8dB, and the
work is stable.

1.3 Importance of LNA

A low-noise amplifier (LNA) is an electronic amplifier that amplifies a very

low-power signal.LNA increases the power of both the signal and the noise
present at its input, introducing some additional noise by itself to the circuit.
LNAs are designed to minimize that additional noise. Designers can minimize
additional noise by choosing low-noise components, operating points, and
circuit topologies. Minimizing additional noise must balance with other design
goals such as power gain and impedance matching.

The low noise performance of an LNA is critical in many applications because

noise can mask or distort the signals of interest, reducing the overall signal-to-
noise ratio (SNR) of the system. A high SNR is important because it allows the
system to detect and process weak signals more effectively, improving the overall
sensitivity and accuracy of the system.In addition to low noise, an LNA must also
have high gain and good linearity to ensure that the amplified signal is faithful to
the original signal. The gain of the LNA determines the amount by which the
signal is amplified, while the linearity ensures that the LNA does not distort the
signal.
 1.4 LNA as first stage of RF receiver
There are several reasons why a low noise amplifier (LNA) is often used as the first
stage of a RF (radio frequency) receiver:

i. Amplification: The primaryfunction of an amplifier is to amplify the strength

of a weak signal. By using an LNA as the first stage of a receiver, the
incoming signal is amplified, making it easier for the rest of the receiver to
process.
ii. Noise reduction: As the name suggests, LNAs are designed to have a low
noise figure, which means they add very little noise to the signal being
amplified. This is important because it helps to preserve the signal-to-noise
ratio of the system.
iii. Impedance matching: LNAs are often used to match the impedance of the
antenna to the rest of the receiver. This helps to minimize reflections and
maximize the transfer of power from the antenna to the rest of the receiver.
iv. Protection:LNAs can also provide protection to the rest of the receiver by
limiting the amount of power that is fed into it. This can help to prevent
damage to the receiver due to high levels of RF power.

1.5Types of Low Noise Amplifiers

There are different types of low noise amplifiers like the following-

i. General Purpose LNA.

ii. GPS/GLONASS/COMPASS LNA.
iii. 4G/5GLNA.
i. General Purpose LNA

These low noise amplifiers mainly include SiGe LNA & Wideband LNA
product families. SiGe-type LNAs are optimized for various supply
currents. They offer low noise figures & absolute stability for Wideband &
MMIC driver amplifiers LNA designs. Their optimized internal transistor
cell arrangement leads to the best noise figures & power gains at high
frequencies.Wideband LNA design offers a variety of high-performance BFP
products. These products utilize silicon germanium carbon bipolar
technology for wireless applications. MMIC driver amplifiers use the
Darlington configuration that offers a single package to RF designers.
ii. GPS/GLONASS/COMPASS LNA

GNSS low noise amplifiers need a low or ultra-low noise RF amplifier and
high linearity to improve the sensitivity of the receiver for best localization
even in low battery or bad conditions. At present, most of smartphones
have navigation applications, which impose even greater demands on size,
linearity & power consumption as compared to stand-alone PNDs
(personal navigation devices). These amplifiers improve signal sensitivity
with very low current consumption and a wide range of voltage supply.[4]
iii.4G/5G LNA

These low noise amplifiers are very important when it comes to

communication systems as well as future technologies. By including a low
noise amplifier to the antenna, then the signal can be improved without
adding extra surplus noise to the system. The main benefits of using these
low noise amplifiers are; high linearity, Ultra-low noise figure & low
current consumption that improves the signal sensitivity, enhances data
transfer rate, increases system integration & power consumption can be
reduced.[4]

1.6Advantages and Disadvantages

The advantages of a low noise amplifier include the following-

▪ These are designed to reduce that extra noise.

▪ These electronic amplifiers are helpful in amplifying very low-
strengthsignals.
▪ This amplifier is used once the SNR or signal-to-noise ratio is high &
needs to be decreased by almost 50% while power is enhanced.
▪ These are commonly available in all receivers.
▪ While designing LNA, we use both active & passive feedback.

The disadvantages of low noise amplifiers include the following

▪ Low noise amplifiers are expensive.
▪ These are very sensitive to flicker noise & DC offsets.
 Chapter-2

LITERATURE SURVEY
A chronological survey of low noise amplifiers (LNAs) would involve
reviewing the development and evolution of LNAs over time. Some key
milestones in the history of LNAs include:

1950s: The first LNAs are developed, primarily for use in radio
astronomy and satellite communication systems.

1960s and 1970s: LNAs become widely used in microwave and

millimeter-wave applications, such as radar and telecommunications.

1980s: Advances in semiconductor technology lead to the development of

low- noise monolithic microwave integrated circuits (MMICs), which
greatly improve the performance and reduce the cost of LNAs.

1990s: LNAs are increasingly used in wireless communications systems,

such as cellular networks and satellite systems.

2000s: The use of LNAs continues to expand in wireless

communications, including in the emerging field of wireless sensor
networks.

2010s: LNAs are increasingly integrated into multi-function devices such

as smartphones and IoT devices.

2020s: Advancements in technologies such as 5G, mmWave

communication and IoT leads to increasing demands for LNAs with high
linearity, high gain and low noise figure.
A Low Noise Amplifier (LNA) is an essential component of any radio
frequency (RF) communication system, which amplifies the weak signals
received from the antenna with minimal added noise. The performance of
the LNA is critical for the overall performance of the RF system, including
its sensitivity, selectivity, and dynamic range. In this literature survey, we
will review the recent advancements in LNA design, optimization, and
performance analysis.One of the key challenges in LNA design is
achieving low noise and high gain simultaneously. Various design
techniques have been proposed in the literature to overcome this challenge,
including the use of feedback, cascode configuration, and common-gate
topology. Feedback-based LNAs offer improved noise and linearity
performance, while cascode configuration provides high gain and improved
output impedance matching. The common-gate topology is also a popular
choice for low-noise and high-gain applications.[5]

Optimization of LNA performance parameters, such as noise figure (NF),

gain, and input impedance, is essential for achieving optimal system
performance. The optimization can be performed using various methods,
including load-pull, noise matching, and multi-objective optimization.
Load-pull optimization involves tuning the load impedance to maximize
the output power and gain, while noise matching optimizes the LNA for
minimum NF. Multi-objective optimization considers multiple performance
parameters simultaneously and provides a trade-off between them.[6]
Various performance metrics are used to evaluate the LNA, including
NF, gain, input/output impedance, linearity, and stability. The choice of
performance metrics depends on the specific application requirements.
For example, in low-power applications, the power consumption of the
LNA is also a critical performance parameter. In high-frequency
applications, the parasitic elements of the LNA become significant,
affecting its performance. Various methods have been proposed in the
literature to analyze the performance of the LNA, including small-signal
analysis, noise analysis, and large-signal analysis.

In this literature survey, we reviewed the recent advancements in LNA

design, optimization, and performance analysis. Various design techniques,
optimization methods, and performance metrics were discussed. The choice
of LNA design and optimization methods depends on the specific
application requirements. Further research is required to develop more
efficient and robust LNA designs that can meet the ever-increasing
demands of modern wireless communication systems.

The recent works are the followings-

In the paper[6] a design of a wideband differential low-noise amplifier

(LNA) is presented for 5G new radio handset receivers. It is shown that a
RC feedback instead of the conventional resistive feedback in common-
source topology consumes less dc power, maintains low noise figure and
flat gain over a wide frequency band.

Further, use of an inter-stage gm boosting inductor and a parallel LC tank

circuit at the input side keep other parameters like linearity, absolute gain,
input matching and IIP3 comparable to other designs. As an example, a
single stage differential LNA is designed in 180 nm C-MOS technology.
The LNA provides a flat gain of 13.6 dB over 1.9-4.5 GHz. The input
reflection remains below -10 dB, noise figure below 2.9 dB, reverse
isolation over 41 dB over the whole bandwidth. While overall DC power
consumption is 10.5 mW and IIP3 is -2.5 dBm.

Fig- 2.a Proposed differential CS-LNA with RC feedback [6]

In the paper[7] An inductorless noise-cancelling CMOS low-noise

amplifier (LNA) with wideband linearization technique is proposed. The
complementary configuration by stacked NMOS/PMOS is employed to
compensate second-order nonlinearity of the circuit. The third-order
distortion of the auxiliary stage is also mitigated by that of the weak
inversion transistors in the main path. The bias and scaling size combined
by digital control words is further tuned to obtain enhanced linearity over
the desired band.Implemented in a 0.18-ȝP &026 SURFHVV simulated
results show that the proposed LNA provides a voltage gain of 16.1 dB
and a NF of 2.8~3.4 dB from 0.1 to 1.4 GHz. The IIP3 and IIP2 of
13~18.9 and 24~40 dBm are obtained, respectively. The circuit core
consumes 19 mW from a 1.8 V supply.
 Fig-2.b (i) Proposed single ended noise cancelling LNA (ii)Equivalent small signal
circuit model for linearity analysis [7]

In the paper, [8] presents the design of a 0.1 to 5GHz wideband

common-gate (CG) low-noise amplifier (LNA) in 130nm CMOS
technology. The capacitive cross-coupling topology boosts the equivalent
transconductance of input CG transistor. The active differential pairs for
bias path contribute to not only noise cancel of input CG and bias
transistors, but also flexible input matching. Moreover, the circuit is
inductorless, only occupying an area of 0.015mm2. The voltage gain
ranges from 17.7 to 20.0dB. The minimum noise figure is 3.04dB, and
IIP3 is -1.7dBm. The circuit consumes 4.4mW under a 1.2V single
voltage supply. Many common-source (CS) LNAs have been proposed to
meet the requirements. However, it is complex for CS LNA to obtain
wideband, and a series of LC networks occupy a large area.common-gate
LNA is a good solution due to its stable input impedance, but limited by
the larger noise and the lower gain. So as to optimize the noise and
improve the gain, some gm-boosted and noise cancel techniques have
been employed to enhance the equivalent transconductance. In order to
save the area and the cost, some inductorless topologies have been
employed. The schematic of core circuit can be expressed in Fig. 1.The
cross-coupling capacitor C5 and C6 serves as a feedforward amplifier to
enhance the equivalent transconductance, and reduce the power
consumption.

Fig-2.c Proposed Gm boosted LNA [8]

In the paper [9] A wideband noise-cancelling low-noise amplifier (LNA)
combining resistor feedback and source-follower feedback (SFF) is proposed.
The SFF facilitates upsizing of the feedback resistor to improve the gain and
noise figure (NF), without compromising the input-impedance matching.
Another benefit is that the noise contributions of both the feedback resistor
and noise-cancelling transistors are significantly reduced. Fabricated in 65-nm
CMOS, the LNA exhibits a voltage gain of 16.8 dB, and a flat NF of 3.3 ±0.45
dB over a −3-dB bandwidth of 0.5 to 7 GHz. The power consumption is 11.3
mW at 1.2 V, and the die area is 0.044 mm2.

Fig.2.d noise-cancellinglow-noise amplifier (LNA) [9]

In the paper[10], propose the body floating and self-bias technique, in which the
body of the transistor is connected to its drain through a resistance (13.6 k in
this work). A low-power 3–9-GHz CMOS low-noise amplifier (LNA) using the
technique for sub-6-GHz 5G systems is reported. An enhancement in S21 and
noise figure (NF) of the LNA is achieved due to the forward body-to-source
bias (VBS) (i.e., small threshold voltage Vth) and the transistors being free
from the substrate leakage. Low power is achieved since low supply voltage
(VDD) of 1 or 0.8 V is applicable because of small Vth. At VDD of 1 V, the
LNA consumes 3.3 mW and achieves prominent S11 of −10.1 to −41.6 dB,
S21 of 10.7 dB, and NF of 2.89 dB for 3–9 GHz. At VDD of 0.8 V, the LNA
consumes 1.36 mW and achieves S11 of −10 to −45.8 dB, S21 of 9.4 dB, and
NF of 3.46 dB.To the authors’ knowledge, both are one of the lowest power
values ever reported for CMOS LNAs with bandwidth greater than 6 GHz and
NF under 3.5 dB.
 Fig.2.e Schematic of proposed circuit [10]

In the paper [11], A low-power and high power-gain (S21) ultrawideband

low noise amplifier (UWB LNA) with flat noise figure (NF) based on Global
Foundies 0.13-μm CMOS technology is reported. The load effect of common-
gate (CG) topology is applied with dual-resonance load network for both
wideband input matching and NF flatness. Combined with inductive-series
peaking technique, the frequency response of CG-common-source cascade
topology is further extended. The LNA circuit achieves the high and flat
power gain of 13.5±1.5 dB with input return loss better than 13 dB and a flat
NF of 4.3 dB ±0.4 dB for frequencies 3–12 GHz. The fabricated LNA occupies
a die area of 1.09 0.8 mm2 including pads and draw 8.5 mW from 1.2-V dc
supply.

Fig.2.f Schematic of proposed circuit [11]

In the paper[12], a 22.9–38.2-GHz dual-path noise- canceling low noise
amplifier (LNA) is proposed, which can achieve a low noise figure (NF) by
reducing the noise of both paths. Such LNA consists of one common gate
(CG) amplifier with one three-stage transformer, one resistive feedback common-
source (CS) amplifier, and two amplitude-adjusting amplifiers. The three-
stage transformer is used in the CG amplifier to provide gain-boosting, noise-
reducing, and wideband inter-stage matching operation, simultaneously.
Meanwhile, amplitude-adjusting amplifiers with reconfigurable phase-tuning
lines are utilized in both paths to optimize the noise-canceling performance.
To verify the aforementioned principle, a dual- path noise-canceling LNA is
implemented and fabricated using a conventional 28-nm CMOS technology.
The proposed LNA consumed 18.9 mW under a 0.9-V supply. The
measured NF is 2.65–4.62 dB within the operating frequency range of 22.9–38.2
GHz, while the peak gain is 14.5 dB. The in-band input 1-dB compression
point (IP1 dB) and input third-order intercept point (IIP3) are −13.2 to −6.6 and
−3.6 to 3.2 dBm, respectively.

Fig.2.g Dual-path noise-canceling LNA [12]

In the paper[13], presents a wideband millimeter-wave(mm-Wave) low noise
amplifier (LNA) with a triple- coupled technique for multiband wireless
applications. To enlarge the gain and reduce the supply voltage, a modified
cascode topology exploiting a triple-coupled transformer is developed. Thanks
to the transformer, the transconductance of the common-gate (CG) transistor
of the cascode topology is also effectively boosted, and hence the gain is
further increased. Furthermore, high-order networks, which are realized by
combinations of π- and T/L- type structures or transformers, are employed to
implement the input, inter-stage, and output impedance matching. They
significantly broaden the bandwidth of the circuit. The LNA is demonstrated
using a commercial 65-nm CMOS process. The measurement results show that
the circuit achieves a maximum gain of 28.5 dB and a 3-dB gain bandwidth of 20
GHz with 32-mW dc power consumption (Pdc).

Fig.2.h Schematic of proposed LNA and the Values/sizes of the used devices [13]

In the paper[14], presents the design of a V-band low-power compact low-

noise amplifier (LNA) in a 130-nm SiGe BiCMOS technology. For the low-
power and low-noise requirements, transistors need to operate with low-
voltage supply and low current density, which comes at the cost of lower
gain per BJT stage. The circuit topology is analyzed, and the transistor core
layout and the matching network design considerations are discussed.
The measured circuit shows a peak gain of 14.1 dB in a 3-dB bandwidth from
44 to 67 GHz while consuming 5.1 mW. Experimental results show an output
power of 7.1 dBm at 1-dB compression with an associated power-added
efficiency of 30%. The simulated noise figure is 3.3 dB at the center frequency.
To the best of the authors’ knowledge, the highest figure of merit among V-
band LNAs based on silicon is reported.

Fig.2.i Circuit schematic of the differential LNA [14]

In the paper[15] ,Two inductorless low-power differential low-noise amplifiers

(LNAs) are designed for multiband wireless communication applications.
Both LNAs are based on the combination of common-gate (CG) and shunt
feedback topologies. In the first LNA, the cross-coupled push-pull structure with
separated bias for nMOS and pMOS CG transistors is utilized to realize gm
enhancement, partial noise cancellation, and bandwidth extension
In the second LNA, cascode transistors are utilized on the basis of the first
topology to alleviate the Miller effect and to construct current steering
structures, so as to extend the bandwidth. For both LNAs, in-depth analysis is
given, and methods for sizing and biasing optimization under power constraint
are proposed to obtain good overall performance tradeoffs while maintaining
low-power consumption. The prototypes are implemented in 65-nm low-power
CMOS technology.The first LNA achieves a gain of 21.2 dB, a noise figure
(NF) of 3–3.5 dB over the 3-dB bandwidth of 200 MHz to 2.7 GHz and an
IIP3 of −2 dBm at 1.1 GHz. It consumes 0.96 mW from 1.2-V supply.The
second LNA exhibits a gain of 21.2 dB, an NF of 2.8–4 dB over the 3-dB
bandwidth of 100 MHz to 4.3 GHz. It consumes 2 mW from 1.2-V supply.
Each LNA occupies an area of 0.05 mm2.

Fig.2.j (i) CG LNA (ii) CG-CS LNA with noise cancelling (iii) Generic CG LNA with Gm
boosting [15]
This paper[16],presents a compact wideband low-noise amplifier (LNA) with
utilizing the transformers for gain and input matching bandwidth extensions based
on the source degeneration topology. The wideband gain response is achieved by
using a transformer gate–drain feedback technique to peak the gain at high
frequency while the wideband input matching is obtained by employing a new
transformer-based input matching network to produce two resonant points
separately located at low and high frequencies within the operating band.
Implemented in 65-nm CMOS process, the proposed LNA shows a measured
peak gain of 10.2 dB with its 3-dB bandwidth ranging from 15.8 to 30.3 GHz and
minimum noise figure of 3.3 dB. Taking advantage of the superior compactness
from the transformer-based techniques, the LNA occupies very compact chip area
of only 0.18 mm2, exhibiting as one of the most compact wideband LNAs.

Fig.2.k Simplified circuit schematic (a) Source degeneration LNA (b) Proposed Wideband
LNA [16]

In the article [17],a wideband low-noise amplifier (LNA) with low and flat noise
figure (NF) is presented . For conventional wideband noise matching, the noise
performance in the high-frequency region of the entire wideband is usually
deteriorated due to the frequency-dependent nature of the minimum noise figure
(NFmin) for a MOSFET. To address this issue, a novel wideband noise matching
approach aiming at noise matching in high band is proposed. This approach can
reduce the NF in high band at the cost of a slight NF increase in low band,
eventually achieving a low and flat NF and thus a better overall noise performance
for a wideband LNA. In addition, the multistage noise matching technique is
employed at high frequencies to further reduce the NF caused by the second
amplification stage. To validate the proposed techniques, a twostage LNA
prototype was designed and fabricated using a 65 nm CMOS process. The
experimental results indicate a peak gain of 16.6 dB with a −3 dB bandwidth (BW)
from 7.2 to 27.3 GHz (a fractional BW of 116%). Within the entire band of
interest, the simulated NF is low and almost constant (3.3–3.4 dB), while the
measured NF falls within the range of 3.30–3.72 dB.
 Fig.2.l Schematic of the proposed wideband LNA [17]

In the paper [18], a noise-cancelling variable gain low noise amplifier (VG-LNA)
is presented for ultra-wideband (UWB) applications. The proposed VG-LNA is
designed for 3.5-9 GHz frequency bands using RF-TSMC CMOS 0.18 μm
technology. The proposed LNA employs a common gate input stage and a
common source second stage while a noise cancellation technique is used to
minimize the noise figure of the input stage. By utilizing a feedback loop at the
second stage, the gain of the LNA is continuously controlled. Simulation results
exhibit the flat power gains (S21) of 12 dB, noise figure (NF) of 3.4 dB and input
return loss (S11) less than –10 dB over the wide bandwidth of 3.5 to 9 GHz. The
linearity parameter of third order input intercept point (IIP3) is -10.5 dBm at
8GHz. The proposed VG-LNA has power dissipation of 11.9 mW under a 1.3 V.

Fig.2.m Schematic of the proposed VG LNA [18]

This paper [19], presents a differential wideband low noise amplifier (LNA)
targeting 5G applications in 130 nm TSMC CMOS technology. The proposed
LNA is based on the capacitive cross-coupled common-gate (CCC-CG) push-pull
architecture. The LNA utilizes inductors for wideband input matching that resonate
with the input parasitic capacitors.The CCC-CG structure along with a current-
reuse PMOS and NMOS technique enhances transconductance, reducing noise
figure (NF) and increasing voltage gain. simulation results show that the
differential LNA achieves a gain of 21 ±1.5 dB, NF of less than 4 dB and IIP3 of
higher than -2.5 dBm over the bandwidth of 3.5 to 7 GHz. The LNA consumes 2.4
mA from 1 V supply, and occupies an active area of 0.24 mm2.

Fig.2.n Schematic of the proposed Wideband differential CCC_CG LNA [19]

In this paper [20], a wideband low noise amplifier (LNA) with local active
feedback is proposed. The proposed LNA exploits a differential common-source
stage with current-reuse technique to reduce the power consumption. A source
follower is utilized as an active feedback path and the feedback signal is taken
preceding the cascode transistor to broaden the bandwidth and improve the
linearity. Implemented in a 130-nm SOI CMOS technology, the proposed LNA
achieves simulated 21.1 dB voltage gain with a 3-dB bandwidth of 0.5-5.6 GHz
without using any inductors. The minimum NF is 3.63 dB while the maximum
IIP3 is -4.86 dBm. The power consumption is 15.2 mW under a supply voltage of
1.5 V.
 Fig.2.p Schematic of the proposed Wideband LNA [20]

In this paper [21], a two-stage wideband low-noise amplifier (LNA) using

source-follower feedback (SFF) is presented. A novel approach using a
combination of asymmetrical inductive peaking and SFF is used to alleviate the
trade-off between input matching and noise figure, thus making more space for
design. A peaking inductor in the gate of the NMOS in the first stage is added to
resonate with the capacitance of the node, resulting better input matching. In
addition, a second stage is added to widen gain bandwidth using inductive load.
Simulated in TSMC 0.18-μm CMOS technology for 1-6.7 GHz, voltage gain of
12.5 dB and a NF of 2.2dB over the 3-dB bandwidth is achieved. The LNA
consumes 9.3 mW from a 1.8 V supply.

Fig.2.q Complete Schematic of the proposed LNA [21]

 This paper [22], presents a wideband low-noiseamplifier using current-reused
technique with transformer feedback for wideband input/output matching;
simultaneously covering two major 5G millimeter frequency bands (28-GHz, 37-
GHz). The LNA is based on a 2-stage current-reused common source and
common source (CS-CS), which integrated gate-drain transformer feedback for
achieving wideband input/output matching. The LNA, which operates from 17
GHz up to 48 GHz with 95% 3-dB bandwidth (17-48 dB) and 74.6% 1-dB
bandwidth (21-46 GHz), exhibits maximum gain of 18.7 dB and minimum noise
figure of 4.3 dB. The LNA is designed in a 65-nm CMOS technology of TSMC
and only dissipates 16 mW from 1.2-V supply voltage.

Fig.2.r Complete Schematic of the proposed current-reused CS-CS wideband LNA with gate-
drain transformer for input/output matching [22]

In this paper [23],a low power wideband low-noise amplifier (LNA) using input
series peaking and gm-boosting is proposed. The proposed LNA uses NMOS
transistors in CG topology as input stage. Capacitor cross coupling is used to
realize gm boosting. The required input matching is achieved using shunt
feedback and the LNA’s bandwidth is increased by using series peaking at the
input. The proposed circuit is designed in UMC 180nm CMOS and the post-
layout simulations using Cadence Spectre RF shows a maximum gain (S21) of
15.7dB, minimum noise figure (NF) of 3.2dB in the -3dB frequency range of
0.5 – 3.5 GHz. Also, the designed LNA achieves a maximum IIP3 of - 2.8dBm
at 3.5GHz while consuming 1.4mW from a 1-Vsupply. The core area of the
LNA is 0.35mm2.
 Fig.2.s proposed LNA with cross-coupled gm enhancement and input series peaking [23]

Table-1. Specifications of recently proposed LNAs

Serial No Technique Freq. Range Noise Figure Gain

1 SFF 0.5-7 GHz 3.3 0.45 dB 16.8 dB

65 nm [9]

2 Body Floating & 3-9 GHz 2.89 dB -

Self Bias
0.18 μm [10]
3 Dual Resonance 3-12 GHz 4.3 0.4 dB 13.5 1.5 dB
0.13-μm [11]

4 Dual Path 22.9-38.2 GHz 2.65-4.62 dB 14.5 dB

28 nm [12]
5 Triple Coupled 21-41 GHz 2.7-3.2 dB 28.5 dB
65 nm [13]

6 SiGe BiCMOS 44-67 GHz 3.3 dB 14.1 dB

130 nm [14]

7 CMOS 5-19 GHz 1.5-3.5 dB 6.2 dB

65nm [15]

8 Differential 1.9-4.5 GHz 2.9 dB 13.6 dB

CMOS 180nm [16]

9 Linearization [17] 0.1-1.4 GHz 2.8-3.4 dB 16.1 dB

10 Gm boosting [18] 11.8-37.2 GHz 2.95-4 dB 12.5 dB

 Chapter-3

Basic Theory of LNA

3.1 Two Port Network

Signal amplification is one of the most basic and prevalent circuit functions in
modern RF and microwave systems. Early microwave amplifiers relied on tubes,
such as klystrons and traveling-wave tubes, or solid-state reflection amplifiers
based on the negative resistance characteristics of tunnel or varactor diodes.
However, due to the dramatic improvements and innovations in solid-state
technology, most RF and microwave amplifiers today use transistor devices.
Microwave transistor amplifiers are rugged, low-cost, and reliable and can be
easily integrated in both hybrid and monolithic integrated circuitry. Transistor
amplifiers can be used at frequencies in excess of 120 GHz in a wide range of
applications requiring small size, low noise figure, broad bandwidth, and medium
to high power capacity. Although microwave tubes are still useful for very high
power and/or very high frequency applications, continuing improvement in the
performance of microwave transistors is steadily reducing the need for microwave
tubes.

3.1 Two-port power gains :

Fig-3.1 A two-port network with arbitrary source and load impedances [24]

Consider an arbitrary two-port network, characterized by its scattering matrix

[S](discussed later [24]), connected to source and load impedances ZS and ZL ,
respectively, as shown in Figure 3.1. We will derive expressions for three types of
power gain in terms of the scattering parameters of the two-port network and the
reflection coefficients, _S and _L , of the source and load.Power gain = G =
PL/Pin,is the ratio of power dissipated in the load ZL to the power delivered to the
input of the two-port network. This gain is independent of ZS, although the
characteristics of some active devices may be dependent on ZS.
The reflection coefficient seen looking toward the load is
--- (3.i)
while the reflection coefficient seen looking toward the source is
--- (3.ii)

where Z0 is the characteristic impedance reference for the scattering parameters of

the two-port network. In general, the input impedance of the terminated two-port
network will be mismatched with a reflection coefficient which can be determined
using a signal flow graph or by the following analysis. From the definition of the
scattering parameters, and the fact that,
 (3.a)
(3.b)
(3.c)

(3.d)

(3.e)

The power gain can then be expressed as,

(3.f)

A two-port network is a type of electrical circuit that has two pairs of terminals, or
ports, that are used to connect the circuit to other devices or components. In
amplifier design, a two-port network is often used to model the behavior of the
amplifier and to determine its performance characteristics. There are different types
of two-port networks that can be used for amplifier design, such as the T-network,
the Pi-network, and the L-network. Each of these networks has its own advantages
and disadvantages, depending on the specific requirements of the amplifier
design.One common approach to designing an amplifier using a two-port network is
to use a transmission line model. This involves modeling the amplifier as a series of
transmission lines connected in a specific configuration, such as a cascade or a
parallel combination. This allows for a more detailed analysis of the amplifier's
behavior, including its gain, bandwidth, and frequency response.Another approach
is to use a S-parameter model, which describes the behavior of the two-port
network in terms of its scattering parameters. This allows for a more simplified
analysis of the amplifier's behavior, and can be useful for quickly assessing the
performance of the amplifier under different operating conditions.Overall, the use
of a two-port network can be a powerful tool for amplifier design, allowing
engineers to model and analyze the behavior of the amplifier in a more detailed and
precise way.

Two-port network allows the response of the network to signals applied to the ports
to be calculated easily, without solving for all the internal voltages and currents in
the network. It also allows similar circuits or devices to be compared easily.
3.2 Impedance Matching :
Impedance matching is a critical aspect of designing a low noise amplifier (LNA) as
it affects the gain, noise figure, and stability of the amplifier. In order to achieve
optimal performance, the input and output impedances of the LNA must be matched
to the source and load impedances, respectively.The first step in impedance
matching for an LNA is to determine the input and output impedance of the
amplifier. This can be done using a variety of techniques, including simulation
tools, impedance analyzers, and network analyzers. Once the input and output
impedances have been determined, the next step is to design a matching network
that will transform the source and load impedances to the desired values.One
common technique for impedance matching in an LNA is to use a quarter-wave
transformer. This involves placing a quarter-wavelength transmission line between
the input or output of the amplifier and the source or load, respectively. The length
and characteristic impedance of the transmission line are chosen to achieve the
desired impedance transformation.Another common technique is to use a shunt or
series matching network, such as a pi or T network. These networks can be
designed using standard circuit analysis techniques, and are often used in
conjunction with other matching techniques to achieve optimal performance.In
addition to matching the input and output impedances of the LNA, it is also
important to ensure that the matching network does not introduce additional noise
or instability into the circuit. This can be achieved through careful design and
simulation, as well as by using high-quality components and materials.Impedance
matching is the process of adjusting the impedance of a circuit so that it matches the
impedance of the source or load. This is important in many applications, including
in radio frequency (RF) and microwave engineering, where impedance matching is
critical for achieving maximum power transfer and minimizing reflections.The
Smith chart is a graphical tool that is commonly used in impedance matching. It
provides a way to visualize the complex impedance of a circuit, and to perform
impedance transformations using simple geometric operations.

To use the Smith chart for impedance matching, the first step is to plot the
impedance of the circuit on the chart. The impedance can be represented in terms of
its magnitude and phase angle, or in terms of its real and imaginary components.
Once the impedance has been plotted on the chart, the next step is to use the chart to
design a matching network that will transform the impedance to the desired value.
This can be done using a variety of techniques, including series and shunt stubs,
transmission line transformers, and L-networks.The Smith chart allows for easy
visualization of the impedance transformation process, as well as the effects of
various matching techniques on the circuit's performance. By using the chart,
engineers can quickly evaluate the performance of different matching networks and
choose the best one for their specific application.
 Overall, impedance matching is an important aspect of circuit design in many
applications, and the Smith chart is a valuable tool for achieving optimal
performance. By using the chart, engineers can quickly and easily visualize the
impedance of a circuit and design matching networks that provide maximum power
transfer and minimize reflections.
Impedance matching or tuning is important for the following reasons:

• Maximum power is delivered when the load is matched to the line (assuming the
generator is matched), and power loss in the feed line is minimized.
• Impedance matching sensitive receiver components (antenna, low-noise
amplifier, etc.) may improve the signal-to-noise ratio of the system.
• Impedance matching in a power distribution network (such as an antenna array
feed network) may reduce amplitude and phase errors.

Factors that may be important in the selection of a particular matching network

include the following:

Complexity-As with most engineering solutions, the simplest design that satisfies
the required specifications is generally preferable. A simpler matching network is
usually cheaper, smaller, more reliable, and less lossy than a more complex
design.
Bandwidth—Any type of matching network can ideally give a perfect match (zero
reflection) at a single frequency. In many applications, however, it is desirable to
match a load over a band of frequencies. There are several ways of doing this,
with, of course, a corresponding increase in complexity.
Implementation—Depending on the type of transmission line or waveguide being
used,one type of matching network may be preferable to another. For example,
tuning stubs are much easier to implement in waveguide than are multisection
quarter-wave transformers.
Adjustability—In some applications the matching network may require
adjustment to match a variable load impedance. Some types of matching networks
are more amenable than others in this regard.Instead of Analytic Solutions for
impedance matching here Smith chat is discussed as it is very easy method.
The Smith chart is made up of multiple circles, and segments of circles arranged
in a way to plot impedance values in the form of R ± jX (Fig. 3.2). A horizontal
line through the center of the main circle represents the resistance with R = 0 at
the far left of the line and infinite resistance at the far right. Resistance values are
plotted on the resistance circles, all of which are tangent to one another at the far
right of the resistance line. The R = 1 circle passes through the center of the R
line. The remaining curves are parts of circles representing reactance. These
curves all come together at the R = infinity point at the far right. The curves above
the horizontal line represent inductive-reactance values and the curves below the
line represent capacitive reactance. The Smith chart, as shown, is normalized,
thereby permitting you to customize it to your application.
Plotting Values on the Chart

• Z1 = 0 + j0.7
• Z2 = 0.2 – j0
• Z3 = 3.0 + j1.0
• Z4 = 1.0 – j0.5
• Z5 =0-j1.6

Figure 3.2 shows five examples of impedance plots

Example-1

Develop a two-element matching network to match a source with an impedance

of RS=25Ω to a load RL=200Ω=200Ω (see Figure 3.3).

The design objective is to present conjugate matched impedances to the source and
load. However, since here the source and load impedances are real, the design
objective is Z1=RS and Z2=RL. The load and source resistances are plotted on the
Smith chart in Figure 6.7.46.7.4(a) after choosing a normalization impedance
of Z0=50Ω (and so rS=RS/Z0=0.5 and rL=RL/Z0=4). The normalized source
impedance, rS, is Point A, and the normalized load impedance, rL, is Point C. The
matching network must be lossless, which means that the design must follow lines
of constant resistance (on the impedance part of the Smith chart) or constant
conductance (on the admittance part of the Smith chart). So Points A and C must
be on the above circles and the circles must intersect if a design is possible. The
design can be viewed as moving back from the source toward the load or moving
back from the load toward the source. (The views result in identical designs.) Here
the view taken is moving back from the source toward the load.

One possible design is shown in Figure-3.5 (a). From Point A, the line of constant
resistance is followed to Point B(there is increasing series reactance along this
path). From Point B, the locus follows a line of constant conductance to the final
point, Point C. There is also an alternative design that follows the path shown in
Figure 3.5(b). There are only two designs that have a path from A to B following
just two arcs. At this point two designs have been outlined. The next step is
assigning element values.
 The design shown in Figure-3.5(a) begins with rS followed by a series
reactance, xS, taking the locus from A to B. Then a shunt capacitive
susceptance, bP, takes the locus from B to C and rL. At Point A the reactance xA=0,
at Point B the reactance xB=1.323. This value is read off the Smith chart, requiring
that an arc as shown be interpolated between the arcs provided. It should be noted
that not all versions of Smith charts include negative signs, as the chart becomes
too complicated. Thus the user needs to be aware and add signs where appropriate.
The normalized series reactance is,
xS=xB−xA=1.323−0=1.323,that is XS=xsZ0=1.323×50=66.1Ω
A shunt capacitive element takes the locus from Point B to Point C and
bP=bC−bB=0−(−0.661)=0.661,so
BP−bP/Z0=0.661/50=13.22 mS or XP=−1/BP=−75.6Ω
The final design is shown in Figure-3.4

Figure 3.3: Design objectives for Example-1. RS=25Ω,RL=200Ω

Figure 3.4: Final design for Example-1 using the path shown in Figure3.5(a).

Figure 3.5: Alternative designs for Example -1. The normalization impedance is 50Ω
One of the advantages of using the Smith chart is that the design progresses in
stages, with the structure of the design developed before actual numerical values
are calculated. Of course, it is difficult to extract accurate values from a chart, so
designs are regularly roughed out on a Smith chart and refined using CAD tools.
Example-1 matched a resistive source to a resistive load. The next example
considers the matching of complex load and source impedances. In the earlier
algorithmic approach to matching network design absorption and resonance were
introduced as strategies for dealing with complex terminations. Design was not
always straightforward. It will be seen that this complication disappears with a
Smith chart-based design, as it is conceptually not much different from the
resistive problem of Example-1.

Performance Parameters of a good LNA-

• Low Noise Figure

• Enough Gain to boost the signal

• Large enough inter-modulation and compression point (IIP3 and P1dB)

to do the work required of it. Further specifications are the LNA's
operating Bandwidth, Input Return Loss, Stability, Linearity, Quality
Factor, Sensitivity, Dynamic range, Power Dissipation, Gain flatness,
Impedance Matching, Input and Output voltage standing wave ratio
(VSWR).

3.3 CMOS LNA

A CMOS low noise amplifier (LNA) is an amplifier that is implemented using
complementary metal-oxide-semiconductor (CMOS) technology. CMOS
technology is a type of integrated circuit (IC) technology that uses transistors
made from metal-oxide-semiconductor (MOS) materials to build electronic
circuits.CMOS LNAs have several advantages over LNAs implemented
using other technologies. They are low cost, low power, and can be
easily integrated with other CMOS circuits on a single chip. They also have
a wide bandwidth, which makes them suitable for use in applications where the
signal frequency may vary.There are several design considerations that must be
taken into account when designing a CMOS LNA. These include the gain, noise
figure, input and output impedance, and power consumption of the amplifier. To
achieve a low noise figure, it is important to carefully design the input stage
of the amplifier to minimize noise. The output stage of the amplifier should be
designed to match the impedance of the load in order to maximize the power
transfer. The power consumption of the amplifier should also be carefully
controlled to ensure that it does not consume too much power.
3.4 Working of LNA :
An amplifier is a device that increases the strength of a weak electrical
signal. A low noise amplifier (LNA) is a type of amplifier that is designed to
amplify very low-power signals while adding minimal noise to the signal.To
understand how an LNA works, it is helpful to first understand the basic principles
of amplification. An amplifier consists of two main components:a gain stage and
a power supply. The gain stage is the part of the amplifier that actually
amplifies the signal, while the power supply provides the necessary power
to the gain stage.The gain stage of an LNA typically consists of one or
more transistor stages. The input signal is applied to the transistor, which
amplifies the signal and outputs it at a higher level. The gain of the amplifier is
determined by the characteristics of the transistor and the circuit design.One of the
key features of an LNA is its low noise figure, which refers to the amount of
noise that is added to the signal as it is amplified. To minimize noise,
LNAs often use transistors with a low noise figure and are designed with careful
attention to minimizing noise at every stage of the amplification process.

3.5 Low Noise Amplifier Block Diagram

In a communication system, the receiver section needs amplification for the

weak signal which is received from the antenna. So this amplification can be
accomplished through the main component called Low Noise Amplifier or LNA.
The characteristics of this amplifier can be described by certain parameters
like gain, noise figure, chip area, linearity, power consumption &
bandwidth.The block diagram of the low noise amplifier is shown below
as an example. The designing of a low noise amplifier can be done by using a
common gate amplifier, active inductor & common drain stage. Generally, the
common gate amplifier is mainly used at the input stage whereas the common
drain amplifier is used at the output stage to provide the best input as well
as output matching. The low noise amplifier is bound with particular
characteristics like gain & noise figure but the selection of LNA mainly depends
on some specific parameters like power supply, bandwidth, chip area & linearity.
 Fig.3.1- Block Diagram of Low Noise Amplifier [2]

Common Gate Amplifier- The common gate (CG) amplifier forms the primary
stage of the proposed LNA example. By this stage, it is not much complex
to get input impedance matching. This amplifier can be used as a current buffer or
voltage amplifier.

Active Inductor- An active inductor mainly includes CMOS transistors & its
operation is simply the same as a passive inductor. This inductor is mainly
designed to give good quality factors to determine its efficiency. The performance
of this inductor can be enhanced by introducing dual feedback while
designing the circuit.

Common Drain Amplifier- Generally, a common drain amplifier is known as a

buffer or a source follower. It is normally used at the output stage of the LNA
design. This amplifier has less output impedance. So, it can provide good
output impedance matching.

The noise signal is transmitted to the next stage of the LNA like an active
inductor.In an active inductor, the noise of the received signal can be
reduced because of noise-canceling & resistive degeneration. An active inductor
is used to get low power consumption, reducing complexity. This low noise
signal is given to the final stage of LNA like a common drain amplifier.
This is also called a buffer or source follower. This amplifier is capable to
obtain small output impedance matching. So this amplifier has potentially very
less noise. In this way, the noise is reduced from input to output of LNA.
3.6 Important LNA Parameters

A. Noise Figure (NF)

In Communication Systems Noise is any unwanted signal, random or

deterministic, which interfere with the faithful reproduction of the desired
signal in a system. This interfering signal is usually noticed as random fluctuations
in voltage(rms value) or current tending to obscure and mask the desired
signals.Noise figure is the Signal to Noise Ratio(SNR) in dB where SNR is the
ratio of signal power to the Noise Power.

Noise Factor=SNR=Signal power/Noise Power, Psig|dBm= (3.6.1)

NF|dB = (3.6.2)

Figure-3.4.A.1 (a) LNA with input-referred noise voltage (b) simplified circuit [25]

The noise figure of the LNA directly adds to that of the receiver and it is about NF
=2 to 3 dB. Rearranging the input network in Fig.2(a), shown in Fig.2(b).

Noise Figure in this circuit is given by,

(3.6.3)
Noise in BJT :
Bipolar transistors contain physical resistances in their base, emitter, and
collector regions, all of which generate thermal noise. Moreover, they also
suffer from “shot noise” associated with the transport of carriers across the
base-emitter junction. As shown in Fig.3, this noise is modeled by two
current sources having the following PSDs:

(3.6.4)

where IB and IC are the base and collector bias currents, respectively. Since
gm=IC/(kT/q) for bipolar transistors, the collector current shot noise is often
expressed as

(3.6.5)

in analogy with the thermal noise of MOSFETs or resistors. In low- noise circuits,
the base resistance thermal noise and the collector current shot noise become
dominant. For this reason, wide transistors biased at high current levels are
employed.

Figure -3.4.A.2 Noise sources in a bipolar transistor [25]

Noise in MOSFET
The thermal noise of MOS transistors operating in the saturation region is
approximated by a current source,
(3.6.6)
tied where γ is the “excess noise coefficient” and gm the transconductance. The
value of γ is 2/3 for long-channel transistors and may rise to even 2 in
short-channel devices.The actual value of γ has other dependencies and is usually
obtained by measurements for each generation of CMOS technology.
The noise can alternatively be modeled by a voltage source,
(3.6.7)
in series with the gate .The noise can alternatively be modeled by a voltage
source in series with the gate .Noise is measured in saturation. Generally We
calculate Channel Thermal Noise.
Others noise in a MOS are the followings-
1/f noise, Noise in the resistive poly gate, noise due to the distributed
substrate resistance, shot noise associated with the leakage current of the
drain source reverse diodes.

Fig -3.4.A.3 Thermal channel noise of a MOSFET modeled as a (a) current source (b)
voltage source.[25]

3.4.A.1 MOSFET is used over BJT because MOSFET generate less noise than
BJT.A BJT is having two p-n junctions whereas an FET is having only one
p-n junction. Hence charge carriers will have to cross more depletion regions
in BJT and hence the possibility of addition of thermal noise and minority
charge carriers is much higher. But in an FET, there is no significant
depletion region between drain and source. Therefore,the possibility of the
addition of the above two is not much. Hence less noisy. But for Speed BJT is
faster as it has only 3 internal equivalent Capacitor but for MOSFET it has 4
internal equivalent Capacitor.
B. GAIN
Gain is the ratio of output swings and input swings.It is a unitless quantity and
generally express in dB .Typical gain of a LNA is about Av =10 dB.

Av|dB = = S21=Forward Gain

The gain of the LNA must be large enough to minimize the noise
contribution of subsequent stages. specifically, the down conversion
mixer(s). For NF calculations of a circuit, the noise of the next stages are
divided by the gain from the input voltage source to the LNA output.The
amount of gain applied is often a compromise. On one hand, high gain
makes weak signals strong. On the other hand, high gain means higher level
signals, and such high- level signals with high gain may exceed the
amplifier's dynamic range or cause other types of noise such as harmonic
distortion or nonlinear mixing and makes the nonlinearity of the subsequent
stages more pronounced.
3.4.B.1 dB Gain

i. We use the dB system when the working range of a measurement is so

enormous that we have to revert to a logarithmic scale to keep the
measurements to sensible values. The logarithm of 1 is 0 (10^0 = 1) and the
logarithm of 1,000,000,000,000 is 12 (10^12 = 1 Trillion). So our scale is now
0 to 12 scale is reduced.so to measure high gain dB scale is more convenient.
ii. Total Gain of subsequent stages is just the sum of dB measurement. So
calculation is very easy.
iii. Also our own senses are responding logarithmically to the
intensity of a stimulus such as sound, thus the Decibel scale was introduced as
a convenient measure of sound intensity.
iv. From dB gain characteristics we can easily find the band width i.e –
3dB points.

C. SCATTERING PARAMETERS
Scattering parameters or S-parameters (the elements of a scattering matrix or S-
matrix) describe the electrical behavior of linear electrical networks when
undergoing various steady state stimuli by electrical signals.The parameters are
useful for several branches of electrical engineering, including electronics,
communication systems design, and especially for microwave engineering.
The S-parameters are members of a family of similar parameters, other examples
being: Y-parameters, Z-parameters, H-parameters, T- parameters or ABCD-
parameters. They differ from these, in the sense that S-parameters do not use
open or short circuit conditions to characterize a linear electrical network;
instead, matched loads are used. These terminations are much easier to use at
high signal frequencies than open-circuit and short-circuit terminations. Contrary
to popular belief, the quantities are not measured in terms of power

(except in now-obsolete six-port network analyzers). Modern vector network

analyzers measure amplitude and phase of voltage traveling wave phasors using
essentially the same circuit as that used for the demodulation of digitally
modulated wireless signals.
For a 2 port network-

i. input return loss (s11)

ii. reverse gain (s12)
iii. forward gain (s21)
iv. output return loss (s22)
i. INPUT RETURN LOSS S11
Signal reflected back from LNA to source.
Considering the LNA as a voltage amplifier, we may expect that its input
impedance must ideally be infinite ( for impedance matching it should be
50Ω ). From the noise point of view, we may precede the LNA with a
transformation network to obtain minimum NF. From the signal power
point of view, we may realize conjugate matching between the antenna and
the LNA.
Here the quality of the input match is expressed by the input “return loss,” defined
as the reflected power divided by the incident power. For a source impedance of
RS, the return loss is given by

where Zin denotes the input impedance & RS source impedance S11= -10 dB,
S11= -20 dB is better value.

ii. REVERSE GAIN S12

Signal reflected back from load to source.

Reverse Transmission or isolation means if we do change something at the load
side the source side must not be effected.
S12= -20 dB, S12= -30 dB is better vaule

iii. FORWARD GAIN S21

Signal received from source to load. S21= 10 dB, S21= 20 dB is better
value

iv. OUTPUT RETURN LOSS S22

Signal reflected back from load to LNA. S22= -20 dB, S22= -30 dB is better
value
D. STABILITY

If the user of a cell phone wraps his/her hand around the antenna, the
antenna impedance changes. For this reason, the LNA must remain stable
for all source impedances at all frequencies. One may think that the LNA
must operate properly only in the frequency band of interest and not
necessarily at other frequencies, but if the LNA begins to oscillate at any
frequency, it becomes highly nonlinear and its gain is very heavily compressed.

A parameter often used to characterize the stability of circuits is the

“Stern stability factor” defined as

S11=Input return loss, S22=Output return loss , S12=Reverse Gain ,

S21=Forward Gain , S22 < -30 dB.

LNAs can be stabilized by maximizing their reverse isolation. A high

reverse isolation is also necessary for suppressing the LO leakage to the input of
the LNA.

E. LINEARITY
• Linearity of a circuit means its output is proportional to its input, but
capable of delivering more power into a load.
• LNA linearity is most often specified as a third order intercept
point (IP3). A 1 dB improvement in LNA IP3 corresponds to a2dB
reduction in third order cross−modulation products. IIP3<= 0dBm
• With an LNA gain of 15 to 20 dB, an input of -15 dBm yields an output of 0
to 15 dBm, possibly compressing the LNA at its output. The LNA linearity
is therefore critical. Similarly, the 1-dB compression point of the down
conversion mixer(s) must reach 0 to 15 dBm. (The corresponding mixer IP3 is
roughly 110 to 115 dBm.) Thus, the mixer design also becomes challenging.
F. SENSITIVITY

The sensitivity is defined as the minimum signal level that a receiver can
detect with “acceptable quality.” In the presence of excessive noise, the
detected signal becomes unintelligible and carries little information. We
define acceptable quality as sufficient signal-to-noise ratio, which itself
depends on the type of modulation and the corruption (e.g., bit error rate) that the
system can tolerate. Receiver sensitivity is the minimum power level at which
the receiving node is able to clearly receive the signal/bits being transmitted.
Expresses of sensitivity as the minimum input signal that yields a given value
for the output SNR.

where Psen is the sensitivity.

B is Band Width & expressed in Hz.

Note that above expression does not directly depend on the gain of the system.

If the receiver is matched to the antenna, then

PRS =kT = -174 dBm/Hz,

The sum of the first three terms is the total integrated noise of the system &
sometimes called the “noise floor”.
G. DYNAMIC RANGE
• Dynamic range is equal to a maximum power of signal over minimum power
signal at the system’s input. Converting this to log domain, we get the
difference between maximum acceptable power Psig, in(max) in dBm, and
minimum acceptable power Psig(min).

• We can say that Psig(max), the maximum level of the signal power,
is equal to the power of 1dB. If the input power increases more than this value,
then the system will experience compression, and it will become non-linear and
will not work properly. So dynamic range in the log domain is defined as the
difference between the maximum signal power and minimum signal power.

3.4.G.1 Dynamic range is an important parameter.

i. Within DR the LNA is linear , if it exceeds DR LNA shows non- linearity.

ii. If DR is exceeds due to high signal level, harmonic distortion takes place at
output.

Fig. 3.4.G.3 Dynamic Range vs SNR

H.QUALITY FACTOR

In simplest form, the quality factor, Q, indicates how close to ideal an energy-
storing device is. An ideal capacitor dissipates no energy, exhibiting an
infinite Q.where the numerator denotes the “desired” component and the
denominator, the “undesired” component. If the resistive loss in the capacitor
is modeled by a parallel resistance , then we must define the Q asThe quality
factor or Q factor is a dimensionless parameter that describes how
underdamped an oscillator or resonator is. It is defined as the ratio of the
initial energy stored in the resonator to the energy lost in one radian of the
cycle of oscillation.Additionally, for a second-order tank, the Q can be defined
in terms of the resonance frequency, ω0, and the -3dB bandwidth, ωBW.

I. BANDWIDTH

The LNA must provide a relatively flat response for the frequency range of
interest, preferably with less than 1 dB of gain variation. The LNA -3dB
bandwidth must therefore be substantially larger than the actual band so
that the roll-off at the edges remains below 1 dB.In order to quantify the
difficulty in achieving the necessary bandwidth in a circuit, we often refer to
its “fractional bandwidth” ( 1/Q ), defined as the total -3dB bandwidth
divided by the center frequency of the band. Bandwidth is the measure of the
speed of the system.

J. 1dB GAIN COMPRESSION POINT

“1-dB compression point,” is defined as the input signal level that causes the gain
to drop by 1 dB.

Fig.J.1 Plot Aout vs Ain [25]

The output level, Aout, falls below its ideal value by 1 dB at the 1- dB
compression point Ain,1dB. Ain and Aout are voltage quantities here.Then
amplifier response tracks the ideal response over a limited range, then begins to
saturate, resulting in reduced gain.Compression can also be expressed in terms
of power quantities. 1-dB compression point is typically in the range of -
20dBm to -25 dBm at the input of RF receivers.

K. 1dB GAIN COMPRESSION POINT

“1-dB compression point,” is defined as the input signal level that causes the
gain to drop by 1 dB.

Fig.J.1 Plot Aout vs Ain [25]

The output level, Aout, falls below its ideal value by 1 dB at the 1- dB
compression point Ain,1dB. Ain and Aout are voltage quantities here.Then
amplifier response tracks the ideal response over a limited range, then begins to
saturate, resulting in reduced gain.Compression can also be expressed in terms
of power quantities. 1-dB compression point is typically in the range of -
20dBm to -25 dBm at the input of RF receivers.
.

L. rd
3 ORDER INTERCEPT POINT

• Third order intercept point is an hypothetical point where the power of

third order components will reach to the same level of fundamental component's
power.
• The input level at which this occurs is called the “input third intercept point”
(IIP3).Similarly, the corresponding output is represented by OIP3.
• If we draw the power input versus power output, we will observe the different
frequency components having different slopes.
• Third order intercept point is an ideal point as once the device reaches to 1 dB
compression point the two curves will become parallel to each other and they
will never cut.

Fig.K.1 Plot Pout vs Pin [25]

• The third-order intermodulation intercept point (IIP3) is typically
equal to or below −10 dBm.

➢ It is the most common measure of device linearity.

➢ Higher the TOI, better the linearity and lower the level of IMD.

Improvement of TOI :
• The first approach is to use an auxiliary transistor biased in the weak
inversion region to cancel the third-order nonlinearity coefficient.
• But the main transistor has to be operatedin strong inversion with higher
linear transconductance (g1 = gm) than that in the auxiliary path.
• The second method is to operate the main transistor between the
moderate inversion and subthreshold regions for finding the optimum bias
zone.

3.4 LNA Topology:

There are several topologies that can be used to design a low-noise

amplifier (LNA). Some common ones include the common-source
configuration, the common-gate configuration, and the common-drain
configuration.In a common-source LNA, the input signal is applied to the
gate of a transistor, and the amplified output is taken from the drain. This
configuration is generally used when a high voltage gain is required.In a
common-gate LNA, the input signal is applied to the drain of the
transistor, and the amplified output is taken from the source. This
configuration is generally used when a low voltage gain is required, but a
high current gain is needed.In a common-drain LNA, the input signal is
applied to the gate of the transistor, and the amplified output is taken from
the source. This configuration is generally used when a low voltage gain
and a low current gain are required.
Each of these topologies has its own advantages and disadvantages, and the
choice of which one to use will depend on the specific requirements of
the application.
Table 2. LNA topologies [25]
Common Source Stage Common Gate Stage Broadband Topologies
With With

Inductive Load Inductive Load Noise Cancelling LNAs

Resistive Load Feedback Reactance Cancelling

LNAs

Cascode, Feedforward
Inductive Load,
-
Inductive
Degeneration
Cascode and Inductive
- Load
-
i. Common-Source Topology
In a common-source low-noise amplifier (LNA), the input signal is
applied to the gate of a transistor, and the amplified output is taken from the
drain. The transistor is typically a field-effect transistor (FET), as these tend
to have lower noise characteristics than bipolar transistors.The common-source
LNA configuration is generally used when a high voltage gain is required. It
can also provide some power gain, although this is usually not the primary
design goal. The voltage gain of a common-source LNA is given by the
transconductance of the transistor (gm) and the load impedance (RL) according
to the following equation:
|Av |= gm *RL (3.4.1)
The noise figure of a common-source LNA is determined by the noise
generated by the transistor itself, as well as any noise introduced by passive
components in the circuit. Careful design and selection of components can help
to minimize the noise figure of the amplifier. One important consideration in
the design of a common-source LNA is the impedance matching of the input
and output ports to the amplifier. Proper impedance matching can help to
maximize the power transfer and minimize reflections, which can improve the
overall performance of the amplifier.

Fig.- 3.5.1 (a) Inductively-loaded CS stage, (b) input impedance in the presence of CF,
(c) equivalent circuit. [25]
 Fig.- 3.5.2. - Inductively-degenerated cascode CS LNA. [25]

ii. Common-Gate Topology

A common-gate amplifier is a type of amplifier that uses a common-gate
transistor configuration. It is often used as a low- noise amplifier, as it can
provide a high voltage gain with low noise.In a common-gate amplifier, the
input signal is applied to the gate of a transistor, and the output is taken
from the transistor's drain. The transistor's source is connected to ground.
Because the gate and the drain are both used as input and output terminals,
this configuration is called a common-gate amplifier.One advantage of the
common- gate amplifier is that it has a high input impedance and a low output
impedance, making it suitable for use in high-impedance circuits. It is also
relatively insensitive to changes in load impedance, which makes it useful
in applications where the load impedance may vary.
However, the common-gate amplifier has some limitations. It has a
relatively low voltage gain compared to other amplifier topologies, and it can
also suffer from poor power efficiency due to the high current flowing
through the transistor. Despite these limitations, the common-gate amplifier is
still widely used in a variety of applications, particularly as a low-noise
amplifier.
 Fig.- 3.5.3. a) CG stage, (b) effect of noise of M1. [25]

3.5.1 There are several steps involved in designing a low noise amplifier
(LNA):

i. Define the specifications: Determine the desired frequency range, gain,

noise figure, and input and output power levels.
ii. Select the transistor: Choose a transistor that is suitable for the desired
frequency range and has a low noise figure.
iii. Design the matching circuits: Design the input and output matching
circuits to optimize the impedance matching between the transistor and the
surrounding components.
iv. Calculate the bias voltage: Determine the appropriate bias voltage for the
transistor based on its operating point.
v. Design the layout: Use a computer-aided design (CAD) program to lay
out the LNA circuit on a printed circuit board (PCB) to ensure that the
desired performance is achieved.
vi. Test and optimize the design: Build and test the LNA to verify that it
meets the desired specifications. Make any necessary adjustments to optimize the
performance.Some additional considerations for designing an LNA include
selecting appropriate passive components, such as inductors and capacitors, and
using shielding and grounding techniques to reduce noise and interference.
 Chapter-4

Circuit Design
4.1 Body Floating Technique

A body floating transistor (BFT) is a type of transistor that has a floating body
instead of being connected to a fixed voltage reference. In traditional transistors, the
body is usually connected to a voltage source to maintain its potential and prevent
unwanted effects such as leakage currents and parasitic capacitance.In a BFT, the
body is not connected to any fixed voltage, but is allowed to float with respect to
the surrounding substrate. This can result in improved performance in some
applications, such as in high-speed analog and mixed-signal circuits, as well as in
power electronics.
One of the main advantages of a BFT is that it reduces the parasitic capacitance
between the body and the substrate, which can improve the high-frequency
performance of the transistor. Additionally, by floating the body, the transistor
can be made more immune to latch-up, a condition in which the transistor
becomes "stuck" in an unstable state and can cause damage to the circuit.BFTs are
used in a variety of applications, including in operational amplifiers, voltage
regulators, and other analog and mixed-signal circuits. However, they require
careful design and layout considerations, as well as specific process technologies,
to ensure reliable and consistent performance. Fig-4.1 shows a body floating
MOSFET (connection between drain to body/bulk through resistor RB).

Fig-4.1.1 Schematic of body floating MOSFET

4.2 Self Biased Technique
In a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) circuit, self-
biasing is a technique used to establish the correct operating point or bias voltage for
the transistor without the use of an external biasing circuit.The self-biasing technique
involves connecting a resistor between the gate and the drain of the MOSFET.
This resistor provides a feedback loop that generates a voltage drop proportional
to the current flowing through the transistor. The voltage drop is then used to bias
the transistor to the desired operating point.The self-biasing technique is commonly
used in amplifier circuits, where it is important to maintain a stable operating point.
By using a self-biasing circuit, the amplifier can automatically adjust the bias
voltage to compensate for changes in temperature, supply voltage, and other
factors that may affect the operating point of the transistor. One of the advantages of
using self- biasing is that it allows for a simplified circuit design, eliminating the
need for external biasing components such as resistors or capacitors. Additionally,
self-biasing can help reduce power consumption by minimizing the voltage drop
across the biasing circuit.
However, there are some drawbacks to using self-biasing. For example, it may not
provide the most accurate or stable bias voltage compared to more complex biasing
circuits. Additionally, the resistor used in the self-biasing circuit may introduce
additional noise into the circuit, which can affect the overall performance of the
amplifier.So, self-biasing is a useful technique for MOSFET circuits, but its
effectiveness and suitability depend on the specific application requirements and
design considerations.

Fig-4.1.2 Self-bias Circuit

The input impedance of the proposed LNA can be given by,

Zin = sLS1 + (1)

The voltage gain (Av) can be given by,

Av ( (2)

Output impedance (Zout) of the LNA can be given by,

Zout || (3)

Where the output resistance of MOSFET M3 is ro3 .For the MOSFET M4,the
gate–source capacitance is Cgs4,transconductance is gm4, and output resistance is
ro4.Here instead of connecting the substrate to the ground directly,the substrate is
connected to the ground through RB1,at the buffer stage.

Fig. 4. Circuit Diagram of the proposed Low Noise Amplifier

4.3 Flow Chart

Input RF Signal

Matching
Network

Cascode
Amplifier

Output Buffer

The proposed Low noise amplifier is demonstrated by a GPDK 45-nm CMOS

Technology. Fig.-4 shows the schematic The proposed LNA is designed with a
cascode CG stage and a buffer stage. Here in the schematic, MOSFET M1 acts
as an input stage where the RF signal is entering through a matching network
(consisting of Ls1 and Ls2).M1 and M2 have formed a cascode and M3,M4 formed
the buffer stage (see in fig-4).Here the substrate to drain with a resistor (20.6
KΩ) attains better gain and noise figure primarily due to free from body
leakage. In the schematic Supply voltage of VDD 1.8 Volt and Rf1 of 600 ohm is
used. Body floating technique is achieved by connecting Ls and RB between the
body and drain terminal of M1 and M2 respectively. Then the signal goes to the
output buffer stage. It is also a cascade configuration of an amplifier. It is used as
an output buffer to improve the gain.

The applied supply voltage is VDD of 1.8 V and the proposed LNA consumes
70.48 mW power. The reported CMOS LNA having B.W more than 4 GHz and
N.F 2.5dB. The simulation of S11 parameter of the LNA is shown in Fig.5(a). The
measured S11 is closed to the calculated one. The measured S21 and S12 are
shown in fig.3[b]. and fig.5[c] respectively. The proposed LNA has attained a
minimum S11 of -16.26 dB at 6.54 GHz and S11 less than -10 dB at 5 GHz to 9
GHz.The noticeable S11 has been achieved due to a T-matched input network
consisting of LS1, LS2, CGS1 and 1/gm1 . The LNA achieves maximum S21 of 13.02
dB at 9 GHz and 3-dB BW (f3dB) of 4.47 GHz (3.16-9 GHz).
Above all, the LNA achieves an excellent S12 of -31.3 dB to -24.3 dB (4.9-8.9
GHz).A notable S12 is attributed to the addition of the cascaded CG input
stage, for that the reverse signal through Cgd is relatively insignificant. The LNA
achieves a notable minimum NF (NFmin) of 2.28 dB at 5 GHz and NFavg of
2.84 dB. The important parameter NF is attributed to the adoption of body
floating. Simulation results of S22,min NF,NF and gain are shown in fig.5[d],
fig.5[e] , fig.5[f] and fig.5[g] respectively.

S21 is in magnitude in dB, Band-Width BW [GHz] is f3dB in GHz, (NF - 1) is

the excess noise factor (of NFavg) in magnitude and dissipated power PD [mW] in
mW.

4.4 Specifications
Table 3- specifications of proposed LNA

Circuit BW S21 S11 NF min/ NF avg FOM CMOS

configuration GHz dB dB dB GHz/mW process

2-stages: 4.9-8.9 12.42- -10 ~ - 2.28/2.5 0.34 45nm

CG+CG 13.02 16.25

Our aim was to design the LNA having bandwidth greater than 3.5 GHz and keeping
the noise figure as low as possible.
 Chapter-5

Result and Discussion

The proposed LNA has been designed using body floating technique. There are
several reasons behind the use of body floating technique. Without body floating
technique,it could be seen that the range of frequency is getting reduced in fig[5.a]
and in fig[5.b],the GA(gain) and S curves do not overlapped .Therefore, it is
21

intended to demonstrate a Low Noise Amplifier (LNA) using body floating

technique.
The proposed LNA has been gone through several experiments so that the proper
value of L and R can be chosen. In fig[5.c], fig[5.d], fig[5.e] and fig[5.f] the
c f1

simulation of noise figure(NF) has shown. The noise figure(NF) is increased to

2.82dB when R is 500Ω in fig[5.c], and 3.02dB when R is 400 Ω in fig[5.d].
f1 f1

Similarly, the proposed LNA attained the noise figure of 2.82dB and 2.6dB when
the value of L is 4nH and 1nH respectively in fig[5.g] and fig[5.h]. Though the
O

value of the noise figure is about 3dB discussed above,but the LNA achieved the
best noise figure and gain when R is of 600 Ω and L is of 2.7nH.
f1 c

Fig- 5.(b) Simulation Result of

Fig- 5.(a) Simulation Result of
S21 and gain without body
S11 without body floating
floating

Fig- 5.(c) Simulation Result of

Noise Figure(NF) when Rf1 Fig- 5.(d) Simulation Result of
=500 Ω Noise Figure(NF) when Rf1
=400 Ω

Fig- 5.(e) Simulation Result of

Noise Figure(NF) Fig- 5.(f) Simulation Result of
Noise Figure(NF) when L c
when L c =4nH =1nH
Fig. 5.(g) Simulation Result
11 of S Fig. 5.(h) Simulation Result of S21

Fig. 5.(i) Simulation Result of S12 Fig. 5.(j) Simulation Result of S22

Fig. 5.(k) Simulation Result of min. NF Fig. 5.(l) Simulation Result of NF

Fig-5.(m) Simulation Result of Gain

 Table 4 -Different CMOS LNAs with same operation frequency (recently proposed work)

Circuit BW S21 S11 NF min/ NF avg FOM CMOS

configuratio GHz dB dB dB GHz/mW process
n
This work 2- 4.9-8.9 12.42- -10 ~ - 2.28/2.5 0.34 45nm
stages: 13.02 16.25
CG+C
[2], 2019,TMTT 3 stage
G BDDA 3-12 6-9 <-10 5.9/6.65 0.04 180nm
[3], 2007 ,JSSC 3 stages 1.2-11.9 6.7-9.7 <-11 4.5/4.8 0.68 180nm
:CG+CS+CS

[4], 2020,TMTT 3 stages 1-20 9.8 <-10 3.3/5.3 2.03 65nm

:CG+CS+CS -
12.
[5],2019,TCAS-II 3 stages 0.5-7 13.8
8 <-10 2.87/3.32 2.92 180nm
:CS+CD+CS -
16.8
[6],2019,EE 3 stages 3.1-10.6 12.4 <-10 3.3/3.9 1.07 180nm
:CG+CS+CS -
13.6

Smith Chart of proposed LNA :

fig.5.n Smith Chart of proposed LNA

Chapter-6

Conclusion
The body floating technique helps to minimize the effect of substrate noise,
which can be a significant source of noise in the LNA. By isolating the substrate,
the technique reduces the parasitic capacitances between the substrate and other
components, resulting in lower noise levels.The reduction in noise achieved
through body floating improves the overall performance of the LNA. It enhances
the signal-to-noise ratio (SNR), leading to improved sensitivity and lower noise
figure. As a result, the LNA can amplify weak signals with higher fidelity and
accuracy. This technique can also contribute to increased gain in the LNA. By
reducing the noise figure, the LNA can achieve higher gain without
compromising its noise performance. This is particularly beneficial in
applications where signal amplification is critical, such as in wireless
communication systems.While this technique offers several advantages, it also
introduces some design challenges. It requires careful consideration of the
biasing scheme, as the floating body affects the transistor's threshold voltage and
other electrical characteristics. Additionally, the technique may require
additional circuitry or modifications to ensure proper operation and stability.This
model technique is a valuable approach for reducing noise and improving the
performance of low noise amplifiers. By isolating the substrate and minimizing
parasitic capacitances, it helps achieve lower noise figures, increased gain, and
improved overall performance. However, designers must address the associated
design challenges to ensure proper implementation.

As semiconductor technologies continue to advance, the body floating technique

can be integrated with emerging technologies such as FinFETs, nanowires, or
tunnel FETs. These advancements can further enhance the performance of LNAs
by reducing leakage currents, improving control over the body terminal, and
enabling higher levels of integration.LNAs using the body floating technique can
find significant applications in millimeter-wave and terahertz frequency bands.
These frequency ranges are crucial for high-speed wireless communications,
automotive radar, and imaging systems. Future research can focus on optimizing
the body floating technique specifically for these frequency ranges to achieve
low noise, high gain, and wide bandwidth.Energy efficiency is a critical concern
in many applications, especially in portable devices and wireless sensor
networks. Future developments in LNAs using the body floating technique can
aim to reduce power consumption while maintaining or improving performance.
This could involve exploring advanced biasing schemes, optimization
algorithms, or adaptive techniques that dynamically adjust LNA parameters
based on the operating conditions.The body floating technique can be combined
with noise-canceling and self-calibration techniques to further improve LNA
performance. Noise-canceling techniques can help mitigate external noise
sources, while self-calibration techniques can compensate for process variations,
temperature changes, or aging effects. Integrating these techniques with the body
floating LNA can enhance robustness, reliability, and adaptability.LNAs using
the body floating technique have potential applications in biomedical and
healthcare systems. They can be used in wireless medical implants, wearable
devices, or bio-sensing applications where low power consumption, high
sensitivity, and reliability are critical. Future research can focus on optimizing
the body floating technique for these specific applications, taking into account
power constraints, biocompatibility, and integration with other components.
As quantum computing and quantum communication technologies continue to
advance, there will be a need for LNAs operating at extremely low temperatures
and with ultra-low noise figures. The body floating technique can be explored in
this context to develop LNAs that meet the unique requirements of quantum
computing and quantum communication systems.In summary, the future scope
of LNAs using the body floating technique involves advancements in
semiconductor technologies, applications in millimeter-wave and terahertz
frequencies, energy efficiency improvements, integration with noise-canceling
and self-calibration techniques, biomedical and healthcare applications, and
addressing the requirements of quantum technologies. These developments have
the potential to enhance the performance, reliability, and versatility of LNAs in
various domains.

The demonstrated CMOS LNA using body floating is best operating at 4.9-8.9
GHz frequency. The S21 and Noise Figure(NF) of the LNA have been enhanced
as forward-biasing has been done for body to source (VBS).(Substrate leakage of
the transistors being almost null,provides low noise) . Considering the low NF,
this designed LNA is suitable for 5G systems,such as wifi.
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