FPGA Emulation of Quantum Circuits

Ahmed Usman Khalid Zeljko Zilic Katarzyna Radecka

Microelectronics and Computer Microelectronics and Computer Department of Electrical and
Systems Laboratory Systems Laboratory Computer Engineering
McGill University McGill University Concordia University
Montreal, Quebec Montreal, Quebec Montreal, Quebec
Email: [email protected] Email: [email protected] Email: [email protected]

Abstract— Quantum computing offers immense speedup in tems, it is advantageous to have a hardware emulator which
performing tasks such as data encryption and searching. The approximates quantum effects, but mimics the parallel nature
quantum algorithms can be modeled using classical computing of quantum computation more closely than software-based
devices, however classical computer simulations cannot deal
efficiently with the parallelism present in quantum algorithms. simulators.
The quantum circuit model for quantum algorithms is sufficient Quantum circuits are one convenient way of describing
to describe the known quantum algorithms. Using analogies quantum algorithms. Such circuits comprise of analogues to
between quantum and digital circuits, we design the emulator of digital bits and gates. These components can be emulated
quantum algorithms in FPGAs that allows efficient experimen-
in existing FPGAs, which can map inherently parallel com-
tation with new quantum algorithms. This paper concentrates
on new techniques for modeling quantum circuits, including the putational tasks more efficiently than software simulations.
entanglement and probabilistic computing realization, as well as For this reason, we investigate the design of quantum circuit
the critical issues in the required precision of computing. emulators by classical circuits, and devise an FPGA-based
quantum circuit emulator. Using quantum circuit primitives,
I. I NTRODUCTION the construction of new quantum algorithms becomes intuitive
There is an increased interest in quantum computing and and similar to the common software library approaches.
algorithms [5]. Many quantum algorithms outperform their The paper is organized as follows. In Section II, we provide
classical counterparts through parallelism that is impossible in the background on quantum computation. In Section III, we
classical computing. Quantum algorithms use physical effects give details of our quantum circuit emulation system, followed
like entanglement and super-position to achieve the speedup. by several case studies and performance analysis in Section IV.
These effects are hard to replicate at large scale and lead
to reliability and precision issues, as well as to the need to II. BACKGROUND
employ suitable quantum measurement procedures [1]. Nev-
ertheless, some of the quantum effects have been successfully In this section, we provide a brief review of the concepts
used in practical applications such as data encryption and com- in quantum computing that have implications to the design of
munication [5]. Further, several quantum-computing systems a quantum circuit emulator.
are being developed [7]. IBM has developed a small-scale
A. Probabilistic vs. Deterministic Computing
quantum machine that is able to execute the celebrated Shor’s
algorithms for factoring numbers. However, creating larger One of the major distinctions of quantum computing is
and more practical quantum computers is still not possible, that it is probabilistic and that quantum algorithms have to
as knowledge about building quantum systems is still in its deal with the reality of measurement errors. Surprisingly,
infancy. To develop quantum algorithms, simulation models this difference often gets overlooked when modeling quantum
nevertheless suffice. circuits and most modeling approaches still try to make the
Feynman noted that a quantum computer can be modeled simulations fit within the deterministic mode of computation.
efficiently only by another quantum machine. In absence Deterministic circuits present a computation model where
of large-scale quantum machines, quantum algorithms are results of the computation can be obtained without any mea-
currently being simulated by classical computers. Modeling surement error. A classical (non-quantum) probabilistic circuit
of quantum processes in software is the arduous task that is runs a series of inputs through the network of gates and outputs
currently facilitated mostly by quantum computing libraries the bits according to the probability distribution induced by the
[3], [11], [12]. The challenge here comes from the need for given network. Hence, in probabilistic computing the result
using approximations of quantum processes, as their exact of computation cannot be determined correctly every time a
representation in classical computing is not possible. Even by measurement of the result is made. Consequently, there is
using approximations, it is estimated that a single simulation a probability of an error in measuring probabilistic circuit
run over a 20-bit quantum system requires a day of computing outputs, and the computation has to be performed a sufficient
time on modern computers [8]. For developing quantum sys- number of times to make the expected error acceptable. In
this paper, we address both modes of modeling by FPGA is a key design issue. The second goal is to emulate the
emulators. parallelism in quantum computing using FPGAs. Finally, it
is desired that the modeling tool be simple to use and that the
B. Quantum Information Representation construction of the model does not require significant effort
The second major difference to classical computing arises from the developer.
from the types of signal values required to perform computing.
While the basic information units for classical circuits are 0 Import quantum
and 1, quantum computing uses complex numbers as bearers of circuit package to
design
information. Hence, representing a single quantum information
unit might require a large number of classical bits, depending
on the precision required. Construct quantum circuit
More formally, the states of the quantum system belong to using gates provided
a vector space over complex numbers in which there exists
an inner product of vectors. Such a vector space is usually
referred to as the Hilbert Space H. For our purposes, it suffices Synthesize circuit on FPGA
Simulate circuit using VHDL for hardware emulation of
to say that the quantum states are depicted as vectors of simulation tools the quantum circuit
complex numbers.
In denoting these vectors, commonly used is the Dirac bra-
ket notation. Elements of H are ”ket” vectors given by |xi ∈ Fig. 1. Modeling quantum circuits using the VHDL quantum gate library
H. A corresponding ”bra” vector hx| is an element of the
dual space H ∗ of all operators on the vector space that act on The overall design process is illustrated in Figure 1. Quan-
vectors and produce scalar values. tum circuits are constructed from the quantum gate com-
ponents provided in the library that we have created. The
C. Quantum Bits correctness of the circuit can be verified either by software
The basic units of quantum information can be viewed as simulation or by FPGA emulation. We thus, have a technique
simple two-state systems, such as magnetic spin of plus/minus for modeling quantum ciruits using VHDL and then synthe-
one half. The state of a spin is given as a continuous quantity sizing the circuit in hardware to achieve performance needed
represented by two real numbers. It is exactly this continuity to make the whole process more practical.
in spin representation that contributes to the ability of storing We next show how the fundamental constructs of quantum
the infinite classical information by a single quantum system. circuits and the rules governing quantum computation are
Quantum bits defined this way are commonly referred to as simulated by classical technology.
qubits. Qubits can be realized by means such as NMR and
trapped ion interactions. α real α imaginary
Binary qubits have two computational base states denoted Sign Decimal
N bit Mantissa
Sign Decimal
N bit Mantissa
Bit bit Bit bit
as |0i and |1i. Unlike classical bits, quantum bits are in a
linear superposition of the basis states |0i and |1i. β real β imaginary
Sign Decimal Sign Decimal
N bit Mantissa N bit Mantissa
|ψi = α|0i + β|1i (1) Bit bit Bit bit

where α and β are complex coefficients related as Fig. 2. Fixed-point quantum bit representation

|α|2 + |β|2 = 1. (2)

B. Emulation of Pure Quantum Bits
The superposition phenomena, by which the qubits simulta- The quantum bit is implemented using Equation 1. Thus, we
neously exist in states |0i and |1i is explained by considering need to store the values of α and β to describe a qubit. The
|α|2 and |β|2 as probabilities of being in |0i and |1i, respec- finite precision description of α and β introduces imprecision
tively. However, when a measurement is performed on a qubit, errors, as quantum gates involve operations like add and
it collapses to either of the two basis states. multiply on α and β. To keep the size of the quantum circuit
III. FPGA Q UANTUM C IRCUIT E MULATOR to a manageable proportion, we implement the α and β using
the fixed point scheme described in Figure 2.
A. Challenges in Emulating Quantum Circuits Each qubit is represented by four fixed point numbers.
Emulation of quantum circuits requires mapping concepts The fixed point scheme was chosen over the floating point
from quantum physics to classical technologies. The main goal representations because α and β can have a decimal part
is to simulate quantum computation in a way that is more of 0 or 1 only. Having the exponent field in the number
flexible and efficient than software simulators. As most quan- representation (as in floating point arithmetic) does not bring
tum algorithms require an exponential amount of resources benefits in this case. Regarding the precision, the emulator
when simulated by classical technology, resource management has been designed in a modular way - changing the size of
the fractional part is achieved without any modifications to and β, the third dimension is attributed to the use of complex
the other components of the system. This is an advantage numbers. The representation error in the qubit is then given
for experiments dealing with precision and fault-tolerance of as the absolute difference between the true and discretized
quantum algorithms that incorporate ideas of quantum error positions of the vector representing the qubit.
correction to the emulator.
Quantum gates, described by matrices of complex numbers, C. Quantum Gates
bring additional imprecision to the system. The error model of A quantum gate is the analogue of a logic gate in a classical
a quantum gate is depicted in Figure 3. Here, δ is the error in circuit model. Few gates that are useful in developing quantum
the input that is propagated and augmented with error , the algorithms are given next, together with the error magnitudes
discretization error of the matrix coefficients representing the obtained in their modeling by classical circuits.
given gate. Quantum systems are reversible by nature. Information can
travel freely in both directions: from inputs to outputs and vice
versa. Thus, each gate must have the same number of inputs
ε
and the outputs. The single input gates are defined by a 2 × 2
⎡α in ⎤ ⎡a b ⎤ ⎡α out ⎤ matrix with complex entries.
⎢β ⎥ + δ ⎢c d ⎥ ⎢β ⎥
⎣ in ⎦ ⎣ ⎦ ⎣ out ⎦ 1) Walsh-Hadamard Gate: The Walsh-Hadamard gate (H
Quantum Gate gate) facilitates the superposition of pure quantum states.
 
1 1 1
Fig. 3. Quantum gate error model H=√
2 1 −1
The error model can be expanded as in Figure 4. Thene, the If |ψi = α|0i + β1i is the input qubit to the Hadamard gate,
multiple sources of an error are added linearly. This model is then the transformed state is:
used to evaluate the error at each gate in the network. 1
H|ψi = √ ((α + β)|0i + (α − β)|1i)
2
⎡ aα in + bβ in ⎤ ⎡α + β in ⎤ ⎡ 2εδ ⎤ ⎡α out ⎤ The new state H|ψi is a superposition of the computational
⎡a + b⎤ ε ⎢ in
⎢cα + d β ⎥ δ⎢ ⎥ ⎥ ⎢ 2εδ ⎥ ⎢β ⎥ basis states. This gate is also referred to as the square root of
⎣ in in ⎦
⎣c + d ⎦ ⎣α in + β in ⎦ ⎣ ⎦ ⎣ out ⎦
the identity, since H 2 = I, and therefore H|H|φi = |φi.
Actual Value Input Error Gate Computation
Imprecision Error The implementation of the H gate requires four multiplica-
Error
tions and four additions, as both α and β are complex. Since
the coefficients of the Hadamard gate cannot be represented
Fig. 4. Expanded gate error model without imprecision, the gate incurs a discretization error on
both the α and β values of the output qubit.
2) Phase Shift Gate: The operation of the phase shift gate
(α , β ) Absolute
Error
φ on the single qubit is defined in the following way:
1
(α + α e , β + β e ) |0i → |0i and |1i → eiφ |1i
The definition of a phase shift gate is given by matrix NS
0 as:  
i 1 0
NS =
0 eiφ
The phase-shift gate requires multiplication of two complex
entities: eiφ and β. This means that 4 multiplications and two
additions have to be performed in this gate. Due to the finite
representation of eiφ , a discretization error is incurred on the
Fig. 5. Discretization error in a qubit β value of the qubit at the output.
3) X-Gate: The X-gate is a single-qubit gate that performs
The absolute error E is thus, the quantum equivalent of a NOT operation on the qubit. The
quantum NOT operation simply swaps the α and β values of
E=
p
αe2 + βe2 (3) a qubit:  
0 1
X=
where αe and βe are described in Figure 4. These error values 1 0
effect the probability of the qubit to be in |0i or |1i state when
For the vector |ψi = α|0i + β|1i, this transformation
the qubit is subjected to a quantum measurement.
amounts to producing
The qubit can be considered as a three dimensional unit
vector in Figure 5 - while two dimensions are needed for α X|ψi = β|0i + α|1i
The gate does not incur any error to the algorithm as the parameter to the code generating script. For efficiency reasons,
emulation of the gate involves swapping the bits of α and the script produces the VHDL description of the resulting
β transformation, rather than a large matrix form. The outlined
4) Controlled NOT Gate: Controlled NOT, or CNOT gate procedure hence automates the construction of arbitrary size
accepts two quantum bits: a control qubit, |ηi and a target quantum gates.
qubit, |ψi, and produces the outputs: |ηi and |(η ⊕ ψ)i where
⊕ is the XOR operation. Qubit 1 Quantum Quantum
Its transform matrix in input order |ηi and |ψi is: Gate Gate

  Quantum Quantum
1 0 0 0 State
Register
State
Register
 0 1 0 0  Qubit N
Nc =  0 0 0 1 
 Quantum
Gate
Quantum
Gate

0 0 1 0 Clock

In simple terms, if |ηi = |0i, then |ψi is inverted, hence Fig. 6. Emulated quantum circuit overview
the name CNOT. This operation is well-defined for any linear
superposition of states, unlike binary NOT gates which only To construct network of quantum gates, we insert interme-
convert 0 to 1, and vice-versa. diate registers to hold the qubit values after each gate. These
5) Z-Gate: The Z-gate is a single-qubit gate that inverts the quantum state registers (QSRs) essentially represent the state
phase of the qubit in 1i basis. of the entire quantum system at any given stage of evolution.
 
1 0 The gates are important as they synchronize the data flow in
Z=
0 −1 the system, which is important for large circuits.
That is,
Z|ψi = α|0i − β|1i
Quantum Quantum
The Z-gate does not introduce any error as it simply flips State State
Register Register
the sign bits for the complex beta value. 00> real 00> real
The data in Table I was obtained by computing the absolute 00> complex Quantum 00> complex
error in the output of each gate using 16-bit mantissa length Qubit 1 01> real Gate 01> real
for gate coefficients and the inputs. The input to each gate unentangled Quantum 01> complex 01> complex
Gate
was chosen to be |ψi = √12 |0i + √12 |1i. From experiment it Qubit 2 causing 10> real 10> real
unentangled entangle 10> complex 10> complex
was found that the error is maximum when the qubit is in a ment
Quantum
11> real Gate 11> real
superposition state.
11> complex 11> complex

TABLE I
√ √
A BSOLUTE E RROR ON Q UBIT IN STATE |ψi = 1/ 2|0i + 1/ 2|1i Fig. 7. Emulation of quantum evolution of an entangled system

Gate Absolute Error

(16-bit mantissa) E. Emulation of Entanglement
Hadamard Gate 3.05 × 10−5 A gate resulting in entanglement requires considerably more
Phase-Shift Gate 3.08 × 10−5
X-Gate 0
resources than a gate where no entanglement occurs. This is
Z-Gate 0 the reason why efficient simulation of quantum computation is
difficult on classical computing devices. Consider a two-input
C-NOT gate and a situation where the controlled qubit is in
D. Emulation of Quantum Gates superposition. In such a case the gate operation is described
A library of common quantum gates has been developed as follows
comprising of most of the simple quantum gates (Hadamard
gate, CNOT gate, X-gate, Z-gate, phase-shift gate) that are |ψcontrol i = α1 |0i + β1 |1i
commonly used. The gates are realized by mapping their
transformation to VHDL code. Therefore, gates with simple |ψtarget i = α2 |0i + β2 |1i
transformations like the X-gate and Z-gate require less re- |ψout i = α1 α2 |00i + α1 β2 |01i + β1 β2 |10i + β1 α2 |11i
sources than the other gates.
We then decided to use the code-generating capability of In an entangled state, the qubits cannot be represented
the VHDL language to automatically produce descriptions individually. For the case of two qubits |ψ1 i and |ψ2 i, if
of multiple input quantum gates from single-input gates. In they are unentangeled we can represent them as two distince
general, a n-input gate is represented by a 2n by 2n matrix. For qubits |ψ1 i|ψ2 i. However, once entangled the qubits can only
controlled gates, the number of control variables is passed as a be represented in |ψ1 ψ2 i form.
 The C-NOT gate requires 4 complex multiplications in this be constructed. The potential of this emulation technique for
case. For an n input C-NOT gate, the number of complex large quantum circuits is also evident as by combining multiple
multiplications is 2n . This exponential increase becomes a FPGAs we have a possibility of emulating the functionality
serious issue with entangled systems. FPGAs have a large and other pertinent quantum effects (like quantum error-
amount of logic cells (and multiple FPGAs can be combined correction) of more complex quantum circuits.
for even bigger circuits) and therefore large quantum circuits
TABLE II
with entangled states can be emulated. While efforts are
G ATE L OGIC C ELL U SAGE ON A LTERA S TRATIX EP1S80F1020C-5
made to overcome this overhead in the resource usage when
simulating the evolution of an entangled system [10], we Gate LC Usage LC Usage
note that the entanglement poses a fundamental bottleneck in (8-bit mantissa) (16-bit mantissa)
modeling quantum systems by classical means. Hadamard Gate 704 1284
Phase-Shift Gate 386 708
From C-Not Gate 40 231
software X-Gate 0 0
Z-Gate 0 0

State
Detection
Probabilities Quantum Qubit n
measurement State H Rn −1 Rn
simulator Detected
Input from
emulated
Qubit n-1
quantum H Rn −2 Rn −1
circuit

Qubit 2
Fig. 8. Emulation of probabilistic quantum computing H R2

Qubit 1
H
F. Emulation of Quantum Measurements and Probabilistic
Computing
Fig. 9. A N-qubit QFT Circuit
Quantum measurements and the probabilistic nature of
quantum algorithms are currently supported directly by a
combination of hardware and software means. Due to the com- B. Quantum Fourier Transform
plexity of quantum measurement algorithms (which are being The quantum Fourier transform (QFT) [5], [6], [2] is an
investigated and developed in parallel), software simulation of important quantum algorithm as it plays a key role in phase
quantum measurements is currently employed [1]. We however estimation, order-finding and factoring algorithms. A N qubit
foresee the posibility of emulating quantum measurement in QFT circuit is depicted in Figure 9. The QFT algorithm
hardware once their algorithms become developed and stable. achieves exponential speedup compared even to FFT, which
To perform the measurement in hardware, it suffices that by itself is one of the most important nontrivial algorithms.
the probabilities for detecting each state are pre-computed in The entire QFT circuit is constructed from one or two input
software and stored in hardware. The probabilities can then quantum gates. The QFT comprises of Hadamard gates and
be used as weights to emulate the random state detection in the controlled-Rj . The Rj transform is defined as follows
hardware.  
1 0
IV. Q UANTUM C IRCUIT C ASE S TUDIES Rj = j
0 e2πi/2
A. Emulator Mapping Results
The Rj gate is similar to the phase-shift gate so the
The techniques presented in this paper offer the means for controlled-Rj is implemented using controlled phase-shift
quantum circuit emulations in FPGAs by including quantum gates. We implemented a 3-qubit QFT circuit using our library.
gate library and entanglement components, like most quan-
tum software simulators [11]. No changes to standard FPGA C. Grover’s Search Algorithm
mapping and the overall design flow are required. The Grover’s search algorithm [5], [6], [9] is yet another
Table II depicts the logic cell usage for the quantum gates illustration of quantum algorithms significantly outperforming
in the library and that of the quantum circuits described above. classical
√ algorithms. The algorithm performs searches in is
The device chosen were Altera Stratix EP1S80F1020C. The O( N ) time, rather than classically possible O(N ), for a
simulation tool used is ModelSim and Leonardo Spectrum was database with N entries. The Grover’s search algorithm circuit
used to obtain synthesis results. The mantissa length for the for 4 element data base is depicted in Figure 10. The oracle
qubit was chosen to be 16 bits. gate is itself a “black box” quantum circuit that queries the
As the number of qubits increases, the circuit size grows database for the search key. The oracle gate can be constructed
exponentially due to entanglement effects. However, from the using the quantum gates provided in the library. In this circuit,
emulation results we can observe that fairly large circuits can entanglement can occur depending on the query result from
the oracle gate. The circuit in Figure 10 was implemented V. C ONCLUSIONS AND F UTURE W ORK
using our library. We presented the issues in the design and the operation of
a quantum circuit emulator based on FPGAs and developed
Qubit 1 H H X X H a platform for the development of quantum circuits. The
emulator allows the construction of fairly complex quantum
Qubit 2 Oracle
H H X H H X H circuits from the component library in a simple way. At the
Gate
Qubit 3 same time, it emulates the parallelism present in quantum
H H computers by constructing parallel evolution paths for each
quantum bit on the FPGA. We show that FPGA emulations are
Fig. 10. Grover’s search algorithm for a 4 element database advantageous, as it is difficult to efficiently emulate the parallel
evolution of the quantum system in software. The emulator
Emulation data for the algorithms is provided in Table III. is also scalable and has the potential of emulating complex
Both of the algorithms were synthesized on the Altera Stratix quantum circuits. This emulator can also incorporate further
EP1S80F1020C chip using 16-bit mantissas. quantum computing concepts like quantum error-correction,
fault-tolerant quantum computing and quantum measurement
TABLE III
techniques. These would be especially helpful in developing
Q UANTUM C IRCUIT P ERFORMANCE
practical systems for quantum computers.
Other uses of the quantum emulator can be for the anal-
Circuit LC Usage Clock Speed
(16-bit mantissa) ysis, optimization and approximation of quantum Fourier
3-qubit Quantum Fourier Transform 5076 82.1 MHz transforms, which are critical for most spectacular quantum
Grover’s Search 12636 82.1 MHz algorithms. We plan to further explore the development of
quantum/reversible gate libraries and specialized architectures
for emulation of quantum algorithms [8] and [15].
D. Comparison to software simulation Finally, we plan to undertake a study and optimization of
The hardware emulation of quantum circuits has significant quantum measurement algorithms using this emulator, which
advantages over software simulators. First, the evolution of is currently not practical by software simulations.
each quantum bit can occur in parallel. Software simulators R EFERENCES
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