P55 Datasheet

TMS320F28P550SJ, TMS320F28P559SJ-Q1
SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024
TMS320F28P55x Real-Time Microcontrollers

1 Features – 5V failsafe and tolerant capability on 4 GPIOs
for PMBUS/I2C support
• Real-time processing: – Configurable 1.35V VIH on 4 GPIOs
– 150MHz C28x 32-bit DSP CPU • System peripherals
– Equivalent to 300MHz Arm® Cortex®-M7 – 6-channel Direct Memory Access (DMA)
based device on real-time signal chain controller
performance (see the Real-time Benchmarks – 91 individually programmable multiplexed
Showcasing C2000™ Control MCU's Optimized General-Purpose Input/Output (GPIO) pins
Signal Chain Application Note (22 shared with Analog)
– IEEE 754 single-precision Floating-Point Unit – 17 digital inputs on analog pins
(FPU32) – Enhanced Peripheral Interrupt Expansion
– Trigonometric Math Unit (TMU) (ePIE)
• Support for Nonlinear Proportional Integral – Multiple low-power mode (LPM) support
Derivative (NLPID) control • Communications peripherals
– CRC Engine and Instructions (VCRC) – One Power-Management Bus (PMBus)
• Programmable Control Law Accelerator (CLA) interface
– 150MHz • Fast Plus Mode Support - 1MHz SCL
– Equivalent to 200MHz Arm® Cortex®-M7 • 5V/3.3V/1.35V VIH support on select pins
based device on real-time signal chain – Two Inter-integrated Circuit (I2C) interfaces
performance (see the Real-time Benchmarks – Two Controller Area Network with Flexible
Showcasing C2000™ Control MCU's Optimized Data-Rate (CAN FD/MCAN) bus port
Signal Chain Application Note • 4KB message RAM per MCAN module,
– IEEE 754 single-precision floating-point independent of system memory
instructions • Ability to re-use RAM for CPU data variables
– Executes code independently of main CPU if MCAN is not used
• On-chip memory – One Universal Serial Bus (USB 2.0 MAC +
– 1088KB of flash (ECC-protected) across five PHY)
independent banks – Two Serial Peripheral Interface (SPI) ports
• Four 256KB banks – Three UART-compatible Serial Communication
• One 64KB bank, ideal of LFU/Bootloaders/ Interface (SCI)
data – One UART-compatible Local Interconnect
– 8KB of OTP (One Time Programmable flash Network (LIN) interface
memory) – Fast Serial Interface (FSI) with one transmitter
– 133KB of RAM (ECC/Parity protected) and one receiver (up to 200Mbps)
• Security • Analog system
– Secure Boot – Five 3.9MSPS, 12-bit Analog-to-Digital
– JTAG Lock Converters (ADCs)
– Advanced Encryption Standard (AES) • Up to 39 external channels (includes one
accelerator gpdac output)
– Unique Identification (UID) number • Four integrated Post-Processing Blocks
• Clock and system control (PPB) per ADC
– Two internal 10MHz oscillators – Four windowed comparators (CMPSS) with
– Crystal oscillator or external clock input 12-bit reference Digital-to-Analog Converters
– Windowed watchdog timer module (DACs)
– Missing clock detection circuitry • Digital glitch filters
– Dual-clock Comparator (DCC) • Low DAC output to pin capability on
• 3.3V I/O design CMPSS1
– Internal VREG generation allows for single- – One 12-bit buffered DAC output
supply design
– Brownout reset (BOR) circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024 www.ti.com
– Three Programmable Gain Amplifiers (PGAs) – 80-pin TQFP [PNA suffix]

• Unity gain support – 64-pin LQFP [PM suffix]
• Inverting and non-inverting gain mode – 56-pin Very Thin Quad Flatpack No-Lead
support (VQFN) [RSH suffix]
• Programmable output filtering • Temperature options:
• Enhanced control peripherals – Junction (TJ): –40°C to 150°C
– 24 ePWM channels with 12 channels that have
high-resolution capability (150ps resolution)
2 Applications
• Integrated dead-band support • Appliances
• Integrated hardware trip zones (TZs) – Air conditioner outdoor unit
– Two Enhanced Capture (eCAP) modules • Building automation
– Three Enhanced Quadrature Encoder Pulse – Door operator drive control
(eQEP) modules with support for CW/CCW • Industrial machine & machine tools
operation modes – Automated sorting equipment
– Embedded Pattern Generator (EPG) – Textile machine
• Configurable Logic Block (CLB) • AC inverter & VF drives
– 2 tiles – AC drive control module
– Augments existing peripheral capability – AC drive position feedback
– Supports position manager solutions – AC drive power stage module
• Neural-network Processing Unit (NPU) • Linear motor transport systems
– Highly Optimized for Deep Convolutional – Linear motor power stage
Neural Networks (CNN) • Single & multi axis servo drives
– Variable weights and data lengths
– Servo drive position feedback
• 8-bit and 4-bit weights – Servo drive power stage module
• 8-bit and 4-bit data • Speed controlled BLDC drives
– 600MOPS (Mega Operations Per Second) at
– AC-input BLDC motor drive
75MHz on 8bWx8bD
– DC-input BLDC motor drive
– 1200MOPS at 75MHz on 4bWx8bD
• Factory automation
– Up to 10x NN inferencing performance
– Robot servo drive
improvement vs SW techniques
– Mobile robot motor control
– No direct coding required, TI AI tools generate
– Position sensor
FW libraries
• Industrial power
– Real-time control focused Edge AI Models
– Industrial AC-DC
• ARC fault example
• UPS
• Motor fault example
• Live Firmware Update (LFU) – Three-phase UPS
• Diagnostic features – Single-phase online UPS
• Telecom & server power
– Memory Power-On Self-Test (MPOST)
• Functional Safety-Compliant targeted – Merchant DC/DC
– Merchant network & server PSU
– Developed for functional safety applications
– Merchant telecom rectifiers
– Documentation available to aid ISO 26262 and
• Hybrids, electric & powertrain systems
IEC 61508 system design
– Systematic capability up to ASIL D and SIL 3 – DC/DC converter
targeted – Inverter & motor control
– Hardware integrity up to ASIL B targeted – On-board (OBC) & wireless charger
• Safety-related certification – Virtual engine sound system (VESS)
– Engine fan
– ISO 26262 certification up to ASIL B by TÜV
– eTurbo/charger
SÜD planned
– Pump
• Package options:
– Electric power steering (EPS)
– 128-pin Thin Quad Flatpack (TQFP)
• Infotainment and cluster
[PDT suffix]
– Head-up display
– 100-pin Low-profile Quad Flatpack (LQFP)
– Automotive head unit
[PZ suffix]
– Automotive external amplifier
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TMS320F28P550SJ TMS320F28P559SJ-Q1

www.ti.com SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024
• Body electronics & lighting • Renewable energy storage

– Automotive HVAC compressor module – Energy storage power conversion system
– DC/AC inverter (PCS)
– Headlight – Portable Power Station
• ADAS • Solar energy
– Mechanically scanning LIDAR – Central inverter
• EV charging infrastructure – Micro inverter
– AC charging (pile) station – Solar power optimizer
– DC charging (pile) station – Solar arc protection
– EV charging station power module – Rapid shutdown
– Wireless EV charging station – String inverter
3 Description
The TMS320F28P55x (F28P55x) is a member of the C2000™ real-time microcontroller family of scalable,
ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power
density, high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
• Motor drives
• Appliances
• Hybrid, electric & powertrain systems
• Solar & EV charging
• Digital power
• Body electronics & lighting
• Test & measurement
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 150MHz of signal-
processing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The
C28x CPU is further boosted by the Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and VCRC
(Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control
systems.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent
32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The Neural-network Processing Unit (NPU) can support machine-learning inferencing using pre-trained models.
Capable of 600–1200MOPS (Mega Operations Per Second) with model support for ARC fault detection or
Motor Fault detection, the NPU provides up to 10x NN inferencing cycle improvement versus a SW-only-based
implementation. Load and train models with the Model Composer GUI from TI or with the Tiny ML Modelmaker
for an advanced set of capabilities. Source code for the C28x is generated by these tools, no manual coding is
necessary. For customers who rely on their own AI training framework, TI's Neural Network Compiler can help
port your AI model to be compatible with many C28x-based MCUs. For those interested in reference solutions,
request access to TI's Arc Fault Detection Project or the Motor Bearing Fault Detection Project.
The F28P55x supports up to 1088KB of flash memory divided into four 256KB banks plus one 64KB bank, which
enable programming one bank and execution in another bank in parallel. Up to 133KB of on-chip SRAM is also
available to supplement the flash memory.
The Live Firmware Update hardware enhancements on F28P55x allow fast context switching from the old
firmware to the new firmware to minimize application downtime when updating the device firmware.
High-performance analog blocks are integrated on the F28P55x real-time microcontroller (MCU) and are closely
coupled with the processing and PWM units to provide optimal real-time signal chain performance. Twenty-four
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

PWM channels, all supporting frequency-independent resolution modes, enable control of various power stages
from a 3-phase inverter to power factor correction and advanced multilevel power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,
LIN, and CAN FD) and offers multiple pin-muxing options for optimal signal placement.
Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control
system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the
C2000™ real-time control MCUs page.
The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all
aspects of development with C2000 devices from hardware to support resources. In addition to key reference
documents, each section provides relevant links and resources to further expand on the information covered.
Ready to get started? Check out the TMDSCNCD28P55X evaluation board or the LAUNCHXL-F28P55X
development kit, and download C2000Ware.
Package Information
PART NUMBER(1) PACKAGE(2) PACKAGE SIZE(3)
PDT (QFP, 128) 16mm x 16mm
PZ (QFP, 100) 16mm x 16mm
TMS320F28P559SJ-Q1(4)
PNA (QFP, 80) 12mm x 12mm
PM (QFP, 64) 12mm x 12mm
TMS320F28P550SJ PNA (QFP, 80) 12mm x 12mm
RSH (VQFN, 56) 7mm x 7mm
TMS320F28P559SG-Q1(4)
PNA (QFP, 80) 12mm x 12mm
TMS320F28P550SG(4) PNA (QFP, 80) 12mm x 12mm
RSH (VQFN, 56) 7mm x 7mm
(1) For more information on these devices, see the Device Comparison table.
(2) For more information, see the Mechanical, Packaging and Orderable Information section.
(3) Package size (length x width) is a nominal value and includes pins, where applicable
(4) Preview information (not Production Data).

3.1 Functional Block Diagram
C28x CPU
(150 MHz)
FPU32 CLA
Boot ROM
TMU (150 MHz)
VCRC
Secure ROM
Flash Bank0
128 Sectors, 256KB CLA to CPU MSG RAM
SYSTEM CONTROL
CPU Timers
XTAL Flash Bank1 CPU to CLA MSG RAM
INTOSC1, INTOSC2 128 Sectors, 256KB
PLL
ePIE
Windowed WD Flash Bank2 CLA Data ROM
NMI WD 128 Sectors, 256KB
CLA Program ROM
Flash Bank3
128 Sectors, 256KB
SECURITY
JTAG Lock Flash Bank4 CLA to DMA MSG RAM
Secure Boot 32 Sectors, 64 KB
DMA to CLA MSG RAM
M0-M1 RAM
4KB
DIAGNOSTICS Buses Legend
DCC
MPOST LS0-LS9 RAM CPU
ERAD 64KB
NPU CLA
JTAG/cJTAG
DMA
GS0-GS3 RAM NPU

64KB DMA
OTHERS
EPG 6 Channels Secure Memories Shown in Red
PF1 PF3 PF4 PF2 PF7 PF8 PF9 PF10 PF11 PF12
Result Data 1x PMBUS 2x CAN FD 1x LIN 3x SCI 2x CLB 1x USB 1x AES LFU
24x ePWM Channels
4x CMPSS NPU 2x I2C
(12Ch Hi-Res Capable) 5x 12-Bit ADC 65x GPIO 2x SPI
1x FSI RX
Input XBAR
2x eCAP 1x Buffered DAC 1x FSI TX
Output XBAR
ePWM XBAR
3x eQEP CLB XBAR
3x PGA
(CW/CCW Support)
CLB Input XBAR
CLB Output XBAR
A. The internal DAC from one of the CMPSS modules can be configured as an output DAC.
B. The LIN module can also be used as a SCI module.
Figure 3-1. Functional Block Diagram

Table of Contents
1 Features............................................................................1 6.17 Communications Peripherals................................ 179
2 Applications..................................................................... 2 7 Detailed Description....................................................212
3 Description.......................................................................3 7.1 Overview................................................................. 212
3.1 Functional Block Diagram........................................... 5 7.2 Functional Block Diagram....................................... 213
4 Device Comparison......................................................... 7 7.3 Memory................................................................... 214
4.1 Related Products........................................................ 9 7.4 Identification............................................................225
5 Pin Configuration and Functions.................................10 7.5 Bus Architecture – Peripheral Connectivity.............226
5.1 Pin Diagrams............................................................ 10 7.6 C28x Processor...................................................... 227
5.2 Pin Attributes.............................................................15 7.7 Control Law Accelerator (CLA)............................... 229
5.3 Signal Descriptions................................................... 40 7.8 Embedded Real-Time Analysis and Diagnostic
5.4 Pin Multiplexing.........................................................52 (ERAD)...................................................................... 231
5.5 Pins With Internal Pullup and Pulldown.................... 64 7.9 Direct Memory Access (DMA).................................232
5.6 Connections for Unused Pins................................... 65 7.10 Device Boot Modes...............................................233
6 Specifications................................................................ 67 7.11 Security................................................................. 240
6.1 Absolute Maximum Ratings...................................... 67 7.12 Watchdog.............................................................. 241
6.2 ESD Ratings – Commercial...................................... 68 7.13 C28x Timers..........................................................242
6.3 ESD Ratings – Automotive....................................... 69 7.14 Dual-Clock Comparator (DCC)............................. 243
6.4 Recommended Operating Conditions.......................70 7.15 Configurable Logic Block (CLB)............................244
6.5 Power Consumption Summary................................. 71 8 Reference Design........................................................ 246
6.6 Electrical Characteristics...........................................76 9 Device and Documentation Support..........................248
6.7 Special Considerations for 5V Fail-Safe Pins........... 78 9.1 Device Nomenclature..............................................248
6.8 Thermal Resistance Characteristics for PDT 9.2 Markings................................................................. 249
Package...................................................................... 79 9.3 Tools and Software................................................. 252
6.9 Thermal Resistance Characteristics for PZ 9.4 Documentation Support.......................................... 253
Package...................................................................... 79 9.5 Support Resources................................................. 255
6.10 Thermal Resistance Characteristics for PNA 9.6 Trademarks............................................................. 255
Package...................................................................... 79 9.7 Electrostatic Discharge Caution..............................255
6.11 Thermal Resistance Characteristics for PM 9.8 Glossary..................................................................255
Package...................................................................... 80 10 Revision History........................................................ 256
6.12 Thermal Resistance Characteristics for RSH 11 Mechanical, Packaging, and Orderable
Package...................................................................... 80 Information.................................................................. 259
6.13 Thermal Design Considerations..............................80 11.1 Package Option Addendum.................................. 260
6.14 System.................................................................... 81 TAPE AND REEL INFORMATION................................ 262
6.15 Analog Peripherals................................................124 TRAY.............................................................................264
6.16 Control Peripherals............................................... 168

4 Device Comparison
Table 4-1. Device Comparison
FEATURE(1) (4) F28P559SJ-Q1(3) (6) F28P550SJ F28P559SG-Q1(3) (6) F28P550SG(6)
C28x Subsystem
Frequency (MHz) 150
32-bit Floating-Point Unit (FPU) Yes
C28x VCRC Yes
TMU - Type 1 Yes - Type 1 - NLPID Instruction Supported
1: F28P559SJ9-Q1, 1: F28P559SG9-Q1,
Number F28P559SJ6-Q1 1 F28P559SG8-Q1 1
CLA - Type 2 0: F28P559SJ2-Q1 0: F28P559SG2-Q1
Frequency (MHz) 150
6-Channel DMA - Type 0 1
External Interrupts 5
MIPS 300 (CPU + CLA)
Memory
Main Array 1MB (4 x 256KB Banks) 512KB (2 x 256KB Banks)
F28P559SJ9-Q1, F28P550SJ9, F28P559SJ6-Q1, F28P550SJ6, F28P559SG9-Q1,
Flash 64KB Bank
F28P550SG9
User OTP 8KB 2KB
Dedicated 4KB
Local Shared RAM 64KB
RAM Message 1KB
Global Shared RAM 64KB 32KB
Total RAM 133KB 101KB
C28x CPUs and CLAs 512 bytes (256 bytes per direction)
Message RAM Types
DMAs and CLAs 512 bytes (256 bytes per direction)
ECC FLASH, Mx RAM
Parity ROM, CAN RAM, Message RAM, LSx RAM, GSx RAM
System
2 tiles - F28P559SJ9-Q1, F28P559SJ6-Q1, F28P550SJ9, F28P550SJ6, F28P559SG9-Q1,
Configurable Logic Block (CLB)
F28P550SG9, F28P559SG8-Q1, F28P550SG8
Neural-Network Processing Unit (NPU) 1 - F28P559SJ9-Q1, F28P550SJ9, F28P559SG9-Q1, F28P550SG9
Embedded Pattern Generator (EPG) 1
32-bit CPU Timers 3
Advanced Encryption Standard (AES) Accelerator 1
Live Firmware Update (LFU) Support Yes, with enhancements and flash bank erase time improvements
Security for on-chip flash and RAM Yes
Zero-pin Boot Yes
Secure Boot Yes
JTAG Lock Yes
MPOST Yes
Embedded Real-time Analysis and Diagnostic (ERAD) - Type 2 1

Non-maskable Interrupt Watchdog (NMIWD) timers 1
Watchdog (WD) timers 1
Crystal oscillator/External clock input 1
Internal Oscillator (Optional External Precision Resistor) 2

Table 4-1. Device Comparison (continued)

Digital and Analog Pin Counts
128-pin PDT 65 65 - F28P559SG9-Q1, F28P550SG9
100-pin PZ 43
80-pin PNA 32
GPIO
64-pin PM 17
56-pin RSH - 15 - 15
Additional GPIO 4 (2 from cJTAG and 2 from X1/X2)
100-pin PZ 16
AIO (analog with digital inputs) 80-pin PNA 12
64-pin PM 12
56-pin RSH - 12 - 12
100-pin PZ 19
AGPIO (analog with digital inputs and outputs) 80-pin PNA 16
64-pin PM 16
56-pin RSH - 14 - 14
C28x Analog Peripherals(5)
Number of ADCs 5
MSPS 3.9
Analog-to-Digital Converter (ADC) (12-bit) - Type 6
Conversion Time
187
(ns)(2)
100-pin PZ 35
ADC Input channels (single-ended) (includes the two DAC
80-pin PNA 28
outputs)
64-pin PM 28
56-pin RSH 26 26
PGA - Type 2 3
Temperature Sensor 1
Comparator subsystem (CMPSS) (each CMPSS has two comparators and two internal
4
DACs) - Type 6
Buffered Digital-to-Analog Converter (DAC) - Type 2 1
DAC Out from CMPSS 1
C28x Control Peripherals(5)
eCAP - Type 2 Total inputs 2
24 - F28P559SJ9-Q1, 24 - F28P559SG9-Q1,
F28P559SJ6-Q1 F28P559SG8-Q1
Total channels 24 24
16 - F28P559J2-Q1 16 - F28P559SG2-Q1
(ePWM1-ePWM8) (ePWM1-ePWM8)
ePWM/HRPWM - Type 4
12- F28P559SJ9-Q1, 12 - F28P559SG9-Q1,
F28P559SJ6-Q1 F28P559SG8-Q1
Channels with high-resolution capability 12 12
8 - F28P559SJ2-Q1 8 - F28P559SG2-Q1
(HRPWM1-HRPWM4) (HRPWM1-HRPWM4)
eQEP modules - Type 2 3
C28x Communications Peripherals(5)
CAN with Flexible Data-Rate (CAN-FD) - Type 2 2
Fast Serial Interface (FSI) RX - Type 2 1
Fast Serial Interface (FSI) TX - Type 2 1
Inter-Integrated Circuit (I2C) - Type 2 2
Local Interconnect Network (LIN) - Type 1 1
Power Management Bus (PMBus) - Type 1 1
Serial Communications Interface (SCI) - Type 0 (UART-compatible) 3
Serial Peripheral Interface (SPI) - Type 2 2
1 - F28P559SJ9-Q1, F28P550SJ9,
Universal Serial Bus (USB) - Type 0 1 - F28P559SG9-Q1, F28P550SG9
F28P559SJ6-Q1, F28P550SJ6

Table 4-1. Device Comparison (continued)

Temperature and Qualification
Junction temperature (TJ) -40°C to 150°C
Free-Air temperature (TA) -40°C to 125°C
F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
128-pin PDT
F28P559SG9-Q1, F28P550SG9
100-pin PZ
F28P559SG9-Q1, F28P559SG8-Q1, F28P559SG2-Q1, F28P550SG9, F28P550SG8
Package Options 80-pin PNA
64-pin PM
F28P550SJ9, F28P550SG9,
56-pin RSH - -
F28P550SJ6 F28P550SG8
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) The suffix -Q1 refers to AEC Q100 qualification for automotive applications.
(4) "-" on the feature entry indicates that the corresponding package type in not available.
(5) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number.
(6) Preview information (not Production Data).
4.1 Related Products
TMS320F280013x Real-Time Microcontrollers
The F280013x has common pinouts with the F28P55x series of devices. The F28P55x series adds CLA and
DMA support, in addition to faster CPU clock speed and increased memory size. Additionally the F28P55x has
Programmable Gain Amplifiers(PGA), USB, CLB and supports live FW update.
The F280015x has common pinouts with the F28P55x series of devices. The F28P55x series adds CLA and
DMA support, in addition to faster CPU clock speed and increased memory size. Additionally the F28P55x
has Programmable Gain Amplifiers(PGA), USB, CLB and supports live FW update. The F280015x series has
lockstep C28x CPUs for safety related systems.
The F28003x has common pinouts with the F28P55x series of devices. The F28P55x series has a faster overall
CPU clock and increased memory options in addition to Programmable Gain Amplifiers(PGA) and USB support.
The F28003x series offers SDFM support, along with BGCRC and HWBIST.

5 Pin Configuration and Functions

5.1 Pin Diagrams
Figure 5-1 shows the pin assignments on the 128-pin PDT thin quad flatpack. Figure 5-2 shows the pin
assignments on the 100-pin PZ low-profile quad flatpack. Figure 5-3 shows the pin assignments on the 80-pin
PNA thin quad flatpack. Figure 5-4 shows the pin assignments on the 64-pin PM low-profile quad flatpack.
Figure 5-5 shows the pin assignments on the 56-pin RSH very thin quad flatpack no-lead.
GPIO31
GPIO30
GPIO14
GPIO15
GPIO34
GPIO10
GPIO59
GPIO61
GPIO81
GPIO80
GPIO79
GPIO78
GPIO77
GPIO76
GPIO75
GPIO45
GPIO44
GPIO22
GPIO41
GPIO23
GPIO40
VDDIO
GPIO6
GPIO9
GPIO5
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
VDD
VSS
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
GPIO29 1 96 GPIO4
A16,B16,C16,GPIO28 2 95 GPIO8
XRSn 3 94 GPIO42
GPIO46 4 93 VREGENZ
VDDIO 5 92 VSS
VDD 6 91 GPIO43
VSS 7 90 VDD
GPIO47 8 89 VDDIO
GPIO66 9 88 GPIO19,X1
GPIO48 11 86 GPIO74
GPIO49 12 85 GPIO73
GPIO50 13 84 GPIO72
GPIO51 14 83 GPIO71
GPIO52 15 82 GPIO58
GPIO53 16 81 GPIO57
GPIO54 17 80 GPIO56
A6,D14,E14,GPIO228 18 79 GPIO32
B2,C6,E12,GPIO226 19 78 GPIO35/TDI
A3,B3,C5,GPIO242,PGA2_INP 20 77 TMS
A2,B6,C9,GPIO224,PGA1_INP 21 76 GPIO37/TDO
A15,B9,C7,PGA1_INM 22 75 TCK
C25,D5,E5 23 74 GPIO70
A26,D6,E6 24 73 GPIO69
B26,D7,E7 25 72 GPIO68
A14,B14,C4,PGA1_OUT 26 71 GPIO27
A5,B12,C2,PGA2_INM 28 69 GPIO25
A1,B7,CMP1_DACL,D11 29 68 B25,D4,E4,GPIO24
A0,B15,C15,DACA_OUT 30 67 A25,D3,E3,GPIO17
D20,E20,VREFHI 31 66 C24,D2,E2,GPIO16
D20,E20,VREFHI 32 65 B24,D1,E1,GPIO33
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Not to scale
A13,B13,C13,D13,E13,VREFLO
A12,C1,E11,PGA3_INP
B11,D16,E16,PGA3_INM
A7,B30,C3,D12,E30
B5,D15,E15,PGA3_OUT
A8,B0,C11
VSSA
VDDA
A4,B8,C14
C26,D8,E8,GPIO211
A27,D9,E9,GPIO212
B27,D10,E10,GPIO213
C27,D18,E18,GPIO214
A28,D19,E19,GPIO215
A9,GPIO227
B4,C8,GPIO236
A10,B1,C10,GPIO230
GPIO55
GPIO60
VSS
VDD
VDDIO
GPIO64
GPIO65
GPIO62
GPIO63
A17,B17,C17,GPIO20
A18,B18,C18,GPIO21
A19,B19,C19,GPIO13
A20,B20,C20,GPIO12
A24,D0,E0,GPIO11
A. Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.
Figure 5-1. 128-pin PDT Thin Quad Flatpack (Top View)

GPIO29
GPIO31
GPIO30
GPIO14
GPIO15
GPIO34
GPIO10
GPIO59
GPIO61
GPIO44
GPIO22
GPIO41
GPIO23
GPIO40
VDDIO
GPIO6
GPIO9
GPIO5
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
VDD
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A16,B16,C16,GPIO28 1 75 GPIO4
XRSn 2 74 GPIO8
VDDIO 3 73 VREGENZ
VDD 4 72 VSS
VSS 5 71 VDD
GPIO47 6 70 VDDIO
GPIO50 9 67 GPIO58
GPIO51 10 66 GPIO57
GPIO52 11 65 GPIO56
GPIO53 12 64 GPIO32
GPIO54 13 63 GPIO35/TDI
A6,D14,E14,GPIO228 14 62 TMS
B2,C6,E12,GPIO226 15 61 GPIO37/TDO
B3,GPIO242,PGA2_INP 16 60 TCK
A2,B6,C9,GPIO224,PGA1_INP 17 59 GPIO27
A11,B10,C0,PGA2_OUT 20 56 B25,D4,E4,GPIO24
B12,C2,PGA2_INM 21 55 A25,D3,E3,GPIO17
A1,B7,CMP1_DACL,D11 22 54 C24,D2,E2,GPIO16
A0,B15,C15,DACA_OUT 23 53 B24,D1,E1,GPIO33
D20,E20,VREFHI 24 52 A24,D0,E0,GPIO11
D20,E20,VREFHI 25 51 A20,B20,C20,GPIO12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Not to scale
A12,C5
C1,E11,PGA3_INP
B11,D16,E16,PGA3_INM
A7,B30,C3,D12,E30
B5,D15,E15,PGA3_OUT
VSSA
VDDA
A5
A4,B8
A8
A9,GPIO227
B4,C8,GPIO236
A10,B1,C10,GPIO230
B0,C11,GPIO253
C14,GPIO247
GPIO55
GPIO60
VSS
GPIO62
GPIO63
A17,B17,C17,GPIO20
A18,B18,C18,GPIO21
A19,B19,C19,GPIO13
Figure 5-2. 100-Pin PZ Low-Profile Quad Flatpack (Top View)

GPIO14
GPIO15
GPIO34
GPIO10
GPIO45
GPIO44
GPIO22
GPIO41
GPIO23
GPIO40
VDDIO
GPIO6
GPIO9
GPIO5
GPIO7
GPIO0
GPIO1
GPIO2
VDD
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
GPIO30 1 60 GPIO3
GPIO31 2 59 GPIO4
GPIO29 3 58 GPIO8
A16,B16,C16,GPIO28 4 57 GPIO42
XRSn 5 56 VREGENZ
GPIO46 6 55 VSS
VDDIO 7 54 GPIO43
VDD 8 53 VDD
VSS 9 52 VDDIO
A6,D14,E14,GPIO228 10 51 GPIO19,X1
B2,C6,E12,GPIO226 11 50 GPIO18,X2
A2,B6,C9,GPIO224,PGA1_INP 13 48 GPIO35/TDI
A15,B9,C7,PGA1_INM 14 47 TMS
A14,B14,C4,PGA1_OUT 15 46 GPIO37/TDO
A11,B10,C0,PGA2_OUT 16 45 TCK
A1,B7,CMP1_DACL,D11 18 43 GPIO26
A0,B15,C15,DACA_OUT 19 42 GPIO25
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Not to scale
A12,C1,E11,PGA3_INP
A7,B30,C3,D12,E30,PGA3_INM
A8,B0,C11,PGA3_OUT
VSSA
VDDA
A4,B8,C14
A9,B4,C8,GPIO227,GPIO236
A10,B1,C10,GPIO230
VSS
GPIO62
GPIO63
A17,B17,C17,GPIO20
A18,B18,C18,GPIO21
A19,B19,C19,GPIO13
A20,B20,C20,GPIO12
A24,D0,E0,GPIO11
B24,D1,E1,GPIO33
C24,D2,E2,GPIO16
A25,D3,E3,GPIO17
Figure 5-3. 80-Pin PNA Thin Quad Flatpack (Top View)

GPIO10
GPIO22
GPIO41
GPIO23
GPIO40
VDDIO
GPIO6
GPIO9
GPIO5
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
GPIO29 1 48 GPIO4
A16,B16,C16,GPIO28 2 47 GPIO8
XRSn 3 46 VREGENZ
VDD 4 45 VSS
VSS 5 44 VDD
A6,D14,E14,GPIO228 6 43 VDDIO
B2,C6,E12,GPIO226 7 42 GPIO19,X1
A3,B3,C5,GPIO242,PGA2_INP 8 41 GPIO18,X2
A15,B9,C7,PGA1_INM 10 39 GPIO35/TDI
A14,B14,C4,PGA1_OUT 11 38 TMS
A5,B12,C2,PGA2_INM 13 36 TCK
A1,B7,CMP1_DACL,D11 14 35 B25,D4,E4,GPIO24
A0,B15,C15,DACA_OUT 15 34 A25,D3,E3,GPIO17
D20,E20,VREFHI 16 33 C24,D2,E2,GPIO16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Not to scale
A12,C1,E11,PGA3_INP
A8,B0,C11,PGA3_OUT
VSSA
VDDA
A4,B8,C14
A10,B1,C10,GPIO230
VSS
A17,B17,C17,GPIO20
A18,B18,C18,GPIO21
A19,B19,C19,GPIO13
A20,B20,C20,GPIO12
A24,D0,E0,GPIO11
B24,D1,E1,GPIO33
Figure 5-4. 64-Pin PM Low-Profile Quad Flatpack (Top View)

GPIO22
GPIO41
GPIO23
GPIO40
VDDIO
GPIO9
GPIO5
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
VDD
56
55
54
53
52
51
50
49
48
47
46
45
44
43
GPIO6 1 42 VREGENZ
GPIO29 2 41 VDD
A16,B16,C16,GPIO28 3 40 VDDIO
XRSn 4 39 GPIO19,X1
VDD 5 38 GPIO18,X2
A2,B6,C9,GPIO224,PGA1_INP 7 36 GPIO35/TDI
VSS
A15,B9,C7,PGA1_INM 8 35 TMS
A11,B10,C0,PGA2_OUT 10 33 TCK
A5,B12,C2,PGA2_INM 11 32 B25,D4,E4,GPIO24
A1,B7,CMP1_DACL,D11 12 31 A25,D3,E3,GPIO17
A0,B15,C15,DACA_OUT 13 30 C24,D2,E2,GPIO16
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A12,C1,E11,PGA3_INP
A8,B0,C11,PGA3_OUT
VSSA
VDDA
A4,B8,C14
A10,B1,C10,GPIO230
A17,B17,C17,GPIO20
A18,B18,C18,GPIO21
A19,B19,C19,GPIO13
A20,B20,C20,GPIO12
A24,D0,E0,GPIO11
Not to scale
Figure 5-5. 56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View)

5.2 Pin Attributes

Table 5-1. Pin Attributes
128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
ANALOG
A0 I ADC-A Input 0
B15 I ADC-B Input 15
C15 I ADC-C Input 15
CMP3_HP2 30 23 19 15 13 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
DACA_OUT O Buffered DAC-A Output.
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231
A1 I ADC-A Input 1
B7 I ADC-B Input 7
CMP1_DACL I CMPSS-1 Low DAC Output
D11 I ADC-D Input 11
A2 I ADC-A Input 2
B6 I ADC-B Input 6
C9 I ADC-C Input 9
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
21 17 13 9 7
General-Purpose Input Output 224 This pin also has
GPIO224 I/O digital mux functions which are described in the GPIO
section of this table.
PGA1_INP I PGA-1 Plus
A3 I ADC-A Input 3
18
A3 I ADC-A Input 3
CMP3_HP5 20 12 8 6 I CMPSS-3 High Comparator Positive Input 5
A4 I ADC-A Input 4
B8 I ADC-B Input 8
A5 I ADC-A Input 5
35
A5 I ADC-A Input 5

Table 5-1. Pin Attributes (continued)

128 100 64 PIN
PDT PZ PM TYPE
A6 I ADC-A Input 6
D14 18 14 10 6 I ADC-D Input 14
E14 I ADC-E Input 14
A7 I ADC-A Input 7
C3 I ADC-C Input 3
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
37 31 23 19 17
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
A8 I ADC-A Input 8
37
A8 I ADC-A Input 8
B0 I ADC-B Input 0
39 24 20 18
A9 I ADC-A Input 9
CMP2_LP2 48 38 28 24 22 I CMPSS-2 Low Comparator Positive Input 2
A10 I ADC-A Input 10
B1 I ADC-B Input 1


128 100 64 PIN
PDT PZ PM TYPE
C0 I ADC-C Input 0
PGA2_OUT O PGA-2 Output
35 28 22 18 16
D13 34 26 21 17 15 I ADC-D Input 13
VREFLO(1) I ADC Low Reference
D13 33, 34 26, 27 21 17 15 I ADC-D Input 13
VREFLO(1) I ADC Low Reference
AIO235 ALT I Analog Pin Used For Digital Input 235
C4 I ADC-C Input 4
PGA1_OUT O PGA-1 Output
22 14 10 8
C16 2 1 4 2 3 I ADC-C Input 16


128 100 64 PIN
PDT PZ PM TYPE
C17 60 48 33 27 24 I ADC-C Input 17
C18 61 49 34 28 25 I ADC-C Input 18
C19 62 50 35 29 26 I ADC-C Input 19
C20 63 51 36 30 27 I ADC-C Input 20
D0 I ADC-D Input 0
E0 64 52 37 31 28 I ADC-E Input 0
D3 I ADC-D Input 3
E3 67 55 40 34 31 I ADC-E Input 3
D6 I ADC-D Input 6
24
E6 I ADC-E Input 6
AIO227 I Analog Pin Used For Digital Input 227
44
D9 I ADC-D Input 9
E9 I ADC-E Input 9
47
B0 I ADC-B Input 0
41


128 100 64 PIN
PDT PZ PM TYPE
B2 I ADC-B Input 2
C6 I ADC-C Input 6
CMP3_LP0 19 15 11 7 I CMPSS-3 Low Comparator Positive Input 0
B3 I ADC-B Input 3
20 16 12 8 6
B4 I ADC-B Input 4
C8 I ADC-C Input 8
49 39 28 24 22
GPIO236 0, 4, 8, 12 I/O digital mux functions which are described in the GPIO
B5 I ADC-B Input 5
38 32
B9 I ADC-B Input 9
C7 22 18 14 10 8 I ADC-C Input 7
PGA1_INM I PGA-1 Minus
36 30
C2 I ADC-C Input 2
28 21 17 13 11
PGA2_INM I PGA-2 Minus
D1 I ADC-D Input 1
E1 65 53 38 32 29 I ADC-E Input 1


128 100 64 PIN
PDT PZ PM TYPE
D4 I ADC-D Input 4
E4 68 56 41 35 32 I ADC-E Input 4
D7 I ADC-D Input 7
25
E7 I ADC-E Input 7
45
C1 I ADC-C Input 1
35 29 22 18 16
C5 20 28 12 8 6 I ADC-C Input 5
CMP4_LN0 42 I CMPSS-4 Low Comparator Negative Input 0
D2 I ADC-D Input 2
E2 66 54 39 33 30 I ADC-E Input 2
D5 23 I ADC-D Input 5
E5 I ADC-E Input 5
43
D8 I ADC-D Input 8
E8 I ADC-E Input 8


128 100 64 PIN
PDT PZ PM TYPE
46
ADC High Reference. In external reference mode,
externally drive the high reference voltage onto this
31 24 20 16 14 pin. In internal reference mode, a voltage is driven
VREFHI(2) I onto this pin by the device. In either mode, place at
least a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
between the VREFHI and VREFLO pins.
ADC High Reference. In external reference mode,
externally drive the high reference voltage onto this
32 25 20 16 14 pin. In internal reference mode, a voltage is driven
VREFHI(2) I onto this pin by the device. In either mode, place at
least a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
AIO234 ALT I Analog Pin Used For Digital Input 234
PGA3_INM 36 30 23 19 17 I PGA-3 Minus
PGA3_OUT 38 32 24 20 18 O PGA-3 Output
GPIO
GPIO236 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
EPWM7_A 1 49 39 28 24 22 O ePWM-7 Output A
EQEP1_INDEX 5 I/O eQEP-1 Index
EPWM12_A 9 O ePWM-12 Output A
GPIO0 0, 4, 8, 12 I/O General-Purpose Input Output 0
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_RX 5 I SCI-A Receive Data
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SPIA_PTE 7 100 79 63 52 47 I/O SPI-A Peripheral Transmit Enable (PTE)
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANA_RX 10 I CAN/CAN FD Receive
CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8
EPWM1_B 1 O ePWM-1 Output B
SCIA_TX 5 O SCI-A Transmit Data
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_POCI 7 I/O SPI-A Peripheral Out, Controller In (POCI)
99 78 62 51 46
EQEP1_STROBE 9 I/O eQEP-1 Strobe
MCANA_TX 10 O CAN/CAN FD Transmit


128 100 64 PIN
PDT PZ PM TYPE
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
SCIA_TX 9 98 77 61 50 45 O SCI-A Transmit Data
FSIRXA_D1 10 I FSIRX-A Optional Additional Data Input
I2CB_SDA 11 I/OD I2C-B Open-Drain Bidirectional Data
MCANB_TX 14 O CAN/CAN FD Transmit
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIA_CLK 7 I/O SPI-A Clock
97 76 60 49 44
FSIRXA_D0 10 I FSIRX-A Primary Data Input
I2CB_SCL 11 I/OD I2C-B Open-Drain Bidirectional Clock
MCANB_RX 14 I CAN/CAN FD Receive
SPIB_CLK 7 I/O SPI-B Clock
96 75 59 48 43
118 89 74 61 55
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSITXA_D1 9 O FSITX-A Optional Additional Data Output


128 100 64 PIN
PDT PZ PM TYPE
SYNCOUT 3 O External ePWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
126 97 80 64 1
SPIB_POCI 7 I/O SPI-B Peripheral Out, Controller In (POCI)
FSITXA_D0 9 O FSITX-A Primary Data Output
EQEP1_B 5 I eQEP-1 Input B
SPIB_PICO 7 105 84 68 57 52 I/O SPI-B Peripheral In, Controller Out (PICO)
FSITXA_CLK 9 O FSITX-A Output Clock
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
95 74 58 47
SCIB_TX 2 O SCI-B Transmit Data
SPIA_CLK 7 119 90 75 62 56 I/O SPI-A Clock
LINA_RX 11 I LIN-A Receive


128 100 64 PIN
PDT PZ PM TYPE
ADCSOCBO 3 O ADC Start of Conversion B for External ADC
SPIA_POCI 7 122 93 76 63 I/O SPI-A Peripheral Out, Controller In (POCI)
LINA_TX 11 O LIN-A Transmit
SCIB_RX 6 64 52 37 31 28 I SCI-B Receive Data
63 51 36 30 27
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 7 I/O
Output
62 50 35 29 26
SCIB_RX 6 I SCI-B Receive Data
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert Signal


128 100 64 PIN
PDT PZ PM TYPE
PMBUSA_SDA 7 125 96 79 I/OD PMBus-A Open-Drain Bidirectional Data
PMBUSA_SCL 7 124 95 78 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIB_PTE 9 I/O SPI-B Peripheral Transmit Enable (PTE)
EQEP1_STROBE 9 66 54 39 33 30 I/O eQEP-1 Strobe
External Clock Output. This pin outputs a divided-
XCLKOUT 11 O down version of a chosen clock signal from within the
device.
67 55 40 34 31


128 100 64 PIN
PDT PZ PM TYPE
87 68 50 41 38
PMBUSA_CTL 10 I/O
Output
device.
X2 ALT I/O Crystal oscillator output.
88 69 51 42 39
Crystal oscillator input or single-ended clock input. The
device initialization software must configure this pin
before the crystal oscillator is enabled. To use this
X1 ALT I/O
oscillator, a quartz crystal circuit must be connected
to X1 and X2. This pin can also be used to feed a
single-ended 3.3-V level clock.
SPIB_PICO 6 60 48 33 27 24 I/O SPI-B Peripheral In, Controller Out (PICO)
ADCE_EXTMUXSEL0 10 O ADCE external mux selection pin for position 0
SCIC_TX 15 O SCI-C Transmit Data
SPIB_POCI 6 61 49 34 28 25 I/O SPI-B Peripheral Out, Controller In (POCI)
SCIC_RX 15 I SCI-C Receive Data


128 100 64 PIN
PDT PZ PM TYPE
104 83 67 56 51
LINA_TX 9, 11 O LIN-A Transmit
LINA_RX 9, 11 102 81 65 54 49 I LIN-A Receive
USB0DM ALT O USB-0 PHY differential data
68 56 41 35 32
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
Error Status Output. This signal requires an external
ERRORSTS 13 O
pulldown.
SPIB_POCI 6 69 57 42 I/O SPI-B Peripheral Out, Controller In (POCI)
FSITXA_D0 9 70 58 43 O FSITX-A Primary Data Output
PMBUSA_CTL 10 I/O
Output


128 100 64 PIN
PDT PZ PM TYPE
71 59 44
EQEP1_A 6 2 1 4 2 3 I eQEP-1 Input A
ERRORSTS 13 O
pulldown.
1 100 3 1 2
ERRORSTS 13 O
pulldown.
AUXCLKIN ALT I Auxiliary Clock Input
127 98 1
EQEP1_INDEX 6 128 99 2 I/O eQEP-1 Index


128 100 64 PIN
PDT PZ PM TYPE
79 64 49 40 37
LINA_RX 6 65 53 38 32 29 I LIN-A Receive
123 94 77
78 63 48 39 36
PMBUSA_CTL 10 I/O
Output
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled by
TDI 15 I default. The internal pullup should be enabled or an
external pullup added on the board if this pin is used
as JTAG TDI to avoid a floating input.


128 100 64 PIN
PDT PZ PM TYPE
EQEP1_B 9 76 61 46 37 34 I eQEP-1 Input B
JTAG Test Data Output (TDO) - TDO is the default
mux selection for the pin. The internal pullup is
disabled by default. The TDO function will be in a tri-
TDO 15 O state condition when there is no JTAG activity, leaving
this pin floating; the internal pullup should be enabled
or an external pullup added on the board to avoid a
floating GPIO input.
101 80 64 53 48
SCIB_RX 9 103 82 66 55 50 I SCI-B Receive Data
USB0DP ALT O USB-0 PHY differential data
PMBUSA_CTL 5 I/O
94 57 Output


128 100 64 PIN
PDT PZ PM TYPE
PMBUSA_ALERT 5, 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 6 91 54 I/OD I2C-A Open-Drain Bidirectional Clock
106 85 69
PMBUSA_CTL 9 I/O
Output
FSITXA_D0 7 110 73 O FSITX-A Primary Data Output
MCANA_TX 5 4 6 O CAN/CAN FD Transmit
MCANA_RX 5 8 6 I CAN/CAN FD Receive
12 8
13 9


128 100 64 PIN
PDT PZ PM TYPE
14 10
15 11
SYNCOUT 9 O External ePWM Synchronization Pulse
SPIB_PTE 6 16 12 I/O SPI-B Peripheral Transmit Enable (PTE)
OUTPUTXBAR2 6 17 13 O Output X-BAR Output 2
ERRORSTS 9 O
pulldown.
80 65


128 100 64 PIN
PDT PZ PM TYPE
81 66
LINA_TX 9 82 67 O LIN-A Transmit
121 92
58 46 31
59 47 32


128 100 64 PIN
PDT PZ PM TYPE
56
ERRORSTS 13 O
pulldown.
57
9
SCIB_RX 6 10 I SCI-B Receive Data
72
PMBUSA_CTL 7 I/O
Output


128 100 64 PIN
PDT PZ PM TYPE
73
74
EQEP1_STROBE 9 83 I/O eQEP-1 Strobe
device.
SCIA_RX 6 84 I SCI-A Receive Data


128 100 64 PIN
PDT PZ PM TYPE
85
ERRORSTS 13 O
pulldown.
86
EPWM6_A 5 111 O ePWM-6 Output A
112
SPIA_PICO 6 113 I/O SPI-A Peripheral In, Controller Out (PICO)
114


128 100 64 PIN
PDT PZ PM TYPE
MCANA_RX 5 115 I CAN/CAN FD Receive
SPIA_PTE 7 116 I/O SPI-A Peripheral Transmit Enable (PTE)
SPIB_CLK 5 117 I/O SPI-B Clock
EPWM10_B 1 44 O ePWM-10 Output B


128 100 64 PIN
PDT PZ PM TYPE
21 17 13 9 7
19 15 11 7
48 38 28 24 22
MCANA_TX 5 18 14 10 6 O CAN/CAN FD Transmit
50 40 29 25 23


128 100 64 PIN
PDT PZ PM TYPE
SPIA_PTE 6 20 16 12 8 6 I/O SPI-A Peripheral Transmit Enable (PTE)
42 section of this table.
41
TEST, JTAG, AND RESET
TCK 75 60 45 36 33 I JTAG test clock with internal pullup.
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK. This device does not have a
TMS 77 62 47 38 35 I/O TRSTn pin. An external pullup resistor (recommended
2.2 kΩ) on the TMS pin to VDDIO should be placed
on the board to keep JTAG in reset during normal
operation.
Device Reset (in) and Watchdog Reset (out). During
a power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by the
MCU when a watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for the watchdog
reset duration of 512 OSCCLK cycles. A resistor
between 2.2 kΩ and 10 kΩ should be placed between
XRSn 3 2 5 3 4 I/OD
XRSn and VDDIO. If a capacitor is placed between
XRSn and VSS for noise filtering, it should be 100
nF or smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within 512
OSCCLK cycles when the watchdog reset is asserted.
This pin is an open-drain output with an internal pullup.
If this pin is driven by an external device, it should be
done using an open-drain device.
POWER AND GROUND
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD pin with
6, 54, 4, 71, 8, 53, 4, 44, 5, 41,
VDD a minimum total capacitance of approximately 10 µF.
90, 108 87 71 59 53
It is also recommended that all VDD pins be externally
connected to each other when internal VREG is used.
3.3-V Analog Power Pins. Place a minimum 2.2-µF
VDDA 41 34 26 22 20
decoupling capacitor on each pin.
5, 55, 3, 70, 7, 52, 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
VDDIO 43, 60 40, 54
89, 109 88 72 decoupling capacitor on each pin.
Internal voltage regulator enable with internal
VREGENZ 93 73 56 46 42 I pulldown. Tie low to VSS to enable internal VREG. Tie
high to VDDIO to use an external supply.
7, 53, 5, 45, 9, 30, 5, 26,
VSS PAD Digital Ground
92, 107 72, 86 55, 70 45, 58
VSSA 40 33 25 21 19 Analog Ground
(1) On the 128-PDT package, VREFLO is assigned to pins 33 and 34; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFLO is assigned to pins 26 and 27; these pins should be tied together at the PCB level.
(2) On the 128-PDT package, VREFHI is assigned to pins 31 and 32; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFHI is assigned to pins 24 and 25; these pins should be tied together at the PCB level.

5.3 Signal Descriptions

5.3.1 Analog Signals
Table 5-2. Analog Signals
PIN
SIGNAL NAME DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
A0 I ADC-A Input 0 30 23 19 15 13
A1 I ADC-A Input 1 29 22 18 14 12
A2 I ADC-A Input 2 21 17 13 9 7
A3 I ADC-A Input 3 20 18 12 8 6
A4 I ADC-A Input 4 42 36 27 23 21
A5 I ADC-A Input 5 28 35 17 13 11
A6 I ADC-A Input 6 18 14 10 6
A7 I ADC-A Input 7 37 31 23 19 17
A8 I ADC-A Input 8 39 37 24 20 18
A9 I ADC-A Input 9 48 38 28 24 22
A10 I ADC-A Input 10 50 40 29 25 23
A11 I ADC-A Input 11 27 20 16 12 10
A12 I ADC-A Input 12 35 28 22 18 16
A13 I ADC-A Input 13 33, 34 26, 27 21 17 15
A14 I ADC-A Input 14 26 19 15 11 9
A15 I ADC-A Input 15 22 14 10 8
A16 I ADC-A Input 16 2 1 4 2 3
A17 I ADC-A Input 17 60 48 33 27 24
A18 I ADC-A Input 18 61 49 34 28 25
A19 I ADC-A Input 19 62 50 35 29 26
A20 I ADC-A Input 20 63 51 36 30 27
A24 I ADC-A Input 24 64 52 37 31 28
A25 I ADC-A Input 25 67 55 40 34 31
A26 I ADC-A Input 26 24
AIO208 I Analog Pin Used For Digital Input 208 23
AIO225 I Analog Pin Used For Digital Input 225 42 36 27 23 21
AIO233 I Analog Pin Used For Digital Input 233 22 14 10 8
AIO234 I Analog Pin Used For Digital Input 234 31, 32 24, 25 20 16 14
AIO235 I Analog Pin Used For Digital Input 235 33, 34 26, 27 21 17 15

Table 5-2. Analog Signals (continued)

PIN
TYPE
AIO241 I Analog Pin Used For Digital Input 241 39 24 20 18
AIO251 I Analog Pin Used For Digital Input 251 36 30
AIO252 I Analog Pin Used For Digital Input 252 38 32
B0 I ADC-B Input 0 39 41 24 20 18
B1 I ADC-B Input 1 50 40 29 25 23
B2 I ADC-B Input 2 19 15 11 7
B3 I ADC-B Input 3 20 16 12 8 6
B4 I ADC-B Input 4 49 39 28 24 22
B5 I ADC-B Input 5 38 32
B6 I ADC-B Input 6 21 17 13 9 7
B7 I ADC-B Input 7 29 22 18 14 12
B8 I ADC-B Input 8 42 36 27 23 21
B9 I ADC-B Input 9 22 18 14 10 8
B10 I ADC-B Input 10 27 20 16 12 10
B11 I ADC-B Input 11 36 30
B12 I ADC-B Input 12 28 21 17 13 11
B13 I ADC-B Input 13 33, 34 26, 27 21 17 15
B14 I ADC-B Input 14 26 19 15 11 9
B15 I ADC-B Input 15 30 23 19 15 13
B16 I ADC-B Input 16 2 1 4 2 3
B17 I ADC-B Input 17 60 48 33 27 24
B18 I ADC-B Input 18 61 49 34 28 25
B19 I ADC-B Input 19 62 50 35 29 26
B20 I ADC-B Input 20 63 51 36 30 27
B24 I ADC-B Input 24 65 53 38 32 29
B25 I ADC-B Input 25 68 56 41 35 32
B26 I ADC-B Input 26 25
B27 I ADC-B Input 27 45
B30 I ADC-B Input 30 37 31 23 19 17
C0 I ADC-C Input 0 27 20 16 12 10
C1 I ADC-C Input 1 35 29 22 18 16
C2 I ADC-C Input 2 28 21 17 13 11
C3 I ADC-C Input 3 37 31 23 19 17
C4 I ADC-C Input 4 26 19 15 11 9
C5 I ADC-C Input 5 20 28 12 8 6
C6 I ADC-C Input 6 19 15 11 7


PIN
TYPE
C7 I ADC-C Input 7 22 18 14 10 8
C8 I ADC-C Input 8 49 39 28 24 22
C9 I ADC-C Input 9 21 17 13 9 7
C10 I ADC-C Input 10 50 40 29 25 23
C11 I ADC-C Input 11 39 41 24 20 18
C13 I ADC-C Input 13 33, 34 26, 27 21 17 15
C14 I ADC-C Input 14 42 42 27 23 21
C15 I ADC-C Input 15 30 23 19 15 13
C16 I ADC-C Input 16 2 1 4 2 3
C17 I ADC-C Input 17 60 48 33 27 24
C18 I ADC-C Input 18 61 49 34 28 25
C19 I ADC-C Input 19 62 50 35 29 26
C20 I ADC-C Input 20 63 51 36 30 27
C24 I ADC-C Input 24 66 54 39 33 30
C25 I ADC-C Input 25 23
CMP1_DACL I CMPSS-1 Low DAC Output 29 22 18 14 12
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 22 14 10 8
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 27 20 16 12 10
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0 21 17 13 9 7
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 18 14 10 6
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 38 32
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 22 14 10 8
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 27 20 16 12 10
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0 21 17 13 9 7
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 18 14 10 6
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 38 32
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 50 40, 41 29 25 23


PIN
TYPE
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 50 40, 41 29 25 23
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5 36 30
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5 36 30
D0 I ADC-D Input 0 64 52 37 31 28
D1 I ADC-D Input 1 65 53 38 32 29
D2 I ADC-D Input 2 66 54 39 33 30
D3 I ADC-D Input 3 67 55 40 34 31
D4 I ADC-D Input 4 68 56 41 35 32
D5 I ADC-D Input 5 23


PIN
TYPE
D11 I ADC-D Input 11 29 22 18 14 12
D12 I ADC-D Input 12 37 31 23 19 17
D13 I ADC-D Input 13 33, 34 26, 27 21 17 15
D14 I ADC-D Input 14 18 14 10 6
D15 I ADC-D Input 15 38 32
D16 I ADC-D Input 16 36 30
D20 I ADC-D Input 20 31, 32 24, 25 20 16 14
DACA_OUT O Buffered DAC-A Output. 30 23 19 15 13
E0 I ADC-E Input 0 64 52 37 31 28
E1 I ADC-E Input 1 65 53 38 32 29
E2 I ADC-E Input 2 66 54 39 33 30
E3 I ADC-E Input 3 67 55 40 34 31
E4 I ADC-E Input 4 68 56 41 35 32
E5 I ADC-E Input 5 23
E11 I ADC-E Input 11 35 29 22 18 16
E12 I ADC-E Input 12 19 15 11 7
E13 I ADC-E Input 13 33, 34 26, 27 21 17 15
E14 I ADC-E Input 14 18 14 10 6
E15 I ADC-E Input 15 38 32
E16 I ADC-E Input 16 36 30
E20 I ADC-E Input 20 31, 32 24, 25 20 16 14
E30 I ADC-E Input 30 37 31 23 19 17
PGA1_INM I PGA-1 Minus 22 18 14 10 8
PGA1_INP I PGA-1 Plus 21 17 13 9 7
PGA1_OUT O PGA-1 Output 26 19 15 11 9
PGA2_INP I PGA-2 Plus 20 16 12 8 6
PGA3_INP I PGA-3 Plus 35 29 22 18 16


PIN
TYPE
ADC High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by the
VREFHI(1) I 31, 32 24, 25 20 16 14
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor should
be placed as close to the device as possible
VREFLO(2) I ADC Low Reference 33, 34 26, 27 21 17 15
(1) On the 128-PDT package, VREFHI is assigned to pins 31 and 32; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFHI is assigned to pins 24 and 25; these pins should be tied together at the PCB level.
(2) On the 128-PDT package, VREFLO is assigned to pins 33 and 34; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFLO is assigned to pins 26 and 27; these pins should be tied together at the PCB level.

5.3.2 Digital Signals

Table 5-3. Digital Signals
PIN
SIGNAL NAME DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
ADCE_EXTMUXSEL0 O ADCE external mux selection pin for position 0 20, 228 18, 60 14, 48 10, 33 6, 27 24
ADCE_EXTMUXSEL1 O ADCE external mux selection pin for position 1 21, 226 19, 61 15, 49 11, 34 7, 28 25
ADCE_EXTMUXSEL2 O ADCE external mux selection pin for position 2 242 20 16 12 8 6
ADCE_EXTMUXSEL3 O ADCE external mux selection pin for position 3 224 21 17 13 9 7
8, 33, 53, 70, 16, 18, 65, 74,
ADCSOCAO O ADC Start of Conversion A for External ADC 12, 14, 53, 74 10, 38, 58 6, 32, 47 29
74, 228 86, 95
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32, 54 17, 79, 122 13, 64, 93 49, 76 40, 63 37
AUXCLKIN I Auxiliary Clock Input 29 1 100 3 1 2
CLB_OUTPUTXBAR1 O CLB Output X-BAR Output 1 19, 22 88, 104 69, 83 51, 67 42, 56 39, 51
CLB_OUTPUTXBAR2 O CLB Output X-BAR Output 2 7, 47 8, 105 6, 84 68 57 52
CLB_OUTPUTXBAR3 O CLB Output X-BAR Output 3 23, 42, 44 94, 102, 106 81, 85 57, 65, 69 54 49
91, 101, 110,
CLB_OUTPUTXBAR4 O CLB Output X-BAR Output 4 10, 40, 43, 45 80, 93 54, 64, 73, 76 53, 63 48
122
CLB_OUTPUTXBAR5 O CLB Output X-BAR Output 5 5, 8, 52 15, 95, 118 11, 74, 89 58, 74 47, 61 55
CLB_OUTPUTXBAR6 O CLB Output X-BAR Output 6 4, 15, 53 16, 96, 124 12, 75, 95 59, 78 48 43
CLB_OUTPUTXBAR7 O CLB Output X-BAR Output 7 1, 14, 56 80, 99, 125 65, 78, 96 62, 79 51 46
81, 100, 116,
CLB_OUTPUTXBAR8 O CLB Output X-BAR Output 8 0, 6, 57, 80 66, 79, 97 63, 80 52, 64 1, 47
126
0, 4, 30, 77, 21, 96, 100,
EPWM1_A O ePWM-1 Output A 17, 75, 79, 98 1, 13, 59, 63 9, 48, 52 7, 43, 47
80, 224 113, 116, 127
1, 5, 31, 75, 19, 99, 111,
EPWM1_B O ePWM-1 Output B 15, 78, 89, 99 2, 11, 62, 74 7, 51, 61 46, 55
81, 226 117, 118, 128
2, 6, 7, 41, 79, 50, 98, 103, 40, 77, 82, 84, 29, 61, 66, 68, 25, 50, 55, 57, 1, 23, 45, 50,
EPWM2_A O ePWM-2 Output A
230 105, 115, 126 97 80 64 52
3, 7, 40, 74, 18, 48, 86, 97, 14, 38, 76, 80, 10, 28, 60, 64, 6, 24, 49, 53,
EPWM2_B O ePWM-2 Output B 22, 44, 48, 52
78, 227, 228 101, 105, 114 84 68 57
48, 72, 96,
0, 4, 14, 68,
EPWM3_A O ePWM-3 Output A 100, 114, 116, 38, 75, 79, 96 28, 59, 63, 79 24, 48, 52 22, 43, 47
78, 80, 227
125
1, 5, 15, 69, 50, 73, 99,
EPWM3_B O ePWM-3 Output B 40, 78, 89, 95 29, 62, 74, 78 25, 51, 61 23, 46, 55
79, 230 115, 118, 124
2, 6, 22, 76, 20, 98, 104,
EPWM4_A O ePWM-4 Output A 16, 77, 83, 97 12, 61, 67, 80 8, 50, 56, 64 1, 6, 45, 51
242 112, 126
83, 97, 102,
EPWM4_B O ePWM-4 Output B 3, 7, 23, 71 76, 81, 84 60, 65, 68 49, 54, 57 44, 49, 52
105
EPWM5_A O ePWM-5 Output A 8, 37, 72 76, 84, 95 61, 74 46, 58 37, 47 34
EPWM5_B O ePWM-5 Output B 9, 35, 73 78, 85, 119 63, 90 48, 75 39, 62 36, 56
10, 17, 18, 72, 19, 67, 84, 87,
EPWM6_A O ePWM-6 Output A 15, 55, 68, 93 11, 40, 50, 76 7, 34, 41, 63 31, 38
75, 226 111, 122
EPWM6_B O ePWM-6 Output B 11, 19, 69 64, 73, 88 52, 69 37, 51 31, 42 28, 39
12, 28, 41, 64, 2, 49, 56, 63,
EPWM7_A O ePWM-7 Output A 1, 39, 51, 82 4, 28, 36, 66 2, 24, 30, 55 3, 22, 27, 50
68, 236 72, 103
EPWM7_B O ePWM-7 Output B 13, 29, 67, 215 1, 10, 47, 62 50, 100 3, 35 1, 29 2, 26
68, 85, 114,
EPWM8_A O ePWM-8 Output A 14, 24, 73, 78 56, 96 41, 79 35 32
125
EPWM8_B O ePWM-8 Output B 15, 32, 79 79, 115, 124 64, 95 49, 78 40 37
EPWM9_A O ePWM-9 Output A 16, 24, 71, 73 66, 68, 83, 85 54, 56 39, 41 33, 35 30, 32
EPWM9_B O ePWM-9 Output B 17, 72 67, 84 55 40 34 31
EPWM10_A O ePWM-10 Output A 2, 62, 211, 228 18, 43, 58, 98 14, 46, 77 10, 31, 61 6, 50 45
EPWM10_B O ePWM-10 Output B 1, 63, 212, 226 19, 44, 59, 99 15, 47, 78 11, 32, 62 7, 51 46
EPWM11_A O ePWM-11 Output A 8, 64, 213, 242 20, 45, 56, 95 16, 74 12, 58 8, 47 6
EPWM11_B O ePWM-11 Output B 4, 65, 214, 224 21, 46, 57, 96 17, 75 13, 59 9, 48 7, 43
20, 23, 66,
EPWM12_A O ePWM-12 Output A 9, 49, 60, 102 39, 41, 48, 81 28, 33, 65 24, 27, 54 22, 24, 49
236, 253
21, 41, 60, 67,
EPWM12_B O ePWM-12 Output B 10, 52, 61, 103 42, 44, 49, 82 34, 66 28, 55 25, 50
247
6, 10, 20, 25, 2, 13, 21, 56,
1, 9, 17, 48, 4, 13, 33, 42,
28, 35, 40, 44, 57, 60, 69, 78, 2, 9, 27, 39, 1, 3, 7, 24, 36,
EQEP1_A I eQEP-1 Input A 57, 63, 65, 80, 48, 64, 69, 76,
50, 56, 64, 65, 80, 101, 106, 53, 63, 64 48
85, 93, 97 80
77, 224 113, 122, 126

Table 5-3. Digital Signals (continued)

PIN
TYPE
1, 9, 14, 18,
7, 11, 21, 29, 10, 14, 49, 52,
61, 64, 73, 76, 3, 10, 34, 37, 1, 6, 28, 31, 2, 25, 28, 34,
EQEP1_B I eQEP-1 Input B 37, 41, 51, 57, 61, 66, 82, 84,
81, 86, 103, 46, 66, 68 37, 55, 57 50, 52
66, 69, 74, 228 100
105
0, 9, 13, 17, 10, 16, 20, 49,
23, 31, 32, 43, 62, 67, 79, 84, 12, 16, 39, 50, 2, 12, 28, 35,
8, 24, 29, 34, 6, 22, 26, 31,
EQEP1_INDEX I/O eQEP-1 Index 53, 59, 67, 72, 91, 100, 102, 55, 64, 79, 81, 40, 49, 54, 63,
40, 52, 54, 62 37, 47, 49, 56
76, 80, 236, 112, 116, 119, 90, 92, 99 65, 75
242 121, 128
1, 8, 12, 16, 15, 19, 63, 66,
11, 15, 51, 54,
22, 30, 42, 52, 72, 82, 83, 94, 1, 11, 36, 39, 7, 30, 33, 47,
EQEP1_STROBE I/O eQEP-1 Strobe 67, 74, 78, 83, 27, 30, 46, 51
58, 68, 71, 75, 95, 99, 104, 57, 58, 62, 67 51, 56
98
226 111, 127
11, 14, 18, 24, 17, 47, 64, 68, 13, 52, 56, 68,
EQEP2_A I eQEP-2 Input A 37, 41, 50, 79 31, 35, 41 28, 32, 38
54, 69, 215 73, 87, 125 96
15, 16, 19, 25, 51, 65, 66, 69, 43, 53, 54, 57, 38, 39, 42, 51,
EQEP2_B I eQEP-2 Input B 32, 33, 42 29, 30, 39
33, 55, 70 74, 88, 124 69, 95 78
EQEP2_INDEX I/O eQEP-2 Index 26, 29, 57, 71 1, 70, 81, 83 58, 66, 100 3, 43 1 2
4, 27, 28, 56, 2, 56, 71, 80,
EQEP2_STROBE I/O eQEP-2 Strobe 1, 59, 65, 75 4, 44, 59 2, 48 3, 43
64 96
EQEP3_A I eQEP-3 Input A 22, 25, 70, 211 43, 69, 74, 104 57, 83 42, 67 56 51
EQEP3_B I eQEP-3 Input B 9, 26, 72, 212 44, 70, 84, 119 58, 90 43, 75 62 56
11, 18, 30, 69, 46, 64, 73, 87,
EQEP3_INDEX I/O eQEP-3 Index 52, 68, 98 1, 37, 50 31, 41 28, 38
81, 214 117, 127
10, 16, 27, 40, 45, 66, 71, 83,
EQEP3_STROBE I/O eQEP-3 Strobe 54, 59, 80, 93 39, 44, 64, 76 33, 53, 63 30, 48
71, 213 101, 122
Error Status Output. This signal requires an 24, 28, 29, 55, 1, 2, 51, 56,
ERRORSTS O 1, 43, 56, 100 3, 4, 41 1, 2, 35 2, 3, 32
external pulldown. 64, 73 68, 85
0, 4, 13, 30, 10, 17, 62, 65,
13, 50, 53, 66, 1, 35, 38, 59,
FSIRXA_CLK I FSIRX-A Input Clock 33, 54, 57, 67, 74, 81, 96, 29, 32, 48, 52 26, 29, 43, 47
75, 79, 98 63
70 100, 127
15, 63, 72, 79,
3, 12, 32, 40, 11, 51, 64, 67, 36, 49, 60, 64,
FSIRXA_D0 I FSIRX-A Primary Data Input 82, 97, 101, 30, 40, 49, 53 27, 37, 44, 48
44, 52, 58, 68 76, 80, 85 69
106
2, 11, 31, 41, 16, 64, 73, 80, 12, 52, 65, 77,
FSIRXA_D1 I FSIRX-A Optional Additional Data Input 2, 37, 61, 66 31, 50, 55 28, 45, 50
53, 56, 69 98, 103, 128 82, 99
7, 10, 27, 44, 14, 71, 105, 10, 59, 84, 85,
FSITXA_CLK O FSITX-A Output Clock 44, 68, 69, 76 57, 63 52
51, 78 106, 114, 122 93
6, 9, 26, 45, 12, 70, 110,
FSITXA_D0 O FSITX-A Primary Data Output 8, 58, 90, 97 43, 73, 75, 80 62, 64 1, 56
49, 80 116, 119, 126
5, 6, 8, 25, 46, 4, 13, 69, 95, 9, 57, 74, 89, 6, 42, 58, 74,
FSITXA_D1 O FSITX-A Optional Additional Data Output 47, 61, 64 1, 55
50, 81 117, 118, 126 97 80
GPIO0 I/O General-Purpose Input Output 0 0 100 79 63 52 47
GPIO8 I/O General-Purpose Input Output 8 8 95 74 58 47
GPIO14 I/O General-Purpose Input Output 14 14 125 96 79


PIN
TYPE
GPIO42 I/O General-Purpose Input Output 42 42 94 57
GPIO64 I/O General-Purpose Input Output 64 64 56


PIN
TYPE
57, 60, 65, 71,
1, 4, 8, 9, 18, 48, 53, 59, 61, 33, 38, 44, 46,
74, 76, 81, 87, 27, 32, 37, 41, 24, 29, 34, 38,
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 20, 27, 33, 37, 66, 68, 74, 75, 50, 54, 58, 59,
91, 95, 96, 99, 47, 48, 51, 62 43, 46, 56
43, 57, 65, 70 78, 90 62, 75
119
0, 5, 10, 19, 9, 50, 61, 70,
40, 49, 58, 63, 29, 34, 43, 48,
21, 26, 32, 35, 78, 79, 80, 88, 25, 28, 39, 40, 23, 25, 36, 37,
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 64, 65, 69, 79, 49, 51, 57, 63,
42, 56, 66, 79, 94, 100, 115, 42, 52, 61, 63 39, 47, 55
89, 93 74, 76
230 118, 122
3, 9, 15, 29, 1, 14, 48, 97, 10, 38, 76, 90, 3, 28, 60, 75,
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 1, 24, 49, 62 2, 22, 44, 56
51, 81, 227 117, 119, 124 95, 100 78
2, 13, 50, 56,
2, 14, 28, 34, 1, 9, 40, 77, 4, 29, 61, 77,
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 98, 116, 123, 2, 25, 50 3, 23, 45
50, 64, 80, 230 94, 96 79
125
9, 11, 13, 15, 1, 8, 10, 12,
19, 23, 29, 33, 19, 51, 59, 62, 6, 8, 15, 43, 3, 11, 32, 35,
1, 7, 29, 31, 2, 26, 28, 29,
35, 41, 42, 47, 64, 65, 73, 74, 47, 50, 52, 53, 37, 38, 48, 51,
LINA_RX I LIN-A Receive 32, 39, 42, 54, 36, 39, 49, 50,
49, 55, 59, 63, 78, 88, 94, 63, 69, 81, 82, 57, 65, 66, 75,
55, 62 56
67, 69, 70, 75, 102, 103, 111, 90, 92, 95, 100 78
226 119, 121, 124
10, 12, 14, 18, 2, 4, 17, 56,
1, 13, 51, 56,
22, 24, 28, 32, 63, 68, 72, 76, 4, 6, 36, 41, 2, 30, 35, 37,
61, 64, 67, 68, 3, 27, 32, 34,
LINA_TX O LIN-A Transmit 37, 40, 44, 46, 79, 82, 85, 87, 46, 49, 50, 64, 40, 41, 53, 56,
80, 83, 85, 93, 37, 38, 48, 51
54, 58, 64, 68, 101, 104, 106, 67, 69, 76, 79 63
96
73 122, 125
0, 5, 11, 12, 8, 9, 12, 14,
21, 30, 47, 49, 20, 50, 59, 61, 6, 8, 10, 16,
1, 12, 29, 32,
51, 57, 61, 63, 63, 64, 72, 74, 40, 47, 49, 51, 8, 25, 28, 30, 6, 23, 25, 27,
MCANA_RX I CAN/CAN FD Receive 34, 36, 37, 63,
66, 68, 70, 76, 81, 100, 112, 52, 66, 79, 89, 31, 52, 61 28, 47, 55
74
79, 80, 230, 115, 116, 118, 91, 98
242 120, 127
1, 4, 7, 13, 17, 4, 10, 11, 13,
20, 31, 46, 48, 18, 21, 52, 57, 7, 9, 14, 17,
2, 6, 10, 13,
50, 56, 60, 62, 58, 60, 62, 67, 44, 46, 48, 50, 6, 9, 27, 29, 7, 24, 26, 31,
MCANA_TX O CAN/CAN FD Transmit 31, 33, 35, 40,
65, 67, 72, 74, 80, 84, 86, 96, 55, 65, 75, 78, 34, 48, 51, 57 43, 46, 52
59, 62, 68
77, 81, 224, 99, 105, 113, 84, 99
228 117, 128
3, 18, 33, 35, 16, 65, 78, 87, 12, 53, 63, 68,
MCANB_RX I CAN/CAN FD Receive 38, 48, 50, 60 32, 39, 41, 49 29, 36, 38, 44
53, 59, 61 97, 120, 121 76, 91, 92
2, 19, 32, 37, 76, 79, 82, 88, 61, 64, 67, 69,
MCANB_TX O CAN/CAN FD Transmit 46, 49, 51, 61 37, 40, 42, 50 34, 37, 39, 45
58 98 77
2, 24, 34, 58, 48, 68, 82, 85, 38, 56, 67, 77,
OUTPUTXBAR1 O Output X-BAR Output 1 28, 41, 61, 77 24, 35, 50 22, 32, 45
73, 78, 227 98, 114, 123 94
3, 25, 37, 54, 17, 20, 69, 76, 13, 16, 57, 61,
OUTPUTXBAR2 O Output X-BAR Output 2 12, 42, 46, 60 8, 37, 49 6, 34, 44
59, 76, 242 97, 112, 121 76, 92
4, 5, 14, 26, 11, 21, 51, 52, 7, 17, 43, 44,
13, 31, 43, 59,
OUTPUTXBAR3 O Output X-BAR Output 3 48, 55, 60, 62, 58, 70, 96, 46, 58, 75, 89, 9, 48, 61 7, 43, 55
74, 79
77, 224 113, 118, 125 96
12, 59, 65, 71,
6, 15, 27, 33, 8, 47, 53, 59, 32, 38, 44, 78,
OUTPUTXBAR4 O Output X-BAR Output 4 74, 120, 124, 32, 64 1, 29
49, 61, 63, 70 91, 95, 97 80
126


PIN
TYPE
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28, 42, 64 2, 56, 94, 105 1, 84 4, 57, 68 2, 57 3, 52
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43, 81 1, 91, 117, 119 90, 100 3, 54, 75 1, 62 2, 56
64, 66, 73, 83,
0, 11, 16, 30, 52, 54, 79, 85, 1, 37, 39, 63,
OUTPUTXBAR7 O Output X-BAR Output 7 100, 106, 116, 31, 33, 52 28, 30, 47
44, 69, 71, 80 98 69
127
67, 84, 110,
OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45, 72 55, 99 2, 40, 73 34 31
128
13, 19, 27, 37, 10, 62, 71, 76, 35, 44, 46, 51,
PMBUSA_ALERT I/OD PMBus-A Open-Drain Bidirectional Alert Signal 50, 59, 61, 69 29, 37, 42 26, 34, 39
43, 45, 67 88, 91, 110 54, 73
PMBus-A Control Signal - Target Input/ 12, 18, 26, 35, 63, 70, 72, 78, 51, 58, 63, 68, 36, 43, 48, 50,
PMBUSA_CTL I/O 30, 39, 41 27, 36, 38
Controller Output 42, 44, 68 87, 94, 106 85 57, 69
8, 50, 66, 68,
3, 9, 15, 16, 6, 40, 54, 56,
78, 83, 85, 97, 29, 39, 41, 48, 25, 33, 35, 39, 23, 30, 32, 36,
PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock 24, 35, 41, 47, 63, 76, 82, 90,
103, 115, 119, 60, 66, 75, 78 49, 55, 62 44, 50, 56
71, 73, 79, 230 95
124
4, 11, 58, 67,
2, 14, 17, 25, 7, 46, 55, 57, 6, 31, 40, 42,
69, 79, 84, 98,
PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data 32, 34, 40, 44, 64, 77, 80, 85, 49, 61, 64, 69, 34, 40, 50, 53 31, 37, 45, 48
101, 106, 123,
46, 48, 62, 72 94, 96 77, 79
125
2, 12, 56, 59,
0, 3, 5, 9, 17, 1, 8, 47, 55, 4, 32, 40, 42,
67, 69, 78, 84, 2, 34, 39, 49, 3, 31, 36, 44,
SCIA_RX I SCI-A Receive Data 25, 28, 35, 49, 57, 63, 76, 79, 48, 60, 63, 74,
97, 100, 116, 52, 61, 62 47, 55, 56
63, 64, 72, 80 89, 90 75
118, 119
1, 2, 7, 8, 16, 1, 11, 58, 66, 7, 46, 54, 56, 3, 31, 39, 41,
1, 33, 35, 37, 2, 30, 32, 34,
SCIA_TX O SCI-A Transmit Data 24, 29, 37, 48, 68, 76, 83, 85, 61, 74, 77, 78, 46, 58, 61, 62,
47, 50, 51, 57 45, 46, 52
62, 71, 73 95, 98, 99, 105 84, 100 68
11, 13, 15, 19, 10, 62, 64, 73,
50, 52, 66, 69, 35, 37, 51, 65, 29, 31, 42, 54, 26, 28, 39, 49,
SCIB_RX I SCI-B Receive Data 23, 41, 57, 67, 81, 88, 102,
81, 82, 95 66, 78 55 50
69 103, 124
9, 10, 12, 14, 63, 72, 80, 87,
51, 65, 68, 80, 36, 50, 64, 67, 30, 41, 53, 56, 27, 38, 48, 51,
SCIB_TX O SCI-B Transmit Data 18, 22, 40, 56, 101, 104, 119,
83, 90, 93, 96 75, 76, 79 62, 63 56
68 122, 125
21, 33, 42, 67, 10, 19, 61, 65,
SCIC_RX I SCI-C Receive Data 15, 49, 53 11, 34, 38, 57 7, 28, 32 25, 29
75, 81, 226 94, 111, 117
20, 43, 68, 77, 21, 60, 72, 91,
SCIC_TX O SCI-C Transmit Data 17, 48 13, 33, 54 9, 27 7, 24
224 113
19, 63, 72, 80,
3, 9, 12, 18, 15, 51, 65, 68, 11, 36, 50, 60, 7, 30, 41, 49,
SPIA_CLK I/O SPI-A Clock 87, 97, 111, 27, 38, 44, 56
56, 68, 75, 226 76, 90 75 62
119
2, 8, 11, 16, 17, 21, 64, 66,
13, 17, 52, 54, 13, 37, 39, 58, 9, 31, 33, 47,
SPIA_PICO I/O SPI-A Peripheral In, Controller Out (PICO) 54, 69, 71, 77, 73, 83, 95, 98, 7, 28, 30, 45
74, 77 61 50
224 113
1, 4, 10, 13, 10, 18, 51, 62,
14, 43, 50, 55, 10, 35, 40, 48, 6, 29, 34, 39, 26, 31, 36, 43,
SPIA_POCI I/O SPI-A Peripheral Out, Controller In (POCI) 17, 35, 55, 67, 67, 78, 84, 86,
63, 75, 78, 93 59, 62, 76 48, 51, 63 46
72, 74, 228 96, 99, 122
20, 64, 68, 73,
0, 5, 11, 19,
76, 81, 85, 88, 16, 52, 56, 61, 12, 37, 41, 46, 8, 31, 35, 37, 6, 28, 32, 34,
SPIA_PTE I/O SPI-A Peripheral Transmit Enable (PTE) 24, 37, 57, 69,
100, 112, 116, 66, 69, 79, 89 51, 63, 74 42, 52, 61 39, 47, 55
73, 76, 80, 242
118
4, 14, 22, 26, 2, 15, 56, 70,
1, 11, 58, 64, 4, 43, 49, 59,
SPIB_CLK I/O SPI-B Clock 28, 32, 52, 58, 79, 82, 96, 2, 40, 48, 56 3, 37, 43, 51
67, 75, 83, 96 67, 79
64, 81 104, 117, 125
7, 20, 24, 30, 13, 52, 57, 60,
9, 44, 48, 56, 1, 33, 41, 64,
SPIB_PICO I/O SPI-B Peripheral In, Controller Out (PICO) 40, 50, 56, 60, 68, 80, 85, 27, 35, 53, 57 24, 32, 48, 52
65, 80, 84, 98 68
65, 73 101, 105, 127
9, 14, 61, 66,
6, 16, 21, 25, 10, 49, 54, 57,
69, 81, 83, 2, 34, 39, 42,
SPIB_POCI I/O SPI-B Peripheral Out, Controller In (POCI) 31, 41, 51, 57, 66, 82, 91, 97, 28, 33, 55, 64 1, 25, 30, 50
103, 120, 126, 66, 80
61, 66, 71 99
128
1, 16, 65, 71,
15, 23, 27, 29, 12, 53, 59, 81, 3, 38, 44, 65,
SPIB_PTE I/O SPI-B Peripheral Transmit Enable (PTE) 74, 102, 121, 1, 32, 54 2, 29, 49
33, 53, 59, 70 92, 95, 100 78
124
SYNCOUT O External ePWM Synchronization Pulse 6, 52 15, 126 11, 97 80 64 1
JTAG Test Data Input (TDI) - TDI is the default
mux selection for the pin. The internal pullup is
disabled by default. The internal pullup should
TDI I 35 78 63 48 39 36
be enabled or an external pullup added on the
board if this pin is used as JTAG TDI to avoid a
floating input.


PIN
TYPE
JTAG Test Data Output (TDO) - TDO is the
default mux selection for the pin. The internal
pullup is disabled by default. The TDO function
will be in a tri-state condition when there
TDO O 37 76 61 46 37 34
is no JTAG activity, leaving this pin floating;
the internal pullup should be enabled or an
external pullup added on the board to avoid a
floating GPIO input.
USB0DM O USB-0 PHY differential data 23 102 81 65 54 49
USB0DP O USB-0 PHY differential data 41 103 82 66 55 50
Crystal oscillator input or single-ended clock
input. The device initialization software must
configure this pin before the crystal oscillator is
X1 I/O enabled. To use this oscillator, a quartz crystal 19 88 69 51 42 39
circuit must be connected to X1 and X2. This
pin can also be used to feed a single-ended
3.3-V level clock.
X2 I/O Crystal oscillator output. 18 87 68 50 41 38
External Clock Output. This pin outputs a
XCLKOUT O divided-down version of a chosen clock signal 16, 18, 71 66, 83, 87 54, 68 39, 50 33, 41 30, 38
from within the device.
5.3.3 Power and Ground

Table 5-4. Power and Ground
SIGNAL
PIN TYPE DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
NAME
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each
VDD pin with a minimum total capacitance of
VDD 6, 54, 90, 108 4, 71, 87 8, 53, 71 4, 44, 59 5, 41, 53
approximately 10 µF. It is also recommended that
all VDD pins be externally connected to each
other when internal VREG is used.
3.3-V Analog Power Pins. Place a minimum
VDDA 41 34 26 22 20
2.2‑µF decoupling capacitor on each pin.
3.3-V Digital I/O Power Pins. Place a minimum
VDDIO 5, 55, 89, 109 3, 70, 88 7, 52, 72 43, 60 40, 54
0.1-µF decoupling capacitor on each pin.
Internal voltage regulator enable with internal
pulldown. Tie low to VSS to enable internal
VREGENZ I 93 73 56 46 42
VREG. Tie high to VDDIO to use an external
supply.
VSS Digital Ground 7, 53, 92, 107 5, 45, 72, 86 9, 30, 55, 70 5, 26, 45, 58 PAD
VSSA Analog Ground 40 33 25 21 19

5.3.4 Test, JTAG, and Reset

Table 5-5. Test, JTAG, and Reset
SIGNAL PIN
DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
NAME TYPE
TCK I JTAG test clock with internal pullup. 75 60 45 36 33
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
This device does not have a TRSTn pin.
TMS I/O 77 62 47 38 35
An external pullup resistor (recommended
2.2‑kΩ) on the TMS pin to VDDIO should be
placed on the board to keep JTAG in reset
during normal operation.
Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven
low by the device. An external circuit may
also drive this pin to assert a device reset.
This pin is also driven low by the MCU when
a watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for the
watchdog reset duration of 512 OSCCLK
cycles. A resistor between 2.2 kΩ and 10 kΩ
XRSn I/OD should be placed between XRSn and VDDIO. 3 2 5 3 4
If a capacitor is placed between XRSn and
VSS for noise filtering, it should be 100 nF or
smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within
512 OSCCLK cycles when the watchdog
reset is asserted. This pin is an open-drain
output with an internal pullup. If this pin is
driven by an external device, it should be
done using an open-drain device.
5.4 Pin Multiplexing

5.4.1 GPIO Muxed Pins

Table 5-6. GPIO Muxed Pins
0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
OUTPUTXBA CLB_OUTPUTXB
GPIO0 EPWM1_A SCIA_RX I2CA_SDA SPIA_PTE FSIRXA_CLK MCANA_RX EQEP1_INDEX EPWM3_A
R7 AR8
EQEP1_STRO CLB_OUTPUTXB
GPIO1 EPWM1_B SCIA_TX I2CA_SCL SPIA_POCI MCANA_TX EPWM10_B EPWM3_B
BE AR7
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SPIA_PICO SCIA_TX FSIRXA_D1 I2CB_SDA EPWM10_A MCANB_TX EPWM4_A
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL MCANB_RX EPWM4_B
GPIO4 EPWM3_A I2CA_SCL MCANA_TX OUTPUTXBAR3 SPIB_CLK FSIRXA_CLK EPWM11_B SPIA_POCI EPWM1_A
BE AR6
GPIO5 EPWM3_B I2CA_SDA MCANA_RX SPIA_PTE FSITXA_D1 SCIA_RX EPWM1_B
R3 AR5
CLB_OUTPUTXB
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A SPIB_POCI FSITXA_D0 FSITXA_D1 EPWM2_A
AR8
GPIO7 EPWM4_B EPWM2_A EQEP1_B SPIB_PICO FSITXA_CLK SCIA_TX MCANA_TX EPWM2_B
R5 AR2
CLB_OUTPUTXB
GPIO8 EPWM5_A ADCSOCAO EQEP1_STROBE SCIA_TX SPIA_PICO I2CA_SCL FSITXA_D1 EPWM11_A
AR5
OUTPUTXBA
GPIO9 EPWM5_B SCIB_TX EQEP1_INDEX SCIA_RX SPIA_CLK I2CA_SCL FSITXA_D0 LINA_RX PMBUSA_SCL I2CB_SCL EQEP3_B
R6
CLB_OUTPUTXB
GPIO10 EPWM6_A ADCSOCBO EQEP1_A SCIB_TX SPIA_POCI I2CA_SDA FSITXA_CLK LINA_TX EQEP3_STROBE
AR4
OUTPUTXBA
GPIO11 EPWM6_B MCANA_RX EQEP1_B SCIB_RX SPIA_PTE FSIRXA_D1 LINA_RX EQEP2_A SPIA_PICO EQEP3_INDEX
R7
GPIO12 EPWM7_A MCANA_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINA_TX SPIA_CLK
GPIO13 EPWM7_B MCANA_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINA_RX SPIA_POCI
OUTPUTXBAR CLB_OUTPUTXB
GPIO14 EPWM8_A SCIB_TX I2CB_SDA PMBUSA_SDA SPIB_CLK EQEP2_A LINA_TX EPWM3_A
3 AR7
OUTPUTXBAR CLB_OUTPUTXB
GPIO15 EPWM8_B SCIB_RX I2CB_SCL PMBUSA_SCL SPIB_PTE EQEP2_B LINA_RX EPWM3_B
4 AR6
OUTPUTXBA EQEP1_STRO
GPIO16 SPIA_PICO EPWM9_A SCIA_TX PMBUSA_SCL XCLKOUT EQEP2_B SPIB_POCI EQEP3_STROBE
R7 BE
OUTPUTXBA EQEP1_INDE
GPIO17 SPIA_POCI EPWM9_B SCIA_RX PMBUSA_SDA MCANA_TX EPWM6_A
R8 X
GPIO18 SPIA_CLK SCIB_TX MCANB_RX EPWM6_A I2CA_SCL EQEP2_A PMBUSA_CTL XCLKOUT LINA_TX EQEP3_INDEX X2
CLB_OUTPUTXB
GPIO19 SPIA_PTE SCIB_RX MCANB_TX EPWM6_B I2CA_SDA EQEP2_B PMBUSA_ALERT LINA_RX X1
AR1
ADCE_EXTMUXS
GPIO20 EQEP1_A EPWM12_A SPIB_PICO MCANA_TX I2CA_SCL SCIC_TX
EL0
ADCE_EXTMUXS
GPIO21 EQEP1_B EPWM12_B SPIB_POCI MCANA_RX I2CA_SDA SCIC_RX
EL1
GPIO22 SCIB_TX SPIB_CLK LINA_TX LINA_TX EPWM4_A EQEP3_A
BE AR1
EQEP1_INDE CLB_OUTPUTXB
GPIO23 SCIB_RX SPIB_PTE LINA_RX LINA_RX EPWM12_A EPWM4_B USB0DM
X AR3

Table 5-6. GPIO Muxed Pins (continued)

0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
OUTPUTXBAR
GPIO24 EQEP2_A SPIA_PTE EPWM8_A SPIB_PICO LINA_TX PMBUSA_SCL SCIA_TX ERRORSTS EPWM9_A
1
OUTPUTXBAR
GPIO25 EQEP2_B EQEP1_A SPIB_POCI FSITXA_D1 PMBUSA_SDA SCIA_RX EQEP3_A
2
OUTPUTXBAR
GPIO26 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK FSITXA_D0 PMBUSA_CTL I2CA_SDA EQEP3_B
3
OUTPUTXBAR
GPIO27 EQEP2_STROBE OUTPUTXBAR4 SPIB_PTE FSITXA_CLK PMBUSA_ALERT I2CA_SCL EQEP3_STROBE
4
EQEP2_STRO
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
BE
EQEP2_INDE AUXCLKI
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B LINA_RX SPIB_PTE ERRORSTS I2CB_SCL
X N
EQEP1_STRO
GPIO30 SPIB_PICO OUTPUTXBAR7 FSIRXA_CLK MCANA_RX EPWM1_A EQEP3_INDEX
BE
EQEP1_INDE
GPIO31 SPIB_POCI OUTPUTXBAR8 FSIRXA_D1 MCANA_TX EPWM1_B
X
GPIO32 I2CA_SDA EQEP1_INDEX SPIB_CLK EPWM8_B LINA_TX FSIRXA_D0 MCANB_TX PMBUSA_SDA ADCSOCBO
GPIO33 I2CA_SCL SPIB_PTE OUTPUTXBAR4 LINA_RX FSIRXA_CLK MCANB_RX EQEP2_B ADCSOCAO SCIC_RX
OUTPUTXBAR
GPIO34 PMBUSA_SDA I2CB_SDA
1
GPIO35 SCIA_RX SPIA_POCI I2CA_SDA MCANB_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL EPWM5_B TDI
OUTPUTXBAR
GPIO37 SPIA_PTE I2CA_SCL SCIA_TX MCANB_TX LINA_TX EQEP1_B PMBUSA_ALERT EPWM5_A TDO
2
CLB_OUTPUTXB
GPIO40 SPIB_PICO EPWM2_B PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A LINA_TX EQEP3_STROBE
AR4
GPIO41 EPWM7_A EPWM2_A PMBUSA_SCL FSIRXA_D1 SCIB_RX EQEP1_B LINA_RX EPWM12_B SPIB_POCI USB0DP
GPIO42 LINA_RX PMBUSA_CTL I2CA_SDA SCIC_RX EQEP1_STROBE
R5 AR3
OUTPUTXBA PMBUSA_ALE CLB_OUTPUTXB
GPIO43 PMBUSA_ALERT I2CA_SCL SCIC_TX EQEP1_INDEX
R6 RT AR4
GPIO44 EQEP1_A PMBUSA_SDA FSITXA_CLK PMBUSA_CTL FSIRXA_D0 LINA_TX
R7 AR3
OUTPUTXBA PMBUSA_ALE CLB_OUTPUTXB
GPIO45 FSITXA_D0
R8 RT AR4
GPIO46 LINA_TX MCANA_TX FSITXA_D1 PMBUSA_SDA
CLB_OUTPUTXB
GPIO47 LINA_RX MCANA_RX PMBUSA_SCL
AR2
OUTPUTXBAR
GPIO48 MCANA_TX SCIA_TX PMBUSA_SDA
3
OUTPUTXBAR
GPIO49 MCANA_RX SCIA_RX LINA_RX FSITXA_D0
4
GPIO50 EQEP1_A MCANA_TX SPIB_PICO I2CB_SDA FSITXA_D1
GPIO51 EQEP1_B MCANA_RX SPIB_POCI I2CB_SCL FSITXA_CLK
GPIO52 SPIB_CLK SYNCOUT FSIRXA_D0
BE AR5


0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
EQEP1_INDE CLB_OUTPUTXB
GPIO53 SPIB_PTE ADCSOCAO MCANB_RX FSIRXA_D1
X AR6
OUTPUTXBAR
GPIO54 SPIA_PICO EQEP2_A ADCSOCBO LINA_TX FSIRXA_CLK
2
OUTPUTXBAR
GPIO55 SPIA_POCI EQEP2_B ERRORSTS LINA_RX
3
CLB_OUTPUTXB
GPIO56 SPIA_CLK MCANA_TX EQEP2_STROBE SCIB_TX SPIB_PICO I2CA_SDA EQEP1_A FSIRXA_D1
AR7
CLB_OUTPUTXB
GPIO57 SPIA_PTE MCANA_RX EQEP2_INDEX SCIB_RX SPIB_POCI I2CA_SCL EQEP1_B FSIRXA_CLK
AR8
GPIO58 OUTPUTXBAR1 SPIB_CLK LINA_TX MCANB_TX EQEP1_STROBE FSIRXA_D0
GPIO59 OUTPUTXBAR2 SPIB_PTE LINA_RX MCANB_RX EQEP1_INDEX
GPIO60 EPWM12_B MCANA_TX OUTPUTXBAR3 SPIB_PICO
GPIO61 MCANA_RX OUTPUTXBAR4 SPIB_POCI MCANB_RX
GPIO62 EPWM10_A OUTPUTXBAR3 MCANA_TX SCIA_TX PMBUSA_SDA
GPIO63 EPWM10_B OUTPUTXBAR4 MCANA_RX SCIA_RX LINA_RX
EQEP2_STRO
GPIO64 SCIA_RX EPWM11_A EPWM7_A OUTPUTXBAR5 EQEP1_A LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
BE
GPIO65 EQEP1_A EPWM11_B SPIB_PICO MCANA_TX I2CA_SCL
GPIO66 EQEP1_B EPWM12_A SPIB_POCI MCANA_RX I2CA_SDA
GPIO67 EPWM7_B EPWM12_B MCANA_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINA_RX SPIA_POCI SCIC_RX
GPIO68 EPWM7_A EPWM3_A MCANA_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINA_TX SPIA_CLK SCIC_TX
OUTPUTXBA
GPIO69 EPWM6_B EPWM3_B EQEP1_B SCIB_RX SPIA_PTE FSIRXA_D1 LINA_RX EQEP2_A SPIA_PICO EQEP3_INDEX
R7
GPIO70 I2CA_SCL SPIB_PTE OUTPUTXBAR4 LINA_RX FSIRXA_CLK MCANA_RX EQEP2_B ADCSOCAO EQEP3_A
OUTPUTXBA EQEP1_STRO
GPIO71 SPIA_PICO EPWM4_B EPWM9_A SCIA_TX PMBUSA_SCL XCLKOUT EQEP2_INDEX SPIB_POCI EQEP3_STROBE
R7 BE
OUTPUTXBA EQEP1_INDE
GPIO72 SPIA_POCI EPWM5_A EPWM9_B SCIA_RX PMBUSA_SDA MCANA_TX EPWM6_A EQEP3_B
R8 X
OUTPUTXBAR
GPIO73 EPWM5_B SPIA_PTE EPWM8_A SPIB_PICO LINA_TX PMBUSA_SCL SCIA_TX ERRORSTS EPWM9_A
1
GPIO74 EPWM2_B ADCSOCAO MCANA_TX SPIA_POCI EQEP1_B
GPIO75 EPWM1_B LINA_RX EPWM6_A SPIA_CLK EQEP1_STROBE SCIC_RX
GPIO76 EPWM4_A OUTPUTXBAR2 SPIA_PTE MCANA_RX EQEP1_INDEX
GPIO77 EPWM1_A OUTPUTXBAR3 SPIA_PICO MCANA_TX EQEP1_A SCIC_TX
GPIO78 EPWM8_A EPWM3_A OUTPUTXBAR1 EPWM2_B FSITXA_CLK
GPIO79 EPWM8_B EPWM3_B MCANA_RX EPWM2_A I2CA_SDA PMBUSA_SCL
GPIO80 EPWM1_A SCIA_RX I2CB_SDA SPIA_PTE FSITXA_D0 MCANA_RX EQEP1_INDEX EPWM3_A
R7 AR8
GPIO81 EPWM1_B OUTPUTXBAR6 SCIC_RX SPIB_CLK I2CB_SCL FSITXA_D1 MCANA_TX EQEP3_INDEX
GPIO211 EPWM10_A EQEP3_A
GPIO21
EPWM10_B EQEP3_B
2


0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
GPIO21
EPWM11_A EQEP3_STROBE
3
GPIO21
EPWM11_B EQEP3_INDEX
4
GPIO21
EPWM7_B EQEP2_A
5
GPIO22 ADCE_EXTMUXS
EPWM11_B OUTPUTXBAR3 SPIA_PICO EPWM1_A MCANA_TX EQEP1_A SCIC_TX
4 EL3
GPIO22 ADCE_EXTMUXS
EPWM10_B LINA_RX EPWM6_A SPIA_CLK EPWM1_B EQEP1_STROBE SCIC_RX
6 EL1
GPIO22
I2CB_SCL EPWM3_A OUTPUTXBAR1 EPWM2_B
7
GPIO22 ADCE_EXTMUXS
EPWM10_A ADCSOCAO MCANA_TX SPIA_POCI EPWM2_B EQEP1_B
8 EL0
GPIO23
I2CB_SDA EPWM3_B MCANA_RX EPWM2_A I2CA_SDA PMBUSA_SCL
0
GPIO23
EPWM7_A EQEP1_INDEX EPWM12_A
6
GPIO24 ADCE_EXTMUXS
EPWM11_A OUTPUTXBAR2 SPIA_PTE EPWM4_A MCANA_RX EQEP1_INDEX
2 EL2
GPIO24
EPWM12_B
7
GPIO25
EPWM12_A
3
AIO208
AIO209
AIO210
AIO225
AIO229
AIO231
AIO232
AIO233
AIO234
AIO235
AIO237
AIO238
AIO239
AIO240
AIO241
AIO244
AIO245
AIO248
AIO249


0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
AIO251
AIO252

5.4.2 Digital Inputs on ADC Pins (AIOs)

Some GPIOs are multiplexed with analog pins and only have digital input functionality. These are also referred to
as AIOs. Pins with only an AIO option on this port can only function in input mode. See the device data sheet for
list of AIO signals. By default, these pins function as analog pins and the GPIOs are in a high-impedance state.
The GPyAMSEL register is used to configure these pins for digital or analog operation.
Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. Therefore, limit the edge rate of signals connected to AIOs if adjacent
channels are being used for analog functions.
5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)

Some GPIOs are multiplexed with analog pins and have digital input and output functionality. These are also
referred to as AGPIOs. Unlike AIOs, AGPIOs have full input and output capability. By default, the AGPIOs are
not connected and must be configured. Table 5-7 shows how to configure the AGPIOs. To enable the analog
functionality, set the register AGPIOCTRLx from analog subsystem. To enable the digital functionality, set the
register GPxAMSEL from the General-Purpose Input/Output (GPIO) chapter.
Table 5-7. AGPIO Configuration
AGPIOCTRLx.GPIOy GPxAMSEL.GPIOy Pin Connected To:
(Default = 0) (Default = 1) ADC GPIOy
0 0 - Yes
(1) (1)
0 1 - -
1 0 - Yes
1 1 Yes -
(1) By default there are no signals connected to AGPIO pins. One of the other rows in the table must be chosen for pin functionality.
Note
If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with
adjacent analog signals. The user must therefore limit the edge rate of signals connected to AGPIOs,
if adjacent channels are being used for analog functions.
The general schematic of analog subsystem with AGPIO implementation is illustrated in Figure 5-6. The
combinations of use cases for a specific analog input pin need special consideration are shown in Table 5-8.
The AGPIO analog pin path contains an extra series switch of 53Ω. This creates a low capacitance isolated
node shared by the ADC and CMPSS Comparator as shown in Figure 5-6. This node can be disturbed
when the ADC samples the channel (depending on the prior voltage stored on the ADC sample and hold
capacitor), and this disturbance can cause a false CMPSS event of up to 50ns. As shown in Table 5-8, special
considerations or workarounds need to be used for the combination of CMPSS Input, ADC Sampling, and
AGPIO. To accommodate this potential disturbance the following workarounds can be implemented:
1. Use a different pin (that is AIO pin type) for analog channels which need both ADC and CMPSS together.
2. Use the CMPSS Digital Filter with a setting of 50ns or greater, which filters the temporary disturbance.
3. Precondition the sample and hold capacitor of the ADC so the disturbance does not cause a false trip. For
example, perform a dummy read of a 3.3V connection from a different channel on the ADC immediately
before the impacted channel is read so the disturbance is in the positive direction, away from the false trip.
The opposite dummy read of a 0V signal can be used if the false trip is inverted in polarity.

Table 5-8. The Combinations of Use Cases for a Specific Analog Input Pin
Function Used on a Specific Analog Pin Component Used
CMPSS Comparator Input Yes - Yes - Yes
ADC Sampling Yes Yes - Yes Yes
AGPIO Analog Pin Type Yes Yes Yes - -
AIO Analog Pin Type - - - Yes Yes
Result Workaround needed No special analysis or workaround needed
C2000 Device Analog

Interconnect CMPSS
+
GPIO
CMPSS MUX
–
AGPIO pin GPIO Logic –
ADC MUX
Switch RON ADC
AGPIO switch
AIO pin
Cp Ch
GPIO
VREFLO
GPIO Logic
Figure 5-6. Analog Subsystem Block Diagram with AGPIO Implementation

5.4.4 GPIO Input X-BAR

The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see the Input X-BAR figure). The Input X-BAR Destinations table lists the
input X-BAR destinations. For details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the
TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
GPIO0 Asynchronous
Synchronous Input X-BAR
GPIOx Sync. + Qual.
Other Sources
INPUT16
INPUT15
INPUT14
INPUT13
INPUT12
INPUT10
INPUT11
INPUT9
INPUT8
INPUT7
INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
127:16
eCAP1
eCAP2
INPUT[16:1]
15:0
EPG1IN1
EPG EPG1IN2
EPG1IN3
EPG1IN4
TZ1,TRIP1
TZ2,TRIP2 ePWM
DCCx Clock Source-0
TZ3,TRIP3 Modules
TRIP6
DCCx Clock Source-1
INPUT[1-14] CLB X-BAR
XINT1 INPUT[1-16] ERAD

XINT2
CPU PIE
XINT3
ePWM
CLA XINT4 INPUT[1-14] X-BAR
XINT5
CMPSS1/3 FILINIT High ADCEXTSOC ADC

CMPSS CMPSS1/3 FILINIT Low
CMPSS2/4 FILINIT High
CMPSS2/4 FILINIT Low ePWM and
EXTSYNCIN1
eCAP Sync
EXTSYNCIN2 Scheme
Other Sources
Output X-BAR
Figure 5-7. Input X-BAR
Table 5-9. Input X-BAR Destinations

EPWM /
EPWM CLB OUTPU EPWM CPU ADC
Input ECAP ERAD ECAP CMPSS DCCx EPG
XBAR XBAR T XBAR TRIP XINT SOC
SYNC
TZ1,
INPUTXBAR1 Yes Yes Yes Yes Yes
TRIP1
TZ2,
TRIP2
TZ3,
TRIP3
INPUTXBAR4 Yes Yes Yes Yes Yes XINT1
ADCE
EXTSY
INPUTXBAR5 Yes Yes Yes Yes Yes XINT2 XTSO
NCIN1
C
EXTSY
INPUTXBAR6 Yes Yes Yes Yes TRIP6 Yes XINT3
NCIN2

Table 5-9. Input X-BAR Destinations (continued)

EPWM /
EPWM CLB OUTPU EPWM CPU ADC
Input ECAP ERAD ECAP CMPSS DCCx EPG
XBAR XBAR T XBAR TRIP XINT SOC
SYNC
CMPSS1/3
.
INPUTXBAR7 Yes Yes Yes Yes
EXT_FILTI
N_H
CMPSS1/3
.
EXT_FILTI
N_L
CMPSS2/4
.
EXT_FILTI
N_H
CMPSS2/4
.
EXT_FILTI
N_L
INPUTXBAR11 Yes Yes Yes Yes CLK1
INPUTXBAR12 Yes Yes Yes Yes CLK1
EPGAI
INPUTXBAR13 Yes Yes Yes Yes XINT4
N1
EPGAI
INPUTXBAR14 Yes Yes Yes Yes XINT5
N2
EPGAI
INPUTXBAR15 Yes Yes CLK1
N3
EPGAI
INPUTXBAR16 Yes Yes CLK0
N4

5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB
X-BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 5-8. For details on the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28P55x Real-Time
Microcontrollers Technical Reference Manual.

EPG EPG1.EPGOUT
AUXSIG1
CTRIPOUTH AUXSIG2
AUXSIG3
CTRIPOUTL
CLB AUXSIG4
CLB
X-BAR AUXSIG5 Global
CMPSSx AUXSIG6 Mux
CTRIPH AUXSIG7
CTRIPL AUXSIG8
TRIP1
TRIP2
Input X-BAR INPUT1-14 TRIP3
TRIP4
TRIP5
TRIP6
FSI RXTRIG[1-3] TRIP7
ePWM TRIP8 All
X-BAR TRIP9 ePWM
CLB CLBx_OUT[0-7] TRIP10 Modules
TRIP11
ePWM and eCAP TRIP12
EXTSYNCOUT TRIP14
Sync Chain
TRIP15
ADCSOCA0 ADCSOCA0 eQEPx

Select Circuit
OUTPUTXBAR1
ADCSOCB0 OUTPUTXBAR2
ADCSOCB0
Select Circuit OUTPUTXBAR3
Output OUTPUTXBAR4
X-BAR OUTPUTXBAR5
eCAPx ECAPxOUT OUTPUTXBAR6
OUTPUTXBAR7
EVT1 OUTPUTXBAR8
ADCx EVT2
EVT3
EVT4 GPIO
X-BAR Flags
(shared) Mux
CLAHALT CLAHALT
ERAD EVT[8-11] CLB_OUTPUTXBAR1

CLB_OUTPUTXBAR2
CLB CLB_OUTPUTXBAR3
MCANx FEVT[0-2] CLB_OUTPUTXBAR4
Output CLB_OUTPUTXBAR5
X-BAR CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
CLB Input X-BAR CLB TILEx
Figure 5-8. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources

5.5 Pins With Internal Pullup and Pulldown

Some pins on the device have internal pullups or pulldowns. Table 5-10 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 5-10 with pullups and pulldowns are always on and cannot be
disabled.
Table 5-10. Pins With Internal Pullup and Pulldown
RESET
PIN DEVICE BOOT APPLICATION
(XRSn = 0)
GPIOx Pullup disabled Pullup disabled(1) Application defined
GPIO35/TDI Pullup disabled Application defined
GPIO37/TDO Pullup disabled Application defined
TCK Pullup active
TMS Pullup active
XRSn Pullup active
Other pins (including AIOs) No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.

5.6 Connections for Unused Pins

For applications that do not need to use all functions of the device, Table 5-11 lists acceptable conditioning for
any unused pins. When multiple options are listed in Table 5-11, any option is acceptable. Pins not listed in Table
5-11 must be connected according to Section 5.
Table 5-11. Connections for Unused Pins
SIGNAL NAME ACCEPTABLE PRACTICE
ANALOG
VREFHI Tie to VDDA (applies only if ADC is not used in the application)
VREFLO Tie to VSSA
Analog input pins with • No Connect

DACx_OUT • Tie to VSSA through 4.7-kΩ or larger resistor
• No Connect
Analog input pins (except • Tie to VSSA
DACx_OUT)
• Tie to VSSA through resistor
• No connection (digital input mode with internal pullup enabled)

Analog input pins (shared with • No connection (digital output mode with internal pullup disabled)
GPIOs)(1)
• Pullup or pulldown resistor (any value resistor, digital input mode, and with internal pullup disabled)
DIGITAL
• No connection (input mode with internal pullup enabled)
GPIOx • No connection (output mode with internal pullup disabled)
• Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
When TDI mux option is selected (default), the GPIO is in Input mode.
GPIO35/TDI • Internal pullup enabled
• External pullup resistor
When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO • Internal pullup enabled
• External pullup resistor
• No Connect
TCK • Pullup resistor
TMS Pullup resistor

Turn XTAL off and:
• Input mode with internal pullup enabled
GPIO19/X1
• Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled
Turn XTAL off and:

• Input mode with internal pullup enabled
GPIO18/X2
• Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled

Table 5-11. Connections for Unused Pins (continued)

SIGNAL NAME ACCEPTABLE PRACTICE
POWER AND GROUND
VDD All VDD pins must be connected per Section 5.3. Pins should not be used to bias any external circuits.
VDDA If a dedicated analog supply is not used, tie to VDDIO.
VDDIO All VDDIO pins must be connected per Section 5.3.
VSS All VSS pins must be connected to board ground.
VSSA If an analog ground is not used, tie to VSS.
(1) AGPIO pins share analog and digital functionality. The actions here only apply if these pins are also not being used for analog
functions.

6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating conditions (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDD with respect to VSS –0.3 1.5
Supply voltage VDDIO with respect to VSS –0.3 4.6 V
VDDA with respect to VSSA –0.3 4.6
VIN (3.3 V) –0.3 4.6 V
Input voltage (7)
VIN (5.0 V) (5) –0.3 6.0 V
Output voltage VO –0.3 4.6 V
IIK
Input clamp current - per pin (4) (6) - VIN < VSS/VSSA –20 20
- VIN > VDDIO/VDDA
Input clamp current - per pin: IIK
–20 mA
GPIO2/3/9/32 - VIN < VSS
IIKTOTAL
Input clamp current - total for all inputs (6) - VIN < VSS/VSSA –20 20
- VIN > VDDIO/VDDA
Output current Digital output (per pin), IOUT –20 20 mA
Operating junction temperature TJ –40 155 °C
Storage temperature(3) Tstg –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Note.
(4) Continuous clamp current per pin is ±2mA
(5) GPIO2, GPIO3, GPIO9, GPIO32 Only
(6) Applying a VIN greater than VDDIO/VDDA or less than VSS/VSSA will turn on the ESD current clamping diode causing additional
current flow to the respective supply rail. If this occurs, the current must be kept within the MIN/MAX listed to prevent permanent
damage to the device.
(7) Input clamp current must also be observed.

6.2 ESD Ratings – Commercial

VALUE UNIT
All F28P550Sxx devices in 128-pin PDT package
Human-body model (HBM), per All pins ±2000
ANSI/ESDA/JEDEC JS-001(1)
5V FS Pins: ±500
79, 97, 98, 119
V(ESD) Electrostatic discharge V
Charged-device model (CDM), All pins ±500
per ANSI/ESDA/JEDEC JS-002(2)
Corner pins on 128-pin PDT: ±750
1, 32, 33, 64, 65, 96, 97, 128
All F28P550Sxx devices in 100-pin PZ package
5V FS Pins: ±500
64, 76, 77, 90
Corner pins on 100-pin PZ: ±750
1, 25, 26, 50, 51, 75, 76, 100
All F28P550Sxx devices in 80-pin PNA package
5V FS Pins: ±500
49, 60, 61, 75
Corner pins on 80-pin PNA: ±750
1, 20, 21, 40, 41, 60, 61, 80
All F28P550Sxx devices in 64-pin PM package
5V FS Pins: ±500
40, 49, 50, 62
Corner pins on 64-pin PM: ±750
1, 16, 17, 32, 33, 48, 49, 64
All F28P550Sxx devices in 56-pin RSH package
5V FS Pins: ±500
37, 44, 45, 56
Corner pins on 56-pin RSH: ±750
1, 14, 15, 28, 29, 42, 43, 56
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings – Automotive

VALUE UNIT
All F28P559Sxx-Q1 devices in 128-pin PDT package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
5V FS Pins: ±500
79, 97, 98, 119
Charged device model (CDM), All pins ±500
per AEC Q100-011
Corner pins on 128-pin PDT: ±750
1, 32, 33, 64, 65, 96, 97, 128
All F28P559Sxx-Q1 devices in 100-pin PZ package
AEC Q100-002(1)
5V FS Pins: ±500
64, 76,77, 90
per AEC Q100-011
Corner pins on 100-pin PZ: ±750
1, 25, 26, 50, 51, 75, 76, 100
All F28P559Sxx-Q1 devices in 80-pin PNA package
AEC Q100-002(1)
5V FS Pins: ±500
49, 60,61, 75
per AEC Q100-011
Corner pins on 80-pin PNA: ±750
1, 20, 21, 40, 41, 60, 61, 80
All F28P559Sxx-Q1 devices in 64-pin PM package
AEC Q100-002(1)
5V FS Pins: ±500
40, 49,50, 62
per AEC Q100-011
Corner pins on 64-pin PM: ±750
1, 16, 17, 32, 33, 48, 49, 64
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
Internal BOR enabled(3) VBOR-VDDIO(MAX) + VBOR-GB (2) 3.3 3.63
Device supply voltage, VDDIO and VDDA V
Internal BOR disabled 2.8 3.3 3.63
Device supply voltage, VDD 1.14 1.2 1.32 V
Device ground, VSS 0 V
Analog ground, VSSA 0 V
Supply ramp rate of VDDIO, VDD,
SRSUPPLY
VDDA with respect to VSS.(4)
Digital input voltage(6) VSS – 0.3 VDDIO + 0.3 V
Digital input voltage(GPIO2, 3, 9, and
VIN VSS – 0.3 5.5 V
32)(5)
Analog input voltage(6) VSSA – 0.3 VDDA + 0.3 V
Junction temperature, TJ (1) –40 150 °C
Free-Air temperature, TA –40 125 °C
(1) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
(2) See the Power Management Module (PMM) section.
(3) Internal BOR is enabled by default.
(4) See the Power Management Module Operating Conditions table.
(5) These pins support applied voltage prior to the device being powered
(6) Applying a VIN greater than VDDIO/VDDA or less than VSS/VSSA will turn on the ESD current clamping diode causing additional
current flow to the respective supply rail. VDDIO/VDDA voltage will internally rise and could impact other electrical characteristics.

6.5 Power Consumption Summary

Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations.
6.5.1 System Current Consumption - VREG Enable - Internal Supply
Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING MODE
This is an estimation of 30°C 92 mA
VDDIO current consumption current for a typical heavily
IDDIO 85°C 105 mA
during operational usage loaded application. Actual
currents will vary depending 125°C 115 mA
on system activity, I/O
electrical loading and
switching frequency. This
includes Core supply current
with Internal Vreg Enabled.
- CPU is running from RAM
- Flash is powered up
- X1/X2 crystal is powered up
VDDA current consumption - PLL is enabled,
IDDA 125°C 14 mA
during operational usage SYSCLK=Max Device
frequency
- Analog modules are
powered up
- Outputs are static without
DC Load
- Inputs are static high or low
IDLE MODE
- CPU is in IDLE mode 30°C 30 mA
VDDIO current consumption - Flash is powered down
IDDIO 85°C 36 mA
while device is in Idle mode - PLL is Enabled,
SYSCLK=Max Device 125°C 54 mA
Frequency, CPUCLK is gated
- Analog Modules are
VDDA current consumption while powered down
IDDA 125°C 3 mA
device is in Idle mode - Outputs are static without
DC Load
STANDBY MODE (PLL Enabled)
- CPU is in STANDBY mode 30°C 8 mA
IDDIO 85°C 14 mA
while device is in Standby mode- PLL is Enabled, SYSCLK &
CPUCLK are gated 125°C 29 mA
- X1/X2 crystal is powered
down
IDDA 125°C 3 mA
device is in Standby mode - Outputs are static without
DC Load

6.5.1 System Current Consumption - VREG Enable - Internal Supply (continued)

STANDBY MODE (PLL Disabled)
IDDIO 85°C 10 mA
while device is in Standby mode- PLL is Disabled, SYSCLK &
down
IDDA 125°C 3 mA
device is in Standby mode - Outputs are static without
DC Load
HALT MODE
- CPU is in HALT mode 30°C 4 mA
IDDIO 85°C 10 mA
while device is in Halt mode - PLL is Disabled, SYSCLK
and CPUCLK are gated 125°C 25 mA
down
IDDA 125°C 3 mA
device is in Halt mode - Outputs are static without
DC Load
FLASH ERASE/PROGRAM
VDDIO current consumption - CPU is running from RAM
IDDIO 91 128 mA
during Erase/Program cycle(1) - Flash going through
continuous Program/Erase
operation
- PLL is enabled, SYSCLK at
120 MHz.
- Peripheral clocks are turned
OFF.
VDDA current consumption - X1/X2 crystal is powered up
IDDA 0.1 8 mA
during Erase/Program cycle - Analog is powered down
DC Load
RESET MODE
30°C 10 mA
VDDIO current consumption
IDDIO 85°C 13 mA
while reset is active(2)
Device is under Reset 125°C 20 mA
VDDA current consumption while
IDDA 125°C 0.01 mA
reset is active(2)
(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, that is XRSn is low.

6.5.2 System Current Consumption - VREG Disable - External Supply

OPERATING MODE
This is an estimation of 30°C 85 mA
VDD current consumption during current for a typical heavily
IDD 85°C 96 mA
operational usage loaded application. Actual
currents will vary depending 125°C 115 mA
on system activity, I/O 30°C 13 mA
VDDIO current consumption electrical loading and
IDDIO switching frequency. This 85°C 17 mA
during operational usage
includes Core supply current 125°C 18 mA
with Internal Vreg Enabled.
- CPU is running from RAM
- Flash is powered up
- PLL is enabled,
SYSCLK=Max Device
VDDA current consumption frequency
IDDA 125°C 14 mA
during operational usage - Analog modules are
powered up
DC Load
IDLE MODE
- CPU is in IDLE mode 30°C 28 mA
VDD current consumption while - Flash is powered down
IDD 85°C 35 mA
device is in Idle mode - PLL is Enabled,
SYSCLK=Max Device 125°C 54 mA
Frequency, CPUCLK is gated 30°C 3 mA
VDDIO current consumption - X1/X2 crystal is powered up
IDDIO - Analog Modules are 85°C 6 mA
while device is in Idle mode
powered down 125°C 7 mA
VDDA current consumption while DC Load
IDDA 125°C 3 mA
device is in Idle mode - Inputs are static high or low
STANDBY MODE (PLL Enabled)
IDD 85°C 12 mA
device is in Standby mode - PLL is Enabled, SYSCLK &
- X1/X2 crystal is powered 30°C 3 mA
VDDIO current consumption down
IDDIO 85°C 6 mA
while device is in Standby mode - Analog Modules are
IDDA 125°C 3 mA
device is in Standby mode - Inputs are static high or low

6.5.2 System Current Consumption - VREG Disable - External Supply (continued)

STANDBY MODE (PLL Disabled)
IDD 85°C 8 mA
device is in Standby mode - PLL is Disabled, SYSCLK &
IDDIO 85°C 5 mA
while device is in Standby mode - Analog Modules are
IDDA 125°C 8 mA
device is in Standby mode - Inputs are static high or low
HALT MODE
- CPU is in HALT mode 30°C 2 mA
IDD 85°C 8 mA
device is in Halt mode - PLL is Disabled, SYSCLK
and CPUCLK are gated 125°C 29 mA
IDDIO - Analog Modules are 85°C 5 mA
while device is in Halt mode
IDDA 125°C 3 mA
device is in Halt mode - Inputs are static high or low
FLASH ERASE/PROGRAM
VDD current consumption during - CPU is running from RAM
IDD 80 108 mA
Erase/Program cycle(1) - Flash going through
continuous Program/Erase
IDDIO operation 11 20 mA
during Erase/Program cycle(1)
- PLL is enabled, SYSCLK at
100 MHz.
- Peripheral clocks are turned
OFF.
VDDA current consumption - Analog is powered down
IDDA 0.1 8 mA
during Erase/Program cycle - Outputs are static without
DC Load
RESET MODE
30°C 5 mA
VDD current consumption while
IDD 85°C 8 mA
reset is active(2)
125°C 15 mA
30°C 5 mA
Device is under Reset
IDDIO 85°C 5 mA
while reset is active(2)
125°C 5 mA
VDDA current consumption while
IDDA 125°C 0.01 mA
reset is active(2)
(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, that is XRSn is low.

6.5.3 Operating Mode Test Description

The System Current Consumption - VREG Enable - Internal Supply table, System Current Consumption - VREG
Disable - External Supply table, and Section 6.5.4 list the current consumption values for the operational mode
of the device. The operational mode provides an estimation of what an application might encounter. The test
condition for these measurements has the following properties:
• Code is executing from RAM.
• FLASH is read and kept in active state.
• No external components are driven by I/O pins.
• All peripherals have clocks enabled.
• The CPU is actively executing code.
• All analog peripherals are powered up. ADCs and DACs are periodically converting.
6.5.4 Reducing Current Consumption
The F28P55x devices provide some methods to reduce the device current consumption:
• One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the
application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. The Typical Current
Reduction per Disabled Peripheral table lists the typical current reduction that may be achieved by disabling
the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
6.5.4.1 Typical Current Reduction per Disabled Peripheral
For peripherals with multiple instances, the current quoted is for all modules combined.
PERIPHERAL IDDIO CURRENT REDUCTION (mA)
ADC(1) 1.0
CLA 0.56
CLB 1.41
CMPSS(1) 0.31
CPU TIMER 0.06
GPDAC 0.12
MCAN 1.01
DCC 0.08
eCAP 0.12
ERAD 1.56
EPG 0.32
ePWM (for 1 ePWM) 0.95
eQEP 0.18
SCI 0.50
I2C 0.51
SPI 0.11
FSI RX 0.34
FSI TX 0.27
PMBUS 0.28
(1) This current represents the current drawn by the digital portion of the each module.

6.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
Digital and Analog IO
IOH = IOH MIN VDDIO * 0.8
VOH High-level output voltage V
IOH = –100 μA VDDIO – 0.2
IOL = IOL MAX 0.4
VOL Low-level output voltage V
IOL = 100 µA 0.2
IOH High-level output source current for all output pins –4 mA
Low-level output sink
current for all output 4 mA
pins
IOL IO_DRVSEL:DRVSELG
Low-level output 4 mA
PIOx = 0
sink current for
GPIO2/3/9/32 IO_DRVSEL:DRVSELG
12 mA
PIOx = 1
ROH High-level output impedance for all output pins VOH=VDDS-0.4V 50 66 96 Ω
Low-level output
impedance for all output 48 60 84 Ω
pins
ROL IO_DRVSEL:DRVSELG VOL=0.4V
Low-level output 48 60 84 Ω
PIOx = 0
impedance for
GPIO2/3/9/32 IO_DRVSEL:DRVSELG
15 21 33 Ω
PIOx = 1
High-level input voltage 2.0 V
High-level input voltage
2.21 V
- GPIO23/41
VIH IO_MODSEL:MODSEL
0.7*VDDIO V
High-level input voltage GPIOx = 0
- GPIO2/3/9/32 IO_MODSEL:MODSEL
1.35 V
GPIOx = 1
Low-level input voltage 0.8 V
IO_MODSEL:MODSEL
0.3*VDDIO V
VIL Low-level input voltage - GPIOx = 0
GPIO2/3/9/32 IO_MODSEL:MODSEL
0.8 V
GPIOx = 1
Input hysteresis (AIO) 115
VHYSTERESIS mV
Input hysteresis (GPIO) 115
VDDIO = 3.3 V
IPULLDOWN Input current Pins with pulldown 120 µA
VIN = VDDIO
Digital inputs with pullup VDDIO = 3.3 V
IPULLUP Input current 160 µA
enabled(1) VIN = 0 V
RPULLDOWN Weak pulldown resistance 22 31 62 kΩ
19 29 54 kΩ
RPULLUP Weak pullup resistance
GPIO2/3/9/32 20 31 65 kΩ

6.6 Electrical Characteristics (continued)

TEST
CONDITIONS
Digital inputs Pullups and outputs
Pin leakage (all inputs except disabled 0.150
GPIO2/3/9/32) 0 V ≤ VIN ≤ VDDIO
Pin leakage
Pullups and outputs
(Device-powered).
Digital inputs disabled
See the Special 30
(GPIO2/3/9/32) 0 V ≤ VIN ≤ 5.5 V
Considerations for 5V
VDDIO = 3.3 V
ILEAK Fail-Safe Pins section. µA
Pullups and outputs
Pin leakage Digital inputs disabled
5
(Device-unpowered) (GPIO2/3/9/32) 0 V ≤ VIN ≤ 5.5 V
VDDIO = 0 V
Analog drivers
Pin leakage Analog pins disabled 0.150
0 V ≤ VIN ≤ VDDA
Digital inputs 2
CI Input capacitance pF
Analog pins(2)
VREG and BOR
VREG, POR,
BOR(3)
(1) See the Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown.
(2) The analog pins are specified separately; see the Per-Channel Parasitic Capacitance tables that are in the ADC Input Model section.
(3) See the Power Management Module (PMM) section.

6.7 Special Considerations for 5V Fail-Safe Pins

GPIO2, GPIO3, GPIO9, and GPIO32 are 5V Fail-Safe (5V FS) pins on this device. This means two things:
• These pins can accept a voltage input of up to 5.5V, regardless of the supply voltage (VDDIO) level.
• These pins are also "Fail-Safe", meaning they can also have voltage applied to them prior to the device being
powered.
In order to achieve the above characteristics, the construction of the input buffer of these GPIOs is different
from the other GPIOs on this device. As such, there is both an additional leakage current parameter defined
(unpowered leakage), and a behavioral difference for the powered leakage current when the device is powered.
Figure 6-1 shows the typical leakage current profile for these pins. As shown in the figure, there is an increased
leakage current present as the voltage on the pin exceeds the device's supply (VDDIO) voltage. It is during
this transition phase that the highest leakage current is observed. Once the input pin voltage is greater than
approximately 4V, the current settles to a nominal value through the remainder of the input voltage range.
Figure 6-1. Leakage Current vs Input Voltage (Device Powered)

6.8 Thermal Resistance Characteristics for PDT Package

°C/W(1)
RΘJC Junction-to-case thermal resistance 10.6
RΘJB Junction-to-board thermal resistance 24.9
RΘJA (High k PCB) Junction-to-free air thermal resistance 42.5
PsiJT Junction-to-package top 0.4
PsiJB Junction-to-board 24.4
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
6.9 Thermal Resistance Characteristics for PZ Package

°C/W(1)
RΘJC Junction-to-case thermal resistance 11
6.10 Thermal Resistance Characteristics for PNA Package

°C/W(1)

6.11 Thermal Resistance Characteristics for PM Package

°C/W(1)
RΘJA (High k PCB) Junction-to-free air thermal resistance 45
6.12 Thermal Resistance Characteristics for RSH Package

°C/W(1)
Junction-to-case thermal resistance(top) 11.6
RΘJC
Junction-to-case thermal resistance(bottom) 1.2
6.13 Thermal Design Considerations

Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems
that exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application note Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.

6.14 System
6.14.1 Power Management Module (PMM)
6.14.1.1 Introduction
The Power Management Module (PMM) handles all the power management functions required for device
operation.
6.14.1.2 Overview
The block diagram of the PMM is shown in Figure 6-2. As can be seen, the PMM comprises of various
subcomponents, which are described in the subsequent sections.
To Rest of Chip
MCU
PMM
I/O CPU Reset
POR RISE Release
DELAY
(80us)
I/O
BOR Internal
All RISE DELAY
Monitors (Ext VREG = 320us)
Release (Int VREG = 40us)
Signal
EN
VMONCTL.bit.BORLVMONDIS
VDD
POR
EN
OUT
IN
Internal 1.2v LDO Internal

VREG
VREGENZ
VDDIO
XRSn
VDD
VSS
VSS
External External
CVDDIO CVDD
Figure 6-2. PMM Block Diagram
6.14.1.2.1 Power Rail Monitors

The PMM has voltage monitors on the supply rails that release the XRSn signal high once the voltages cross the
set threshold during power up. They also function to trip the XRSn signal low if any of the voltages drop below
the programmed levels. The various voltage monitors are described in subsequent sections.
Note
Not all the voltage monitors are supported for device operation in an application after boot up. In the
case where a voltage monitor is not supported, an external supervisor is recommended if the device
needs supply voltage monitoring while the application is running.
The three voltage monitors (I/O POR, I/O BOR, VDD POR) all have to release their respective outputs before the
device begins operation (that is, XRSn goes high). However, if any of the voltage monitors trips, XRSn is driven
low. The I/Os are held in high impedance when any of the voltage monitors trip.

6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor

The I/O POR monitor supervises the VDDIO rail. During power up, this is the first monitor to release (that is, first
to untrip) on VDDIO.
6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
The I/O BOR monitor also supervises the VDDIO rail. During power up, this is the second monitor to release
(that is, second to untrip) on VDDIO. This monitor has a tighter tolerance compared to the I/O POR.
Any drop in voltage below the recommended operating voltages will trip the I/O BOR and reset the device but
this can be disabled by setting VMONCTL.bit.BORLVMONDIS to 1. The I/O BOR can only be disabled after the
device has fully booted up. If the I/O BOR is disabled, the I/O POR will reset the device for voltage drops.
Note
The level at which the I/O POR trips is well below the minimum recommended voltage for VDDIO, and
therefore should not be used for device supervision.
Figure 6-3 shows the operating region of the I/O BOR.
3.63 V +10%
Recommended
System Voltage
3.3 V 0% Regulator Range
VDDIO
Operating
Range
3.1 V –6.1%
VBOR-GB
BOR Guard Band
3.0 V –9.1%
VBOR-VDDIO
Internal BOR Threshold
2.81 V –14.8%
2.80 V –15.1%
Figure 6-3. I/O BOR Operating Region
6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor

The VDD POR monitor supervises the VDD rail. During power up, this monitor releases (that is, untrips) once the
voltage crosses the programmed trip level on VDD.
Note
VDD POR is programmed at a level below the minimum recommended voltage for VDD, and therefore
it should not be relied upon for VDD supervision if that is required in the application.
6.14.1.2.2 External Supervisor Usage

VDDIO Monitoring: The I/O BOR is supported for application use, so an external supervisor is not required to
monitor the I/O rail.

VDD Monitoring:
• VDD supplied from the internal VREG: The VDD supply is derived from the VDDIO supply. The VREG is
designed in such a way that a valid VDDIO supply(monitored by the IO BOR) implies a valid VDD supply.
• VDD supplied from an external supply: The VDD POR is not supported for application use. If VDD monitoring
is required by the application, an external supervisor can be used to monitor the VDD rail.
Note
The use of an external supervisor with the internal VREG is not supported.If VDD monitoring is
required by the application, a package with a VREGENZ pin must be used to power VDD externally.
6.14.1.2.3 Delay Blocks

The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage
monitors and XRSn. This is to ensure that the voltages are stable when XRSn releases. The delay blocks are
only active during power up (that is, when VDDIO and VDD are ramping up).
The delay blocks contribute to the minimum slew rates specified in Power Management Module Electrical Data
and Timing for the power rails.
Note
The delay numbers specified in the block diagram are typical numbers.
6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)

The internal VREG is supplied by the VDDIO rail and can generate the 1.2 V required to power the VDD pins.
Although the internal VREG eliminates the need to use an external supply for VDD, decoupling capacitors are
still required on the VDD pins for VREG stability and transients. See the VDD Decoupling section for details.
6.14.1.2.5 VREGENZ
The VREGENZ (VREG disable) pin controls the state of the internal VREG. To enable the internal VREG,
connect the VREGENZ pin to a logic low voltage. For applications supplying VDD externally (external VREG),
disable the internal VREG by tying the VREGENZ pin high.
Note
Not all device packages have VREGENZ pinned out. For packages without VREGENZ, external
VREG mode is not supported.
6.14.1.3 External Components
6.14.1.3.1 Decoupling Capacitors

VDDIO and VDD require decoupling capacitors for correct operation. The requirements are outlined in
subsequent sections.
6.14.1.3.1.1 VDDIO Decoupling
Place a minimum amount of decoupling capacitance on VDDIO. See the CVDDIO parameter in Power
Management Module Electrical Data and Timing. The actual amount of decoupling capacitance to use is a
requirement of the power supply driving VDDIO. Either of the configurations outlined below is acceptable:
• Configuration 1: Place a decoupling capacitor on each VDDIO pin per the CVDDIO parameter.
• Configuration 2: Install a single decoupling capacitor that is the equivalent of CVDDIO * VDDIO pins.
Note
Having the decoupling capacitor or capacitors close to the device pins is critical.

6.14.1.3.1.2 VDD Decoupling

Place a minimum amount of decoupling capacitance on VDD. See the CVDD TOTAL parameter in Power
Management Module Electrical Data and Timing.
In external VREG mode, the actual amount of decoupling capacitance to use is a requirement of the power
supply driving VDD.
Either of the configurations outlined below is acceptable:
• Configuration 1: Divide CVDD TOTAL equally across the VDD pins. In this configuration, the VDD pins may
be separated at the PCB level.
• Configuration 2: Install a single decoupling capacitor with value of CVDD TOTAL. In this configuration, all
VDD pins must be connected to each other on the PCB.
Note
Having the decoupling capacitor or capacitors close to the device pins is critical.
6.14.1.4 Power Sequencing

6.14.1.4.1 Supply Pins Ganging
Connecting all 3.3-V rails together and supplying from a single source are strongly recommended. This list
includes:
• VDDIO
• VDDA
In addition, connect all power pins to avoid leaving any unconnected.
In external VREG mode, the VDD pins should be tied together and supplied from a single source.
In internal VREG mode, tying the VDD pins together is optional as long as each VDD pin has a capacitor
connected to pin. See the VDD Decoupling section for VDD decoupling configurations.
The analog modules on the device have fairly high PSRR; therefore, in most cases, noise on VDDA will
have to exceed the recommended operating conditions of the supply rails before the analog modules see
performance degradation. Therefore, supplying VDDA separately typically offers minimal benefits. Nevertheless,
for the purposes of noise improvement, placing a pi filter between VDDIO and VDDA is acceptable.
Note
All the supply pins per rail are tied together internally. For example, all VDDIO pins are tied together
internally, all VDD pins are tied together internally, and so forth.
6.14.1.4.2 Signal Pins Power Sequence

Before powering the device, do not apply voltage larger than 0.3 V above VDDIO or 0.3 V below VSS to any
digital pin and 0.3 V above VDDA or 0.3 V below VSSA to any analog pin (including VREFHI). Simply, the signal
pins should only be driven after XRSn goes high, provided all the 3.3-V rails are tied together. This sequencing is
still required even if VDDIO and VDDA are not tied together.
CAUTION
If the above sequence is violated, device malfunction and possibly damage can occur as current will
flow through unintended parasitic paths in the device.

6.14.1.4.3 Supply Pins Power Sequence
6.14.1.4.3.1 External VREG/VDD Mode Sequence

Figure 6-4 depicts the power sequencing requirements for external VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.
VDDIO VDDIO
(A)
VBOR-VDDIO-UP VDD VDD VBOR-VDDIO-DN(B)
Internal Internal All
All Monitors Release Monitors Release
Signal(C) Signal(D)
XRSn XRSn
SRVDDIO-UP SRVDD-UP SRVDD-DN SRVDDIO-DN
VPOR-VDDIO VPOR-VDD-UP(A) VPOR-VDD-DN(B) VPOR-VDDIO

VDDIO - VDD
Delay
VDDIO-MON-TOT-DELAY VXRSn-PU-DELAY VXRSn-PD-DELAY
A. This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table.
B. This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table.
C. During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block
Diagram.
D. During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block
Diagram.
Figure 6-4. External VREG Power Up Sequence
• For Power Up:

1. VDDIO (that is, the 3.3-V rail) should come up first with the minimum slew rate specified.
2. VDD (that is, the 1.2-V rail) should come up next with the minimum slew rate specified.
3. The time delta between the VDDIO rail coming up and when the VDD rail can come up is also specified.
4. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PD-DELAY, XRSn will be released and the
device starts the boot-up sequence.
5. The I/O BOR monitor has different release points during power up and power down.
6. During power up, both VDDIO and VDD rails have to be up before XRSn releases.
• For Power Down:
1. There is no requirement between VDDIO and VDD on which should power down first; however, there is a
minimum slew rate specification.
3. Any of the POR or BOR monitors that trips during power down will cause XRSn to go low after
VXRSN-PD-DELAY.
Note
The All Monitors Release Signal is an internal signal.
Note
If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does not
start until the XRSn pin is released by all internal and external sources.

6.14.1.4.3.2 Internal VREG/VDD Mode Sequence

Figure 6-5 depicts the power sequencing requirements for internal VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.
VDDIO VDDIO
VBOR-VDDIO-UP(A) VBOR-VDDIO-DN(B)
Internal Internal All
All Monitors Release Monitors Release
Signal(C) Signal(D)
XRSn XRSn
SRVDDIO-UP SRVDDIO-DN
VPOR-VDDIO VPOR-VDDIO
VDDIO-MON-TOT-DELAY VXRSn-PU-DELAY VXRSn-PD-DELAY
A. This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table.
B. This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table.
C. During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block
Diagram.
D. During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block
Diagram.
Figure 6-5. Internal VREG Power Up Sequence
• For Power Up:

1. VDDIO (that is, the 3.3-V rail) should come up with the minimum slew rate specified.
2. The Internal VREG powers up after the I/O monitors (I/O POR and I/O BOR) are released.
3. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PU-DELAY, XRSn will be released and the
device starts the boot-up sequence.
• For Power Down:
1. The only requirement on VDDIO during power down is the slew rate.
3. The I/O BOR tripping will cause XRSn to go low after VXRSN-PD-DELAY and also power down the Internal
VREG.
Note
The All Monitors Release Signal is an internal signal.
Note
If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does not
start until the XRSn pin is released by all internal and external sources.
6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations

The acceptable power-up sequence for the rails is summarized below. "Power up" here means the rail in
question has reached the minimum recommended operating voltage.
CAUTION
Non-acceptable sequences leads to reliability concerns and possibly damage.
For simplicity, connecting all 3.3-V rails together and following the descriptions in Supply Pins Power Sequence
is recommended.

Table 6-1. External VREG Sequence Summary
RAILS POWER-UP ORDER
CASE ACCEPTABLE
VDDIO VDDA VDD
A 1 2 3 Yes
B 1 3 2 Yes
C 2 1 3 No
D 2 3 1 No
E 3 2 1 No
F 3 1 2 No
G 1 1 2 Yes
H 2 2 1 No
Table 6-2. Internal VREG Sequence Summary

RAILS POWER-UP ORDER
CASE ACCEPTABLE
VDDIO VDDA
A 1 2 Yes
B 2 1 No
C 1 1 Yes
Note
The analog modules on the device should only be powered after VDDA has reached the minimum
recommended operating voltage.
6.14.1.4.3.4 Supply Slew Rate

VDDIO has a minimum slew rate requirement. If the minimum slew rate is not met, XRSn might toggle a few
times until VDDIO crosses the I/O BOR region.
Note
The toggling on XRSn has no adverse effect on the device as boot only starts once XRSn is steadily
high. However if XRSn from the device is used to gate the reset signal of other ICs, then the slew rate
requirement should be met to prevent this toggling.
VDD has a minimum slew rate requirement in external VREG mode. If the minimum slew rate is not met, the
VDD POR may release before the VDD operational minimum voltage is met and the device may not start in a
properly reset state.

6.14.1.5 Power Management Module Electrical Data and Timing

6.14.1.5.1 Power Management Module Operating Conditions
General
VDDIO Capacitance Per
CVDDIO (1) (2) 0.1 uF
Pin(7)
CVDDA (1) (2) VDDA Capacitance Per Pin(7) 2.2 uF
Supply Ramp Rate of 3.3V
SRVDD33 (3) 20 100 mV/us
Rails (VDDIO, VDDA)
VBOR-VDDIO-GB VDDIO Brown Out Reset
(5) 0.1 V
Voltage Guardband
External VREG
CVDD
Total VDD Capacitance(7) 10 uF
TOTAL(1) (4)
Supply Ramp Rate of 1.2V
SRVDD12 (3) 10 100 mV/us
Rail (VDD)
VDDIO - VDD Ramp Delay Between VDDIO
0 us
Delay(6) and VDD
Internal VREG
CVDD Total Nominal VDD
10 22 uF
TOTAL(1) (4) Capacitance(7)
(1) A bulk capacitor should also be used. The exact value of the decoupling capacitance depends on the system voltage regulation
solution that is supplying these pins.
(2) It is recommended to tie the 3.3V rails (VDDIO, VDDA) together and supply them from a single source.
(3) See the Supply Slew Rate section. Supply ramp rate faster than the maximum can trigger the on-chip ESD protection.
(4) See the Power Management Module (PMM) section on possible configurations for the total decoupling capacitance.
(5) TI recommends VBOR-VDDIO-GB to avoid BOR-VDDIO resets due to normal supply noise or load-transient events on the 3.3-V VDDIO
system regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are
important to prevent activation of the BOR-VDDIO during normal device operation. The value of VBOR-VDDIO-GB is a system-level design
consideration; the voltage listed here is typical for many applications.
(6) Delay between when the 3.3-V rail ramps up and when the 1.2-V rail ramps up. See the VREG Sequence Summary table for the
allowable supply ramp sequences.
(7) Max capacitor tolerance should be 20%.
6.14.1.5.2 Power Management Module Characteristics

Internal Voltage Regulator
VVREG 1.152 1.2 1.248 V
Output
Internal Voltage Regulator
VVREG-PU 350 us
Power Up Time
VVREG-INRUSH Internal Voltage Regulator
(4) 650 mA
Inrush Current
VDDIO Power on Reset Before and After XRSn
VPOR-VDDIO 2.3 V
Voltage Release
VBOR-VDDIO-UP VDDIO Brown Out Reset
(1) Before XRSn Release 2.7 V
Voltage on Ramp Up
VBOR-VDDIO- VDDIO Brown Out Reset
(1) After XRSn Release 2.81 3.0 V
DOWN Voltage on Ramp Down
XRSn Release Delay after
VXRSn-PU-
(2) Supplies are Ramped Up 40 us
DELAY
During Power-Up
XRSn Trip Delay after
VXRSn-PD-
(3) Supplies are Ramped Down 2 us
DELAY
During Power-Down

6.14.1.5.2 Power Management Module Characteristics (continued)

VDDIO-MON- Total Delays in Path of
80 us
TOT-DELAY VDDIO Monitors (POR, BOR)
XRSn Release Delay after a
40 us
VDD POR Event
VXRSn-MON- XRSn Release Delay after a Supplies Within Operating
40 us
RELEASE-DELAY VDDIO BOR Event Range
XRSn Release Delay after a
120 us
VDDIO POR Event
(1) See the I/O BOR Operating Region figure.

(2) Supplies are considered fully ramped up after they cross the minimum recommended operating conditions for the respective rail. All
POR and BOR monitors need to be released before this delay takes effect.
(3) On power down, any of the POR or BOR monitors that trips will immediately trip XRSn. This delay is the time between any of the POR,
BOR monitors tripping and XRSn going low. It is variable and depends on the ramp down rate of the supply.
(4) This is the transient current drawn on the VDDIO rail when the internal VREG turns on. Due to this, there might be some voltage drops
on the VDDIO rail when the VREG turns on which could cause the VREG to ramp up in steps. There is no detriment to the device from
this but the effect can be reduced if desired by using sufficient decoupling capacitors on VDDIO or picking an LDO/DC-DC that can
supply this transient current.

6.14.2 Reset Timing

XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR) and brown-out reset (BOR) monitors. During power up, the monitor circuits keep the XRSn pin low.
For more details, see the Power Management Module (PMM) section. A watchdog or NMI watchdog reset will
also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should
be placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow
the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 6-6 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
Optional open-drain
XRSn
Reset source
£100 nF
Figure 6-6. Reset Circuit
6.14.2.1 Reset Sources

The Reset Signals table summarizes the various reset signals and their effect on the device.
Table 6-3. Reset Signals
Reset Source CPU Core Reset Peripherals JTAG / Debug IOs XRS Output
(C28x, FPU, TMU) Reset Logic Reset
POR Yes Yes Yes Hi-Z Yes
BOR Yes Yes Yes Hi-Z Yes
XRS Pin Yes Yes No Hi-Z -
WDRS Yes Yes No Hi-Z Yes
NMIWDRS Yes Yes No Hi-Z Yes
SYSRS (Debugger Reset) Yes Yes No Hi-Z No
SCCRESET Yes Yes No Hi-Z No
SIMRESET. XRS Yes Yes No Hi-Z Yes
SIMRESET. CPU1RS Yes Yes No Hi-Z No
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP.

6.14.2.2 Reset Electrical Data and Timing

6.14.2.2.1 Reset - XRSn - Timing Requirements
MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1.5 ms
tw(RSL2) Pulse duration, XRSn low on warm reset 3.2 µs
6.14.2.2.2 Reset - XRSn - Switching Characteristics

tw(RSL1) Pulse duration, XRSn driven low by device after supplies are stable 100 µs
tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles
tboot-flash Boot-ROM execution time to first instruction fetch in flash 1.2 ms
6.14.2.2.3 Reset Timing Diagrams
VDDIO VDDA
(3.3V)
VDD (1.2V)
tw(RSL1)
XRSn(A)
tboot-flash
Boot ROM
CPU
Execution
Phase
User code
th(boot-mode)(B) User code dependent
Boot-Mode GPIO pins as input

Pins
Boot-ROM execution starts Peripheral/GPIO function
Based on boot code
GPIO pins as input (pullups are disabled)

I/O Pins
User code dependent
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see the Pin Attributes table. On-chip monitors will
hold this pin low until the supplies are in a valid range.
B. After reset from any source (see the Reset Sources section), the boot ROM code samples Boot Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on
conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based
on user environment and could be with or without PLL enabled.
Figure 6-7. Power-on Reset

tw(RSL2)
XRSn
User code
CPU
Execution User code Boot ROM
Phase
Boot ROM execution starts
(initiated by any reset source) th(boot-mode)(A)
Boot-Mode Peripheral/GPIO function GPIO Pins as Input Peripheral/GPIO function

Pins
User-Code Execution Starts
I/O Pins User-Code Dependent GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
A. After reset from any source (see the Reset Sources section), the Boot ROM code samples BOOT Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on
conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be
based on user environment and could be with or without PLL enabled.
Figure 6-8. Warm Reset

6.14.3 Clock Specifications

6.14.3.1 Clock Sources
Table 6-4. Possible Reference Clock Sources
CLOCK SOURCE DESCRIPTION
INTOSC1 Internal oscillator 1.
10-MHz internal oscillator.
INTOSC2(1) Internal oscillator 2.
10-MHz internal oscillator.
X1 (XTAL) External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).

WDCLK Watchdog
Timer
PERCLKDIVSEL.USBCLKDIV
/1 CLBCLKCTL
/2
. SYSCLK
USBBITCLK
.
.
/8 CLB_TILE_CLK
/1 /1 or /2
PLLCLK
/2
.
.
CLB_REG_CLK
.
SYSCLKDIVSEL /8
SYSCLK
SYS PLLSYSCLK
Divider NMIWD
INTOSC1 SYSPLL PLLRAWCLK
INTOSC2 OSCCLK
PLLCLKEN
X1 (XTAL)
OSCCLKRCSEL CPUCLK
CPU FPU
TMU
GSx RAMs
Boot ROM CLA ROM LSx RAMs
SYSCLK SYSCLK ePIE DCSM Mx RAMs
FLASH XINT Message RAM
GPIO WD System Control
KDIV
Flash Wrapper Clock FLCLK

Flash Wrapper
Divider
One per SYSCLK peripheral

ADC
CLA AES
PCLKCRx CMPSS
CPUTIMERs CLB
PERx.SYSCLK GPDAC
EPWM ERAD
PGA
ECAP EPG
DCC
EQEP FSI
PMBUS
HRCAL I2C
USB
LSPCLKDIV
PCLKCRx
LSP LSPCLK PERx.LSPCLK SCI
Divider SPI

LINACLKDIV PLLRAWCLK LIN Xmit
PCLKCRx Clock Gen
PERx.LINACLK
LIN Clock LINACLK LIN
Divider

NPUCLKDIV
PCLKCRx
PERx.NPUCLK
NPU Clock NPUCLK NPU
Divider
AUXCLKDIVSEL.MCANxCLKDIV
/1
0
/2
Reserved 1
.
AUXCLKIN(GPIO29) MCAN Bit Clock
2 .
PLLRAWCLK 3 .
/20
CLKSRCCTL2.MCANxBCLKSEL
Figure 6-9. Clocking System

SYSPLL
OSCCLK ÷ INTCLK VCOCLK ÷ PLLRAWCLK

VCO
(REFDIV+1) (ODIV+1)
÷
IMULT
Figure 6-10. System PLL
In the System PLL figure,
fOSCCLK
fPLLRAWCLK = × IMULT (1)
REFDIV + 1 ODIV + 1

6.14.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
6.14.3.2.1.1 Input Clock Frequency
MIN MAX UNIT
f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz
f(X1) Frequency, X1, from external oscillator 10 25 MHz
6.14.3.2.1.2 XTAL Oscillator Characteristics

X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V
X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V
6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
PARAMETER MIN MAX UNIT
X1 VIL Valid low-level input voltage (Buffer) –0.3 0.3 * VDDIO V
X1 VIH Valid high-level input voltage (Buffer) 0.7 * VDDIO VDDIO + 0.3 V
6.14.3.2.1.4 X1 Timing Requirements

MIN MAX UNIT
tf(X1) Fall time, X1 6 ns
tr(X1) Rise time, X1 6 ns
tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55%
tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55%
6.14.3.2.1.5 AUXCLKIN Timing Requirements

MIN MAX UNIT
tf(AUXI) Fall time, AUXCLKIN 6 ns
tr(AUXI) Rise time, AUXCLKIN 6 ns
tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55%
tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55%
6.14.3.2.1.6 APLL Characteristics

PLL Lock time
SYS PLL Lock Time(1) 5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)) us
(1) The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().

6.14.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled

PARAMETER(1) MIN MAX UNIT
tf(XCO) Fall time, XCLKOUT 6 ns
tr(XCO) Rise time, XCLKOUT 6 ns
tw(XCOL) Pulse duration, XCLKOUT low H – 2(2) H + 2(2) ns
tw(XCOH) Pulse duration, XCLKOUT high H– 2(2) H+ 2(2) ns
f(XCO) Frequency, XCLKOUT 50 MHz
(1) A load of 6 pF is assumed for these parameters.

(2) H = 0.5tc(XCO)
6.14.3.2.1.8 Internal Clock Frequencies

MIN NOM MAX UNIT
f(SYSCLK) Frequency, device (system) clock 2 150 MHz
tc(SYSCLK) Period, device (system) clock 6.67 500 ns
f(INTCLK) Frequency, system PLL going into VCO (after REFDIV) 2 20 MHz
f(VCOCLK) Frequency, system PLL VCO (before ODIV) 220 600 MHz
f(PLLRAWCLK) Frequency, system PLL output (before SYSCLK divider) 6 300 MHz
f(PLL) Frequency, PLLSYSCLK 2 150 MHz
f(PLL_LIMP) Frequency, PLL Limp Frequency (1) 45/(ODIV+1) MHz
f(LSP) Frequency, LSPCLK 2 150 MHz
tc(LSPCLK) Period, LSPCLK 6.67 500 ns
Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or
f(OSCCLK) See respective clock MHz
X1)
f(EPWM) Frequency, EPWMCLK 150 MHz
f(HRPWM) Frequency, HRPWMCLK 60 150 MHz
f(NPU) Frequency, NPUCLK 37.5 75 MHz
(1) PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).

6.14.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
• A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 6-11,
with the XTALCR.SE bit set to 1.
• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 6-12.
• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 6-13.
Microcontroller Microcontroller
GPIO19 GPIO18* GPIO19 GPIO18

VSS X1 X2 VSS X1 X2
* Available as a
+3.3 V
GPIO when X1 is
used as a clock
VDD Out
3.3-V Oscillator
Gnd
Figure 6-12. External Crystal

Figure 6-11. Single-ended 3.3-V External Clock
Microcontroller
GPIO19 GPIO18
VSS X1 X2
Figure 6-13. External Resonator
6.14.3.4 XTAL Oscillator

6.14.3.4.1 Introduction
The crystal oscillator in this device is an embedded electrical oscillator that, when paired with a compatible
quartz crystal (or a ceramic resonator), can generate the system clock required by the device.
6.14.3.4.2 Overview
The following sections describe the components of the electrical oscillator and crystal.
6.14.3.4.2.1 Electrical Oscillator
The electrical oscillator in this device is a Pierce oscillator. It is a positive feedback inverter circuit that requires a
tuning circuit in order to oscillate. When this oscillator is paired with a compatible crystal, a tank circuit is formed.
This tank circuit oscillates at the fundamental frequency of the crystal. On this device, the oscillator is designed
to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure
6-14 illustrates the components of the electrical oscillator and the tank circuit.

MCU To Rest of Chip
XTAL Oscillator
Buffer
Comp
1
XCLKOUT
Circuit
[XTAL On]
Rbias
XCLKOUT
Pierce Inverter
Internal Internal
GPIO
X1
X2
External External
Rd
Crystal
CL1 CL2
GND GND
Figure 6-14. Electrical Oscillator Block Diagram
6.14.3.4.2.1.1 Modes of Operation

The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode.
6.14.3.4.2.1.1.1 Crystal Mode of Operation
In the crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2.
This mode of operation is engaged when [XTAL On] = 1, which is achieved by setting XTALCR.OSCOFF = 0
and XTALCR.SE = 0. There is an internal bias resistor for the feedback loop so an external one should not be
used. Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias
point of operation and possibly leading to clipped waveforms, out-of-specification duty cycle, and reduction in the
effective negative resistance.
In this mode of operation, the resultant clock on X1 is passed through a comparator (Comp) to the rest of the
chip. The clock on X1 needs to meet the VIH and VIL of the comparator. See the XTAL Oscillator Characteristics
table for the VIH and VIL requirements of the comparator.
6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz
crystal should not be used in this mode.
This mode is enabled when [XTAL On] = 0, which can be achieved by setting XTALCR.OSCOFF = 1 and
XTALCR.SE = 1.

In this mode of operation, the clock on X1 is passed through a buffer (Buffer) to the rest of the chip. See
the X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input
requirements of the buffer.
6.14.3.4.2.1.2 XTAL Output on XCLKOUT
The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for
observation by configuring the CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers.
See the GPIO Muxed Pins table for a list of GPIOs that XCLKOUT comes out on.
6.14.3.4.2.2 Quartz Crystal
Electrically, a quartz crystal can be represented by an LCR (Inductor-Capacitor-Resistor) circuit. However, unlike
an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped.
Components of the crystal are shown in Figure 6-15 and explained below.
Quartz Crystal
Internal External
Cm
Rm C0 CL
Lm
Figure 6-15. Crystal Electrical Representation
Cm (Motional capacitance): Denotes the elasticity of the crystal.

Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but
can be approximated as such depending on the values of the other crystal components.
Lm (Motional inductance): Denotes the vibrating mass of the crystal.
C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package
capacitance.
CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external to
the crystal. The frequency ppm specified in the crystal data sheet is usually tied to the CL parameter.
Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins, while
some crystal manufacturers specify CL as the capacitance on just one of the crystal pins. Check with the crystal
manufacturer for how the CL is specified in order to use the correct values in calculations.
From Figure 6-14, CL1 and CL2 are in series; so, to find the equivalent total capacitance seen by the crystal, the
capacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1 = CL2.
It is recommended that a stray PCB capacitance be added to this value. 3 pF to 5 pF are reasonable estimates,
but the actual value will depend on the PCB in question.
Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has
to satisfy both the electrical oscillator and the crystal.

The effect of CL on the crystal is frequency-pulling. If the effective load capacitance is lower than the target, the
crystal frequency will increase and vice versa. However, the effect of frequency-pulling is usually very minimal
and typically results in less than 10-ppm variation from the nominal frequency.
6.14.3.4.2.3 GPIO Modes of Operation
On this device, X1 and X2 can be used as GPIO19 and GPIO18, respectively, depending on the operating mode
of the XTAL. Refer to the External Oscillator (XTAL) section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual .
6.14.3.4.3 Functional Operation
6.14.3.4.3.1 ESR – Effective Series Resistance

Effective Series Resistance is the resistive load the crystal presents to the electrical oscillator at resonance. The
higher the ESR, the lower the Q, and less likely the crystal will start up or maintain oscillation. The relationship
between ESR and the crystal components is indicated below.
2
ESR = Rm * 1 + C0
CL (2)
Note that ESR is not the same as motional resistance of the crystal, but can be approximated as such if the
effective load capacitance is much greater than the shunt capacitance.
6.14.3.4.3.2 Rneg – Negative Resistance
Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount of
energy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. Rneg
depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of the
circuit.
The generally accepted practice is to have Rneg > 3x ESR to 5x ESR to ensure the crystal starts up under
all conditions. Note that it takes slightly more energy to start up the crystal than it does to sustain oscillation;
therefore, if it can be ensured that the negative resistance requirement is met at start-up, then oscillation
sustenance will not be an issue.
Figure 6-16 and Figure 6-17 show the variation between negative resistance and the crystal components for this
device. As can be seen from the graphs, the crystal shunt capacitance (C0) and effective load capacitance (CL)
greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs; so, refer to
Table 6-5 for minimum and maximum values for design considerations.
6.14.3.4.3.3 Start-up Time
Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned
in the Rneg – Negative Resistance section, for reliable start-up across all conditions, it is recommended that the
Rneg > 3x ESR to 5x ESR of the crystal.
Crystal ESR and the dampening resistor (Rd) greatly affect the start-up time. The higher the two values, the
longer the crystal takes to start up. Longer start-up times are usually a sign that the crystal and components are
not a correct match.
Refer to Crystal Oscillator Specifications for the typical start-up times. Note that the numbers specified here are
typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question and
the external components.
6.14.3.4.3.3.1 X1/X2 Precondition
On this device, the GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the
crystal if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a known
state before the XTAL is turned on. See the TMS320F28P55x Real-Time Microcontrollers Technical Reference
Manual for details.

6.14.3.4.3.4 DL – Drive Level

Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The
maximum drive level specified in the crystal manufacturer’s data sheet is usually the maximum the crystal can
dissipate without damage or significant reduction in operating life. On the other hand, the drive level specified
by the electrical oscillator is the maximum power it can provide. The actual power provided by the electrical
oscillator is not necessarily the maximum power and depends on the crystal and board components.
For cases where the actual drive level from the electrical oscillator exceeds the maximum drive level
specification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce the
power dissipated by the crystal. Note that Rd reduces the circuit gain; and therefore, the actual value to use
should be evaluated to make sure all other conditions for start-up and sustained oscillation are met.
6.14.3.4.4 How to Choose a Crystal
Using Crystal Oscillator Specifications as a reference:
1. Pick a crystal frequency (for example, 20 MHz).
2. Check that the ESR of the crystal <=50 Ω per specifications for 20 MHz.
3. Check that the load capacitance requirement of the crystal manufacturer is within 6 pF and 12 pF per
specifications for 20 MHz.
• As mentioned, CL1 and CL2 are in series; so, provided CL1 = CL2, effective load capacitance CL =
[CL1]/2.
• Adding board parasitics to this results in CL = [CL1]/2 + Cstray
4. Check that the maximum drive level of the crystal >= 1 mW. If this requirement is not met, a dampening
resistor Rd can be used. Refer to DL – Drive Level on other points to consider when using Rd.
6.14.3.4.5 Testing
It is recommended that the user have the crystal manufacturer completely characterize the crystal with their
board to ensure the crystal always starts up and maintains oscillation.
Below is a brief overview of some measurements that can be performed:
Due to how sensitive the crystal circuit is to capacitance, it is recommended that scope probes not be connected
to X1 and X2. If scope probes must be used to monitor X1/X2, an active probe with less than 1-pF input
capacitance should be used.
Frequency
1. Bring out the XTAL on XCLKOUT.
2. Measure this frequency as the crystal frequency.
Negative Resistance
2. Place a potentiometer in series with the crystal between the load capacitors.
3. Increase the resistance of the potentiometer until the clock on XCLKOUT stops.
4. This resistance plus the crystal’s actual ESR is the negative resistance of the electrical oscillator.
Start-Up Time
1. Turn off the XTAL.
3. Turn on the XTAL and measure how long it takes the clock on XCLKOUT to stay within 45% and 55% duty
cycle.

6.14.3.4.6 Common Problems and Debug Tips

Crystal Fails to Start Up
• Go through the How to Choose a Crystal section and make sure there are no violations.
Crystal Takes a Long Time to Start Up
• If a dampening resistor Rd is installed, it is too high.
• If no dampening resistor is installed, either the crystal ESR is too high or the overall circuit gain is too low due
to high load capacitance.
6.14.3.4.7 Crystal Oscillator Specifications
6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
ESR MAX = 110 Ω
f = 10 MHz CL1 = CL2 = 24 pF 4 ms
Start-up C0 = 7 pF
time(1) ESR MAX = 50 Ω
f = 20 MHz CL1 = CL2 = 24 pF 2 ms
C0 = 7 pF
Crystal drive level (DL) 1 mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements

For the Crystal Equivalent Series Resistance (ESR) Requirements table:
1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
2. ESR = Negative Resistance/3
Table 6-5. Crystal Equivalent Series Resistance (ESR) Requirements
MAXIMUM ESR (Ω) MAXIMUM ESR (Ω)
CRYSTAL FREQUENCY (MHz)
(CL1 = CL2 = 12 pF) (CL1 = CL2 = 24 pF)
10 55 110
12 50 95
14 50 90
16 45 75
18 45 65
20 45 50
Negative Resistance vs. 10MHz Crystal

3000
C0 (pF)
1
2500 3
5
7
Rneg (Ohms)
2000 9
1500
1000
500
0
2 4 6 8 10 12 14 16
Effective CL (pF)
Figure 6-16. Negative Resistance Variation at 10 MHz

Negative Resistance vs. 20MHz Crystal

1600
C0 (pF)
1400 1
3
1200 5
7
Rneg (Ohms)
1000 9
800
600
400
200
0
2 4 6 8 10 12 14 16
Effective CL (pF)
Figure 6-17. Negative Resistance Variation at 20 MHz
6.14.3.4.7.3 Crystal Oscillator Parameters

MIN MAX UNIT
CL1, CL2 Load capacitance 12 24 pF
C0 Crystal shunt capacitance 7 pF

6.14.3.5 Internal Oscillators

To reduce production board costs and application development time, all devices contain two independent internal
oscillators, referred to as INTOSC1 and INTOSC2. By default, INTOSC2 is set as the source for the system
reference clock (OSCCLK) and INTOSC1 is set as the backup clock source.
Applications requiring tighter SCI baud rate matching can use the SCI baud tuning example
(baud_tune_via_uart) available in C2000Ware.
6.14.3.5.1 INTOSC Characteristics
PACKAGE TEST
PARAMETER PART MIN TYP MAX UNIT
SUFFIX CONDITIONS
-40°C to 125°C 9.82 (–1.8%) 10 10.1 (1.0%)
Frequency, INTOSC1 and
fINTOSC All All -30°C to 90°C 9.86 (–1.4%) 10 10.1 (1.0%) MHz
INTOSC2(1)
-10°C to 85°C 9.9 (–1.0%) 10 10.1 (1.0%)
fINTOSC- Frequency stability at room
All All 30°C, Nominal VDD ±0.1 %
STABILITY temperature
tINTOSC-ST Start-up and settling time All All 20 µs
(1) INTOSC frequency may shift due to the thermal and mechanical stress of solder reflow. A post-reflow bake can restore the unit to its
original data sheet performance.

6.14.4 Flash Parameters

Table 6-6 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is
the value set in register FRDCNTL[RWAIT].
Table 6-6. Minimum Required Flash Wait States with Different Clock Sources and Frequencies
Wait States
CPUCLK (MHz)
(FRDCNTL[RWAIT](1))
120 < CPUCLK ≤ 150 3
80 < CPUCLK ≤ 120 2
0 < CPUCLK ≤ 80 1
(1) Minimum required FRDCNTL[RWAIT] is 1, RWAIT=0 is not supported.
The F28P55x devices have a 128-bit prefetch buffer that provides high flash code execution efficiency across
wait states. Figure 6-18 and Figure 6-19 illustrate typical efficiency across wait-state settings compared to
previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer
will depend on how many branches are present in application software. Two examples of linear code and
if-then-else code are provided.
100% 100%
95%
90%
90%
80%
Efficiency (%)
Efficiency (%)
85%
70% 80%
60% 75%
Flash with 64-Bit Prefetch 70% Flash with 64-Bit Prefetch

50% Flash with 128-Bit Prefetch
Flash with 128-Bit Prefetch
65%
40%
60%
30% 55%
0 1 2 3 4 5 0 1 2 3 4 5
Wait State D005 Wait State D006
Figure 6-18. Application Code With Heavy 32-Bit Figure 6-19. Application Code With 16-Bit If-Else
Floating-Point Math Instructions Instructions
Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle.

6.14.4.1 Flash Parameters

128 data bits + 16 ECC bits 62.5 625 µs
Program Time(1)
2KB (Sector) 8 80 µs
2KB (Sector) 15 55 ms
64KB 17 61 ms
Erase Time(2) (3) at < 25 cycles
128KB 18 66 ms
256KB 21 78 ms
64KB 28 143 ms
Erase Time(2) (3) at 1000 cycles
128KB 30 157 ms
256KB 35 183 ms
64KB 33 243 ms
Erase Time(2) (3) at 2000 cycles
128KB 36 265 ms
256KB 42 310 ms
64KB 132 1102 ms
Erase Time(2) (3) at 20K cycles
128KB 145 1205 ms
256KB 169 1410 ms
Nwec Write/Erase Cycles per Bank (4) 100000 cycles
tretention Data retention duration at TJ = 85oC 20 years
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(4) The combined total of bank and sector write/erase cycles is limited to this number

6.14.5 RAM Specifications

All volatile memory (RAM and ROM) on the F28P55x device is 0 Wait-state for both reads and writes, meaning
the memory operates at the same speed as SYSCLK. Table 6-7 and Table 6-8 summarize the characteristics of
the different RAM instances on the device.
Table 6-7. RAM Parameters – F28P55xSJ
FETCH READ NUMBER OF NUMBER OF
STORE TIME BURST
RAM TYPE SIZE TIME(1) TIME(1) BUS WIDTH BUSES WAIT
(CYCLES) ACCESS
(CYCLES) (CYCLES) AVAILABLE STATES
LS RAM 64KB 2 2 1 16/32 bits 2 0 No
M0 2KB 2 2 1 16/32 bits 1 0 No
M1 2KB 2 2 1 16/32 bits 1 0 No
GS RAM 64KB 2 2 1 16/32 bits 3 0 No
CLA-to-CPU
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CPU-to-CLA
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CLA-to-DMA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM
DMA-to-CLA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM
(1) Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.
Table 6-8. RAM Parameters – F28P55xSG
STORE TIME BURST
RAM TYPE SIZE TIME(1) TIME(1) BUS WIDTH BUSES WAIT
(CYCLES) ACCESS
LS RAM 64KB 2 2 1 16/32 bits 2 0 No
M0 2KB 2 2 1 16/32 bits 1 0 No
M1 2KB 2 2 1 16/32 bits 1 0 No
GS RAM 32KB 2 2 1 16/32 bits 2 0 No
CLA-to-CPU
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CPU-to-CLA
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CLA-to-DMA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM
DMA-to-CLA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM
followed.

6.14.6 ROM Specifications

All volatile memory (RAM and ROM) on the F28P55x device is 0 Wait-state for both reads and writes, meaning
the memory operates at the same speed as SYSCLK. Table 6-9 summarizes the aspects of the ROM instances
on the device.
Table 6-9. ROM Parameters – F28P55xSJ and F28P55xSG
STORE TIME BURST
ROM TYPE SIZE TIME(1) TIME(1) BUS WIDTH BUSES WAIT
(CYCLES) ACCESS
Boot ROM +
96KB 2 2 1 16/32 bits 1 0 No
Secure ROM
CLA Data
8KB 2 2 1 16/32 bits 2 0 No
ROM
followed.

6.14.7 Emulation/JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port has
four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for Reduced-Pin and
Enhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a compact JTAG interface
requiring only two pins (TMS and TCK), which allows other device functionality to be muxed to the traditional
GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
The PD (Power Detect) pin of the JTAG debug probe header should be connected to the board's 3.3-V supply.
Header GND pins should be connected to board ground. TDIS (Cable Disconnect Sense) should also be
connected to board ground. The JTAG clock should be looped from the header TCK output pin back to the
RTCK input pin of the header (to sense clock continuity by the JTAG debug probe). This MCU does not support
the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should
always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to
4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
Header pin RESET is an open-drain output from the JTAG debug probe header that enables board components
to be reset through JTAG debug probe commands (available only through the 20-pin header). Figure 6-20 shows
how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 6-21 shows how to connect to
the 20-pin JTAG header. The 20-pin JTAG header pins EMU2, EMU3, and EMU4 are not used and should be
grounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
in CCS for C2000 devices.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Note
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is disabled by
default. If this pin is used as JTAG TDI, the internal pullup should be enabled or an external pullup
added on the board to avoid a floating input. In the cJTAG option, this pin can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is disabled
by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this
pin floating. The internal pullup should be enabled or an external pullup added on the board to avoid a
floating GPIO input. In the cJTAG option, this pin can be used as GPIO.

Distance between the header and the target

should be less than 6 inches (15.24 cm).
3.3 V
2.2 kΩ
1 2
TMS TMS TRST
3.3 V
10 kΩ
(A)
3 4
TDI TDI TDIS GND
MCU 3.3 V 100 Ω
5 6
3.3 V PD KEY
10 kΩ
(A)
7 8
TDO TDO GND
9 RTCK GND 10
TCK 11 TCK GND 12

4.7 kΩ 4.7 kΩ
3.3 V 13 EMU0 EMU1 14 3.3 V
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 6-20. Connecting to the 14-Pin JTAG Header
Distance between the header and the target

should be less than 6 inches (15.24 cm).
3.3 V
2.2 kΩ
1 2
TMS TMS TRST
3.3 V
10 kΩ
(A)
3 TDI TDIS 4 GND
MCU TDI
3.3 V 100 Ω
3.3V 5 PD KEY 6
10 kΩ
(A)
7 TDO GND 8
TDO
9 RTCK GND 10
TCK 11 TCK GND 12

4.7 kΩ 4.7 kΩ
3.3 V 13 EMU0 EMU1 14 3.3 V
15 RESET GND 16
Open
Drain 17 EMU2 EMU3 18
A low pulse from the JTAG debug probe 19 EMU4 GND 20

can be tied with other reset sources
to reset the board. GND GND
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 6-21. Connecting to the 20-Pin JTAG Header

6.14.7.1 JTAG Electrical Data and Timing

6.14.7.1.1 JTAG Timing Requirements
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 66.66 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.66 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 26.66 ns
tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 7
3 ns
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 7
th(TCKH-TDI) Input hold time, TDI valid from TCK high 7
4 ns
th(TCKH-TMS) Input hold time, TMS valid from TCK high 7
6.14.7.1.2 JTAG Switching Characteristics

NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDO) Delay time, TCK low to TDO valid 6 20 ns
6.14.7.1.3 JTAG Timing Diagram

1
1a 1b
TCK
TDO
3 4
TDI/TMS
Figure 6-22. JTAG Timing

6.14.7.2 cJTAG Electrical Data and Timing

6.14.7.2.1 cJTAG Timing Requirements
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 100 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 40 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 40 ns
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 7 ns
3
tsu(TMS-TCKL) Input setup time, TMS valid to TCK low 7 ns
th(TCKH-TMS) Input hold time, TMS valid from TCK high 2 ns
4
th(TCKL-TMS) Input hold time, TMS valid from TCK low 2 ns
6.14.7.2.2 cJTAG Switching Characteristics

NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TMS) Delay time, TCK low to TMS valid 6 20 ns
5 tdis(TCKH-TMS) Delay time, TCK high to TMS disable 20 ns
6.14.7.2.3 cJTAG Timing Diagram

1
1a 1b
2
3 4 3 4 5
TCK
TMS TMS Input TMS Input TMS Output
Figure 6-23. cJTAG Timing

6.14.8 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
Many GPIOs have mux options for Output X-BAR which allows an assortment of internal signals to be routed to
a GPIO. All of the GPIOs are connected to each Input X-BAR which can route the GPIO's high or low state to
different IP blocks, such as the ADCs, eCAPs, ePWMs, and external interrupts. For more details, see the X-BAR
chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
6.14.8.1 GPIO – Output Timing
6.14.8.1.1 General-Purpose Output Switching Characteristics
tr(GPO) Rise time, GPIO switching low to high All GPIOs 6(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 6(1) ns
All GPIOs not listed
50
below
tfGPO Toggling frequency, GPIO pins MHz
GPIO 2, 3, 9, and 32 40
GPIO 23 and 41 25
(1) Rise time and fall time vary with load. These values assume a 6-pF load.
6.14.8.1.2 General-Purpose Output Timing Diagram
GPIO
tr(GPO)
tf(GPO)
Figure 6-24. General-Purpose Output Timing

6.14.8.2 GPIO – Input Timing

6.14.8.2.1 General-Purpose Input Timing Requirements
MIN MAX UNIT
QUALPRD = 0 1tc(SYSCLK) cycles
tw(SP) Sampling period
QUALPRD ≠ 0 2tc(SYSCLK) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
Synchronous mode 2tc(SYSCLK) cycles
tw(GPI) (2) Pulse duration, GPIO low/high
With input qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
6.14.8.2.2 Sampling Mode
(A)
GPIO Signal GPxQSELn = 1,0 (6 samples)
1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1
tw(SP) Sampling Period determined

(B)
by GPxCTRL[QUALPRD]
tw(IQSW)
(C)
Sampling Window (SYSCLK cycle * 2 * QUALPRD) * 5
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.
Figure 6-25. Sampling Mode

6.14.8.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 6-26. General-Purpose Input Timing

6.14.9 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through
the enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to sixteen peripheral
interrupts into each CPU interrupt line. It also expands the vector table to allow each interrupt to have its own
ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 6-27 shows the interrupt architecture for this device.
TINT0
TIMER0
LPM Logic LPMINT

WAKEINT
WDINT NMI module NMI
WD
INPUTXBAR4 XINT1 Control CPU

INPUTXBAR5 XINT2 Control
GPIO0 ePIE INT1
Input
to INPUTXBAR6 XINT3 Control to
X-BAR
GPIOx INT12
TIMER1 INT13
TIMER2 INT14
Peripherals
See ePIE Table
Figure 6-27. Device Interrupt Architecture

6.14.9.1 External Interrupt (XINT) Electrical Data and Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.14.9.1.1 External Interrupt Timing Requirements
MIN MAX UNIT
Synchronous 2tc(SYSCLK) cycles
tw(INT) Pulse duration, INT input low/high
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
6.14.9.1.2 External Interrupt Switching Characteristics

td(INT) Delay time, INT low/high to interrupt-vector fetch(1) tw(IQSW) + 14tc(SYSCLK) tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
(1) This assumes that the ISR is in a single-cycle memory.
6.14.9.1.3 External Interrupt Timing
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
Interrupt Vector
(internal)
Figure 6-28. External Interrupt Timing

6.14.10 Low-Power Modes

This device has HALT, IDLE and STANDBY as clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the
Low-Power Modes section of the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
6.14.10.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 6-10 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 6-10. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
IDLE STANDBY HALT
CLOCK DOMAIN
SYSCLK Active Gated Gated
CPUCLK Gated Gated Gated
Clock to modules connected Active Gated Gated
to PERx.SYSCLK
WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
PLL Powered Powered Software must power down PLL before entering HALT.
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash(1) Powered Powered Powered
XTAL(2) Powered Powered Powered
(1) The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the
application.
(2) The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.

6.14.10.2 Low-Power Mode Wake-up Timing

6.14.10.2.1 IDLE Mode Timing Requirements
MIN MAX UNIT
Without input qualifier 2tc(SYSCLK)
tw(WAKE) Pulse duration, external wake-up signal cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW)
6.14.10.2.2 IDLE Mode Switching Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT
Without input qualifier 40tc(SYSCLK) cycles
From Flash (active state)
Delay time, external wake signal to With input qualifier 40tc(SYSCLK) + tw(WAKE) cycles
td(WAKE-IDLE)
program execution resume(1) Without input qualifier 25tc(SYSCLK) cycles
From RAM
With input qualifier 25tc(SYSCLK) + tw(WAKE) cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
6.14.10.2.3 IDLE Entry and Exit Timing Diagram

td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
(A)
WAKE
A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.
Figure 6-29. IDLE Entry and Exit Timing Diagram

6.14.10.2.4 STANDBY Mode Timing Requirements

MIN MAX UNIT
QUALSTDBY = 0 | 2tc(OSCCLK) 3tc(OSCCLK)
Pulse duration, external
tw(WAKE-INT) QUALSTDBY > 0 | cycles
wake-up signal (2 + QUALSTDBY) * tc(OSCCLK)
(2 + QUALSTDBY)tc(OSCCLK) (1)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
6.14.10.2.5 STANDBY Mode Switching Characteristics

Delay time, IDLE instruction executed to
td(IDLE-XCOS) 16tc(INTOSC1) cycles
XCLKOUT stop
Wakeup from flash
td(WAKE-STBY) Delay time, external wake signal to program (Flash module in 175tc(SYSCLK) + tw(WAKE-INT) cycles
execution resume(1) active state)
td(WAKE-STBY) Wakeup from RAM 3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
6.14.10.2.6 STANDBY Entry and Exit Timing Diagram

(A) (C) (F)
(B) (D)(E) (G)
Device STANDBY STANDBY Normal Execution

Status
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.

B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-30. STANDBY Entry and Exit Timing Diagram

6.14.10.2.7 HALT Mode Timing Requirements

MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See the Crystal Oscillator (XTAL) section for more information. For applications using INTOSC1
or INTOSC2 for OSCCLK, see the Internal Oscillators section for toscst. Oscillator start-up time does not apply to applications using a
single-ended crystal on the X1 pin, as it is powered externally to the device.
6.14.10.2.8 HALT Mode Switching Characteristics

Delay time, IDLE instruction executed to XCLKOUT
td(IDLE-XCOS) 16tc(INTOSC1) cycles
stop
Delay time, external wake signal end to CPU1 program
execution resume
td(WAKE-HALT) cycles
Wakeup from Flash - Flash module in active state 75tc(OSCCLK)
Wakeup from RAM 75tc(OSCCLK)

6.14.10.2.9 HALT Entry and Exit Timing Diagram

(A) (C) (F)
(B) (D)(E) (G)
Device
HALT HALT
Status
Flushing Pipeline Normal

Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.

B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock
source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible
to keep the internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up
sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean
clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure,
care should be taken to maintain a low noise environment before entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 6-31. HALT Entry and Exit Timing Diagram

6.15 Analog Peripherals

The analog subsystem module is described in this section.
The analog modules on this device include the Analog-to-Digital Converter (ADC), temperature sensor,
Comparator Subsystem (CMPSS), Programmable Gain Amplifier (PGA), and buffered Digital-to-Analog
Converter (DAC).
The analog subsystem has the following features:
• Flexible voltage references
– The ADCs are referenced to VREFHIx and VSSA pins
• VREFHIx pin voltage can be driven in externally or can be generated by an internal bandgap voltage
reference
• The internal voltage reference range can be selected to be 0 V to 3.3 V or 0 V to 2.5 V
– The buffered DACs are referenced to VREFHIx and VSSA
– The comparator DACs are referenced to VDDA and VSSA
• Flexible pin usage
– Buffered DAC outputs, comparator subsystem inputs, and digital inputs (AIOs)/outputs (AGPIOs) are
multiplexed with ADC inputs
– Internal connection to VREFLO on all ADCs for offset self-calibration
6.15.1 Block Diagram
The following analog subsystem block diagrams show the connections between the different integrated analog
modules to the device pins. These pins fall into two categories: analog module inputs/outputs and reference
pins.
The reference pins, VREFHI and VREFLO, can be used to supply an external voltage reference to the
associated ADCs. VREFHI can also be used to supply the voltage reference to buffered DAC. The choice
of reference is configurable per module for each CMPSS or buffered DAC; the selection is made using the
module's configuration registers.
Some analog pins support digital functionality through muxed AIOs and AGPIOs. AIOs only support digital input
functionality, while AGPIOs support full digital input and output functionality.
The following notes apply to all packages:
• Not all analog pins are available on all devices. See the device data manual to determine which pins are
available.
• See the device data manual to determine the allowable voltage range for VREFHI and VREFLO.
• An external capacitor is required on the VREFHI pins. See the device data manual for the specific value
required.
Figure 6-32 shows the Analog Subsystem Block Diagram for the 128-/80-pin TQFP, the 64-pin LQFP, and the
56-pin VQFN.
Figure 6-33 shows the Analog Subsystem Block Diagram for the 100-pin LQFP.
Figure 6-34 shows the general overview of the analog group connections.
The analog pins and internal connections are given in Analog Pins and Internal Connections. Analog Signal
Descriptions lists descriptions of analog signals.

VREFHI CMP1_HP Comparator Subsystem 1 CMPSS Module

VREFLO Digital CTRIP1H
CMP1_HN Filter
ADC Module
VDDA CTRIPOUT1H
Reference Circuit
Misc. Analog DAC12
Buffered DAC Module
ANAREFSEL
Temp Sensor DAC12 Digital CTRIP1L
CMP1_LN CMPSS Input MUX
(C12) Vref Filter CTRIPOUT1L
CMP1_LP Temp Sensor
REFLO
CMP2_HP Comparator Subsystem 2 Analog Interconnect
Digital CTRIP2H
A15 HPMXSEL3/HNMXSEL0 /LPMXSEL3/LNMXSEL0 CMP2_HN VDDA Filter CTRIPOUT2H Reference Circuit
A1/B7/D11/CMP1_DACL HPMXSEL4/ /LPMXSEL4/
(64/80/128-pin) A6/D14/E14 HPMXSEL2/ /LPMXSEL2/ REFHI DAC12
ADC Inputs
Input MUX
A2/B6/C9/PGA1_INP HPMXSEL0/ /LPMXSEL0/ DAC12
A0 to A30 Digital CTRIP2L
A11/B10/C0/PGA2_OUT HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1 ADC-A CMP2_LN
Filter
(128-pin) B5/D15/E15 HPMXSEL5/ /LPMXSEL5/ CTRIPOUT2L
AGPIO
12-bits
Analog Interconnect
AGPIO
AGPIO CMP2_LP
AIO
AIO
CMPSS1 Input MUX AIO Comparator Subsystem 3
REFLO CMP3_HP
Digital CTRIP3H
A10/B1/C10 HPMXSEL2/HNMXSEL0/LPMXSEL2/LNMXSEL0
HPMXSEL1/ /LPMXSEL1/ CMP3_HN VDDA Filter CTRIPOUT3H
A9
A12 HPMXSEL0/HNMXSEL1/LPMXSEL0/LNMXSEL1
DAC12
A5 HPMXSEL4/ /LPMXSEL4/
REFHI
DAC12 Digital CTRIP3L
ADC Inputs
Input MUX
AGPIO
AGPIO
CMP3_LN
AGPIO
B0 to B30 Filter CTRIPOUT3L
AIO
AIO
ADC-B
CMPSS2 Input MUX AIO CMP3_LP
12-bits
(64/80/128-pin) B2/C6/E12 HPMXSEL0/ /LPMXSEL0/ CMP4_HP Comparator Subsystem 4
B3/PGA2_INP HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 REFLO Digital CTRIP4H
A14/B14/C4/PGA1_OUT HPMXSEL4/ /LPMXSEL4/ CMP4_HN VDDA Filter CTRIPOUT4H
B12/C2/PGA2_INM HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A3 HPMXSEL5/ /LPMXSEL5/ DAC12
AGPIO
AGPIO
A0/B15/C15/DACA_OUT HPMXSEL2/ /LPMXSEL2/ AGPIO
DAC12
AIO REFHI CMP4_LN Digital CTRIP4L
CMPSS3 Input MUX AIO
AIO ADC Inputs Filter CTRIPOUT4L
Input MUX
C0 to C30 ADC-C
B4/C8 HPMXSEL0/ /LPMXSEL0/ CMP4_LP
C14 HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 12-bits
C1/E11/PGA3_INP HPMXSEL2/ /LPMXSEL2/
A8/B0/C11 HPMXSEL4/ /LPMXSEL4/
REFLO
(128-pin) B11/D16/E16 HPMXSEL5/ /LPMXSEL5/
A7/C3/D12/B30/E30 HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
AGPIO
AGPIO
AGPIO
AIO
AIO
REFHI
ADC Inputs
Input MUX
D0 to D30 ADC-D
12-bits
REFLO
REFHI
ADC Inputs
Input MUX
E0 to E30 ADC-E
12-bits
REFLO
CMPSS Inputs
VREFHI
DACA_OUT 12-bit
Buffered
DAC-A
Figure 6-32. Analog Subsystem Block Diagram (128-/80-/64-/56-Pin Packages)

VREFHI CMP1_HP Comparator Subsystem 1 CMPSS Module

VREFLO Digital CTRIP1H
CMP1_HN VDDA Filter CTRIPOUT1H
ADC Module
Reference Circuit
DAC12 Buffered DAC Module
ANAREFSEL
Misc. Analog DAC12 Digital CTRIP1L
CMP1_LN CMPSS Input MUX
Temp Sensor Filter CTRIPOUT1L
Vref
(C12) CMP1_LP Temp Sensor
REFLO
CMP2_HP Comparator Subsystem 2 Analog Interconnect
Digital CTRIP2H
CMP2_HN VDDA Filter CTRIPOUT2H Reference Circuit
A1/B7/D11/CMP1_DACL HPMXSEL4/ /LPMXSEL4/
A6/D14/E14 HPMXSEL2/ /LPMXSEL2/ REFHI DAC12
ADC Inputs
Input MUX
A2/B6/C9/PGA1_INP HPMXSEL0/ /LPMXSEL0/ DAC12
A0 to A30 Digital CTRIP2L
A11/B10/C0/PGA2_OUT HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1 ADC-A CMP2_LN
Filter
B5/D15/E15 HPMXSEL5/ /LPMXSEL5/ CTRIPOUT2L
AGPIO
12-bits
Analog Interconnect
AGPIO
AGPIO CMP2_LP
AIO
AIO
CMPSS1 Input MUX AIO Comparator Subsystem 3
REFLO CMP3_HP
Digital CTRIP3H
A10/B1/C10 HPMXSEL2/HNMXSEL0/LPMXSEL2/LNMXSEL0
HPMXSEL1/ /LPMXSEL1/
A9
B0/C11 HPMXSEL3/ /LPMXSEL3/
DAC12
A12 HPMXSEL0/HNMXSEL1/LPMXSEL0/LNMXSEL1
REFHI
A5 HPMXSEL5/ /LPMXSEL5/ DAC12 Digital CTRIP3L
ADC Inputs CMP3_LN
Input MUX
AGPIO
AGPIO
AGPIO
B0 to B30 Filter CTRIPOUT3L
AIO
AIO
ADC-B
CMPSS2 Input MUX AIO CMP3_LP
12-bits
B2/C6/E12 HPMXSEL0/ /LPMXSEL0/ CMP4_HP Comparator Subsystem 4
B3/PGA2_INP HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 REFLO Digital CTRIP4H
A14/B14/C4/PGA1_OUT HPMXSEL4/ /LPMXSEL4/ CMP4_HN VDDA Filter CTRIPOUT4H
B12/C2/PGA2_INM HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A3 HPMXSEL5/ /LPMXSEL5/ DAC12
AGPIO
AGPIO
A0/B15/C15/DACA_OUT HPMXSEL2/ /LPMXSEL2/ AGPIO
DAC12
AIO REFHI CMP4_LN Digital CTRIP4L
AIO ADC Inputs Filter CTRIPOUT4L
Input MUX
C0 to C30 ADC-C
B4/C8 HPMXSEL0/ /LPMXSEL0/ CMP4_LP
C14 HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 12-bits
C1/E11/PGA3_INP HPMXSEL2/ /LPMXSEL2/
A8/B0/C11 HPMXSEL4/ /LPMXSEL4/
REFLO
B11/D16/E16 HPMXSEL5/ /LPMXSEL5/
A7/B30/C3/D12/E30 HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
AGPIO
AGPIO
AGPIO
AIO
AIO
REFHI
ADC Inputs
Input MUX
D0 to D30 ADC-D
12-bits
REFLO
REFHI
ADC Inputs
Input MUX
E0 to E30 ADC-E
12-bits
REFLO
CMPSS Inputs
VREFHI
DACA_OUT 12-bit
Buffered
DAC-A
Figure 6-33. Analog Subsystem Block Diagram (100-Pin Package)

CMPSSx Input MUX PGA Module

CMPSS Input MUX
CMPxHPMX
CMPx_HP0
0 AIO
CMPx_HP1
1
CMPx_HP2 AGPIO
2
CMPx_HP3
3 CMPx_HP
CMPx_HP4
4
CMPx_HP5 5
CMPx_HP6 6
CMPxHNMX
CMPx_HN0 0
CMPx_HN1 CMPx_HN
1
To CMPSSx
CMPxLNMX
CMPx_LN0 0
CMPx_LN1 CMPx_LN
1
CMPxLPMX
CMPx_LP0
0
CMPx_LP1
1
CMPx_LP2
2
CMPx_LP3 CMPx_LP
3
CMPx_LP4 4
CMPx_LP5 5
CMPx_LP6 6
ADCA ADCA
AIO
AGPIO
ADCB ADCB
AIO
AGPIO
ADCC ADCC
AIO
TO Device Pins
AGPIO
To ADCs
ADCD ADCD
AIO
AGPIO
ADCE ADCE
AIO
PGAx_OUT
AGPIO
VDDA
PGAx_OUT_INT
PGAx_INP +
PGAx_INM
- PGAx_OUT
VSSA
Figure 6-34. Analog Group Connections

Input connections to the CMPSS modules are selectable through a programmable input mux. Figure 6-34
demonstrates the connection between the input MUX of CMPSS modules, PGA modules, and ADC modules.
Table 6-11 shows the mapping of ADC input signals and PGA input and output signals to CMPSS mux inputs.
• To configure the CMPx_HP input mux for CMPSSx, write to the CMPxHPMXSEL field in the CMPHPMXSEL
analog subsystem register.
• To configure the CMPx_HN input mux for CMPSSx, write to the CMPxHNMXSEL field in the CMPHNMXSEL
• To configure the CMPx_LP input mux for CMPSSx, write to the CMPxLPMXSEL field in the CMPLPMXSEL
• To configure the CMPx_LN input mux for CMPSSx, write to the CMPxLNMXSEL field in the CMPLNMXSEL
Table 6-11. CMPSS Input Mux Options
CMPSSx Input MUX CMP1 CMP2 CMP3 CMP4
HP0 A2, B6, C9, PGA1_INP A4, B8 B2,C6, E12 B4, C8
HP1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, C3, D12, B30, E30,
HP2 A6, D14, E14(3) A9 A0, B15, C15, DACA_OUT C1, E11, PGA3_INP
A10, B1, C10
HP3 A15(2) B3, PGA2_INP C14
B0, C11(1)
A8
HP4 A1, B7, D11, CMP1_DACL A14, B14, C4, PGA1_OUT
B0, C11(2)
HP5 B5, D15, E15(4) A5(1) A3 B11, D16, E16(4)
HP6 PGA1_OUT_INT PGA3_OUT_INT PGA2_OUT_INT
HP7 TEMP SENSOR
HN0 A15(2) A10, B1, C10 B3, PGA2_INP C14
HN1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, B30, C3, D12, E30
LP0 A2, B6, C9, PGA1_INP A4, B8 B2, C6, E12 B4, C8
LP1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, B30, C3, D12, E30
LP2 A6, D14, E14(3) A9 A0, B15, C15, DACA_OUT C1, E11, PGA3_INP
A10, B1, C10
LP3 A15(2) B3, PGA2_INP C14
B0, C11(1)
A8
LP4 A1, B7, D11, CMP1_DACL A14, B14, C4, PGA1_OUT
B0, C11(2)
LP5 B5, D15, E15(4) A5(1) A3 B11, D16, E16(4)
LP6 PGA1_OUT_INT PGA3_OUT_INT PGA2_OUT_INT
LN0 A15 A10, B1, C10 B3, PGA2_INP C14
LN1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, C3, D12, B30,E30
(1) These MUX options are available only on 100 QFP package.
(2) This MUX option is available only on 56 QFN, 64 QFP, 80 QFP, and 128 QFP packages.
(3) This MUX option is available only on 64 QFP, 80 QFP, 100 QFP, and 128 QFP packages.
(4) This MUX option is available only on 100 QFP and 128 QFP packages.

6.15.2 Analog Pins and Internal Connections

Table 6-12. Analog Pins and Internal Connections
Pins/Package ADC Comparator Subsystem (MUX)
AIO Input/
Pin Name 128 100 80 64 56 DAC PGA High High Low Low
A B C D E AGPIO
QFP QFP QFP QFP QFN Positive Negative Positive Negative
31 24
VREFHI 20 16 14 - - - D20 E20
32 25
33 26
VREFLO 21 17 15 A13 B13 C13 D13 E13
34 27
Analog Group 1 CMP1
CMP1 CMP1 AGPIO228
A6/D14/E14 18 14 10 6 - A6 - - D14 E14 - - (3)
(HPMXSEL=2) (LPMXSEL=2)
CMP1 CMP1 AGPIO224
A2/B6/C9/PGA1_INP 21 17 13 9 7 A2 B6 C9 - - PGA1_INP - - (3)
CMP1 CMP1 CMP1 CMP1 AGPIO233
A15 - A15 - - (3)
22 14 10 8 - - (HPMXSEL=3) (HNMXSEL=0) (LPMXSEL=3) (LNMXSEL=0)
B9/C7/PGA1_INM 18 - B9 C7 PGA1_INM
CMP1 CMP1 CMP1 CMP1
A11/B10/C0/PGA2_OUT 27 20 16 12 10 A11 B10 C0 - - PGA2_OUT AIO237
(HPMXSEL=1) (HNMXSEL=1) (LPMXSEL=1) (LNMXSEL=1)
CMP1 CMP1
A1/B7/D11/CMP1_DACL 29 22 18 14 12 A1 B7 - D11 - CMP1_DACL - - AIO232
CMP1 CMP1
B5/D15/E15 - - - - B5 D15 E15 - AIO252
38 32 - (HPMXSEL=5) - (LPMXSEL=5) -
PGA3_OUT 24 20 18 - - - PGA3_OUT
Analog Group 2 CMP2
CMP2 CMP2
A4/B8 42 36 27 23 21 A4 B8 - - - - - AIO225
CMP2 CMP2
A12 35 28 22 18 16 A12 - - - - - - AIO238
CMP2 CMP2 AGPIO227
A9 48 38 28 24 22 A9 - - - - - - (3)
A10/B1/C10 50 40 29 25 23 A10 B1 C10 - - (3)
CMP2 CMP2 AGPIO231
B0/C11 - 41 - - - - B0 C11 - - (3)
28 - 17 13 11 CMP2 CMP2
A5 A5 - - - - - - AIO249
- 35 - - - (HPMXSEL=5) (LPMXSEL=5)
Analog Group 3 CMP3

CMP3 CMP3 AGPIO226
B2/C6/E12 19 15 11 7 - - B2 C6 - E12 - - (3)
CMP3 CMP3 CMP3 CMP3
B12/C2/PGA2_INM 28 21 17 13 11 - B12 C2 - - PGA2_INM AIO244

Table 6-12. Analog Pins and Internal Connections (continued)

Pins/Package ADC Comparator Subsystem (MUX)
AIO Input/
Pin Name 128 100 80 64 56 DAC PGA High High Low Low
A B C D E AGPIO
QFP QFP QFP QFP QFN Positive Negative Positive Negative
CMP3 CMP3
A0/B15/C15/DACA_OUT 30 23 19 15 13 A0 B15 C15 - - DACA_OUT - - AIO231
B3/PGA2_INP 16 B3 - (3)
20 12 8 6 - - - PGA2_INP (HPMXSEL=3) (HNMXSEL=0) (LPMXSEL=3) (LNMXSEL=0)
C5 28 - C5
CMP3 CMP3
A14/B14/C4/PGA1_OUT 26 19 15 11 9 A14 B14 C4 - - PGA1_OUT - - AIO239
20 - 12 8 6 CMP3 CMP3
A3 A3 - - - - - -
- 18 - - - (HPMXSEL=5) (LPMXSEL=5) AIO229
Analog Group 4 CMP4
CMP4 CMP4 AGPIO236
B4/C8 49 39 28 24 22 - B4 C8 - - - - (3)
CMP4 CMP4
C1/E11/PGA3_INP 35 29 22 18 16 - - C1 - E11 PGA3_INP - - -
C14 42 42 27 23 21 - - C14 - - (3)
B0/C11 39 - 24 20 18 - B0 C11 CMP4 CMP4 AIO241
- - - -
A8 - 37 - - - A8 - - (HPMXSEL=4) (LPMXSEL=4) AIO240
CMP4 CMP4
B11/D16/E16 36 30 - - - - B11 - D16 E16 - - AIO251
PGA3_INM 36(1) 30(1) - - - - - PGA3_INM
23 19 17 CMP4 CMP4 CMP4 CMP4
A7/B30/C3/D12/E30 37 31 A7 B30 C3 D12 E30 AIO245
Other Analog
CMP2
TempSensor(2) - - C12 - - - - - -
(HPMXSEL=7)
PGA1_OUT_I CMP1 CMP1
PGA1_OUT_INT(2) A21 B21 - - - - - -
NT (HPMXSEL=6) (LPMXSEL=6)
PGA2_OUT_INT(2) - B22 C21 - - - - -
PGA3_OUT_INT(2) A22 - C22 - - - - -
(1) Signal is bonded together with another signal as a single pin on this package.
(2) Internal connection only; does not come to a device pin.
(3) Only on 100 QFP package, AGPIO 247 is available.

Note
The GPIOs on the analog pins support full digital input and output functionality and are referred to as AGPIOs. By default, the AGPIOs are
unconnected; that is, the analog and digital functions are both disabled. For configuration details, see the Digital Inputs and Outputs on ADC
Pins (AGPIOs) section.

6.15.3 Analog Signal Descriptions

Table 6-13. Analog Signal Descriptions
Signal Name Description
AIOx Digital input on ADC pin
AGPIOx Digital input/output pin with ADC functionality
ADCINAx, Ax ADC A Input
ADCINBx, Bx ADC B Input
ADCINCx, Cx ADC C Input
ADCINDx, Dx ADC D Input
ADCINEx, Ex ADC E Input
CMPx_HP Comparator subsystem high comparator positive input
CMPx_HN Comparator subsystem high comparator negative input
CMPx_LP Comparator subsystem low comparator positive input
CMPx_LN Comparator subsystem low comparator negative input
DACA_OUT Buffered DAC Output
CMP1_DACL CMPSS1 DAC Output
PGAx_INP PGA module non-inverting pin
PGAx_INM PGA module inverting pin

PGAx_OUT PGA module output
PGAx_OUT_INT PGA module internal output connected to CMPSS and ADC modules
TEMP SENSOR, TS Internal temperature sensor

6.15.4 Analog-to-Digital Converter (ADC)

The ADC module described here is a successive approximation (SAR) style ADC with resolution of 12 bits.
This section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX,
the sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and other
analog support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic
for programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses,
post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of
the Analog-to-Digital Converter (ADC) chapter in the TMS320F28P55x Real-Time Microcontrollers Technical
Reference Manual).
Each ADC has the following features:
• Resolution of 12 bits
• Ratiometric external reference set by VREFHI/VREFLO
• Selectable internal reference of 2.5 V or 3.3 V
• Single-ended signal mode
• Input multiplexer with up to 32 channels
• 16 configurable SOCs
• 16 individually addressable result registers
• External analog input mux selection per SOC, up to 4 bits
• Sample cap reset feature for memory crosstalk mitigation
• Multiple trigger sources
– Software immediate start
– All ePWMs: ADCSOC A or B
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
– ECAP events in capture mode (CEVT1, CEVT2, CEVT3, and CEVT4) and APWM mode (period match,
compare match, or both).
– Global software trigger for multiple ADCs
• Four flexible PIE interrupts
• Burst-mode triggering option
• Hardware oversampling mode up to 128x, with configurable trigger spread delay
• Hardware undersampling mode
• Trigger phase delay function
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Configurable digital filter for high/low/zero-crossing compare
– Trigger-to-sample delay capture
– Absolute value calculation
– 24-bit accumulation register for oversampling, with configurable binary shift
– Minimum/maximum calculation for outlier rejection
Note
Not every channel can be pinned out from all ADCs. See the Pin Configuration and Functions section
to determine which channels are available.

The block diagram for the ADC core and ADC wrapper are shown in Figure 6-35.
ADCEXTMUX[3:0]
ADCCLK SYSCLK
Clock Prescaler Analog to Digital Control Logic
SIGNALMODE
SIGNALMODE
RESOLUTION Post Processing Block
RESOLUTION
SOCx (0-15) Analog to Digital Core
TRIGSEL
Triggers
CHSEL [15:0]
Reference Voltage Generator
[15:0] REPEATx (1-2)
ADCIN0 0 ACQPS Analog System Control
SOC Arbitration& TRIGSEL
ADCIN1 1 [15:0]
Control CHSEL MODE
ADCIN2 2 ADCSOC Input Circuit
NSEL
ADCIN3 3 [15:0]
EXTCHSEL PHASE
ADCIN4 4 SPREAD Converter
ADCIN5 5
ADCIN6 6 REPEATx (1-2)
...
...
ADCIN7 7 VIN+
ADCIN8 8 DOUT SOCxSTART[15:0] TRIGGER[15:0] SOCx (0-15)
ADCIN9 9 VIN-
ADCIN10 10 RESULT
ADCIN11 11 EOCx[15:0]
EOCx[15:0]
... ... S/H
Circuit Converter
ADCIN29 29
FREECOUNT
ADCIN30 30
ADCIN31 31 ADCRESULT 0–15 Regs
Conversion Start Delay Sync

Calculation Logic
PPBxRESULT
Input Circuit Sample Correction
(OFFCAL, OFFREF, INV, ABS,
last-sample delta)
Analog to Digital Core
Oversampling and
Accumulation
(COUNT, SUM, MAX, MIN)
VREFHI ADCEVTINT
Limit Compare and Event
1 Logic, Digital Filters ADCEVT
Bandgap
Reference
0 ADCOSINT1
Circuit Post Processing Block (1-4)
Interrupt Block (1-4) ADCINT1-4

VREFLO Analog to Digital Control Logic ADCINT1-4_DMA
REFPMUXSEL
ANAREFx1P65SEL
Reference Voltage Generator Analog System Control
Figure 6-35. ADC Module Block Diagram

6.15.4.1 ADC Configurability

Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 6-14 summarizes the basic ADC options and their level of configurability.
Table 6-14. ADC Options and Configuration Levels
OPTIONS CONFIGURABILITY
Clock Per module(1)
Resolution Not configurable (12-bit resolution only)
Signal mode Not configurable (single-ended signal mode only)
Reference voltage source Either external or internal for all modules
Trigger source Per SOC(1)
Converted channel Per SOC
Acquisition window duration Per SOC(1)
EOC location Per module
Burst mode Per module(1)
(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual .
6.15.4.1.1 Signal Mode
The ADC supports single-ended signaling. The input voltage to the converter is sampled through a single pin
(ADCINx), referenced to VREFLO.
Pin Voltage
VREFHI
VREFHI
ADCINx ADCINx
VREFHI/2 ADC
VREFLO
VREFLO
(VSSA)
Digital Output
2n - 1
ADC Vin
Figure 6-36. Single-ended Signaling Mode

6.15.4.2 ADC Electrical Data and Timing
Note
The ADC inputs should be kept below VDDA + 0.3 V. If an ADC input goes above this level, ADC
disturbances to other channels may occur by two mechanisms:
• ADC input overvoltage will overdrive the CMPSS mux, disturbing all other channels which share a
common CMPSS mux. This disturbance will be continuous regardless of if the overvoltage input is
sampled by the ADC
• When the ADC samples the overvoltage ADC input, VREFHI will be pulled up to a higher level.
This will disturb subsequent ADC conversions on any channel until the VREF stabilizes
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion.
6.15.4.2.1 ADC Operating Conditions

ADCCLK (derived from PERx.SYSCLK) 5 75 MHz
150-MHz SYSCLK
Sample rate 3.9 MSPS
Sample window duration (set by ACQPS and

With 50 Ω or less Rs 67 ns
PERx.SYSCLK)(1)
VREFHI External Reference 1.55 1.65 or 2.50 VDDA V
Internal Reference = 3.3V Range 1.65 V
VREFHI(2)
Internal Reference = 2.5V Range 2.50 V
VREFLO VSSA VSSA V
VREFHI - VREFLO 2.4 VDDA V
Conversion range Internal Reference = 3.3 V Range 0 3.3 V
Conversion range Internal Reference = 2.5 V Range 0 2.5 V
Conversion range External Reference VREFLO VREFHI V
Conversion range Analog Supply as Reference VSSA VDDA V
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage
into the pin in this mode.
6.15.4.2.2 ADC Characteristics

General
ADCCLK Conversion Cycles 150-MHz SYSCLK 14 ADCCLKs
External Reference mode 500 µs
Internal Reference mode 5000 µs
Power Up Time
Internal Reference mode, when switching between
5000 µs
2.5-V range and 3.3-V range.
VREFHI input current(1) 40 µA
Internal Reference Capacitor
2.2 µF
Value(2)

6.15.4.2.2 ADC Characteristics (continued)

External Reference Capacitor
2.2 µF
Value(2)
DC Characteristics
Internal reference –45 45
Gain Error LSB
External reference –5 ±3 5
Offset Error –5 ±2 5 LSB
Channel-to-Channel Gain Error(4) 2 LSB
Channel-to-Channel Offset
2 LSB
Error(4)
ADC-to-ADC Gain Error(5) Identical VREFHI and VREFLO for all ADCs 4 LSB
ADC-to-ADC Offset Error(5) Identical VREFHI and VREFLO for all ADCs 2 LSB
DNL Error >–1 ±0.5 1 LSB
INL Error –2 ±1.5 2 LSB
ADC-to-ADC Isolation VREFHI = 2.5 V, synchronous ADCs –1 1 LSBs
AC Characteristics
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 69.2
SNR(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from dB
60.1
INTOSC(6)
THD(3) VREFHI = 2.5 V, fin = 100 kHz -83 dB
SFDR(3) VREFHI = 2.5 V, fin = 100 kHz 79.2 dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 68.5
SINAD(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from dB
60.0
INTOSC(6)
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
11.2
X1, Single ADC
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
ENOB(3) 11 bits
X1, synchronous ADCs
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from Not
X1, asynchronous ADCs Supported
VDD = 1.2-V DC + 100mV
105
DC up to Sine at 1 kHz
VDD = 1.2-V DC + 100 mV
102
PSRR dB
VDDA = 3.3-V DC + 200 mV
97
VDDA = 3.3-V DC + 200 mV
85
Sine at 900 kHz
(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(4) Variation across all channels belonging to the same ADC module.
(5) Worst case variation compared to other ADC modules.
(6) Frequency tolerance over temperature of the INTOSC results in lower SNR versus external clock, due to FFT uncertainty

6.15.4.2.3 ADC INL and DNL
0x006
0x005
0x004
Digital Output Code
0x003
0x002
0x001
DNL Error
0x000
Analog Input Voltage
= Ideal Transfer Function

= Transfer Function (Low)
= INL Error
VREFHI – VREFLO
R=
2^n
Figure 6-37. ADC INL and DNL

6.15.4.2.4 ADC Performance Per Pin

ADC performance of each pin is affected by adjacent pins. The following plots provide details on how these pins
differ in performance.
Figure 6-38. Per-Channel ENOB for 128-Pin PDT

Figure 6-39. Per-Channel ENOB for 100-pin PZ

Figure 6-40. Per-Channel ENOB for 80-Pin PNA

Figure 6-41. Per-Channel ENOB for 64-Pin PM

Figure 6-42. Per-Channel ENOB for 56-Pin RSH
6.15.4.2.5 ADC Input Model

Table 6-15. Input Model Parameters
DESCRIPTION REFERENCE MODE VALUE
Cp Parasitic input capacitance All See Table 6-16 to Table 6-20
External Reference, 2.5-V Internal
1000 Ω
Ron Sampling switch resistance Reference
3.3-V Internal Reference 1700 Ω
External Reference, 2.5-V Internal
4 pF
Ch Sampling capacitor Reference
3.3-V Internal Reference 2.5 pF
Rs Nominal source impedance All 50 Ω
ADC
ADCINx
Rs
Switch Ron
AC Cp Ch
VREFLO
Figure 6-43. Input Model

This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analog-
to-Digital Converter (ADC) chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference
Manual. For recommendations on improving ADC input circuits, see the ADC Input Circuit Evaluation for C2000
MCUs Application Note.
Table 6-16. Per-Channel Parasitic Capacitance for 128-Pin QFP
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
A0, B15, C15, DACA_OUT 6.1 9.6
A1, B7, D11, CMP1_DACL 4.1 7.6
A2, B6, C9, PGA1_INP 6.1 9.4
A4, B8 6.0 7.9
A6, D14, E14 4.2 7.6
A7, C3, D12, B30, E30 7.5 10.3
A8, B0, C11 3.4 7.8
A9 3.7 8.7
A10, B1, C10 3.2 10.5
A11, B10, C0,PGA2_OUT 9.4 13.0
A12 6.5 11.5
A14, B14, C4, PGA1_OUT 5.8 8.0
A15 3.3 11.2
A16, B16, C16 5.0 5.6
A17,B17,C17 6.6 6.8
A18,B18,C18 5.2 5.9
A19,B19,C19 4.6 6.0
A20,B20,C20 6.7 6.2
B2, C6, E12 4.6 6.8
A3, B3, C5, PGA2_INP 14.0 20.3
B4, C8 4.3 7.9
B5, D15, E15 6.2 8.8
A15, B9, C7, PGA1_INM 3.8 11.2
B11, D16, E16 4.0 7.4
A5, B12, C2, PGA2_INM 8.6 12.8
A12, C1, E11, PGA3_INP 10.2 10.2
C5 5.4 5.4
C14 4.9 6.4
D0,E0,A24 5.6 6.3
D1,E1,B24 5.5 6.4
D2,E2,C24 4.2 4.3
D3,E3,A25 6.0 6.6
D4,E4,B25 7.2 7.8

Table 6-16. Per-Channel Parasitic Capacitance for 128-Pin QFP (continued)

Cp (pF)
ADC CHANNEL
D5,E5,C25 2.3 2.3
D6,E6,A26 5.0 5.0
D7,E7,B26 5.0 5.0
D8, E8, C26 3.3 3.3
D9,E9, A27 3.6 3.6
D10,E10,B27 3.0 3.8
D18,E18,C27 3.0 3.5
D19,E19,A28 2.1 3.6

Cp (pF)
ADC CHANNEL
A0, B15, C15, DACA_OUT 6.1 9.6
A1, B7, D11, CMP1_DACL 4.1 7.4
A2, B6, C9, PGA1_INP 6.1 9.4
A4, B8 6.0 7.9
A5 4.2 7.6
A6, D14, E14 7.5 10.3
A7, C3, D12, B30, E30 3.4 7.8
A8, B0, C11 3.7 8.7
A9 3.7 8.7
A10, B1, C10 3.2 10.5
A11, B10, C0, PGA2_OUT 9.4 13.0
A12 6.5 11.5
A14, B14, C4, PGA1_OUT 5.8 8.0
A16/B16/C16 5.0 5.6
A17,B17,C17 6.6 6.8
A18,B18,C18 5.2 5.9
A19,B19,C19 4.6 6.0
A20,B20,C20 6.7 6.2
B2, C6, E12 4.6 6.8
B3, PGA2_INP 14.0 20.3
B4, C8 4.3 7.9
B5, D15, E15 6.2 8.8
A3, B9, C7, PGA1_INM 7.0 7.6
B11, D16, E16 4.0 7.4
B12, C2, PGA2_INM 8.6 12.8
C1,E11,PGA3_INP 10.2 10.2
C5 5.4 5.4


Cp (pF)
ADC CHANNEL
C14 4.9 6.4
D0,E0,A24 5.6 6.3
D1,E1,B24 5.5 6.4
D2,E2,C24 4.2 4.3
D3,E3,A25 6.0 6.6
D4,E4,B25 7.2 7.8

Cp (pF)
ADC CHANNEL
A0, B15, C15, DACA_OUT 6.1 9.6
A1, B7, D11, CMP1_DACL 4.1 7.6
A2, B6, C9, PGA1_INP 6.1 9.4
A4, B8 6.0 7.9
A6, D14, E14 4.2 7.6
A7, C3, D12, B30,E30 7.5 10.3
A8, B0, C11 3.4 7.8
A9 3.7 8.7
A10, B1, C10 3.2 10.5
A11, B10, C0,PGA2_OUT 9.4 13.0
A14, B14, C4, PGA1_OUT 5.8 8.0
A16/B16/C16 5.0 5.6
A17,B17,C17 6.6 6.8
A18,B18,C18 5.2 5.9
A19,B19,C19 4.6 6.0
A20,B20,C20 6.7 6.1
B2, C6, E12 4.6 6.8
A3, B3, C9, PGA2_INP 14.0 20.3
B4, C8 4.3 7.9
A15, B9, C7, PGA1_INM 3.8 11.2
A5, B12, C2, PGA2_INM 8.6 12.8
A12, C1,E11,PGA3_INP 10.2 10.2
C5 5.4 5.4
C14 4.9 6.4
D0,E0,A24 5.6 6.3
D1,E1,B24 5.5 6.4
D2,E2,C24 4.2 4.3
D3,E3,A25 6.0 6.6


Cp (pF)
ADC CHANNEL
D4,E4,B25 7.2 7.8

Cp (pF)
ADC CHANNEL
A0, B15, C15, DACA_OUT 6.1 9.6
A1, B7, D11, CMP1_DACL 4.1 7.6
A2, B6, C9, PGA1_INP 6.1 9.4
A4, B8 6.0 7.9
A6, D14, E14 4.2 7.6
A7, C3, D12, B30, E30 7.5 10.3
A8, B0, C11 3.4 7.8
A9 3.7 8.7
A10, B1, C10 3.2 10.5
A11, B10, C0,PGA2_OUT 9.4 13.0
A14, B14, C4, PGA1_OUT 5.8 8.0
A16, B16, C16 5.0 5.6
A17,B17,C17 6.6 6.8
A18,B18,C18 5.2 5.9
A19,B19,C19 4.6 6.0
A20,B20,C20 6.7 6.1
B2, C6, E12 4.6 6.8
A3, B3, PGA2_INP 14.0 20.3
B4, C8 4.3 7.9
A15, B9, C7, PGA1_INM 3.8 11.2
A5, B12, C2, PGA2_INM 8.6 12.8
A12, C1, E11, PGA3_INP 10.2 10.2
C5 5.4 5.4
C14 4.9 6.4
D0,E0,A24 5.6 6.3
D1,E1,B24 5.5 6.4
D2,E2,C24 4.2 4.3
D3,E3,A25 6.0 6.6
D4,E4,B25 7.2 7.8

Table 6-20. Per-Channel Parasitic Capacitance for 56-Pin QFN

Cp (pF)
ADC CHANNEL
A0, B15, C15, DACA_OUT 6.1 9.6
A1, B7, D11, CMP1_DACL 4.1 7.6
A2, B6, C9, PGA1_INP 6.1 9.4
A4, B8 6.0 7.9
A7, C3, D12, B30,E30 7.5 10.3
A8, B0, C11 3.4 7.8
A9 3.7 8.7
A10, B1, C10 3.2 10.5
A11, B10, C0,PGA2_OUT 9.4 13.0
A14, B14, C4, PGA1_OUT 5.8 8.0
A16,B16,C16 5.0 5.6
A17,B17,C17 6.6 6.8
A18,B18,C18 5.2 5.9
A19,B19,C19 4.6 6.0
A20,B20,C20 6.7 6.1
A3, B3, PGA2_INP 14.0 20.3
B4, C8 4.3 7.9
A15, B9, C7, PGA1_INM 3.8 11.2
A5, B12, C2, PGA2_INM 8.6 12.8
A12, C1, E11, PGA3_INP 10.2 10.2
C5 5.4 5.4
C14 4.9 6.4
D0,E0,A24 5.6 6.3
D1,E1,B24 5.5 6.4
D2,E2,C24 4.2 4.3
D3,E3,A25 6.0 6.6
D4,E4,B25 7.2 7.8

6.15.4.2.6 ADC Timing Diagrams

The following diagrams show the ADC conversion timings for two SOCs given the following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round-robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 6-21 lists the descriptions of the ADC timing parameters. Table 6-22 and Table 6-23 list the ADC timings.
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H SOC0 SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0 (old data) Sample n
ADCRESULT1 (old data) Sample n+1
ADCINTFLG.ADCINTx
tSH tLAT
tEOC
tINT
Figure 6-44. ADC Timings for 12-bit Mode in Early Interrupt Mode

Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H SOC0 SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0 (old data) Sample n
ADCRESULT1 (old data) Sample n+1
ADCINTFLG.ADCINTx
tSH tLAT
tEOC
tINT
Figure 6-45. ADC Timings for 12-bit Mode in Late Interrupt Mode

Table 6-21. ADC Timing Parameter Descriptions
PARAMETER DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The
duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH is not
tSH
necessarily the same for different SOCs.
Note: The value on the S+H capacitor is captured approximately 5 ns before the end of the S+H window regardless of
device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results are returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
tEOC
subsequent sample can start before the conversion results are latched.
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT coincides with the end of conversion (EOC) signal.
If the INTPULSEPOS bit is 0, tINT coincides with the end of the S+H window. If tINT triggers a read of the ADC result
tINT register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken to make sure
the read occurs after the results latch (otherwise, the previous results are read).
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there is a delay of
OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or trigger the DMA
exactly when the sample is ready.
The time from the end of the S+H window until a DMA read of the ADC conversion result is triggered, when
ADCCTL1.TDMAEN = 1.
tDMA If TDMAEN is set to 0, then the DMA trigger occurs at TINT. In certain conditions, the ADCINT flag can be set before the
ADCRESULT value is latched. To make sure that the DMA read occurs after the ADCRESULT value has been latched,
write 1 to ADCCTL1.TDMAEN to enable DMA timings.

Table 6-22. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 0

ADCCLK Prescale SYSCLK Cycles
ADCCTL2. tINT tINT
Prescale Ratio tEOC tLAT tDMA
PRESCALE (Early)(1) (Late)
0 1 15 20 1 15 20
2 2 30 35 1 30 35
3 2.5 38 46 1 38 46
4 3 45 50 1 45 50
5 3.5 53 58 1 53 58
6 4 60 65 1 60 65
7 4.5 68 73 1 68 73
8 5 75 80 1 75 80
9 5.5 83 88 1 83 88
10 6 90 95 1 90 95
11 6.5 98 103 1 98 103
12 7 105 110 1 105 110
13 7.5 113 118 1 113 118
14 8 120 125 1 120 125
15 8.5 128 133 1 128 133
(1) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.
Table 6-23. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 1
ADCCLK Prescale SYSCLK Cycles
ADCCTL2. tINT tINT
Prescale Ratio tEOC tLAT tDMA
PRESCALE (Early)(1) (Late)
0 1 14 19 1 14 19
2 2 28 33 1 28 33
3 2.5 35 40 1 35 40
4 3 42 47 1 42 47
5 3.5 49 54 1 49 54
6 4 56 61 1 56 61
7 4.5 63 68 1 63 68
8 5 70 75 1 70 75
9 5.5 77 82 1 77 82
10 6 84 89 1 84 89
11 6.5 91 96 1 91 96
12 7 98 103 1 98 103
13 7.5 105 110 1 105 110
14 8 112 117 1 112 117
15 8.5 119 124 1 119 124
(1) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.

6.15.5 Temperature Sensor

6.15.5.1 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor
is sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in the Temperature
Sensor Characteristics table.
6.15.5.1.1 Temperature Sensor Characteristics
Tacc Temperature Accuracy External reference ±15 °C
Start-up time
tstartup (TSNSCTL[ENABLE] to 500 µs
sampling temperature sensor)
tacq ADC acquisition time 450 ns

6.15.6 Comparator Subsystem (CMPSS)

The Comparator Subsystem (CMPSS) consists of analog comparators and supporting circuits that are useful for
power applications such as peak current mode control, switched-mode power supply, power factor correction,
voltage trip monitoring, and so forth.
The comparator subsystem is built around a number of modules. Each subsystem contains two comparators,
two reference 12-bit DACs, and two digital filters. The subsystem also includes two ramp generators. The
ramp generators ramp up and down. Comparators are denoted "H" or "L" within each module where “H” and
“L” represent high and low, respectively. Each comparator generates a digital output which indicates whether
the voltage on the positive input is greater than the voltage on the negative input. The positive input of
the comparator is driven from an external pin (see the Analog Subsystem chapter of the TMS320F28P55x
Real-Time Microcontrollers Technical Reference Manual for mux options available to the CMPSS). The negative
input can be driven by an external pin or by the programmable reference 12-bit DAC. Each comparator output
passes through a programmable digital filter that can remove spurious trip signals. An unfiltered output is also
available if filtering is not required. Two ramp generator circuits are optionally available to control the reference
12-bit DAC values for the high and low comparators in the subsystem. The DAC along with a wrapper can be
used to generate a ramp which is used for slope compensation in Peak Current Mode Control (PCMC) and other
applications.
Each CMPSS includes:
• Two analog comparators
• Two independently programmable reference 12-bit DACs
• Dual decrementing/incrementing ramp generators
• Two digital filters with max filter clock prescale of 224
• Ability to synchronize submodules with EPWMSYNCPER
• Ability to extend clear signal with EPWMBLANK
• Ability to synchronize output with SYSCLK
• Ability to latch output
• Ability to invert output
• Option to use hysteresis on the input
• Option for negative input of comparator to be driven by an external signal or by the reference DAC
• Option for positive input of comparator to be driven by an external signal or by the PGA
• Option to use the low comparator DAC output, CMPx_DACL, on an external pin (select instances only,
mutually exclusive with use of compare functionality)
• External connection to CMPSS filters
• Supports connection with ePWM for diode emulation
• Ramp generator prescaler
• Wake-up from standby and halt LPM (Low Power Modes) triggered by CMPSS trip outputs
6.15.6.1 CMPx_DACL
Some CMPSS module instances have support for DAC output buffered to a pin. This CMPx_DACL output from
the CMPSS module uses the low-side DAC of the CMPSS module specified. When using DAC output from a
CMPSS instance, all other CMPSS module features for that instance are unavailable.
For CMPx_DACL instances available for a particular device, please see the DAC column of the Analog Pins and
Internal Connections table.
See the Buffered Output from CMPx_DACL Electrical Characteristics section for DAC output capabilities.

6.15.6.2 CMPSS Connectivity Diagram
CMPSS Module
GPIO Mux
CMP1_HP Comparator Subsystem 1 CTRIP1H ePWM X-BAR
Digital CTRIP1H
CMP1_HN VDDA Filter CTRIPOUT1H CTRIP1L ePWMs
DAC12 CMP1_DACL CTRIP2H
CTRIP1L
Output X-BAR
DAC12 Digital
CMP1_LN CTRIP2L
Filter CTRIPOUT1L
CMP1_LP CTRIP3H ePWM X-BAR ePWMs
CMP2_HP Comparator Subsystem 2
CTRIP2H CTRIP3L
Digital
CMP2_HN VDDA Filter CTRIPOUT2H CTRIP4H
DAC12 CTRIP4L
CTRIP2L
DAC12 Digital
CMP2_LN
Filter CTRIPOUT2L
CMP2_LP
Digital CTRIP3H
DAC12
CTRIPOUT1H
CMP3_LN
Filter CTRIPOUT3L CTRIPOUT1L
CMP3_LP CTRIPOUT2H
CTRIPOUT2L
Digital CTRIP4H
CMP4_HN VDDA Filter CTRIPOUT4H CTRIPOUT3H Output X-BAR GPIO Mux
DAC12
CTRIPOUT3L
CMP4_LN
Filter CTRIPOUT4L CTRIPOUT4H
CMP4_LP
CTRIPOUT4L
Figure 6-46. CMPSS Connectivity

6.15.6.3 Block Diagram

The block diagram for the CMPSS is shown in Figure 6-47.
• CTRIPx(x= "H" or "L") signals are connected to the ePWM X-BAR for ePWM trip response. See the
Enhanced Pulse Width Modulator (ePWM) chapter of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual for more details on the ePWM X-BAR mux configuration.
• CTRIPxOUTx(x= "H" or "L") signals are connected to the Output X-BAR for external signaling. See the
General-Purpose Input/Output (GPIO) chapter of the TMS320F28P55x Real-Time Microcontrollers Technical
Reference Manual for more details on the Output X-BAR mux configuration.
To LPM Wakeup
COMPCTL[CTRIPHSEL]
COMPSTS[COMPHSTS] Comparator
ASYNCH
SYSCLK > COMPDACHCTL[SWLOADSEL] COMPCTL[COMPHINV] 3 CTRIPH Digital Filter
CMPx_HP SYSCLK SYNCH
EPWMSYNCPER_H + 2 To EPWM X-BAR
COMPSTS[COMPHSTS]
>
COMPSTS[COMPLSTS] D Q 0 1 CTRIPOUTH Output MUX
2 1|0 DACHVALS 0 12-bit COMPH 0 0 Digital 0

To OUTPUT X-BAR
COMPDACHCTL2[XTRIGCFG] D Q 1 DACHVALA Ramp generator
DACH 0 D RQ Filter S
>
_ R
1 1
>
TRIGSYNCH COMPCTL[CTRIPOUTHSEL] CMPSS DAC
EN CMPx_HN 1 . R Q
EXT_FILTIN_H . OR CMPSS Buffered DAC
Ramp Generator(H) 1 n
COMPCTL[COMPHSOURCE] 0 0
COMPDACHCTL[RAMPSOURCE]+ COMPSTS[COMPHLATCH]
16*COMPDACHCTL2[RAMPSOURCEUSEL] CTRIPHFILCTL[FILTINSEL] 1
COMPDACHCTL[DACSOURCE] OR
COMPSTSCLR[HSYNCCLREN]
EPWM1SYNCPER 0 COMPCTL[ASYNCHEN]
EPWM2SYNCPER 1 EPWMSYNCPER_H 0 0 COMPSTSCLR[HLATCHCLR]
EPWM3SYNCPER 2
OR
EPWMBLANK_H 1
... … AND
EPWMnSYNCPER n-1 COMPDACHCTL[BLANKEN]
COMPSTSCLR[LSYNCCLREN]
COMPSTSCLR[LLATCHCLR]
EPWMSYNCPER_L
COMPDACLCTL[RAMPSOURCE]+ 0 0 COMPCTL[ASYNCLEN]
OR
16*COMPDACLCTL2[RAMPSOURCEUSEL] COMPDACLCTL[BLANKEN]
AND OR
COMPDACHCTL[BLANKSOURCE]+ 1 0 0
EPWMBLANK_L
16*COMPDACHCTL2[BLANKSOURCEUSEL] COMPSTS[COMPLLATCH]
COMPDACHCTL[SWLOADSEL] 1
EPWM1BLANK CMPx_LP CTRIPLFILCTL[FILTINSEL]
0 SYSCLK > + OR
EPWM2BLANK 1 R Q
EPWM3BLANK D Q 0 0
>
2 12-bit COMPL 0 Digital COMPCTL[CTRIPLSEL]
R
>
... … DACLVALS 0
DACL 0 D RQ Filter S
D Q 1 _ 1 1
EPWMnBLANK n-1 3 CTRIPL
CMPx_LN 1 . COMPSTS[COMPLSTS]
DACLVALA 2 To EPWM X-BAR
>
EN EXT_FILTIN_L . SYNCL
COMPDACLCTL[BLANKSOURCE]+ n SYSCLK 1 CTRIPOUTL
ASYNCL To OUTPUT X-BAR
16*COMPDACLCTL2[BLANKSOURCEUSEL] 1 COMPCTL[COMPLSOURCE] 0
Ramp Generator(L) 0 COMPCTL[COMPLINV] To LPM Wakeup
COMPCTL[CTRIPOUTLSEL]
COMPDACLCTL[DACSOURCE] CMPxDACL
TRIGSYNCL
>>1 1 Buer To Pin
COMPDACHCTL2[XTRIGCFG] 1 2|0 CMPxDACOUTEN Enable

COMPSTS[COMPHSTS] (from Analog Subsystem)
COMPSTS[COMPLSTS]
EPWMSYNCPER_L
A. CMPxDACL only exists for the CMPSS 1 module on this device.

B. Enabling the DACL to a pin disables all other functionality: DACH, both COMP, the Ramp Generator, and the digital filters.
Figure 6-47. CMPSS Module Block Diagram
Each reference 12-bit DAC can be configured to drive a reference voltage into the negative input of the
respective comparator. Some CMPSS instances also allow the low DAC output to be routed to a pin to act as
an external DAC. In this case, all other CMPSS module functionality is not useable, including the high DAC, both
comparators, ramp generation, and the digital filters. The reference 12-bit DAC is illustrated in Figure 6-48.
VDDA DACREF
12-bit DACOUTH
DACHVALA DACH To COMPH
12-bit DACOUTL
DACLVALA DACL To COMPL
VSSA
Figure 6-48. Reference DAC Block Diagram

6.15.6.4 CMPSS Electrical Data and Timing

6.15.6.4.1 CMPSS Comparator Electrical Characteristics
TPU Power-up time 500 µs
Comparator input (CMPINxx) range 0 VDDA V
Low common mode, inverting
Input referred offset error –20 20 mV
input set to 50mV
1x 4 12 20
2x 17 24 33
Hysteresis(1) LSB
3x 25 36 50
4x 30 48 67
Step response 21 60
Response time (delay from CMPINx input change to ns
Ramp response (1.65V/µs) 26
output on ePWM X-BAR or Output X-BAR)
Ramp response (8.25mV/µs) 30 ns
PSRR Power Supply Rejection Ratio Up to 250 kHz 46 dB
CMRR Common Mode Rejection Ratio 40 dB
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
CMPSS Comparator Input Referred Offset and Hysteresis
Input Referred Offset
CTRIPx
Logic Level CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0 CMPINxN or
DACxVAL
Figure 6-49. CMPSS Comparator Input Referred Offset
Hysteresis
CTRIPx
Logic Level CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0 CMPINxN or
DACxVAL
Figure 6-50. CMPSS Comparator Hysteresis

6.15.6.4.2 CMPSS DAC Static Electrical Characteristics

CMPSS DAC output range Internal reference 0 VDDA V
Static offset error(1) –25 25 mV
Static gain error(1) –2 2 % of FSR
Static DNL Endpoint corrected >–1 4 LSB
Static INL Endpoint corrected –16 16 LSB
Settling time Settling to 1LSB after full-scale output change 1 µs
Resolution 12 bits
Error induced by comparator trip or CMPSS
CMPSS DAC output disturbance(2) DAC code change within the same CMPSS –100 100 LSB
module
CMPSS DAC disturbance time(2) 200 ns
(1) Includes comparator input referred errors.

(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
6.15.6.4.3 CMPSS Illustrative Graphs
Offset Error
Figure 6-51. CMPSS DAC Static Offset

Ideal Gain
Actual Gain
Actual Linear Range
Figure 6-52. CMPSS DAC Static Gain
Linearity Error
Figure 6-53. CMPSS DAC Static Linearity
6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions

over recommended operating conditions (unless otherwise noted)(1)
RL Resistive Load(2) 5 kΩ
CL Capacitive Load 100 pF

6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions (continued)

RL = 5 kΩ 0.3 VDDA – 0.3 V
VOUT Valid Output Voltage Range(3)
RL = 1 kΩ 0.6 VDDA – 0.6 V
Reference Voltage(4) VREFHI 2.4 2.5 or 3.0 VDDA V
(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
(3) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(4) For best PSRR performance, VREFHI should be less than VDDA.
6.15.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics

General
Resolution(4) 12 bits
Load Regulation –1 1 mV/V
Glitch Energy 1.5 V-ns
Settling to 2 LSBs after 0.3V-
Voltage Output Settling Time Full-Scale 2 µs
to-3V transition
Voltage Output Settling Time 1/4th Full-Scale 1.6 µs
to-0.75V transition
Slew rate from 0.3V-to-3V
Voltage Output Slew Rate 2.8 4.5 V/µs
transition
Load Transient Settling Time 5-kΩ Load 328 ns
TPU Power Up Time Bandgap Not Enabled 500 µs
DC Characteristics
Offset Offset Error –100 100 mV
Gain Gain Error(2) –1.5 1.5 % of FSR
DNL Differential Non Linearity(4) Endpoint corrected –2 2 LSB (12-bit)
INL Integral Non Linearity Endpoint corrected –10 10 LSB (12-bit)
AC Characteristics
Integrated noise from 100 Hz
600 µVrms
Output Noise to 100 kHz
Noise density at 10 kHz 800 nVrms/√Hz
SNR Signal to Noise Ratio 1 kHz, 200 KSPS 64 dB
THD Total Harmonic Distortion 1 kHz, 200 KSPS –64.2 dB
Spurious Free Dynamic
SFDR 1 kHz, 200 KSPS 66 dB
Range
Signal to Noise and Distortion
SINAD 1 kHz, 200 KSPS 61.7 dB
Ratio
Power Supply Rejection DC 70 dB

PSRR
Ratio(3) 100 kHz 30 dB
(2) Gain error is calculated for linear output range.
(3) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
(4) 11-bit effective (monotonic response).

6.15.7 Buffered Digital-to-Analog Converter (DAC)

The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that can drive an
external load. For driving even higher loads than typical, a trade-off can be made between load size and
output voltage swing. For the load conditions of the buffered DAC, see the Buffered DAC Electrical Data and
Timing section. The buffered DAC is a general-purpose DAC that can be used to generate a DC voltage or AC
waveforms such as sine waves, square waves, triangle waves and so forth. Software writes to the DAC value
register can take effect immediately or can be synchronized with EPWMSYNCO events.
Each buffered DAC has the following features:
• 12-bit resolution
• Selectable reference voltage source
• x1 and x2 gain modes when using internal VREFHI
• Ability to synchronize with EPWMSYNCPER
DAC Module
DACCTL[DACREFSEL]
ANAREFx1P65SEL
Reference Voltage Source
0 Output Buer
2.5 V DACREF
0 1 12-Bit DAC
Internal Reference
1
Circuit 1.65 V 0
Internal Reference Circuit
1
VREFHI
ANAREFPCTL[REFPMUXSELx]
VDDA
SYSCLK > DACCTL[LOADMODE]
DACVALS D Q 0
12-bit DACOUT
DACVALA
DAC
D Q 1
EPWM1SYNCPER
0
EN
EPWM2SYNCPER
1
EPWM3SYNCPER VSSA VSSA
2
...
... DACCTL[MODE]
EPWMnSYNCPER (Select x1 or x2 gain)
n-1
DACCTL[SYNCSEL]
A. VDAC is not available for this device; so, VREFHI and VSSA are the reference voltages.
Figure 6-54. DAC Module Block Diagram

6.15.7.1 Buffered DAC Electrical Data and Timing

6.15.7.1.1 Buffered DAC Operating Conditions
RL Resistive Load(2) 5 kΩ
CL Capacitive Load 100 pF
RL = 5 kΩ 0.3 VDDA – 0.3 V
VOUT Valid Output Voltage Range(3)
RL = 1 kΩ 0.6 VDDA – 0.6 V
Reference Voltage(4) VREFHI 2.4 2.5 or 3.0 VDDA V
(2) DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
(3) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(4) For best PSRR performance, VREFHI should be less than VDDA.
6.15.7.1.2 Buffered DAC Electrical Characteristics

General
Resolution 12 bits
Load Regulation –1 1 mV/V
Glitch Energy 1.5 V-ns
Voltage Output Settling Time Full-Scale 2 µs
to-3V transition
Voltage Output Settling Time 1/4th Full-Scale 1.6 µs
to-0.75V transition
Slew rate from 0.3V-to-3V
Voltage Output Slew Rate 2.8 4.5 V/µs
transition
5-kΩ Load 328 ns
Load Transient Settling Time
1-kΩ Load 557 ns
Reference Input Resistance(2) VREFHI 160 200 240 kΩ
External Reference mode 500 µs
TPU Power Up Time
Internal Reference mode 5000 µs
DC Characteristics
Offset Offset Error Midpoint –10 10 mV
Gain Gain Error(3) –2.5 2.5 % of FSR
DNL Differential Non Linearity(4) Endpoint corrected –1 ±0.4 1 LSB
INL Integral Non Linearity Endpoint corrected –5 ±2 5 LSB
AC Characteristics
Integrated noise from 100 Hz
600 µVrms
Output Noise to 100 kHz
Noise density at 10 kHz 800 nVrms/√Hz
SNR Signal to Noise Ratio 1 kHz, 200 KSPS 64 dB
THD Total Harmonic Distortion 1 kHz, 200 KSPS –64.2 dB
Spurious Free Dynamic
SFDR 1 kHz, 200 KSPS 66 dB
Range
Signal to Noise and Distortion
SINAD 1 kHz, 200 KSPS 61.7 dB
Ratio

6.15.7.1.2 Buffered DAC Electrical Characteristics (continued)

Power Supply Rejection DC 70 dB

PSRR
Ratio(5) 100 kHz 30 dB
(2) Per active Buffered DAC module.
(3) Gain error is calculated for linear output range.
(4) The DAC output is monotonic.
(5) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.

6.15.8 Programmable Gain Amplifier (PGA)

The Programmable Gain Amplifier (PGA) is used to amplify an input voltage for the purpose of increasing the
effective resolution of the downstream ADC and CMPSS modules.
The integrated PGA helps to reduce cost and design effort for many control applications that traditionally require
external, stand-alone amplifiers. On-chip integration ensures that the PGA is compatible with the downstream
ADC and CMPSS modules. Software-selectable gain and filter settings make the PGA adaptable to various
performance needs.
The PGA has the following features:
• Rail to rail input and output voltage within VDDA and VSSA range
• Programmable gain modes including unity gain and other values from 2X - 64X
• Standalone gain mode using off-chip passive components
• Post-gain filtering using on-chip resistors
• Differential input support
• Hardware assisted chopping for offset reduction
• Support for Kelvin ground connections using PGA_INM pins
The active component in the PGA is an embedded operational amplifier (op amp) that is configured as a
non-inverting or inverting amplifier with internal feedback resistors. These internal feedback resistor values are
paired to produce software selectable voltage gains.
Three PGA signals are available at the device pins:
• PGA_INP is the positive input to the PGA op-amp.
• PGA_INM is the negative input to the PGA op-amp. See the device data manual for more information.
• PGA_OUT supports op-amp output filtering with RC components. The filtered signal is available for sampling
and monitoring by on-chip ADC and CMPSS modules.
PGA_OUT_INT is an internal signal at the op amp output. It is available for sampling and monitoring by the
internal ADC and CMPSS modules. Figure 6-55 shows the PGA block diagram.
To ADC and CMPSS
VDDA PGA_OUTENABLE & FILT_RES_SEL=0
FILT_RES_SEL
PGA_INP +
_ PGA_OUT
RFILT
PGA_OUTENABLE PGA_OUTENABLE & OUT_EN_INTGAIN &

FILT_RES_SEL FILT_RES_SEL=0
VSSA PGA_OUT_INT To ADC and CMPSS

Ria Rib
PGA_INM
Figure 6-55. PGA Block Diagram

6.15.8.1 PGA Electrical Data and Timing

6.15.8.1.1 PGA Operating Conditions
PGA Output Range(1) VSSA+0.025 VDDA-0.025 V
Cap Load on PGA Out 40 pF
(1) This is the linear output range of the PGA. The PGA can output voltages outside this range, but the voltages will not be linear.
6.15.8.1.2 PGA Characteristics

General
Gain = 1 125
Gain = 2/-1 146
Min ADC S+H Settling within Gain = 4/-3 125
±1 ADC LSB Accuracy
Gain = 8/-7 154 ns
(No Filter; All Gain Settings;
Single ADC Driven) (4) Gain = 16/-15 227
Gain = 32/-31 322
Gain = 64/-63 380
Gain = 1 146
Gain = 2/-1 146
Min ADC S+H Settling within Gain = 4/-3 113
±1 ADC LSB Accuracy
Gain = 8/-7 155 ns
(No Filter; All Gain Settings;
Two ADC Driven) (4) Gain = 16/-15 230
Gain = 32/-31 352
Gain = 64/-63 450
1
2, 4, 8, 16, 32, 64
Gain Settings
-1, -3, -7, -15, -31,
-63
Short Circuit Current (5) 41 mA
Full Scale Step Response G<64 450 ns
(No Filter) Settling within
0.05% Accuracy(4) G = 64/-63 370 ns
Settling Time: Gain

10 µs
Switching
Slew Rate Naked OPA Mode 12 V/µs
Gain = 1 12 V/µs
Gain = 2/-1 24 V/µs
Gain = 4/-3 43 V/µs
Slew Rate Gain = 8/-7 67 V/µs
Gain = 16/-15 35 V/µs
Gain = 32/-31 29 V/µs
Gain = 64/-63 26 V/µs

6.15.8.1.2 PGA Characteristics (continued)

Gain = 1 256 kΩ
Gain = 2/-1 16 kΩ
Gain = 4/-3 8 kΩ
Ria Gain = 8/-7 8 kΩ
Gain = 16/-15 8 kΩ
Gain = 32/-31 8 kΩ
Gain = 64/-63 4 kΩ
Gain = 1 0 kΩ
Gain = 2/-1 16 kΩ
Gain = 4/-3 24 kΩ
Rib Gain = 8/-7 56 kΩ
Gain = 16/-15 120 kΩ
Gain = 32/-31 248 kΩ
Gain = 64/-63 252 kΩ
RFILT = 800 Ω 800 Ω
RFILT = 400 Ω 400 Ω
Filter Resistor Targets RFILT = 200 Ω 200 Ω
RFILT = 100 Ω 100 Ω
RFILT = 50 Ω 50 62 Ω
Gain Bandwidth Product
Gain = 1 7 MHz
(Naked Op-Amp Mode)
Gain = 1 15 MHz
Gain = 2/-1 14 MHz
Gain = 4/-3 13.5 MHz
Closed Loop -3bd BW Gain = 8/-7 12 MHz
Gain = 16/-15 11 MHz
Gain = 32/-31 5.5 MHz
Gain = 64/-63 5.0 MHz
DC Characteristics
Gain Error(1) Gain = 1 –0.18 0.18 %
Gain Error(1) Gain = 2, -1 –0.45 0.45 %
Gain Error(1) Gain = 4, -3 –0.70 0.70 %
Gain Error(1) Gain = 8, -7 –0.84 0.84 %
Gain Error(1) Gain = 16, -15 –0.90 0.90 %
Gain Error(1) Gain = 32, -31 –1.05 1.05 %
Gain Error(1) Gain = 64, -63 –1.82 1.82 %
Offset Error(2) Input Referred –3.0 +/-1.0 3.0 mV
Offset Temp Coefficient Input Referred -7.0 7.0 µV/C
Offset Error - Chopped -0.8 0.8 mV
Offset Temp Coefficient -
0.3 µV/C
Chopped
G<64 2.5 12b LSB
DC Code Spread
G = 64/-63 4 12b LSB

6.15.8.1.2 PGA Characteristics (continued)

AC Characteristics
Phase Margin Cload = 40pF
45 Deg
Naked OPA G=1
Aol (Open loop voltage gain) RL = 7.5kΩ to GND
94 dB
Naked OPA 0.3V<VO<VDDA-0.3V
THD + Noise (THD+N) fin = 1kHz
82 dB
Naked OPA G=1
Gain = 1 68
Gain = 2, -1 68
Gain = 4, -3 66
SNR 10kHz (With ADC) Gain = 8, -7 62 dB
Gain = 16, -15 58
Gain = 32, -31 55
Gain = 64, -63 51
THD(3) DC –78 dB
Gain = 1 –58
Gain = 2, -1 –70
Gain = 4, -3 –70
THD(Up to 100kHz) (3) Gain = 8, -7 –70 dB
Gain = 16, -15 –70
Gain = 32, -31 –58
Gain = 64, -63 –58
DC: VIN <=1.5V –86 dB
CMRR DC: Full Input Range -77 dB
Up to 100 kHz –50 dB
DC –75 dB
PSRR(3) Up to 10 kHz –60 dB
Up to 100 kHz –40 dB
1 kHz 200 nV/sqrt(Hz)
Noise PSD(3)
10 kHz 100 nV/sqrt(Hz)
Integrated Noise
3 Hz to 30 MHz 100 µV
(Input Referred)(3)
(1) Includes ADC gain error.

(2) Includes ADC offset error.
(3) Performance of PGA alone.
(4) Step response time w filter = tS+H + 7.6*Rfilt* Cfilt
(5) Assumes no filter circuit

6.16 Control Peripherals

6.16.1 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced
trip-zone functionality, and global register reload capabilities.
The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules and allows localized synchronization within the modules.
Figure 6-56 shows the ePWM module. Figure 6-57 shows the ePWM trip input connectivity.

Time-Base (TB)
TBPRD Shadow (24) EXTSYNCIN ePWM EXTSYNCOUT

TBPRDHR (8) SYNC
TBPRD Active (24)
Scheme
CTR=PRD
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SWFSYNC]
Counter
DCAEVT1/sync(A)
Up/Down
(16 bit) DCBEVT1/sync(A)
CTR=ZERO
TBCTR
Active (16) CTR_Dir CTR=PRD EPWMx_INT
CTR=ZERO
TBPHSHR (8)
CTR=PRD or ZERO EPWMxSOCA
16 8
CTR=CMPA Event On-chip
Phase EPWMxSOCB
TBPHS Active (24) Trigger ADC
Control CTR=CMPB
And
CTR=CMPC
Interrupt
CTR=CMPD (ET) ADCSOCOUTSELECT
Counter Compare (CC)
CTR_Dir
Action
CTR=CMPA Qualifier DCAEVT1.soc(A) Select and pulse stretch
(AQ) DCBEVT1.soc(A) for external ADC
CMPAHR (8)
16 HiRes PWM (HRPWM)
CMPAHR (8)
CMPA Active (24) ADCSOCAO
ADCSOCBO
CMPA Shadow (24) EPWMA ePWMxA
CTR=CMPB Dead PWM Trip

Band Chopper Zone
(DB) (DB) (TZ)
CMPBHR (8)
16
CMPB Active (16) EPWMB ePWMxB
CMPB Shadow (16)
CMPBHR (8)
EPWMx_TZ_INT
TBCNT (16) CTR=CMPC CTR=ZERO
TZ1 to TZ3
DCAEVT1.inter
EMUSTOP
CMPC[15-0] 16 DCBEVT1.inter
CLOCKFAIL
DCAEVT2.inter
CMPC Active (16) EQEPxERR
DCBEVT2.inter
CMPC Shadow (16) DCAEVT1.force(A)
DCBEVT1.force(A)
TBCNT (16) CTR=CMPD DCAEVT2.force(A)
DCBEVT2.force(A)
CMPD[15-0] 16
CMPD Active (16)

CMPD Shadow (16)
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 6-56. ePWM Submodules and Critical Internal Signal Interconnects

Figure 6-57. ePWM Trip Input Connectivity

6.16.1.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules and allows localized synchronization within the modules. Figure 6-58 shows the synchronization
scheme.
TBCTL
TBCTL2[OSHTSYNC]
TBCTL3[OSSFRCEN]
GLDCTL2[OSHTLD]
SWFSYNC
:ULWH ³1´ WR
:ULWH ³1´ WR
CTR=ZERO
CTR=CMPB
CTR=CMPC
TBCTL2[OSHTSYNCMODE]
CTR=CMPD
CLR
DCAEVT1.sync One Shot
DCBEVT1.sync Latch
0
Set Q
EPWMSYNCOUTEN
1
SWEN
ZEROEN
0 0
CMPBEN
1 EPWMxSYNCOUT
CMPCEN OR 1
0
CMPDEN
DCARVT1EN
TBCTL2[SELFCLRTRREM]
DCBEVT1EN
Disable Clear
Register
EPWM1SYNCOUT 0
|
|
|
EPWMxSYNCOUT
EPWMxSYNCIN HRPCTL[PWMSYNCSELX]
ECAP1SYNCOUT CTR=CMPC UP
|
|
|
CTR=CMPC DOWN
ECAPySYNCOUT CTR=CMPD UP EPWMxSYNCPER
Other Sources CTR=CMPD DOWN CMPSS
DAC
HRPCTL[PWMSYNCSEL]
EPWMSYNCINSEL CTR=PRD
CTR=ZERO
Note: SYNCO and SYNCOUT are used interchangeably
Figure 6-58. Synchronization Chain Architecture

6.16.1.2 ePWM Electrical Data and Timing

6.16.1.2.1 ePWM Timing Requirements
MIN MAX UNIT
Asynchronous 2tc(EPWMCLK)
tw(SYNCIN) Sync input pulse width Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW)
6.16.1.2.2 ePWM Switching Characteristics

PARAMETER(1) MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SYSCLK) cycles
Delay time, trip input active to PWM forced high
td(TZ-PWM) Delay time, trip input active to PWM forced low 25 ns
Delay time, trip input active to PWM Hi-Z
(1) 20-pF load on pin.
6.16.1.2.3 Trip-Zone Input Timing

6.16.1.2.3.1 Trip-Zone Input Timing Requirements
MIN MAX UNIT
Asynchronous 1tc(EPWMCLK) cycles
tw(TZ) Pulse duration, TZx input low Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles
6.16.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
EPWMCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)
(B)
PWM
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery
software.
Figure 6-59. PWM Hi-Z Characteristics

6.16.2 High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
6.16.2.1 HRPWM Electrical Data and Timing
6.16.2.1.1 High-Resolution PWM Characteristics
Micro Edge Positioning (MEP) step size(1) 150 310 ps
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
6.16.3 External ADC Start-of-Conversion Electrical Data and Timing

6.16.3.1 External ADC Start-of-Conversion Switching Characteristics
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(SYSCLK) cycles
6.16.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 6-60. ADCSOCAO or ADCSOCBO Timing

6.16.4 Enhanced Capture (eCAP)

The features of the eCAP module include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed by way of Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module features described in this chapter include:
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single-shot capture of up to four event time-stamps
• Continuous mode capture of time stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
The capture functionality of the Type 1 eCAP is enhanced from the Type 0 eCAP with the following added
features:
• Event filter reset bit
– Writing a 1 to ECCTL2[CTRFILTRESET] clears the event filter, the modulo counter, and any pending
interrupts flags. Resetting the bit is useful for initialization and debug.
• Modulo counter status bits
– The modulo counter (ECCTL2 [MODCNTRSTS]) indicates which capture register is loaded next. In the
Type 0 eCAP, to know the current state of the modulo counter was not possible
• DMA trigger source
– eCAPxDMA was added as a DMA trigger. CEVT[1-4] can be configured as the source for eCAPxDMA.
• Input multiplexer
– ECCTL0 [INPUTSEL] selects one of 128 input signals, which are detailed in the Configuring Device
Pins for the eCAP section of the Enhanced Capture (eCAP) chapter in the TMS320F28P55x Real-Time
Microcontrollers Technical Reference Manual .
• EALLOW protection
– EALLOW protection was added to critical registers. To maintain software compatibility with Type-0,
configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
The capture functionality of the Type 2 eCAP is enhanced from the Type 1 eCAP with the following added
features:
• Added ECAPxSYNCINSEL register
– ECAPxSYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can have
a separate SYNCIN signal.

6.16.4.1 eCAP Block Diagram

ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
CTRPHS
(phase register−32 bit) APWM Mode
SYNC
ECAPxSYNCIN
OVF CTR_OVF CTR [0−31]
ECAPxSYNCOUT TSCTR
PWM
(counter−32 bit) Output
Delta−Mode PRD [0−31] Compare
RST X-Bar
Logic
CMP [0−31]
32
CTR=PRD
CTR [0−31]
CTR=CMP
32
PRD [0−31]
HRCTRL[HRE] ECCTL1 [ CAPLDEN, CTRRSTx]
32
32 CAP1 LD1
Polarity
(APRD Active) LD
Select
APRD
32
shadow CMP [0−31]
HRCTRL[HRE] 32
32 HRCTRL[HRE]
32
CAP2 LD2 Polarity
(ACMP Active) LD Select Other
Event [127:16]
Sources
Prescale
Event
32 ACMP
qualifier 16
shadow ECCTL1[PRESCALE] Input
HRCTRL[HRE] [15:0]
X-Bar
32
Polarity
32 CAP3 LD3
LD Select
(APRD Shadow)
HRCTRL[HRE]
32
32 CAP4 LD4 Polarity
(ACMP Shadow) LD
Select
4 Edge Polarity Select

ECCTL1[CAPxPOL]
4
ECCTL2[CTRFILTRESET]
Interrupt Continuous /
Trigger Oneshot MODCNTRSTS
and CTR_OVF Capture Control
Flag
CTR=PRD
ECAPx Control
(to ePIE) CTR=CMP
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
SYSCLK Capture Pulse
HRCLK HR Submodule
ECAPx_HRCAL HR Input
(to ePIE)
Figure 6-61. eCAP Block Diagram

6.16.4.2 eCAP Synchronization

The eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from
EPWM, eCAP, or X-Bar. The SYNC signal is defined by the selection in the ECAPxSYNCINSEL[SEL] bit for
ECAPx as shown in Figure 6-62.
ECAPx
Disable 0x0
0x1 ECAPxSYNCIN
ECAPxSYNCIN EPWMxSYNCOUT
ECCTL2[SWSYNC] EXTSYNCOUT
Signals ECAPxSYNCOUT
CTR=PRD
(EPWM, ECAP, Disable
INPUTXBAR, «) Disable
0xn SYNCSELECT[SYNCOUT]
ECCTL2[SYNCOSEL]
ECAPSYNCINSEL[SEL]
Figure 6-62. eCAP Synchronization Scheme
6.16.4.3 eCAP Electrical Data and Timing

6.16.4.3.1 eCAP Timing Requirements
MIN NOM MAX UNIT
Asynchronous 2tc(SYSCLK)
tw(CAP) Capture input pulse width Synchronous 2tc(SYSCLK) ns
With input qualifier 1tc(SYSCLK) + tw_(IQSW)
6.16.4.3.2 eCAP Switching Characteristics

tw(APWM) Pulse duration, APWMx output high/low 20 ns

6.16.5 Enhanced Quadrature Encoder Pulse (eQEP)

The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-performance
motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 6-63):
• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)
• Position counter and control unit for position measurement (PCCU)
• Quadrature edge-capture unit for low-speed measurement (QCAP)
• Unit time base for speed/frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
• Quadrature Mode Adapter (QMA)
System
control registers
To CPU
EQEPxENCLK
SYSCLK
Data bus
QCPRD
Enhanced QEP (eQEP) peripheral
QCAPCTL QCTMR
16 16
16
Quadrature
capture unit
QCTMRLAT (QCAP)
QCPRDLAT
Registers QUTMR QWDTMR

used by QUPRD QWDPRD
multiple units
32 16
QEPCTL QDECCTL
QEPSTS UTOUT 16
UTIME QWDOG
QFLG EQEPxAIN EQEPx_A
WDTOUT QMA EQEPxBIN EQEPx_B
EQEPxINT QCLK
PIE
QDIR EQEPxIIN
32 Quadrature
Position counter/ QI decoder EQEPxIOUT GPIO EQEPx_INDEX
control unit QS (QDU) MUX
EQEPxIOE
QPOSLAT (PCCU) PHE
QPOSSLAT PCSOUT EQEPxSIN
QPOSILAT EQEPxSOUT EQEPx_STROBE
EQEPxSOE
32 32 16
QPOSCNT QPOSCMP QEINT

QPOSINIT QFRC
QPOSMAX QCLR
QPOSCTL
Figure 6-63. eQEP Block Diagram

6.16.5.1 eQEP Electrical Data and Timing

6.16.5.1.1 eQEP Timing Requirements
MIN MAX UNIT
Synchronous(1) 2tc(SYSCLK)
tw(QEPP) QEP input period cycles
Synchronous with input qualifier 2[1tc(SYSCLK) + tw(IQSW)]
tw(INDEXH) QEP Index Input High time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)
tw(INDEXL) QEP Index Input Low time cycles
tw(STROBH) QEP Strobe High time cycles
tw(STROBL) QEP Strobe Input Low time cycles
(1) The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.
6.16.5.1.2 eQEP Switching Characteristics

td(CNTR)xin Delay time, external clock to counter increment 5tc(SYSCLK) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 7tc(SYSCLK) cycles

6.17 Communications Peripherals

6.17.1 Modular Controller Area Network (MCAN)
The Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed
real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to
detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides
data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD
feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may
coexist on the same network without any conflict provided that partial network transceivers, which can detect
and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is
compliant to ISO 11898-1:2015.
Note
The availability of the CAN FD feature is dependent on the device's part number. Refer to the device
data sheet for more information.
Device
MCANSS
NMI Uncorrectable ECC
Correctable ECC
Configurable Interrupts (2 lines)
PIE
Counter Overflow and Clock Stop/
Wakeup
CPU BUS mcanss_tx
SYSCLK Peripheral Clock

mcanss_rx
Clock disable/
MCAN Bit Clock Bit Timing Clock
enable
Wakeup
Clock Stop and Wakeup
RESET Reset
Figure 6-64. MCAN Module Overview
The MCAN module implements the following features:

• Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015
• Full CAN FD support (up to 64 data bytes)
• AUTOSAR and SAE J1939 support
• Flexible Message RAM allocation (maximum configuration below is for a device with 4352 32-bit word
message RAM)
– Up to 32 dedicated transmit buffers
– Configurable transmit FIFO, up to 32 elements
– Configurable transmit queue, up to 32 elements
– Configurable transmit Event FIFO, up to 32 elements
– Up to 64 dedicated receive buffers
– Two configurable receive FIFOs, up to 64 elements each
– Up to 128 filter elements
• Loop-back mode for self-test
• Maskable interrupt (two configurable interrupt lines, correctable ECC, counter overflow and clock stop/
wakeup)
• Non-maskable interrupt (uncorrectable ECC)
• Two clock domains (CAN clock/host clock)
• ECC check for Message RAM
• Clock stop and wake-up support
• Timestamp counter
Non-supported features:
• Host bus firewall
• Clock calibration
• Debug over CAN

6.17.2 Inter-Integrated Circuit (I2C)

The I2C module has the following features:
• Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple controller-transmitters and target-receivers
– Support for multiple target-transmitters and controller-receivers
– Combined controller transmit/receive and receive/transmit mode
– Data transfer rate from 10Kbps up to 400Kbps (Fast-mode)
• Supports voltage thresholds compatible to:
– SMBus 3.0 and below
– PMBus 1.3 and below
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• Supports two ePIE interrupts
– I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:
• Transmit Ready
• Receive Ready
• Register-Access Ready
• No-Acknowledgment
• Arbitration-Lost
• Stop Condition Detected
• Addressed-as-Target
– I2Cx_FIFO interrupts:
• Transmit FIFO interrupt
• Receive FIFO interrupt
• Module enable and disable capability
• Free data format mode
Figure 6-65 shows how the I2C peripheral module interfaces within the device.

I2C module
I2CXSR I2CDXR
TX FIFO
FIFO Interrupt
SDA
to CPU/PIE
RX FIFO
Peripheral bus
I2CRSR I2CDRR
Control/status
Clock registers CPU
SCL synchronizer
Prescaler
Noise filters Interrupt to

I2C INT CPU/PIE
Arbitrator
Figure 6-65. I2C Peripheral Module Interfaces

6.17.2.1 I2C Electrical Data and Timing
Note
To meet all of the I2C protocol timing specifications, the I2C module clock must be configured in the
range from 7 MHz to 12 MHz.
A pullup resistor must be chosen to meet the I2C standard timings. In most circumstances, 2.2 kΩ of
total bus resistance to VDDIO is sufficient. For evaluating pullup resistor values for a particular design,
see the I2C Bus Pullup Resistor Calculation Application Note.
6.17.2.1.1 I2C Timing Requirements

NO. MIN MAX UNIT
Standard mode
T0 fmod I2C module frequency 7 12 MHz
Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 4.0 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 4.0 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 250 ns
T5 tr(SDA) Rise time, SDA 1000 ns
T6 tr(SCL) Rise time, SCL 1000 ns
T7 tf(SDA) Fall time, SDA 300 ns
T8 tf(SCL) Fall time, SCL 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 4.0 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF
Fast mode
T0 fmod I2C module frequency 7 12 MHz
Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 0.6 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 0.6 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
T5 tr(SDA) Rise time, SDA 20 300 ns
T6 tr(SCL) Rise time, SCL 20 300 ns
T7 tf(SDA) Fall time, SDA 11.4 300 ns
T8 tf(SCL) Fall time, SCL 11.4 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 0.6 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF

6.17.2.1.2 I2C Switching Characteristics

NO. PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode
S1 fSCL SCL clock frequency 0 100 kHz
S2 TSCL SCL clock period 10 µs
S3 tw(SCLL) Pulse duration, SCL clock low 4.7 µs
S4 tw(SCLH) Pulse duration, SCL clock high 4.0 µs
Bus free time between STOP and START
S5 tBUF 4.7 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 3.45 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 3.45 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
Fast mode
S1 fSCL SCL clock frequency 0 400 kHz
S2 TSCL SCL clock period 2.5 µs
S3 tw(SCLL) Pulse duration, SCL clock low 1.3 µs
S4 tw(SCLH) Pulse duration, SCL clock high 0.6 µs
Bus free time between STOP and START
S5 tBUF 1.3 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 0.9 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 0.9 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
6.17.2.1.3 I2C Timing Diagram

STOP START
SDA
ACK Contd...
S6 T10 S7
T5 T7 S3
SCL S4 Contd...
9th
T6 T8 clock
S2
Repeated
START STOP
S5
SDA
ACK
T2
T9
T1
SCL
9th
clock
Figure 6-66. I2C Timing Diagram

6.17.3 Power Management Bus (PMBus) Interface

The PMBus module has the following features:
• Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
• Supports voltage thresholds compatible to:
– PMBus 1.3and below
– SMBus 3.0and below
• Support for controller and target
• Support for I2C mode
• Support for threespeeds:
– Standard Mode: Up to 100 kHz
– Fast Mode: 400 kHz
– Fast Plus Mode: 1MHz
• Packet error checking
• CONTROL and ALERT signals
• Clock high and low time-outs
• Four-byte transmit and receive buffers
• One maskable interrupt, which can be generated by several conditions:
– Receive data ready
– Transmit buffer empty
– Target address received
– End of message
– ALERT input asserted
– Clock low time-out
– Clock high time-out
– Bus free
Note
Please see the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual to
determine which pins support Fast Plus Mode as well as full SMBUS3.0 and PMBUS1.3 specifications
PCLKCR20
SYSCLK
Div PMBCTRL
ALERT DMA
Bit clock
CTL Other registers
GPIO Mux CPU

PMBTXBUF
SCL
Shift register PMBRXBUF

SDA PMBUSA_INT PIE
PMBus Module
Figure 6-67. PMBus Block Diagram

6.17.3.1 PMBus Electrical Data and Timing
6.17.3.1.1 PMBus Electrical Characteristics

VIL Valid low-level input voltage 0.8 V
VIH Valid high-level input voltage 2.1 VDDIO V
VOL Low-level output voltage At Ipullup = 4 mA 0.4 V
IOL Low-level output current VOL ≤ 0.4 V 4 mA
Pulse width of spikes that must be
tSP 0 50 ns
suppressed by the input filter
Ii Input leakage current on each pin 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
Ci Capacitance on each pin 10 pF
6.17.3.1.2 PMBus Fast Plus Mode Switching Characteristics

Fmod PMBus Module Clock Frequency(2) 20 25 MHz
3.3V Nominal Bus Voltage 10 1000(3) kHz
fSCL SCL clock frequency
5.0V Nominal Bus Voltage 10 1000(4) kHz
Bus free time between STOP and
tBUF 0.5 µs
START conditions
START condition hold time -- SDA fall
tHD;STA 0.26 µs
to SCL fall delay
Repeated START setup time -- SCL
tSU;STA 0.26 µs
rise to SDA fall delay
STOP condition setup time -- SCL rise
tSU;STO 0.26 µs
to SDA rise delay
Data hold time after SCL fall 300 ns
tHD;DAT Data hold time after SCL fall
0 ns
PMBCTRL_ZH_EN = 1 (1)
tSU;DAT Data setup time before SCL rise 50 ns
tTimeout Clock low time-out 25 35 ms
tLOW Low period of the SCL clock 0.5 µs
tHIGH High period of the SCL clock 0.26 50 µs
Cumulative clock low extend time
tLOW;SEXT From START to STOP 25 ms
(target device)
tLOW;MEXT Within each byte 10 ms
(controller device)
tr Rise time of SDA and SCL 5% to 95% 20 120 ns
tf Fall time of SDA and SCL 95% to 5% 20 120 ns
(1) This bit must be set to enable 0ns hold time/SMBUS3.0 Compliance
(2) If the max clock is used all below timings will be met with the default register configurations for the PMBUS
(3) Due to max IO drive strength of 12mA, 1MHz SCL clock is only valid for bus capacitances up to 520pF
(4) Due to max IO drive strength of 12mA, 1MHz SCL clock is only valid for bus capacitances up to 330pF

6.17.3.1.3 PMBus Fast Mode Switching Characteristics

f(SYSCLK)
Fmod PMBus Module Clock Frequency (2) 10 MHz
/ 32
fSCL SCL clock frequency 10 400 kHz

tBUF 1.3 µs
START conditions
tHD;STA 0.6 µs
to SCL fall delay
tSU;STA 0.6 µs
tSU;STO 0.6 µs
to SDA rise delay
0 ns
PMBCTRL_INC_1[ZH+EN] = 1(1)
tHIGH High period of the SCL clock 0.6 50 µs
(target device)
(controller device)
tr Rise time of SDA and SCL 5% to 95% 20 300 ns
tf Fall time of SDA and SCL 95% to 5% 20 300 ns

6.17.3.1.4 PMBus Standard Mode Switching Characteristics

f(SYSCLK)
Fmod PMBus Module Clock Frequency(2) 10 MHz
/ 32
fSCL SCL clock frequency 10 100 kHz

tBUF 4.7 µs
START conditions
tHD;STA 4 µs
to SCL fall delay
tSU;STA 4.7 µs
tSU;STO 4 µs
to SDA rise delay
0 ns
PMBCTRL_INC_1[ZH+EN] = 1 (1)
tHIGH High period of the SCL clock 4 50 µs
(target device)
(controller device)
tr Rise time of SDA and SCL 1000 ns
tf Fall time of SDA and SCL 300 ns

6.17.4 Serial Communications Interface (SCI)

The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
– Baud rate programmable to 64K different rates
• Data-word format
– 1 start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.
Figure 6-68 shows the SCI block diagram.

TXSHF
SCITXD
Register
TXENA
SCICTL1.1
Frame
Format and Mode
Parity
Even/Odd TXEMPTY
0 1
SCICCR.6 8 SCICTL2.6
Enable
TX FIFO_0
TXINT
SCICCR.5 To CPU
TX FIFO_1 TX FIFO Interrupts TX Interrupt
88
Logic
TX FIFO_N
TXINTENA
TXRDY SCICTL2.0
8
TXWAKE 0 1 SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
WUT 8
Transmit Data
Buffer Register
SCITXBUF.7-0 Auto Baud Detect Logic
Baud Rate
MSB/LSB
LSPCLK Registers
RXSHF
SCIRXD
Register
SCIHBAUD.15-8 RXWAKE
SCILBAUD.7-0 SCICTL1.0 SCIRXST.1
RXENA
0 1
8
SCIFFENA
SCIFFTX.14 RX FIFO_0 RXINT
8 RX FIFO_1 To CPU
RX FIFO Interrupts RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8 SCIFFRX.15
0 1
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA BRKDT
RXERRINTENA
SCICTL1.0
SCIRXST.5 SCICTL1.6
SCI RX Interrupt Select Logic

8
SCIRXST.5-2
Receive Data BRKDT FE OE PE
Buffer Register
RXERROR
SCIRXBUF.7-0
SCIRXST.7
Figure 6-68. SCI Block Diagram

6.17.5 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-
transfer rate. The SPI is normally used for communications between the MCU controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications are
supported by the controller or peripheral operation of the SPI. The port supports a 16-level, receive and transmit
FIFO for reducing CPU servicing overhead.
The SPI module features include:
• SPIPOCI: SPI peripheral-output/controller-input pin
• SPIPICO: SPI peripheral-input/controller-output pin
• SPIPTE: SPI peripheral transmit-enable pin
• SPICLK: SPI serial-clock pin
• Two operational modes: Controller and Peripheral
• Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithm
• 16-level transmit/receive FIFO
• DMA support
• High-speed mode
• Delayed transmit control
• 3-wire SPI mode
• SPIPTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 6-69 shows the SPI CPU interfaces.

PCLKCR8
Low-Speed
LSPCLK SYSCLK CPU
Prescaler
Bit Clock
SYSRS
Peripheral Bus
SPIPICO
SPIPOCI
GPIO MUX SPI
SPIINT
SPICLK PIE
SPITXINT
SPIPTE
SPIRXDMA
DMA
SPITXDMA
Figure 6-69. SPI CPU Interface

6.17.5.1 SPI Controller Mode Timings

The following section contains the SPI Controller Mode Timings.
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPIPICO, and SPIPOCI.
6.17.5.1.1 SPI Controller Mode Timing Requirements

NO. PARAMETER (2) (BRR + 1)(1) MIN MAX UNIT
High-Speed Mode
8 tsu(POCI)M Setup time, SPIPOCI valid before SPICLK Even, Odd 0.7 ns
Setup time, SPIPOCI valid before
8 tsu(POCI)M SPICLK(when used on pin muxed with Even, Odd 1.5 ns
PMBUS - GPIO2, 3, 9, or 32)
8 tsu(POCI)M SPICLK(when used on pin muxed with USB Even, Odd 1.5 ns
- GPIO23, or 41)
9 th(POCI)M Hold time, SPIPOCI valid after SPICLK Even, Odd 6.5 ns
Normal Mode
8 tsu(POCI)M Setup time, SPIPOCI valid before SPICLK Even, Odd 15 ns
8 tsu(POCI)M SPICLK(when used on pin muxed with Even, Odd 16.5 ns
9 th(POCI)M Hold time, SPIPOCI valid after SPICLK Even, Odd 0 ns
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
(2) GPIOs 2, 3, 9, 23, 32, or 41 do not support full High-Speed Mode(37.5MHz) SPI operation

6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0

NO. PARAMETER (1) (2) (4) (BRR + 1)(3) MIN MAX UNIT
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
2 tw(SPC1)M Pulse duration, SPICLK, first pulse 0.5tc(SPC)M + ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
3 tw(SPC2)M Pulse duration, SPICLK, second pulse 0.5tc(SPC)M – ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
1.5tc(SPC)M –
Even 1.5tc(SPC)M – 3tc(SYSCLK) – 3
3tc(SYSCLK) + 3
23 td(SPC)M Delay time, SPIPTE active to SPICLK ns
1.5tc(SPC)M –
Odd 1.5tc(SPC)M – 4tc(SYSCLK) – 3
4tc(SYSCLK) + 3
1.5tc(SPC)M –
Delay time, SPIPTE active to Even 1.5tc(SPC)M – 3tc(SYSCLK) – 4
3tc(SYSCLK) + 3
23 td(SPC)M SPICLK(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) 1.5tc(SPC)M –
Odd 1.5tc(SPC)M – 4tc(SYSCLK) – 4
4tc(SYSCLK) + 3
1.5tc(SPC)M –
Even 1.5tc(SPC)M – 3tc(SYSCLK) – 3 3tc(SYSCLK) +
Delay time, SPIPTE active to 5.5
23 td(SPC)M SPICLK(when used on pin muxed with ns
USB - GPIO23 or GPIO41) 1.5tc(SPC)M –
Odd 1.5tc(SPC)M – 4tc(SYSCLK) – 3 4tc(SYSCLK) +
5.5
24 tv(STE)M Valid time, SPICLK to SPIPTE inactive 0.5tc(SPC)M – ns
0.5tc(LSPCLK) + 3
Valid time, SPICLK to SPIPTE Even 0.5tc(SPC)M – 4 0.5tc(SPC)M + 3

24 tv(STE)M inactive(when used on pin muxed with 0.5tc(SPC)M – ns
PMBUS - GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4
0.5tc(LSPCLK) + 3
0.5tc(SPC)M +
Even 0.5tc(SPC)M – 3
Valid time, SPICLK to SPIPTE 5.5
24 tv(STE)M inactive(when used on pin muxed with 0.5tc(SPC)M – ns
USB - GPIO23 or GPIO41) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 0.5tc(LSPCLK) +
5.5
High-Speed Mode
4 td(PICO)M Delay time, SPICLK to SPIPICO valid Even, Odd 1 ns
Delay time, SPICLK to SPIPICO
4 td(PICO)M valid(when used on pin muxed with Even, Odd 2 ns
5 tv(PICO)M Valid time, SPIPICO valid after SPICLK ns
Valid time, SPIPICO valid after Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M SPICLK(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5
Normal Mode
4 td(PICO)M Delay time, SPICLK to SPIPICO valid Even, Odd 2 ns

6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0 (continued)

NO. PARAMETER (1) (2) (4) (BRR + 1)(3) MIN MAX UNIT
Valid time, SPIPICO valid after Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M SPICLK(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5
(1) 10-pF load on pin for High-Speed Mode.

(2) 20-pF load on pin for Normal Mode.
greater than 3.

6.17.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1

NO. PARAMETER(1) (2) (4) (BRR + 1) (3) MIN MAX UNIT
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
2 tw(SPCH)M Pulse duration, SPICLK, first pulse 0.5tc(SPC)M – ns
0.5tc(LSPCLK) + 1
3 tw(SPC2)M Pulse duration, SPICLK, second pulse 0.5tc(SPC)M + ns
0.5tc(LSPCLK) + 1
2tc(SPC)M –
23 td(SPC)M Delay time, SPIPTE valid to SPICLK Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 3 ns
3tc(SYSCLK) + 3
Delay time, SPIPTE valid to
2tc(SPC)M –
23 td(SPC)M SPICLK(when used on pin muxed with Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 4 ns
3tc(SYSCLK) + 3
Delay time, SPIPTE valid to 2tc(SPC)M –
23 td(SPC)M SPICLK(when used on pin muxed with Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 3 3tc(SYSCLK) + ns
USB - GPIO23 or GPIO41) 5.5
Even –3 3
24 td(STE)M Delay time, SPICLK to SPIPTE invalid ns
Odd –3 3
Delay time, SPICLK to SPIPTE Even -4 3
24 td(STE)M invalid(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) Odd -4 3
Delay time, SPICLK to SPIPTE Even –3 5.5

24 td(STE)M invalid(when used on pin muxed with ns
USB - GPIO23 or GPIO41) Odd –3 5.5
High-Speed Mode
4 td(PICO)M Delay time, SPIPICO valid to SPICLK ns
Delay time, SPIPICO valid to SPICLK Even 0.5tc(SPC)M – 3
4 td(PICO)M (when used on pin muxed with PMBUS ns
- GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3
Valid time, SPIPICO valid after SPICLK Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M (when used on pin muxed with PMBUS ns
- GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5
Normal Mode
4 td(PICO)M Delay time, SPIPICO valid to SPICLK ns
Valid time, SPIPICO valid after SPICLK Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M (when used on pin muxed with PMBUS ns
- GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5
(1) 10-pF load on pin for High-Speed Mode.

(2) 20-pF load on pin for Normal Mode.
greater than 3.

6.17.5.1.4 SPI Controller Mode Timing Diagrams

1
SPICLK
(clock polarity = 0)
2
3
SPICLK
4
5
Controller out data
SPIPICO is valid
8
9
Controller out
SPIPOCI data must be valid
23 24
SPIPTE
A. On the trailing end of the word, SPIPTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.
Figure 6-70. SPI Controller Mode External Timing (Clock Phase = 0)
1
SPICLK
2
3
SPICLK
4
5
Controller out data
SPIPICO is valid
8
9
Controller out
SPIPOCI data must be valid
24
23
SPIPTE
A. On the trailing end of the word, SPIPTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.
Figure 6-71. SPI Controller Mode External Timing (Clock Phase = 1)

6.17.5.2 SPI Peripheral Mode Timings

The following section contains the SPI Peripheral Mode Timings.
6.17.5.2.1 SPI Peripheral Mode Timing Requirements
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK, first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK, second pulse 2tc(SYSCLK) – 1 ns
19 tsu(PICO)S Setup time, SPIPICO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(PICO)S Hold time, SPIPICO valid after SPICLK 1.5tc(SYSCLK) ns
Setup time, SPIPTE valid before SPICLK
2tc(SYSCLK) + 15 ns
(Clock Phase = 0)
25 tsu(STE)S
Setup time, SPIPTE valid before SPICLK
2tc(SYSCLK) + 15 ns
(Clock Phase = 1)
26 th(STE)S Hold time, SPIPTE invalid after SPICLK 1.5tc(SYSCLK) ns
6.17.5.2.2 SPI Peripheral Mode Switching Characteristics

NO. PARAMETER(1) MIN MAX UNIT
Delay time, SPICLK to SPIPOCI valid
15 td(POCI)S 17 ns
(non-high speed mode)
12.5 ns
(high-speed mode)
(high-speed mode)(when used on pins 14 ns
15 td(POCI)S
muxed with PMBUS - GPIO2, 3, 9, or 32)
(high-speed mode)(when used on pins 16.7 ns
muxed with USB - GPIO23 or 41)
16 tv(POCI)S Valid time, SPIPOCI valid after SPICLK 0 ns

6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
12
SPICLK
13
14
SPICLK
15 16
SPIPOCI SPIPOCI data is valid
19
20
SPIPICO data
SPIPICO must be valid
25 26
SPIPTE
Figure 6-72. SPI Peripheral Mode External Timing (Clock Phase = 0)
12
SPICLK
13 14
SPICLK
15
SPIPOCI SPIPOCI data is valid Data valid Data valid
19 16
20
SPIPICO SPIPICO data

must be valid
25 26
SPIPTE
Figure 6-73. SPI Peripheral Mode External Timing (Clock Phase = 1)

6.17.6 Local Interconnect Network (LIN)

This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN 2.1
standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial interface
designed for applications where the CAN protocol may be too expensive to implement, such as small
subnetworks for cabin comfort functions like interior lighting or window control in an automotive application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-
commander and multiple-responder with a message identification for multicast transmission between any
network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an SCI.
The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a universal
asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the register/bit
usage in different modes. Because of this, code written for this module cannot be directly ported to the stand-
alone SCI module and vice versa.
The LIN module has the following features:
• Compatibility with LIN 1.3, 2.0 and 2.1 protocols
• Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)
• Two external pins: LINRX and LINTX
• Multibuffered receive and transmit units
• Identification masks for message filtering
• Automatic commander header generation
– Programmable synchronization break field
– Synchronization field
– Identifier field
• Responder automatic synchronization
– Synchronization break detection
– Optional baud rate update
– Synchronization validation
• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver
• Automatic wake-up support
– Wakeup signal generation
– Expiration times on wakeup signals
• Automatic bus idle detection
• Error detection
– Bit error
– Bus error
– No-response error
– Checksum error
– Synchronization field error
– Parity error
• Capability to use direct memory access (DMA) for transmit and receive data
• Two interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error, and status
• Support for LIN 2.0 checksum
• Enhanced synchronizer finite state machine (FSM) support for frame processing
• Enhanced handling of extended frames
• Enhanced baud rate generator

• Update wakeup/go to sleep
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
CHECKSUM
CALCULATOR INTERFACE
ID PARTY
CHECKER
BIT
MONITOR
TXRX ERROR
DETECTOR (TED)
TIME-OUT
CONTROL
COUNTER
LINRX/
SCIRX COMPARE
LINTX/ MASK 8 RECEIVE DMA

SCITX FSM
FILTER BUFFERS CONTROL
8 TRANSMIT
SYNCHRONIZER
BUFFERS
Figure 6-74. LIN Block Diagram

6.17.7 Fast Serial Interface (FSI)

The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust
high-speed communications. The FSI is designed to ensure data robustness across many system conditions
such as chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as
CRC, start- and end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified
after receipt without additional CPU interaction. Line breaks can be detected using periodic transmissions, all
managed and monitored by hardware. The FSI is also tightly integrated with other control peripherals on the
device. To ensure that the latest sensor data or control parameters are available, frames can be transmitted on
every control loop period. An integrated skew-compensation block has been added on the receiver to handle
skew that may occur between the clock and data signals due to a variety of factors, including trace-length
mismatch and skews induced by an isolation chip. With embedded data robustness checks, data-link integrity
checks, skew compensation, and integration with control peripherals, the FSI can enable high-speed, robust
communication in any system. These and many other features of the FSI follow.
The FSI module includes the following features:
• Independent transmitter and receiver cores
• Source-synchronous transmission
• Dual data rate (DDR)
• One or two data lines
• Programmable data length
• Skew adjustment block to compensate for board and system delay mismatches
• Frame error detection
• Programmable frame tagging for message filtering
• Hardware ping to detect line breaks during communication (ping watchdog)
• Two interrupts per FSI core
• Externally triggered frame generation
• Hardware- or software-calculated CRC
• Embedded ECC computation module
• Register write protection
• DMA support
• SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (60 MHz) at dual data rate (120Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis. The
Fast Serial Interface (FSI) Skew Compensation Application Note provides example software on how to configure
and set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in
the FSI Transmitter section and the FSI Receiver section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual, respectively.

6.17.7.1 FSI Transmitter

The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU (or the CLA) program,
control, and monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU, CLA,
and the DMA.
The transmitter has the following features:
• Automated ping frame generation
• Externally triggered ping frames
• Externally triggered data frames
• Software-configurable frame lengths
• 16-word data buffer
• Data buffer underrun and overrun detection
• Hardware-generated CRC on data bits
• Software ECC calculation on select data
• DMA support
• CLA task triggering
Figure 6-75 shows the FSITX CPU interface. Figure 6-76 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLK
PCLKCR18
SYSCLK
SYSRSN
C28x ePIE
FSITXyINT1
FSITXyINT2
CLA
Register Interface
Registers
FSITXyCLK
GPIO MUX
FSITXyD0
DMA FSITX
FSITXyD1
FSITXyDMA
Trigger Muxes(A)
32
A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
Figure 6-75. FSITX CPU Interface

FSITX
PLLRAWCLK
SYSRSN
SYSCLK
FSI Mode:
Transmit Clock TXCLKIN
TXCLK = TXCLKIN/2
Generator SPI Signaling Mode:
Register Interface TXCLK = TXCLKIN
Core Reset
FSITXINT1
Control Registers, TXCLK
FSITXINT2 Interrupt Management
FSITX_DMA_EVT Ping Time-out Counter
TXD0
Transmitter Core
External Frame Triggers TXD1
Transmit Data
Buffer
ECC Logic
Figure 6-76. FSITX Block Diagram
6.17.7.1.1 FSITX Electrical Data and Timing

6.17.7.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
1 tc(TXCLK) Cycle time, TXCLK 16.67 ns
Cycle time, TXCLK(when any FSI signal is
1 tc(TXCLK) used on pins muxed with PMBUS - GPIO2, 3, 26.67 ns
9, or 32)
2 tw(TXCLK) Pulse width, TXCLK low or TXCLK high (0.5tc(TXCLK)) – 1 (0.5tc(TXCLK)) + 1 ns
Delay time, TXCLK rising or falling toTXD
3 td(TXCLK–TXD) (0.25tc(TXCLK)) – 2 (0.25tc(TXCLK)) + 2 ns
valid
Delay time, TXCLK rising or falling toTXD
3 td(TXCLK–TXD) valid(when used on pin muxed with PMBUS - (0.25tc(TXCLK)) – 2 (0.25tc(TXCLK)) + 2.5 ns
GPIO2, 3, 9, or 32)
TXCLK delay compensation at
4 td(TXCLK) 9.4 30 ns
TX_DLYLINE_CTRL[TXCLK_DLY]=31
TXD0 delay compensation at
5 td(TXD0) 9.4 30 ns
TX_DLYLINE_CTRL[TXD0_DLY]=31
TXD1 delay compensation at
6 td(TXD1) 9.4 30 ns
TX_DLYLINE_CTRL[TXD1_DLY]=31
Incremental delay of each delay line element
7 td(DELAY_ELEMENT) 0.29 1 ns
for TXCLK, TXD0, and TXD1

6.17.7.1.1.2 FSITX Timings
FSITXCLK 2
FSITXD0
FSITXD1
3
Figure 6-77. FSITX Timings

6.17.7.2 FSI Receiver

The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they pass
through an optional programmable delay line. The receiver core handles the data framing, CRC computation,
and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is
asynchronous to the device system clock.
The receiver control registers let the CPU program (or the CLA), control, and monitor the operation of the FSIRX.
The receive data buffer is accessible by the CPU, CLA, and the DMA.
The receiver core has the following features:
• 16-word data buffer
• Multiple supported frame types
• Ping frame watchdog
• Frame watchdog
• CRC calculation and comparison in hardware
• ECC detection
• Programmable delay line control on incoming signals
• DMA support
• SPI compatibility mode
• CLA task triggering
Figure 6-78 shows the FSIRX CPU interface. Figure 6-79 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18
SYSCLK
SYSRSN
C28x ePIE
FSIRXyINT1
FSIRXyINT2
CLA
Register Interface
Registers
FSIRXyCLK
GPIO MUX
FSIRXyD0
DMA FSIRX
FSIRXyD1
FSIRXyDMA
Figure 6-78. FSIRX CPU Interface

FSIRX
SYSRSn
SYSCLK
Frame Watchdog
Register Interface
Core Reset
FSIRXINT1 Control Registers,
FSIRXINT2 Interrupt Management
RXCLK
FSIRX_DMA_EVT Ping Watchdog
Receiver Core Skew
RXD0
Control
RXD1
Receive Data
Buffer
ECC Check
Logic
Figure 6-79. FSIRX Block Diagram
6.17.7.2.1 FSIRX Electrical Data and Timing

6.17.7.2.1.1 FSIRX Timing Requirements
NO. MIN MAX UNIT
1 tc(RXCLK) Cycle time, RXCLK 16.67 ns
Cycle time, RXCLK(when any FSI signal is
1 tc(RXCLK) used on pins muxed with PMBUS - GPIO2, 3, 26.67 ns
9, or 32)
2 tw(RXCLK) Pulse width, RXCLK low or RXCLK high. 0.35tc(RXCLK) 0.65tc(RXCLK) ns
Setup time with respect to RXCLK, applies to
3 tsu(RXCLK–RXD) 1.7 ns
both edges of the clock
Setup time with respect to RXCLK, applies
3 tsu(RXCLK–RXD) to both edges of the clock(when used on pin 2.6 ns
muxed with PMBUS - GPIO2, 3, 9, or 32)
Hold time with respect to RXCLK, applies to
4 th(RXCLK–RXD) 2 ns
both edges of the clock
6.17.7.2.1.2 FSIRX Switching Characteristics

RXCLK delay compensation at
1 td(RXCLK) 9.7 30 ns
RX_DLYLINE_CTRL[RXCLK_DLY]=31
RXD0 delay compensation at
2 td(RXD0) 9.7 30 ns
RX_DLYLINE_CTRL[RXD0_DLY]=31
RXD1 delay compensation
3 td(RXD1) 9.7 30 ns
at RX_DLYLINE_CTRL[RXD1_DLY]=31
Incremental delay of each delay line element
4 td(DELAY_ELEMENT) 0.29 1 ns
for RXCLK, RXD0, and RXD1
Delay skew introduced between RXCLK-
TDM1 tskew(TDM_CLK-TDM_Dx ) -3 3 ns
TDM_CLK delay and RXDx-TDM_Dx delays
TDM1 td(RXCLK-TDM_CLK ) Delay time, RXCLK input to TDM_CLK output 2 14.5 ns

6.17.7.2.1.2 FSIRX Switching Characteristics (continued)

TDM2 td(RXD0-TXD0) Delay time, RXD0 input to TXD0 output 2 14.5 ns
TDM3 td(RXD1-TXD1) Delay time, RXD1 input to TXD1 output 2 14.5 ns
6.17.7.2.1.3 FSIRX Timings
FSIRXCLK 2
FSIRXD0
FSIRXD1
3
Figure 6-80. FSIRX Timings

6.17.7.3 FSI SPI Compatibility Mode

The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In this
mode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the
FSI is able to physically interface with a SPI in this mode, the external device must be able to encode and
decode an FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases with
the exception of the preamble and postamble. The FSI provides the same data validation and frame checking
as if it was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the ping
frame watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of SPI compatibility
mode follows:
• Data will transmit on rising edge and receive on falling edge of the clock.
• Only 16-bit word size is supported.
• TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
• No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
• No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phase
is finished.
• It is not possible to transmit in the SPI peripheral configuration because the FSI TXCLK cannot take an
external clock source.
6.17.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Special timings are not required for the FSIRX in SPI signaling mode. FSIRX timings listed in the FSIRX Timing
Requirements table are applicable in SPI compatibility mode. Setup and Hold times are only valid on the falling
edge of FSIRXCLK because this is the active edge in SPI signaling mode.
6.17.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
1 tc(TXCLK) Cycle time, TXCLK 16.67 ns
Cycle time, TXCLK(when any FSI signal is
1 tc(TXCLK) used on pins muxed with PMBUS - GPIO2, 3, 26.67 ns
9, or 32)
2 tw(TXCLK) Pulse width, TXCLK low or TXCLK high (0.5tc(TXCLK)) – 1 (0.5tc(TXCLK)) + 1 ns
3 td(TXCLKH–TXD0) Delay time, TXD0 valid after TXCLK high 3 ns
4 td(TXD1-TXCLK) Delay time, TXCLK high after TXD1 low tw(TXCLK) – 3 ns
5 td(TXCLK-TXD1) Delay time, TXD1 high after TXCLK low tw(TXCLK) ns
(1) 10-pF load on pin
6.17.7.3.1.2 FSITX SPI Signaling Mode Timings

1
2
FSITXCLK
3
FSITXD0
5
4
FSITXD1
Figure 6-81. FSITX SPI Signaling Mode Timings

6.17.8 Universal Serial Bus (USB)

The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
• USB 2.0 full-speed and low-speed operation
• Integrated PHY
• Three transfer types: control, interrupt, and bulk
• 32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB of dedicated endpoint memory
Figure 6-82 shows the USB block diagram.
Endpoint Control
Transmit
EP0 –31
Control
Receive
CPU Interface
Interrupt Interrupts
Host
Combine Control
Transaction
Endpoints
Scheduler
EP Reg.
Decoder
Common CPU Bus

UTM Packet FIFO RAM
Synchronization Encode/Decode Controller Regs
Rx Rx
Data Sync Packet Encode
Buff Buff Cycle
Control
HNP/SRP Packet Decode Tx Tx
Buff Buff
USB FS/LS
PHY FIFO
Timers CRC Gen/Check Cycle Control
Decoder
USB DataLines
D+ andD-
Figure 6-82. USB Block Diagram
Note
The accuracy of the on-chip zero-pin oscillator (see the INTOSC Characteristics section) will not
meet the accuracy requirements of the USB protocol. An external clock source must be used for
applications using USB. For applications using the USB boot mode, see the Boot ROM and Peripheral
Booting section for clock frequency requirements.
6.17.8.1 USB Electrical Data and Timing

6.17.8.1.1 USB Input Ports DP and DM Timing Requirements
MIN MAX UNIT
V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic-low level 0.8 V
VIH Static SE input logic-high level 2.0 V
VDI Differential input voltage 0.2 V

6.17.8.1.2 USB Output Ports DP and DM Switching Characteristics

VOH D+, D– single-ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D– single-ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D– impedance 28 44 Ω
Full speed, differential, CL = 50 pF, 10%/90%,
tr Rise time 4 20 ns
Rpu on D+
Full speed, differential, CL = 50 pF, 10%/90%,
tf Fall time 4 20 ns
Rpu on D+

7 Detailed Description
7.1 Overview
The TMS320F28P55x (F28P55x) is a member of the C2000™ real-time microcontroller family of scalable,
ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power
density, high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
• Industrial motor drives
• Motor control
– Traction inverter motor control
– HVAC motor control
– Mobile robot motor control
• Solar inverters
– Central inverter
– Micro inverter
– String inverter
• Digital power
• Electrical vehicles and transportation
• EV charging infrastructure
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 150 MIPS of signal-
processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM.
The C28x CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy
Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended
instruction sets enable IEEE double-precision 32-bit floating-point math. Finally, the Control Law Accelerator
(CLA) enables an additional 150 MIPS per core of independent processing ability. Machine learning is supported
with the addition of the Neural-network Processing Unit (NPU), capable of 600 MOPS on 8-bit weight/8-bit data
across multiple NN layers.
To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update
(LFU) have been added to F28P55x.
High-performance analog blocks are tightly integrated with the processing and control units to provide optimal
real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to
39 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of
oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware
redundancy checker has been added. The hardware redundancy checker provides the ability to compare
ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Three
Programmable Gain Amplifiers (PGAs) are present, supporting unity gain as well as up to 64x of non-inverting
gain. Twenty-four frequency-independent PWMs, 16 with high-resolution capability, enable control of multiple
power stages, from 3-phase inverters to advanced multilevel power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Industry-standard protocols like CAN FD and USB 2.0 are available on this device. The Fast Serial Interface
(FSI) enables up to 200 Mbps of robust communications across an isolation boundary. Enhancements have
been made to the PMBUS module to support Fast Plus mode.
Want to learn more about features that make C2000 MCUs the right choice for your real-time control system?
Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™
real-time control MCUs page.

7.2 Functional Block Diagram

Figure 7-1 shows the CPU system and associated peripherals.
C28x CPU
(150 MHz)
FPU32 CLA
Boot ROM
TMU (150 MHz)
VCRC
Secure ROM
Flash Bank0
128 Sectors, 256KB CLA to CPU MSG RAM
SYSTEM CONTROL
CPU Timers
XTAL Flash Bank1 CPU to CLA MSG RAM
INTOSC1, INTOSC2 128 Sectors, 256KB
PLL
ePIE
Windowed WD Flash Bank2 CLA Data ROM
NMI WD 128 Sectors, 256KB
CLA Program ROM
Flash Bank3
128 Sectors, 256KB
SECURITY
JTAG Lock Flash Bank4 CLA to DMA MSG RAM
Secure Boot 32 Sectors, 64 KB
DMA to CLA MSG RAM
M0-M1 RAM
4KB
DIAGNOSTICS Buses Legend
DCC
MPOST LS0-LS9 RAM CPU
ERAD 64KB
NPU CLA
JTAG/cJTAG
DMA
GS0-GS3 RAM NPU

64KB DMA
OTHERS
EPG 6 Channels Secure Memories Shown in Red
PF1 PF3 PF4 PF2 PF7 PF8 PF9 PF10 PF11 PF12
Result Data 1x PMBUS 2x CAN FD 1x LIN 3x SCI 2x CLB 1x USB 1x AES LFU
24x ePWM Channels
4x CMPSS NPU 2x I2C
(12Ch Hi-Res Capable) 5x 12-Bit ADC 65x GPIO 2x SPI
1x FSI RX
Input XBAR
2x eCAP 1x Buffered DAC 1x FSI TX
Output XBAR
ePWM XBAR
3x eQEP CLB XBAR
3x PGA
(CW/CCW Support)
CLB Input XBAR
CLB Output XBAR
A. The internal DAC from one of the CMPSS modules can be configured as an output DAC.
B. The LIN module can also be used as a SCI module.
Figure 7-1. Functional Block Diagram

7.3 Memory
7.3.1 Memory Map
The Memory Map table describes the memory map. See the Memory Controller Module section of the System
Control chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
Table 7-1. Memory Map
CPU1.CLA1 CPU1.CLA1
START END CPU1.DMA ECC/
MEMORY SIZE (x16) DATA PROGRAM SECURITY PART NUMBER
ADDRESS ADDRESS ACCESS Parity
ACCESS ACCESS
M0 RAM 1024 0x0000_0000 0x0000_03FF - - - ECC - -
M1 RAM 1024 0x0000_0400 0x0000_07FF - - - ECC - -
PIE Vector Table 512 0x0000_0D00 0x0000_0EFF - - - Parity - -
CLAtoCPU MSG
128 0x0000_1480 0x0000_14FF - YES - Parity - -
RAM
CPUtoCLA MSG
128 0x0000_1500 0x0000_157F - YES - Parity - -
RAM
CLAtoDMA MSG
128 0x0000_1680 0x0000_16FF YES YES - Parity - -
RAM
DMAtoCLA MSG
128 0x0000_1700 0x0000_177F YES YES - Parity - -
RAM
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
LS8 RAM - CLA F28P550SG9,
8192 0x0000_4000 0x0000_5FFF - - YES Parity YES
Prog F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
LS9 RAM - CLA F28P550SG9,
8192 0x0000_6000 0x0000_7FFF - - YES Parity YES
Prog F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6
LS0 RAM 2048 0x0000_8000 0x0000_87FF - YES YES Parity YES -
LS1 RAM 2048 0x0000_8800 0x0000_8FFF - YES YES Parity YES -
LS2 RAM 2048 0x0000_9000 0x0000_97FF - YES YES Parity YES -
LS3 RAM 2048 0x0000_9800 0x0000_9FFF - YES YES Parity YES -
LS4 RAM 2048 0x0000_A000 0x0000_A7FF - YES YES Parity YES -
LS5 RAM 2048 0x0000_A800 0x0000_AFFF - YES YES Parity YES -
LS6 RAM 2048 0x0000_B000 0x0000_B7FF - YES YES Parity YES -
LS7 RAM 2048 0x0000_B800 0x0000_BFFF - YES YES Parity YES -
GS0 RAM 8192 0x0000_C000 0x0000_DFFF YES - - Parity - -
GS1 RAM 8192 0x0000_E000 0x0000_FFFF YES - - Parity - -
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
CLA Data ROM 4096 0x0000_F000 0x0000_FFFF - YES - Parity -
F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
GS2 RAM 8192 0x0001_0000 0x0001_1FFF YES - - Parity - F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6

Table 7-1. Memory Map (continued)

CPU1.CLA1 CPU1.CLA1
ACCESS ACCESS
F28P559SJ9-Q1,
F28P550SJ9,
GS3 RAM 8192 0x0001_2000 0x0001_3FFF YES - - Parity - F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P559SG8-Q1,
LS8 RAM - CPU 8192 0x0001_4000 0x0001_5FFF - - - Parity YES
F28P559SG2-Q1,
F28P559SJ2-Q1,
F28P550SG8,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P559SG8-Q1,
LS9 RAM - CPU 8192 0x0001_6000 0x0001_7FFF - - - Parity YES
F28P559SG2-Q1,
F28P559SJ2-Q1,
F28P550SG8,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
USB RAM 2048 0x0004_1000 0x0004_17FF YES - - - -
F28P550SG9,
F28P559SJ6-Q1,
F28P550SJ6
MCANA Message
RAM (CPU Access 2048 0x0005_8000 0x0005_87FF YES - - ECC - -
mode)
MCANA Message
RAM (Peripheral 4096 0x0005_8000 0x0005_8FFF YES - - ECC - -
mode)
MCANB Message
RAM (Peripheral 4096 0x0005_A000 0x0005_AFFF YES - - ECC - -
mode)
MCANB Message
RAM (CPU Access 2048 0x0005_A000 0x0005_A7FF YES - - ECC - -
mode)
TI OTP Bank 0 1536 0x0007_2000 0x0007_25FF - - - ECC - -
UID_REGS 16 0x0007_2168 0x0007_2177 - - - ECC - -
F28P559SJ9-Q1,
F28P550SJ9,
TI OTP Bank 1 1536 0x0007_3000 0x0007_35FF - - - ECC - F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
TI OTP Bank 2 1536 0x0007_4000 0x0007_45FF - - - ECC - -
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ6-Q1,
F28P550SJ6
DCSM BANK0 Z1
512 0x0007_8000 0x0007_81FF - - - ECC YES -
OTP
DCSM BANK0 Z2
512 0x0007_8200 0x0007_83FF - - - ECC YES -
OTP


CPU1.CLA1 CPU1.CLA1
ACCESS ACCESS
F28P559SJ9-Q1,
F28P550SJ9,
User OTP Bank 1 1024 0x0007_8800 0x0007_8BFF - - - ECC - F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
User OTP Bank 2 1024 0x0007_9000 0x0007_93FF - - - ECC - -
F28P559SJ9-Q1,
F28P550SJ9,
User OTP Bank 3 1024 0x0007_9800 0x0007_9BFF - - - ECC - F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
User OTP Bank 4 1024 0x0007_A000 0x0007_A3FF - - - ECC - F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
Flash Bank 0 131072 0x0008_0000 0x0009_FFFF - - - ECC YES -
F28P559SJ9-Q1,
F28P550SJ9,
Flash Bank 1 131072 0x000A_0000 0x000B_FFFF - - - ECC YES F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
Flash Bank 2 131072 0x000C_0000 0x000D_FFFF - - - ECC YES -
F28P559SJ9-Q1,
F28P550SJ9,
Flash Bank 3 131072 0x000E_0000 0x000F_FFFF - - - ECC YES F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
Flash Bank 4 32768 0x0010_0000 0x0010_7FFF - - - ECC YES F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
Z1-SecureBoot
3072 0x003F_4000 0x003F_4BFF - - - Parity YES -
Functions
Z1-Safe Functions 1536 0x003F_4C00 0x003F_51FF - - - Parity YES -
Z2-Safe Functions 1536 0x003F_5600 0x003F_5BFF - - - Parity YES -
CPU STL 9216 0x003F_5C00 0x003F_7FFF - - - Parity - -
Boot ROM 32768 0x003F_8000 0x003F_FFFF - - - Parity - -
PIE Vector Table
512 0x0100_0900 0x0100_0AFF - - - Parity - -
Swap
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
CLA Data ROM F28P550SG9,
4096 0x0100_1000 0x0100_1FFF - - - Parity -
(CPU Mapped) F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6
TI OTP Bank 0
192 0x0107_0400 0x0107_04BF - - - - - -
ECC
F28P559SJ9-Q1,
F28P550SJ9,
TI OTP Bank 1
192 0x0107_0600 0x0107_06BF - - - - - F28P559SJ2-Q1,
ECC
F28P559SJ6-Q1,
F28P550SJ6
TI OTP Bank 2
192 0x0107_0800 0x0107_08BF - - - - - -
ECC
F28P559SJ9-Q1,
F28P550SJ9,
TI OTP Bank 3
192 0x0107_0A00 0x0107_0ABF - - - - - F28P559SJ2-Q1,
ECC
F28P559SJ6-Q1,
F28P550SJ6


CPU1.CLA1 CPU1.CLA1
ACCESS ACCESS
F28P559SJ9-Q1,
F28P550SJ9,
TI OTP Bank 4
192 0x0107_0C00 0x0107_0CBF - - - - - F28P559SJ2-Q1,
ECC
F28P559SJ6-Q1,
F28P550SJ6
7.3.1.1 Dedicated RAM (Mx RAM)

The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are small
nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
7.3.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are accessible to the CPU and CLA. All LSx RAM blocks have parity. These
memories are secure and have CPU access protection (CPU write/CPU fetch).
7.3.1.3 Global Shared RAM (GSx RAM)
Global shared RAMs (GSx RAMs) are accessible from the CPU and DMA. The CPU and DMA have full read
and write access to these memories. All GSx RAM blocks have parity. The GSx RAMs have access protection
(CPU write/CPU fetch/DMA write/HIC write).
7.3.1.4 Message RAM
There are two types of message RAMs on this device that can be used to share between CPU, CLA and DMA.
CLA-CPU message RAM shares data between the CLA and CPU while the CLA-DMA message RAM shares
data between the CLA and DMA.
7.3.2 Control Law Accelerator (CLA) Memory Map
Table 7-2 shows the CLA data ROM memory map.
Table 7-2. CLA Data ROM Memory Map
MEMORY START ADDRESS LENGTH
FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

7.3.3 Flash Memory Map

On the F28P55x devices, five flash banks (1084KB) are available. 4 banks are 256KB and the 5th bank is 64KB
in size. Flash operations (erase and program) are performed at the bank level. Code cannot be executed from
the same bank as an operation is being performed. Code can be allocated in a different flash bank, SRAM, or
ROM while these operations are in progress. The Addresses of Flash Sectors table lists the addresses of flash
sectors available for each part number.
7.3.3.1 Addresses of Flash Sectors
Table 7-3. Flash Memory Map
PART ADDRESS ECC ADDRESS
SECTOR
NUMBER SIZE START END SIZE START END
OTP Sectors
TI OTP Bank 0
1520 x 16 0x0007 2000 0x0007 25EF 190 x 16 0x0107 0400 0x0107 04BD
(Unsecure)
All F28P55x TI OTP Bank 0
16 x 16 0x0007 25F0 0x0007 25FF 2 x 16 0x0107 04BE 0x0107 04BE
(Secure)
TI OTP Bank 2 1536 x 16 0x0007 4000 0x0007 45FF 192 x 16 0x0107 0800 0x0107 08BF
TI OTP Bank 1 1536 x 16 0x0007 3000 0x0007 35FF 192 x 16 0x0107 0600 0x0107 06BF
F28P55xSJx
TI OTP Bank 3 1536 x 16 0x0007 5000 0x0007 55FF 192 x 16 0x0107 0A00 0x0107 0ABF
F28P55xSJx,
TI OTP Bank 4 1536 x 16 0x0007 6000 0x0007 65FF 192 x 16 0x0107 0C00 0x0107 0CBF
F28P55xSGx
User
configurable
512 x 16 0x0007 8000 0x0007 81FF 64 x 16 0x0107 1000 0x0107 103F
DCSM Z1 OTP
Bank 0
User
All F28P55x configurable
512 x 16 0x0007 8200 0x0007 83FF 64 x 16 0x0107 1040 0x0107 107F
DCSM Z2 OTP
Bank 0
User
configurable 1K x 16 0x0007 9000 0x0007 93FF 128 x 16 0x0107 1100 0x0107 117F
OTP Bank 2
User
configurable 1K x 16 0x0007 8800 0x0007 8BFF 128 x 16 0x0107 1080 0x0107 10FF
OTP Bank 1
F28P55xSJx
User
configurable 1K x 16 0x0007 9800 0x0007 9BFF 128 x 16 0x0107 1180 0x0107 11FF
OTP Bank 3
User
F28P55xSJx,
configurable 1K x 16 0x0007 A000 0x0007 A3FF 128 x 16 0x0107 1200 0x0107 127F
F28P55xSGx
OTP Bank 4
Bank 0 Sectors
Sector 0 1K x 16 0x0008 0000 0x0008 03FF 128 x 16 0x0108 0000 0x0108 007F
Sector 1 1K x 16 0x0008 0400 0x0008 07FF 128 x 16 0x0108 0080 0x0108 00FF
Sector 2 1K x 16 0x000800800 0x0008 0BFF 128 x 16 0x0108 0100 0x0108 017F
All ... ... ... ... ... ... ...
Sector 125 1K x 16 0x0009 F400 0x0009 F7FF 128 x 16 0x0108 3E80 0x0108 3EFF
Sector 126 1K x 16 0x0009 F800 0x0009 FBFF 128 x 16 0x0108 3F00 0x0108 3F7F
Sector 127 1K x 16 0x0009 FC00 0x0009 FFFF 128 x 16 0x0108 3F80 0x0108 3FFF

Table 7-3. Flash Memory Map (continued)

PART ADDRESS ECC ADDRESS
SECTOR
NUMBER SIZE START END SIZE START END
Bank 1 Sectors
Sector 0 1K x 16 0x000A 0000 0x000A 03FF 128 x 16 0x0108 4000 0x0108 407F
Sector 1 1K x 16 0x000A 0400 0x000A 07FF 128 x 16 0x0108 4080 0x0108 40FF
Sector 2 1K x 16 0x000A 0800 0x000A 0BFF 128 x 16 0x0108 4100 0x0108 417F
F28P55xSJx ... ... ... ... ... ... ...
Sector 125 1K x 16 0x000B F400 0x000B F7FF 128 x 16 0x0108 7E80 0x0108 7EFF
Sector 126 1K x 16 0x000B F800 0x000B FBFF 128 x 16 0x0108 7F00 0x0108 7F7F
Sector 127 1K x 16 0x000B FC00 0x000B FFFF 128 x 16 0x0108 7F80 0x0108 7FFF
Bank 2 Sectors
Sector 0 1K x 16 0x000C 0000 0x000C 03FF 128 x 16 0x0108 8000 0x0108 807F
Sector 1 1K x 16 0x000C 0400 0x000C 07FF 128 x 16 0x0108 8080 0x0108 80FF
Sector 2 1K x 16 0x000C 0800 0x000C 0BFF 128 x 16 0x0108 8100 0x0108 817F
All ... ... ... ... ... ... ...
Sector 125 1K x 16 0x000D F400 0x000D F7FF 128 x 16 0x0108 BE80 0x0108 BEFF
Sector 126 1K x 16 0x000D F800 0x000D FBFF 128 x 16 0x0108 BF00 0x0108 BF7F
Sector 127 1K x 16 0x000D FC00 0x000D FFFF 128 x 16 0x0108 BF80 0x0108 BFFF
Bank 3 Sectors
Sector 0 1K x 16 0x000E 0000 0x000E 03FF 128 x 16 0x0108 C000 0x0108 C07F
Sector 1 1K x 16 0x000E 0400 0x000E 07FF 128 x 16 0x0108 C080 0x0108 C0FF
Sector 2 1K x 16 0x000E 0800 0x000E 0BFF 128 x 16 0x0108 C100 0x0108 C17F
F28P55xSJx ... ... ... ... ... ... ...
Sector 125 1K x 16 0x000F F400 0x000F F7FF 128 x 16 0x0108 FE80 0x0108 FEFF
Sector 126 1K x 16 0x000F F800 0x000F FBFF 128 x 16 0x0108 FF00 0x0108 FF7F
Sector 127 1K x 16 0x000F FC00 0x000F FFFF 128 x 16 0x0108F F80 0x0108 FFFF
Bank 4 Sectors
Sector 0 1K x 16 0x0010 0000 0x0010 03FF 128 x 16 0x0109 0000 0x0109 007F
Sector 1 1K x 16 0x0010 0400 0x0010 07FF 128 x 16 0x0109 0080 0x0190 00FF
Sector 2 1K x 16 0x0010 0800 0x0010 0BFF 128 x 16 0x0109 0100 0x0109 0180
F28P55xSJ9,F2
8P55xSJ6, ... ... ... ... ... ... ...
F28P55xSG9
Sector 29 1K x 16 0x0010 7400 0x0010 77FF 128 x 16 0x0109 0E80 0x0109 0EFF
Sector 30 1K x 16 0x0010 7800 0x0010 7BFF 128 x 16 0x0109 0F00 0x0109 0F7F
Sector 31 1K x 16 0x0010 7C00 0x0010 7FFF 128 x 16 0x0109 0F80 0x0109 0FFF

7.3.4 Peripheral Registers Memory Map

Table 7-4. Peripheral Registers Memory Map
Structure DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1 Pipeline Protected
Peripheral Frame 0 (PF0)
CPUTIMER_REGS CPUTIMER0_BASE 0x0000_0C00 YES - - -
CLA_ONLY_REGS CLA1_ONLY_BASE 0x0000_0C00 - - YES -
PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES - - -
CLA_SOFTINT_REGS CLA1_SOFTINT_BASE 0x0000_0CE0 - - YES -
PIE_VECT_TABLE PIEVECTTABLE_BASE 0x0000_0D00 YES - - -
DMA_REGS DMA_BASE 0x0000_1000 YES - - -
DMA_CH_REGS DMA_CH1_BASE 0x0000_1020 YES - - -
DMA_CH_REGS DMA_CH5_BASE 0x0000_10A0 YES - - -
DMA_CH_REGS DMA_CH6_BASE 0x0000_10C0 YES - - -
CLA_REGS CLA1_BASE 0x0000_1400 YES - - -
ADC_RESULT_REGS ADCARESULT_BASE 0x0000_1800 YES YES YES -
ADC_RESULT_REGS ADCBRESULT_BASE 0x0000_1880 YES YES YES -
ADC_RESULT_REGS ADCCRESULT_BASE 0x0000_1900 YES YES YES -
ADC_RESULT_REGS ADCDRESULT_BASE 0x0000_1980 YES YES YES -
ADC_RESULT_REGS ADCERESULT_BASE 0x0000_1A00 YES YES YES -
PCTRACE_BUFFER_REGS ERAD_PCTRACE_BUFFER_BASE 0x0005_FE00 YES - - YES
UID_REGS UID_BASE 0x0007_2168 YES - - -
DCSM_Z1_OTP DCSM_Z1OTP_BASE 0x0007_8000 YES - - -
DCSM_Z2_OTP DCSM_Z2OTP_BASE 0x0007_8200 YES - - -
EPWM_REGS EPWM1_BASE 0x0000_4000 YES YES YES YES

Table 7-4. Peripheral Registers Memory Map (continued)

EPWM_REGS EPWM11_BASE 0x0000_4A00 YES YES YES YES
EPWM_REGS EPWM12_BASE 0x0000_4B00 YES YES YES YES
EQEP_REGS EQEP1_BASE 0x0000_5100 YES YES YES YES
ECAP_REGS ECAP1_BASE 0x0000_5200 YES YES YES YES
ECAP_REGS ECAP2_BASE 0x0000_5240 YES YES YES YES
CMPSS_REGS CMPSS1_BASE 0x0000_5500 YES YES YES YES
CMPSS_REGS CMPSS4_BASE 0x0000_55C0 YES YES YES YES
PGA_REGS PGA1_BASE 0x0000_5B00 YES YES YES YES
DAC_REGS DACA_BASE 0x0000_5C00 YES YES YES YES
SPI_REGS SPIA_BASE 0x0000_6100 YES YES YES YES
SPI_REGS SPIB_BASE 0x0000_6110 YES YES YES YES
PMBUS_REGS PMBUSA_BASE 0x0000_6400 YES YES YES YES
FSI_TX_REGS FSITXA_BASE 0x0000_6600 YES YES YES YES
FSI_RX_REGS FSIRXA_BASE 0x0000_6680 YES YES YES YES
ADC_REGS ADCC_BASE 0x0000_6A00 YES - YES YES
ADC_REGS ADCD_BASE 0x0000_6C00 YES - YES YES
ADC_REGS ADCE_BASE 0x0000_6E00 YES - YES YES
ADC_REGS ADCA_BASE 0x0000_7400 YES - YES YES
ADC_REGS ADCB_BASE 0x0000_7600 YES - YES YES
INPUT_XBAR_REGS INPUTXBAR_BASE 0x0000_7900 YES - - YES
XBAR_REGS XBAR_BASE 0x0000_7920 YES - - YES
SYNC_SOC_REGS SYNCSOC_BASE 0x0000_7940 YES - - YES
INPUT_XBAR_REGS CLBINPUTXBAR_BASE 0x0000_7960 YES - - YES
DMA_CLA_SRC_SEL_REGS DMACLASRCSEL_BASE 0x0000_7980 YES - - YES


EPWM_XBAR_REGS EPWMXBAR_BASE 0x0000_7A00 YES - - YES
CLB_XBAR_REGS CLBXBAR_BASE 0x0000_7A40 YES - - YES
OUTPUT_XBAR_REGS OUTPUTXBAR_BASE 0x0000_7A80 YES - - YES
OUTPUT_XBAR_REGS CLBOUTPUTXBAR_BASE 0x0000_7BC0 YES - - YES
GPIO_CTRL_REGS GPIOCTRL_BASE 0x0000_7C00 YES - - YES
GPIO_DATA_REGS GPIODATA_BASE 0x0000_7F00 YES - YES YES
GPIO_DATA_READ_REGS GPIODATAREAD_BASE 0x0000_7F80 YES - YES YES
DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - YES
CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES - - YES
CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES - - YES
SYS_STATUS_REGS SYSSTAT_BASE 0x0005_D400 YES - - YES
PERIPH_AC_REGS PERIPHAC_BASE 0x0005_D500 YES - - YES
ANALOG_SUBSYS_REGS ANALOGSUBSYS_BASE 0x0005_D700 YES - - YES
ERAD_GLOBAL_REGS ERAD_GLOBAL_BASE 0x0005_E800 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP1_BASE 0x0005_E900 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER1_BASE 0x0005_E980 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER2_BASE 0x0005_E990 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER3_BASE 0x0005_E9A0 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER4_BASE 0x0005_E9B0 YES - - YES
ERAD_CRC_GLOBAL_REGS ERAD_CRC_GLOBAL_BASE 0x0005_EA00 YES - - YES
ERAD_CRC_REGS ERAD_CRC1_BASE 0x0005_EA10 YES - - YES


PCTRACE_REGS ERAD_PCTRACE_BASE 0x0005_EAD0 YES - - YES
EPG_REGS EPG1_BASE 0x0005_EC00 YES - - YES
EPG_MUX_REGS EPG1MUX_BASE 0x0005_ECD0 YES - - YES
DCSM_Z1_REGS DCSM_Z1_BASE 0x0005_F000 YES - - YES
DCSM_Z2_REGS DCSM_Z2_BASE 0x0005_F080 YES - - YES
DCSM_COMMON_REGS DCSMCOMMON_BASE 0x0005_F0C0 YES - - YES
MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES - - YES
ACCESS_PROTECTION_REGS ACCESSPROTECTION_BASE 0x0005_F500 YES - - YES
MEMORY_ERROR_REGS MEMORYERROR_BASE 0x0005_F540 YES - - YES
TEST_ERROR_REGS TESTERROR_BASE 0x0005_F590 YES - - YES
FLASH_CTRL_REGS FLASH0CTRL_BASE 0x0005_F800 YES - - YES
FLASH_ECC_REGS FLASH0ECC_BASE 0x0005_FB00 YES - - YES
EXT_EVT_REGS EXTEVT_BASE 0x0005_4000 YES - - YES
EXT_GPRCM_REGS EXTGPRCM_BASE 0x0005_400A YES - - YES
IPSTANDARD_REGS IPSTANDARD_BASE 0x0005_4020 YES - - YES
IPSPECIFIC_REGS IPSPECIFIC_BASE 0x0005_4100 YES - - YES
DATA_REGS DATA_BASE 0x0005_4700 YES - - YES
ACC_REGS ACC_BASE 0x0005_4C00 YES - - YES
INSTRUCTION_REGS INSTRUCTION_BASE 0x0005_5000 YES - - YES
RFDATA_REGS RFDATA_BASE 0x0005_5800 YES - - YES
MCANSS_REGS MCANASS_BASE 0x0005_9400 YES - - YES
MCAN_REGS MCANA_BASE 0x0005_9600 YES - - YES
MCAN_ERROR_REGS MCANA_ERROR_BASE 0x0005_9800 YES - - YES
MCANSS_REGS MCANBSS_BASE 0x0005_B400 YES - - YES
MCAN_REGS MCANB_BASE 0x0005_B600 YES - - YES
MCAN_ERROR_REGS MCANB_ERROR_BASE 0x0005_B800 YES - - YES
DCC_REGS DCC0_BASE 0x0005_E700 YES - - YES
DCC_REGS DCC1_BASE 0x0005_E740 YES - - YES
LIN_REGS LINA_BASE 0x0000_6800 YES YES YES YES
WD_REGS WD_BASE 0x0000_7000 YES - - YES
NMI_INTRUPT_REGS NMI_BASE 0x0000_7060 YES - - YES


XINT_REGS XINT_BASE 0x0000_7070 YES - - YES
SCI_REGS SCIA_BASE 0x0000_7200 YES - - YES
SCI_REGS SCIB_BASE 0x0000_7210 YES - - YES
SCI_REGS SCIC_BASE 0x0000_7220 YES - - YES
I2C_REGS I2CA_BASE 0x0000_7300 YES - - YES
I2C_REGS I2CB_BASE 0x0000_7340 YES - - YES
CLB_LOGIC_CONFIG_REGS CLB1_LOGICCFG_BASE 0x0000_3000 YES - YES YES
CLB_LOGIC_CONTROL_REGS CLB1_LOGICCTRL_BASE 0x0000_3100 YES - YES YES
CLB_DATA_EXCHANGE_REGS CLB1_DATAEXCH_BASE 0x0000_3180 YES - YES YES
CLB_LOGIC_CONFIG_REGS CLB2_LOGICCFG_BASE 0x0000_3400 YES - YES YES
CLB_LOGIC_CONTROL_REGS CLB2_LOGICCTRL_BASE 0x0000_3500 YES - YES YES
CLB_DATA_EXCHANGE_REGS CLB2_DATAEXCH_BASE 0x0000_3580 YES - YES YES
USB_REGS USBA_BASE 0x0004_0000 YES YES - YES
AES_REGS AESA_BASE 0x0004_2000 YES YES - YES
AES_SS_REGS AESA_SS_BASE 0x0004_2C00 YES YES - YES
LFU_REGS LFU_BASE 0x0000_7FE0 YES - YES YES

7.4 Identification
Table 7-5 lists the Device Identification Registers. Additional information on these device identification registers
can be found in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual. See the register
descriptions of PARTIDH and PARTIDL for identification of production status (TMX or TMS) and other device
information.
Table 7-5. Device Identification Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
Bits Options
14-13 1 = InstaSPIN-FOC
INSTASPIN 2 = NONE
3 = NONE
10-8 0 = 56 pin (QFN)
PIN_COUNT 1 = 64 pin (QFP)
PARTIDL 0x0005 D008 2
2 = 80 pin (QFP)
3 = 100 pin (QFP)
4 = 128 pin (QFP)
7-6 0 = Engineering Sample (TMX)
QUAL 1 = Pilot Production (TMP)
2 = Fully Qualified (TMS)
Device part identification number
TMS320F28P55xSJ9 0x09FF 0500
TMS320F28P55xSJ6 0x09FC 0500
PARTIDH 0x0005 D00A 2 TMS320F28P55xSJ2 0x09F8 0500
TMS320F28P55xSG9 0x09F5 0500
TMS320F28P55xSG8 0x09F4 0500
TMS320F28P55xSG2 0x09EE 0500
Silicon revision number
REVID 0x0005 D00C 2 Revision 0 0x0000 0001
Revision A 0x0000 0002
Unique identification number. This number is different on each
individual device with the same PARTIDH. This unique number
UID_UNIQUE 0x0007 2172 4
can be used as a serial number in the application. This number
is present only on TMS devices.

7.5 Bus Architecture – Peripheral Connectivity

The Peripheral Connectivity table lists a broad view of the peripheral and configuration register accessibility from
each bus controller.
Table 7-6. Peripheral Connectivity
PERIPHERAL DMA CLA C28
SYSTEM PERIPHERALS
CPU Timers Y
ERAD Y
GPIO Data Y Y
GPIO Pin Mapping and Configuration Y
XBAR Configuration Y
System Configuration Y
AES Y Y
EPG Y
LFU Y Y
DCC Y
MEMORY
M0/M1 Y
LSx Y Y
GSx Y Y
ROM Y
FLASH Y
CONTROL PERIPHERALS
ePWM/HRPWM Y Y Y
eCAP Y Y Y
(1)
eQEP Y Y Y
CLB Y Y
ANALOG PERIPHERALS
(1)
CMPSS Y Y Y
(1)
DAC Y Y Y
ADC Configuration Y Y
(1)
ADC Results Y Y Y
(1)
PGA Y Y Y
COMMUNICATION PERIPHERALS
(1)
MCAN(CAN-FD) Y Y
FSITX/FSIRX Y Y Y
I2C Y
LIN Y Y Y
PMBus Y Y Y
SCI Y
SPI Y Y Y
(1)
USB Y Y
(1) These modules are accessible from DMA but cannot trigger a DMA transfer.

7.6 C28x Processor

The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
7.6.1 Floating-Point Unit (FPU)
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-priority
interrupts for fast context save and restore of the floating-point registers.
For more information on the C28x Floating Point Unit (FPU), see the TMS320C28x Extended Instruction Sets
Technical Reference Manual.
7.6.2 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and
leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 7-7.
Table 7-7. TMU Supported Instructions
Instructions C Equivalent Operation Pipeline Cycles
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5
Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation
of floating-point power function for the nonlinear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a
typical of 300 cycles using library emulation to less than 10 cycles.
No changes have been made to existing instructions, pipeline, or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out the operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

7.6.3 VCRC Unit

Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial 1 = 0x8005
• CRC16 polynomial 2 = 0x1021
• CRC24 polynomial = 0x5d6dcb
• CRC32 polynomial 1 = 0x04c11db7
• CRC32 polynomial 2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to three cycles when using a custom polynomial.
For more information on the Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended
Instruction Sets Technical Reference Manual.

7.7 Control Law Accelerator (CLA)

The CLA Type-2 is an independent, fully programmable, 32-bit floating-point math processor that brings
concurrent control-loop execution to the C28x family. The low interrupt-latency of the CLA allows it to read
ADC samples "just-in-time." This significantly reduces the ADC sample to output delay to enable faster system
response and higher MHz control loops. By using the CLA to service time-critical control loops, the main CPU is
free to perform other system tasks such as communications and diagnostics.
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical
control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster
system response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main
CPU to perform other system and communication functions concurrently.
The following is a list of major features of the CLA:
• C compilers are available for CLA software development
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent 8-stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0 to MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and a
main background task.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high-priority
events trigger a foreground task.
• Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership.
– Task8 can be set to be the background task, while Tasks 1 to 7 take peripheral triggers.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– Two dedicated message RAMs for communication between the CLA and the DMA

CLA Control
Register Set
MIFR(16)
MPERINT1 MIOVF(16) CLA_INT1
From Shared to to
Peripherals MPERINT8 MICLR(16) CLA_INT8
MICLROVF(16) C28x
PIE INT11
MIFRC(16) CPU
MIER(16) INT12
MIRUN(16)
LVF
MCTLBGRND(16)
LUF
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable MVECT1(16)
CPU Read/Write Data Bus
SYSRS MVECT2(16)
MVECT3(16)
MVECT4(16) CLA Program
MVECT5(16) CLA Program Bus Memory (LSx)
MVECT6(16)
MVECT7(16)
MVECT8(16) LSxMSEL[MSEL_LSx]
MVECTBGRND(16) LSxCLAPGM[CLAPGM_LSx]
MVECTBGRNDACTIVE(16)
MPSACTL(16)
CPU Data Bus

MPSA1(32) CLA Data
MPSA2(32) Memory (LSx)
MCTL(16)
CLA Data Bus

CLA Message
CLA Execution
RAMs
Register Set
MPC(16)
MSTF(32)
MR0(32)
MR1(32) Shared
MR2(32) MEALLOW Peripherals
MR3(32)
MAR0(16)
MAR1(16)
CPU Read Data Bus
Figure 7-2. CLA Block Diagram

7.8 Embedded Real-Time Analysis and Diagnostic (ERAD)

The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and system-
analysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consists
of the Enhanced Bus Comparator units and the System Event Counter units. The Enhanced Bus Comparator
units are used to generate hardware breakpoints, hardware watch points, and other output events. The System
Event Counter units are used to analyze and profile the system. The ERAD module is accessible by the
debugger and by the application software, which significantly increases the debug capabilities of many real-time
systems, especially in situations where debuggers are not connected. In the TMS320F28P55x devices, the
ERAD module contains eight Enhanced Bus Comparator units (which increases the number of Hardware
breakpoints from two to ten) and four Benchmark System Event Counter units.

7.9 Direct Memory Access (DMA)

The DMA module provides a hardware method of transferring data between peripherals and/or memory without
intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has
the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing. Figure 7-3 shows a
device-level block diagram of the DMA.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– External Interrupts
– ePWM SOC signals
– CPU timers
– eCAP
– SPI transmit and receive
– LIN transmit and receive
• Data sources and destinations:
– GSx RAM
– ADC result registers
– Control peripheral registers (ePWM, eQEP, eCAP)
– SPI, LIN, CAN, and PMBus registers
– USB
– PGA control registers
• Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
• Throughput: Four cycles per word without arbitration
ADC ADC Global Shared (GS0-

CAN LIN USB AES XINT TIMER
WRAPPER RESULTS 3) RAM
DMA bus C28x bus

TINT (0-2)
XINT(1-5)
ADCx.INT(1-5), ADCx.EVT
AESA_ContextIn, AESA_ContextOut, AESA_DataIn, AESA_DataOut
DMA_CHx(1-6)
LINxTXDMA, LINxRXDMA
C28x
DMA Trigger
Source Selection
ECAP(1-2)DMA PIE
DMACHSRCSEL1.CHx DMA
DMACHSRCSEL2.CHx
EPWM(1-12).SOCA, EPWM(1-12).SOCB CHx.MODE.PERINTSEL
(x = 1 to 6)
CLB1-2INT
EPGAINT
SPITXDMA(A-B)
SPIRXDMA(A-B)
FSITXADMA, FSIRXADMA
FSI_DATA_TAG_MATCH,
FSI_PING_TAG_MATCH
PM
PGA DAC CMPSS eQEP eCAP EPWM EPG CLB SPI FSI
Bus
Figure 7-3. DMA Block Diagram

7.10 Device Boot Modes

This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general-purpose input/output (GPIO) pins to determine the boot
mode configuration.
Table 7-8 shows the boot mode options available for selection by the default boot mode select pins. Users have
the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot
mode select pin GPIOs used.
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA, SPIA,
I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as SCI boot, it is
actually referring to the first module instance, which means the SCI boot on the SCIA port. The same applies to
the other peripheral boots.
See the Reset - XRSn - Switching Characteristics table and the Power-on Reset figure for tboot-flash, the boot
ROM execution time to first instruction fetch in flash.
Table 7-8. Device Default Boot Modes
GPIO24 GPIO32
BOOT MODE
(DEFAULT BOOT MODE SELECT PIN 1) (DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO 0 0
(1)
SCI / Wait Boot 0 1
CAN(MCAN-NONFD) 1 0
(2)
Flash(USB) 1 1
(1) SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.
(2) If the default flash entry address is not programmed, the boot mode will switch to USB Boot for those devices that include the USB
peripheral. On devices without a USB, the action will be to enter the ITRAP ISR if the default flash entry address is not programmed.
The switch to USB boot is only supported for the default flash entry address option and not all entry address options.

7.10.1 Device Boot Configurations

This section details what boot configurations are available and how to configure them. This device supports
from 0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot mode up to 8
configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to select
between 3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled). Refer to Section 7.10.1.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to
the decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 7.10.1.2 for all
the details on setting up and configuring the custom boot mode table.
Additionally, the Boot Mode Example Use Cases section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual provides some example use cases on how to configure the BMSPs and custom
boot tables.
Note
The CAN boot mode turns on the XTAL. Be sure an XTAL is installed in the application before using
CAN boot mode.

7.10.1.1 Configuring Boot Mode Pins

This section explains how the boot mode select pins can be customized by the user, by programming
the BOOTPIN-CONFIG location (refer to Table 7-9) in the user-configurable dual-zone security module
(DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG.
When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTP-
BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.
Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will take
priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTP-
BOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTP-
BOOTPIN-CONFIG.
Table 7-9. BOOTPIN-CONFIG Bit Fields

BIT NAME DESCRIPTION
31:24 Key Write 0x5A to these 8-bits to indicate the bits in this register are valid
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description except for BMSP2
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description except for BMSP1
Set to the GPIO pin to be used during boot (up to 255):
- 0x0 = GPIO0
- 0x01 = GPIO1
7:0 Boot Mode Select Pin 0 (BMSP0)
- and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to select
the boot mode.
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM automatically
selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the BMSP).
• GPIO 20 and GPIO 21
• GPIO 36 and GPIO 38
• GPIO 62 to GPIO 223

Table 7-10. Standalone Boot Mode Select Pin Decoding

BOOTPIN_CONFIG
BMSP0 BMSP1 BMSP2 REALIZED BOOT MODE
KEY
!= 0x5A Don’t Care Don’t Care Don’t Care Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode
0xFF 0xFF 0xFF 0
(All BMSPs disabled)
Boot as defined by the value of BMSP0
Valid GPIO 0xFF 0xFF
(BMSP1 and BMSP2 disabled)
0xFF Valid GPIO 0xFF
0xFF 0xFF Valid GPIO
Boot as defined by the values of BMSP0 and
Valid GPIO Valid GPIO 0xFF BMSP1
(BMSP2 disabled)
Valid GPIO 0xFF Valid GPIO BMSP2
(BMSP1 disabled)
= 0x5A Boot as defined by the values of BMSP1 and
0xFF Valid GPIO Valid GPIO BMSP2
(BMSP0 disabled)
Boot as defined by the values of BMSP0,
Valid GPIO Valid GPIO Valid GPIO
BMSP1, and BMSP2
BMSP0 is reset to the factory default BMSP0
GPIO
Invalid GPIO Valid GPIO Valid GPIO
BMSP1, and BMSP2
BMSP1 is reset to the factory default BMSP1
GPIO
Valid GPIO Invalid GPIO Valid GPIO
BMSP1, and BMSP2
BMSP2 is reset to the factory default state,
which is disabled
Valid GPIO Valid GPIO Invalid GPIO
BMSP1
Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significant-
bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.

7.10.1.2 Configuring Boot Mode Table Options

This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual
for examples on how to set up the BOOTPIN_CONFIG and BOOTDEF values.
Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead of Z1-
OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG is
configured. Refer to Configuring Boot Mode Pins for more details on BOOTPIN_CONFIG usage.
Table 7-11. BOOTDEF Bit Fields

BYTE
BOOTDEF NAME NAME DESCRIPTION
POSITION
Set the boot mode for index 0 of the boot table.
Different boot modes and their options can include,

for example, a boot mode that uses different GPIOs
for a specific bootloader or a different flash entry
BOOT_DEF0 7:0 BOOT_DEF0 Mode/Options point address. Any unsupported boot mode will
cause the device to either go to wait boot or boot to
flash.
Refer to GPIO Assignments for valid BOOTDEF

values to set in the table.
BOOT_DEF1 15:8 BOOT_DEF1 Mode/Options
BOOT_DEF4 39:32 BOOT_DEF4 Mode/Options Refer to BOOT_DEF0 description

7.10.2 GPIO Assignments

This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTP-
BOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure BOOT_DEF. When
selecting a boot mode option, make sure to verify that the necessary pins are available in the pin mux options for
the specific device package being used.
Table 7-12. SCI Boot Options
OPTION BOOTDEF VALUE SCITXDA GPIO SCIRXDA GPIO
0 (default) 0x01 GPIO29 GPIO28
1 0x21 GPIO16 GPIO17
2 0x41 GPIO8 GPIO9
3 0x61 GPIO2 GPIO3
4 0x81 GPIO16 GPIO3
Table 7-13. MCAN Boot Options

OPTION BOOTDEF VALUE CANTXA GPIO CANRXA GPIO
1 0x28 GPIO1 GPIO0
Table 7-14. CAN(MCAN in non-FD mode) Boot Options

OPTION BOOTDEF VALUE CANTXA GPIO CANRXA GPIO
1 0x22 GPIO1 GPIO0
Table 7-15. I2C Boot Options

OPTION BOOTDEF VALUE SDAA GPIO SCLA GPIO
0 0x07 GPIO0 GPIO1
2 0x47 GPIO5 GPIO4
Table 7-16. RAM Boot Options

RAM ENTRY POINT
OPTION BOOTDEF VALUE
(ADDRESS)
0 0x05 0x0000 0000
Table 7-17. Flash/Secure Flash Boot Options

FLASH ENTRY POINT
OPTION BOOTDEF VALUE FLASH SECTOR
(ADDRESS)
0 (default) 0x03 0x0008 0000 Bank0 Sector 0
1 0x23 0x0008 8000 Bank 0 Sector 32
2 0x43 0x000C 0000 Bank 2 Sector 0
3 0x63 0x000C 8000 Bank 2, Sector 32
4 0x83 0x0010 0000 Bank 4, Sector 0

Table 7-18. LFU Flash Boot Options

FLASH ENTRY POINT
OPTION BOOTDEF VALUE BANK
(ADDRESS)
0 (default) 0x0B 0x0008 0000 Bank0
0x000C 0000 Bank2
1 0x2B 0x0008 8000 Bank0
0x000C 8000 Bank2
Table 7-19. Wait Boot Options

OPTION BOOTDEF VALUE WATCHDOG
0 0x04 Enabled
1 0x24 Disabled
Table 7-20. SPI Boot Options

OPTION BOOTDEF VALUE SPIPICOA SPIPOCIA SPICLKA SPISPTE
0 0x06 GPIO2 GPIO1 GPIO3 GPIO5
Table 7-21. Parallel Boot Options

28x(DSP) CONTROL
OPTION BOOTDEF VALUE D0-D7 GPIO HOST CONTROL GPIO
GPIO
0 (default) 0x00 D0 - GPIO0 GPIO16 GPIO29
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
1 0x20 D0 - GPIO0 GPIO12 GPIO13
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
Table 7-22. USB Boot Options

OPTION BOOTDEF VALUE USB0 DM USB0 DP

7.11 Security
Security features are enforced by the Dual Code Security Module (DCSM). The primary layer of defense is
securing the boundary of the chip, which should always be enabled. Additionally, the Dual Zone Security feature
is available to support code partitioning.
7.11.1 Securing the Boundary of the Chip
The following two features, along with authentication in the firmware update code, should be used to help to
prevent unauthorized code from running on the device.
7.11.1.1 JTAGLOCK
Enabling the JTAGLOCK feature in the USER OTP disables JTAG access (for example, debug probe) to
resources on the device.
7.11.1.2 Zero-pin Boot
Enabling the Zero-pin Boot option along with Flash Boot in the USER OTP blocks all pin-based external
bootloader options (for example, SCI, CAN, Parallel).
7.11.2 Dual-Zone Security
The dual-zone security mechanism offers protection for two zones: Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both zones is identical. Each zone has its own dedicated secure resource (OTP memory and
secure ROM) and allocated secure resource (LSx RAM and flash sectors).
7.11.3 Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.

7.12 Watchdog
The watchdog module is the same as the one on previous TMS320C2000™ microcontrollers, but with an
optional lower limit on the time between software resets of the counter. This windowed countdown is disabled by
default, so the watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 7-4 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV WDCR.WDPS WDCR.WDDIS
WDCNTR
WDCLK
(INTOSC1) Overflow 1-count
delay
8-bit
WDCLK Watchdog Watchdog
Divider Prescaler Counter
SYSRSn
Clear
Count
WDWCR.MIN
WDKEY (7:0)
Out of Window Watchdog
Watchdog Good Key
Window
Key Detector Detector
WDCR(WDCHK(2:0))
55 + AA
Bad Key
WDRSTn Generate
1 0 1 512-WDCLK Watchdog Time-out
WDINTn Output Pulse
SCSR.WDENINT
Figure 7-4. Windowed Watchdog

7.13 C28x Timers

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLK (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• X1 (XTAL)

7.14 Dual-Clock Comparator (DCC)

The DCC module is used for evaluating and monitoring the clock input based on a second clock, which can
be a more accurate and reliable version. This instrumentation is used to detect faults in clock source or clock
structures, thereby enhancing the system's safety metrics.
7.14.1 Features
The DCC has the following features:
• Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
• Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
• Supports continuous monitoring without requiring application intervention.
• Supports a single-sequence mode for spot measurements.
• Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
7.14.2 Mapping of DCCx Clock Source Inputs
Table 7-23. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0] CLOCK NAME
0x0 XTAL/X1
0x1 INTOSC1
0x2 INTOSC2
0x4 TCK
0x5 CPU1.SYSCLK
0x8 AUXCLKIN
0xC INPUT XBAR (Output16 of input-xbar)
others Reserved
Table 7-24. DCCx Clock Source1 Table

DCCxCLKSRC1[4:0] CLOCK NAME
0x0 PLLRAWCLK
0x2 INTOSC1
0x3 INTOSC2
0x6 CPU1.SYSCLK
0x9 Input XBAR (Output15 of the input-xbar)
0xA AUXCLKIN
0xB EPWMCLK
0xC LSPCLK
0xD ADCCLK
0xE WDCLK
0xF CAN0BITCLK
others Reserved

7.15 Configurable Logic Block (CLB)

The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application notes and users guide, please refer to the following location in your C2000Ware for C2000
MCUs package (C2000Ware_2_00_00_03 and higher):
• C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
• CLB Tool User's Guide
• Designing With the C2000™ Configurable Logic Block (CLB) Application Note
• How to Migrate Custom Logic From an FPGA/CPLD to C2000™ Microcontrollers Application Note
The CLB module and its interconnections are shown in Figure 7-5.
GPIO0 Asynchronous
to Synchronous Input X-BAR
GPIOx Sync. + Qual
IN P U T 1 – IN P U T 6 CLBx T ILE
O t h er OU T 4 /5
S o u rc es
CLB X-BAR
O t her AU XSIG 0 – AU XSIG 7

So u rc es
CLB INPUT X-BAR CLB
CLB TILE1
GPREG CELL
CLB Global Signals IN0-7
Local OUT 0-7

Signals
.
. C L B T i l e O ut p ut s
. I nte rs ec t o t he r
I N P U T 1 – IN P U T 1 6 Pe r i ph eral s
CLB TILEx O U T P U T X-BAR
GPREG CELL
IN0-7
Local OUT 0-7

Signals
All C LB T i l e
Ou t p u t s
CLB OUTPUT X-BAR
GP IO M U X
Figure 7-5. GPIO to CLB Tile Connections

Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality.

8 Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Below is a partial list of applicable reference designs. A full listing of supported reference designs for this device,
as well as other C2000 MCUs, is maintained inside TI resource explorer.
3-kW, 180-W/in3 single-phase totem-pole bridgeless PFC reference design with 16-A max input
This reference design demonstrates a method to control a continuous conduction mode Totem pole power factor
correction converter (PFC) using C2000™ microcontrollers. The PFC also works as inverter in grid connected
(current controlled) mode. The converter is designed to support a maximum input current of 16-ARMS and peak
power of 3.6 kW.
Bidirectional 400-V/12-V DC/DC Converter Reference Design
The Bidirectional 400V-12V DC/DC Converter Reference Design is a microcontroller-based implementation of
an isolated bi-directional DC-DC converter. A phase shifted full-bridge (PSFB) with synchronous rectification
controls power flow from a 400V bus/battery to the 12V battery in step-down mode, while a push-pull stage
controls the reverse power flow from the low voltage battery to the high voltage bus/battery in boost mode.
GaN-based, 6.6-kW, bidirectional, onboard charger reference design
The PMP22650 reference design is a 6.6-kW, bidirectional, onboard charger. The design employs a two-phase
totem pole PFC and a full-bridge CLLLC converter with synchronous rectification. The CLLLC utilizes both
frequency and phase modulation to regulate the output across the required regulation range.
Bidirectional CLLLC resonant dual active bridge (DAB) reference design for HEV/EV onboard charger
CLLLC resonant DAB with bidirectional power flow capability and soft switching characteristics is an ideal
candidate for Hybrid Electric Vehicle/Electric Vehicle (HEV/EV) on-board chargers and energy storage
applications. This design illustrates control of this power topology using a C2000™ MCU in closed voltage
and closed current-loop mode.
7.4-kW on-board charger reference design with CCM totem pole PFC and CLLLC DC/DC using C2000™ MCU
TIDM-02013 is a bidirectional onboard charger reference design. The design consists of an interleaved
continuous conduction mode (CCM) totem-pole (TTPL) bridgeless power-factor correction (PFC) power stage
followed by a CLLLC DCDC power stage all controlled using a single C2000™ real-time control microcontroller
(MCU), while utilizing a TI gallium nitride (GaN) power module.
48-V Three-Phase Inverter With Shunt-Based In-Line Motor Phase Current Sensing Evaluation Module
The BOOSTXL-3PHGANINV evaluation module features a 48-V/10-A three-phase GaN inverter with precision
in-line shunt-based phase current sensing for accurate control of precision drives such as servo drives.
C2000 DesignDRIVE position manager BoosterPack™ plug-in module
The PositionManager BoosterPack is a flexible low voltage platform intended for evaluating interfaces to
absolute encoders and analog sensors like resolvers and SinCos transducers. When combined with thec
DesignDRIVE Position Manager software solutions this low-cost evaluation module becomes a powerful tool
for interfacing many popular position encoder types such as EnDat, BiSS and T-format with C2000 Real-Time
Control devices. C2000 Position Manager technology integrates interfaces to the most popular digital and analog
position sensors onto C2000 Real-Time Controller, thus eliminating the need for external FPGAs for these
functions.
Distributed multi-axis servo drive over fast serial interface (FSI) reference design
This reference design presents an example distributed or decentralized multi-axis servo drive over Fast Serial
Interface (FSI) using C2000™ real-time controllers. Multi-axis servo drives are used in many applications such
as factory automation and robots. The cost per axis, performance and ease of use are always high concerns for
such systems. FSI is a cost-optimized and reliable high speed communication interface with low jitter that can
daisy-chain multiple C2000 microcontrollers.

10-kW, bidirectional three-phase three-level (T-type) inverter and PFC reference design
This verified reference design provides an overview on how to implement a three-level three-phase SiC based
DC:AC T-type inverter stage. Higher switching frequency of 50KHz reduces the size of magnetics for the filter
design and enables higher power density. The use of SiC MOSFETs with switching loss ensures higher DC
bus voltages of up to 1000V and lower switching losses with a peak efficiency of 99 percent. This design is
configurable to work as a two-level or three-level inverter.
Bi-directional, dual active bridge reference design for level 3 electric vehicle charging stations
This reference design provides an overview on the implementation of a single-phase dual active bridge (DAB)
DC/DC converter. DAB topology offers advantages like soft-switching commutations, a decreased number of
devices and high efficiency. The design is beneficial where power density, cost, weight, galvanic isolation, high
voltage conversion ratio and reliability are critical factors, making it ideal for EV charging stations and energy
storage applications. Modularity and symmetrical structure in DAB allow for stacking converters to achieve high
power throughput and facilitate a bidirectional mode of operation to support battery charging and discharging
applications.
1.6kW, bidirectional micro inverter based on GaN reference design
This reference design shows a four-input bidirectional 1.6kW GaN-based microinverter with energy storage
capability.

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MCU
devices and support tools. Each TMS320 ™ MCU commercial family member has one of three prefixes: TMX,
TMP, or TMS (for example, TMS320F28P559SJ-Q1). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX and TMDX) through fully qualified production devices
and tools (TMS and TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZ).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.

Generic Part Number: TMS 320 F28 P 559 S J -Q1
Orderable Part Number: X F28 P 559 S J 9 PDT R Q1
PREFIX(A)
TMX (X) = experimental device AUTOMOTIVE AEC-Q100 QUALIFICATION
TMS (blank) = qualified device (blank) = Not AEC-Q100 qualified
Q1 = AEC-Q100 qualification
DEVICE FAMILY
320 = TMS320 MCU Family SHIPPING OPTIONS
(blank) = Tray
R = Tape and Reel
CPU ARCHITECTURE
F28 = C28 CPU
PACKAGE TYPE
PDT = 128-pin Thin Quad Flatpack (TQFP)
SERIES PZ = 100-pin Low-profile Quad Flatpack (LQFP)
PNA = 80-pin TQFP
P = Performance (150 MIPS to 600 MIPS)
PM = 64-pin LQFP
RSH = 56-pin Very Thin Quad Flatpack No-Lead (VQFN)
MAJOR FAMILY (PLATFORM)

P = 30x to 69x SPECIAL FEATURES CODE
Industrial = Third digit is between 0 and 4
Automotive = Third digit is between 5 and 9 2 = Base + 8 PWM pairs
6 = Base + CLA + CLB + USB + 12 PWM pairs + 64KB Flash
7 = Base + CLA + CLB + 12 PWM pairs + 24KB RAM
8 = Base + CLA + CLB + 12 PWM pairs
CORE 9 = Base + CLA + CLB + USB + NPU + 12 PWM pairs + 64KB Flash
S=1
MEMORY
J = 1MB Flash, 133KB RAM
G = 512KB Flash, 101KB RAM
A. Prefix X is used in orderable part numbers.
Figure 9-1. Device Nomenclature
9.2 Markings
Figure 9-2, Figure 9-3, Figure 9-4, Figure 9-5, Figure 9-6, Figure 9-7, Figure 9-8, and Figure 9-9 show the
package symbolization. Table 9-1 lists the silicon revision codes.
YMLLLLS = Lot Trace Code
YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P559 S = Assembly Site Code
SJ9PDTQ $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = Green (Low Halogen and RoHS-compliant)
Package
Pin 1
Figure 9-2. Package Symbolization for PDT Package – Automotive


SJ9PZQ $$ = Wafer Fab Code (one or two characters) as applicable
G4
Package
Pin 1
Figure 9-3. Package Symbolization for PZ Package – Automotive

F28P550 S = Assembly Site Code
SJ9PZ $$ = Wafer Fab Code (one or two characters) as applicable
G4
Package
Pin 1
Figure 9-4. Package Symbolization for PZ Package – Non-Automotive

SJ9PNAQ $$ = Wafer Fab Code (one or two characters) as applicable
G4
Package
Pin 1
Figure 9-5. Package Symbolization for PNA Package – Automotive


SJ9PNA $$ = Wafer Fab Code (one or two characters) as applicable
G4
Package
Pin 1
Figure 9-6. Package Symbolization for PNA Package – Non-Automotive

SJ9PMQ $$ = Wafer Fab Code (one or two characters) as applicable
G4
Package
Pin 1
Figure 9-7. Package Symbolization for PM Package – Automotive

SJ9PM $$ = Wafer Fab Code (one or two characters) as applicable
G4
Package
Pin 1
Figure 9-8. Package Symbolization for PM Package – Non-Automotive


F28P550 LLLL = Assembly Lot Code
S = Assembly Site Code
SJ9RSH $$ = Wafer Fab Code (one or two characters) as applicable
$$#YMLLLLS # = Silicon Revision Code
TI G4
Package
Pin 1
Figure 9-9. Package Symbolization for RSH Package – Non-Automotive
Table 9-1. Revision Identification

REVID(1)
SILICON REVISION CODE SILICON REVISION COMMENTS
ADDRESS: 0x5D00C
Blank 0 0x0000 0001 This silicon revision is available as TMX.
A A 0x0000 0002 This silicon revision is available as TMS.
(1) Silicon Revision ID

9.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance
of the device, generate code, and develop solutions follow. To view all available tools and software for C2000™
real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
TI Resource Explorer
To enhance your experience, be sure to check out the TI Resource Explorer to browse examples, libraries, and
documentation for your applications.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000™ MCUs is a cohesive set of software and documentation created to minimize
development time. It includes device-specific drivers, libraries, and peripheral examples.
DigitalPower SDK
DigitalPower SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based digital power system development time targeted for various AC-DC, DC-DC and DC-AC
power supply applications. The software includes firmware that runs on C2000 digital power evaluation modules
(EVMs) and TI designs (TIDs), which are targeted for solar, telecom, server, electric vehicle chargers and
industrial power delivery applications. DigitalPower SDK provides all the needed resources at every stage of
development and evaluation in a digital power applications.
MotorControl SDK
MotorControl SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based motor control system development time targeted for various three-phase motor control
applications. The software includes firmware that runs on C2000 motor control evaluation modules (EVMs) and
TI designs (TIDs), which are targeted for industrial drive and other motor control, MotorControl SDK provides
all the needed resources at every stage of development and evaluation for high-performance motor control
applications.
Code Composer Studio™ integrated development environment (IDE)
Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and
processors. It comprises a suite of tools used to develop and debug embedded applications. Code Composer

Studio is available for download across Windows®, Linux® and macOS® desktops. It can also be used in
the cloud by visiting https://dev.ti.com. Code Composer Studio includes an optimizing C/C++ compiler, source
code editor, project build environment, debugger, profiler and many other features. The intuitive IDE takes you
through each step of the application development flow. Familiar tools and interfaces make getting started faster
than ever before. The desktop version of Code Composer Studio combines the advantages of the Eclipse
software framework with advanced capabilities from TI resulting in a compelling feature-rich environment. The
cloud-based Code Composer Studio leverages the Theia application framework enabling development in the
cloud without needing to download and install large amounts of software.
SysConfig System configuration tool
SysConfig is a comprehensive collection of graphical utilities for configuring pins, peripherals, radios,
subsystems, and other components. SysConfig helps you manage, expose and resolve conflicts visually so
that you have more time to create differentiated applications. The tool's output includes C header and code files
that can be used with software development kit (SDK) examples or used to configure custom software. The
SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The SysConfig
tool is delivered integrated in CCS, as a standalone installer, or can be used via the dev.ti.com cloud tools portal.
For more information about the SysConfig system configuration tool, visit the System configuration tool page.
C2000 Third-party search tool
TI has partnered with multiple companies to offer a wide range of solutions and services for TI C2000 devices.
These companies can accelerate your path to production using C2000 devices. Download this search tool to
quickly browse third-party details and find the right third-party to meet your needs.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
Models
Various models are available for download from the product Design & development pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL)
Models. To view all available models, visit the Design tools & simulation section of the Design & development
page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable
hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000
microcontroller family. These training resources have been designed to decrease the learning curve, while
reducing development time, and accelerating product time to market. For more information on the various
training resources, visit the C2000™ real-time control MCUs – Support & training site.
9.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
follows.
Note
TI is transitioning to use more inclusive terminology. Some language may be different than what you
would expect to see for certain technology areas.

Errata
TMS320F28P55x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in
the F28P55x real-time microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v22.6.0.LTS User’s Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v22.6.0.LTS User’s Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Notes
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
The Essential Guide for Developing With C2000™ Real-Time Microcontrollers provides a deeper look into the
components that differentiate the C2000 Microcontroller Unit (MCU) as it pertains to Real-Time Control Systems.
Migrating Software From 8-Bit (Byte) Addressable CPUs to C28x CPU discusses common scenarios of
migrating software from 8-bit (byte) addressable CPUs to C28x CPU, and provides a guide on how to develop
application irrespective of the addressability.
The Hardware Design Guide for F2800x C2000™ Real-Time MCU Series Application Note is an essential guide
for hardware developers using C2000 devices, and helps to streamline the design process while mitigating the
potential for faulty designs. Key topics discussed include: power requirements; general-purpose input/output

(GPIO) connections; analog inputs and ADC; clocking generation and requirements; and JTAG debugging
among many others.
9.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.6 Trademarks
C2000™, TMS320C2000™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
Windows® is a registered trademark of Microsoft Corporation.
Linux® is a registered trademark of Linus Torvalds.
macOS® is a registered trademark of Apple Inc.
All trademarks are the property of their respective owners.
9.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
Changes from April 2, 2024 to September 19, 2024 Page
• This Revision History lists the changes from SPRSP85 to SPRSP85A. .................................................... 1
• Global: TI is transitioning to use more inclusive terminology. Some language may be different than what you
would expect to see for certain technology areas. For SPI, all instances of legacy terminology have been
changed to controller and peripheral. All instances of legacy pin names have been changed to: POCI
(Peripheral OUT Controller IN); PICO (Peripheral IN Controller OUT); and CS (Chip Select). For the I2C Bus
Interface, all instances of legacy terminology have been changed to controller and target. For the CAN and
LIN Interface/BUS, all instances of legacy terminology have been changed to commander and responder.
For the EtherCAT Controller, all instances of legacy terminology have been changed to MainDevice (or
MDevice) and SubordinateDevice (or SubDevice)............................................................................................. 1
• Global: Changed document status statement from "ADVANCE INFORMATION for preproduction products;
subject to change without notice" to "UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA"..................................................................................................................................................................1
• Global: Information on the TMS320F28P550SJ device is Production Data...................................................... 1
• Global: Information on the TMS320F28P559SJ-Q1, TMS320F28P559SG-Q1, and TMS320F28P550SG
devices is preview information only (not Production Data),................................................................................1
• Global: Removed TMS320F28P550SD device................................................................................................. 1
• Global: Changed "NNPU" to "NPU"...................................................................................................................1
• Global: Changed DACB_OUT to CMP1_DACL................................................................................................ 1
• Features section: Removed "Neural-Network Processing Unit (NNPU)" from "Real-time processing"
features...............................................................................................................................................................1
• Features section: Added Fast Serial Interface (FSI) to Communications peripherals........................................1
• Features section: Changed "24 ePWM channels with 16 channels that have high-resolution capability (150ps
resolution)" to "24 ePWM channels with 12 channels that have high-resolution capability (150ps
resolution)"..........................................................................................................................................................1
• Features section: Added "Neural-network Processing Unit (NPU)" features..................................................... 1
• Description section: Updated applications link in "These include such applications as". Added paragraph
about Neural-network Processing Unit (NPU).................................................................................................... 3
• Package Information table: Added "Preview information (not Production Data)" footnote................................. 3
• Functional Block Diagram figure: Changed "24x ePWM Channels (16Ch Hi-Res Capable)" to "24x ePWM
Channels (12Ch Hi-Res Capable)".....................................................................................................................5
• Device Comparison table: Added "Preview information (not Production Data)" footnote...................................7
• Pin Attributes table: Changed DACB_OUT to CMP1_DACL. Added footnotes about VREFLO and VREFHI. 10
• 128-pin PDT Thin Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on Pin 29......... 10
• 100-Pin PZ Low-Profile Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on
Pin 22............................................................................................................................................................... 10
• 80-Pin PNA Thin Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on Pin 18.......... 10
• 64-Pin PM Low-Profile Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on Pin 14..10
• 56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View) figure: Changed DACB_OUT to CMP1_DACL on
Pin 12............................................................................................................................................................... 10
• Analog Signals table: Removed DACB_OUT. Added footnotes about VREFLO and VREFHI........................ 40
• Digital Inputs and Outputs on ADC Pins (AGPIOs) section: Updated section..................................................52
• Absolute Maximum Ratings table: Removed reference to "Continuous clamp current per pin is ±2mA"
footnote from "Input clamp current - total for all inputs"....................................................................................67
• Electrical Characteristics table: Updated IOL, ROL, and ILEAK. Added VIH (High-level input voltage -
GPIO23/41). Updated MIN values of VHYSTERESIS........................................................................................... 67
• ESD Ratings – Commercial table: Added HBM value for 5V FS (fail-safe) pins.............................................. 68
• ESD Ratings – Automotive table: Added HBM value for 5V FS (fail-safe) pins............................................... 69
• System Current Consumption - VREG Enable - Internal Supply table: Updated table.................................... 71
• System Current Consumption - VREG Disable - External Supply table: Updated table.................................. 71

• Typical Current Reduction per Disabled Peripheral table: Changed "ePWM(per)" to "ePWM (for 1 ePWM)"..75
• Special Considerations for 5V Fail-Safe Pins section: Added section..............................................................78
• Clocking System figure: Updated figure........................................................................................................... 93
• Internal Clock Frequencies table: Added f(NPU), NPUCLK frequency............................................................... 96
• Crystal Oscillator Specifications section: Removed duplicate Crystal Oscillator Electrical Characteristics
table................................................................................................................................................................ 103
• RAM Specifications section: Removed RAM Parameters – F28P55xSD table..............................................108
• ROM Specifications section: Changed table title from ROM Parameters – F28P55xSJ, F28P55xSG, and
F28P55xSD to ROM Parameters – F28P55xSJ and F28P55xSG................................................................. 109
• GPIO Electrical Data and Timing section: Updated section........................................................................... 114
• Analog Subsystem Block Diagram (128-/80-/64-/56-Pin Packages) figure: Changed A1/B7/D11/DACB_OUT
to A1/B7/D11/CMP1_DACL............................................................................................................................124
• Analog Subsystem Block Diagram (100-Pin Package) figure: Changed A1/B7/D11/DACB_OUT to A1/B7/D11/
CMP1_DACL..................................................................................................................................................124
• CMPSS Input Mux Options table: Changed "A1, B7, D11, DACB_OUT" to "A1, B7, D11, CMP1_DACL" for
HP4 and LP4.................................................................................................................................................. 124
• Analog Pins and Internal Connections table: Changed "A1/B7/D11/DACB_OUT" to "A1/B7/D11/
CMP1_DACL" in Analog Group 1. Changed DACB_OUT to CMP1_DACL in Analog Group 1. ..................129
• Analog Signal Descriptions table: Changed DACB_OUT to CMP1_DACL. ................................................. 132
• ADC Characteristics table: Updated Offset Error, SNR, THD, ENOB, and PSRR. Added "Frequency tolerance
over temperature of the INTOSC ..." footnote. .............................................................................................. 136
• ADC Performance Per Pin section: Added section........................................................................................ 139
• Per-Channel Parasitic Capacitance for 128-Pin QFP table: Updated table................................................... 143
• Per-Channel Parasitic Capacitance for 100-Pin QFP table: Updated table................................................... 143
• Per-Channel Parasitic Capacitance for 80-Pin QFP table: Updated table..................................................... 143
• Per-Channel Parasitic Capacitance for 64-Pin QFP table: Updated table..................................................... 143
• Per-Channel Parasitic Capacitance for 56-Pin QFN table: Updated table..................................................... 143
• Buffered Output from CMPx_DACL Electrical Characteristics table: Updated MIN and MAX values of INL..157
• PGA Characteristics table: Updated table and footnotes............................................................................... 165
• Overview section: Updated section................................................................................................................ 212
• Functional Block Diagram figure: Changed "24x ePWM Channels (16Ch Hi-Res Capable)" to "24x ePWM
Channels (12Ch Hi-Res Capable)".................................................................................................................213
• Flash Memory Map table: Updated table........................................................................................................218
• Peripheral Registers Memory Map table: Updated table................................................................................220
• Device Identification Registers table: Removed PARTIDH for TMS320F28P55xSD7. Added REVID for silicon
revision A........................................................................................................................................................225
• Reference Design section: Updated section.................................................................................................. 246
• Device Nomenclature figure: Updated figure..................................................................................................248
• Package Symbolization for PDT Package – Automotive figure: Updated definition of G4............................. 249
• Package Symbolization for PZ Package – Automotive figure: Updated definition of G4................................249
• Package Symbolization for PZ Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
• Package Symbolization for PNA Package – Automotive figure: Updated definition of G4.............................249
• Package Symbolization for PNA Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
• Package Symbolization for PM Package – Automotive figure: Updated definition of G4...............................249
• Package Symbolization for PM Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
• Package Symbolization for RSH Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
• Revision Identification table: Changed REVID of Silicon Revision 0 to 0x0000 0001. Added silicon
revision A........................................................................................................................................................ 249

• Documentation Support section: Added Migrating Software From 8-Bit (Byte) Addressable CPUs to C28x
CPU to Application Notes section...................................................................................................................253
• Documentation Support section: Added Hardware Design Guide for F2800x C2000™ Real-Time MCU Series
Application Note..............................................................................................................................................253

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

11.1 Package Option Addendum
Packaging Information
Package Package Lead/Ball MSL Peak
Orderable Device Status(1) Package Type Pins Eco Plan(2) Op Temp (°C) Device Marking(4) (5)
Drawing Qty Finish(6) Temp(3)
F28P550SJ9PDT ACTIVE TQFP PDT 128 90 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PDT
no Sb/Br) 168 HR
F28P550SJ9PDTR ACTIVE TQFP PDT 128 Call TI Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PDT
no Sb/Br) 168 HR
XF28P559SJ9PDTQ1 ACTIVE TQFP PDT 128 90 Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PDTQ
no Sb/Br) 168 HR
XF28P559SJ9PDTRQ1 ACTIVE TQFP PDT 128 Call TI Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PDTQ
no Sb/Br) 168 HR
F28P550SJ9PZ ACTIVE LQFP PZ 100 90 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PZ
no Sb/Br) 168 HR
F28P550SJ9PZR ACTIVE LQFP PZ 100 1000 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PZ
no Sb/Br) 168 HR
XF28P559SJ9PZQ1 ACTIVE LQFP PZ 100 90 Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PZQ
no Sb/Br) 168 HR
XF28P559SJ9PZRQ1 ACTIVE LQFP PZ 100 1000 Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PZQ
no Sb/Br) 168 HR
F28P550SJ9PNA ACTIVE TQFP PNA 80 160 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PNA
no Sb/Br) 168 HR
F28P550SJ9PNAR ACTIVE TQFP PNA 80 1000 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PNA
no Sb/Br) 168 HR
XF28P559SJ9PNAQ1 ACTIVE TQFP PNA 80 160 Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PNAQ
no Sb/Br) 168 HR
XF28P559SJ9PNARQ1 ACTIVE TQFP PNA 80 1000 Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PNAQ
no Sb/Br) 168 HR
F28P550SJ9PM ACTIVE LQFP PM 64 160 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PM
no Sb/Br) 168 HR
F28P550SJ9PMR ACTIVE LQFP PM 64 1000 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9PM
no Sb/Br) 168 HR
XF28P559SJ9PMQ1 ACTIVE LQFP PM 64 160 Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PMQ
no Sb/Br) 168 HR
XF28P559SJ9PMRQ1 ACTIVE LQFP PM 64 1000 Green (RoHS & NIPDAU Level-3260C- –40 to 125 XF28P559SJ9PMQ
no Sb/Br) 168 HR

Package Package Lead/Ball MSL Peak

Orderable Device Status(1) Package Type Pins Eco Plan(2) Op Temp (°C) Device Marking(4) (5)
Drawing Qty Finish(6) Temp(3)
F28P550SJ9RSHR ACTIVE VQFN RSH 56 2500 Green (RoHS & NIPDAU Level-3260C- –40 to 125 F28P550SJ9RSH
no Sb/Br) 168 HR
(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on
information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming
materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS
K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
All dimensions are nominal.

Reel Reel
Package Package Diameter Width W1 A0 B0 K0 P1 W Pin1
Device Type Drawing Pins SPQ (mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
F28P550SJ9RSHR VQFN RSH 56 4000 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2
XF28P559SJ9PMRQ1 LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F28P550SJ9PMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
XF28P559SJ9PNARQ1 TQFP PNA 80 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
F28P550SJ9PNAR TQFP PNA 80 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
XF28P559SJ9PZRQ1 LQFP PZ 100 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2
F28P550SJ9PZR LQFP PZ 100 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2
XF28P559SJ9PDTRQ1 TQFP PDT 128 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2
F28P550SJ9PDTR TQFP PDT 128 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2

TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
F28P550SJ9RSHR VQFN RSH 56 4000 367.0 367.0 35.0
XF28P559SJ9PMRQ1 LQFP PM 64 1000 336.6 336.6 41.3
F28P550SJ9PMR LQFP PM 64 1000 336.6 336.6 41.3
XF28P559SJ9PNARQ1 TQFP PNA 80 1000 336.6 336.6 41.3
F28P550SJ9PNAR TQFP PNA 80 1000 336.6 336.6 41.3
XF28P559SJ9PZRQ1 LQFP PZ 100 1000 367.0 367.0 55.0
F28P550SJ9PZR LQFP PZ 100 1000 367.0 367.0 55.0
XF28P559SJ9PDTRQ1 TQFP PDT 128 1000 367.0 367.0 55.0
F28P550SJ9PDTR TQFP PDT 128 1000 367.0 367.0 55.0

TRAY
L - Outer tray length without tabs KO -

Outer
tray
height
W-
Outer
tray
width
Text
P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

Max
Package Package Unit Array CL
Device Pins SPQ Temp. L (mm) W (mm) K0 (μm) P1 (mm) CW (mm)
Type Name Matrix (mm)
(Deg C)
F28P550SJ9PDT TQFP PDT 128 90 6 x 15 150 315 135.9 7620 15.4 20.3 21
XF28P559SJ9PDTQ1 TQFP PDT 128 90 6 x 15 150 315 135.9 7620 15.4 20.3 21
F28P550SJ9PZ LQFP PZ 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.4
XF28P559SJ9PZQ1 LQFP PZ 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.4
F28P550SJ9PNA TQFP PNA 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
XF28P559SJ9PNAQ1 TQFP PNA 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
F28P550SJ9PM LQFP PM 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13
XF28P559SJ9PMQ1 LQFP PM 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13

PACKAGE OUTLINE
PDT0128A SCALE 1.000
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
14.05
PIN 1 ID B
13.95
A 128 97
1 96
14.05 16.1
TYP
13.95 15.9
32
65
33
64
124X 0.4 0.23
128X
0.13
4X 12.4 0.05 C A B
SEE DETAIL A 1.2 MAX
C
(0.13) TYP
SEATING PLANE
0.08 C
0.25
GAGE PLANE (1)
0.75 0.05 MIN

0 -5
0.45
DETAIL A
TYPICAL
DETAIL A
SCALE: 12
4215171/A 10/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
PDT0128A TQFP - 1.2 mm max height
SYMM
128 97
128X (1.45)
1
96
128X (0.2)
124X (0.4)
(R0.05) TYP
SYMM
(15.35)
32 65
SEE DETAILS
33 64
(15.35)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
EXPOSED EXPOSED
METAL METAL
METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS
4215171/A 10/2023
NOTES: (continued)
3. Publication IPC-7351 may have alternate designs.

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
5. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and
SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PDT0128A TQFP - 1.2 mm max height
SYMM
128 97
128X (1.45)
1
96
128X (0.2)
124X (0.4)
SYMM
(15.35)
(R0.05) TYP
32 65
33 64
(15.35)
SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:6X
4215171/A 10/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
0,27
0,50 0,08 M
0,17
75 51
76 50
100 26 0,13 NOM
1 25
12,00 TYP Gage Plane
14,20
SQ
13,80
16,20 0,25
SQ 0,05 MIN 0°– 7°
15,80
1,45 0,75
1,35 0,45
Seating Plane
1,60 MAX 0,08
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

PACKAGE OUTLINE
PNA0080A SCALE 1.500
TQFP - 1.2 mm max height
10.1
PIN 1 ID B
9.9
80 61
A
1 60
12.2
TYP
11.8
10.1
9.9
20 41
21 40
0.21
76X 0.4 80X
0.15
4X 7.6 0.05 C A B
SEE DETAIL A
1.2 MAX
C
(0.13) TYP
SEATING PLANE
0.08 C
0.25
GAGE PLANE (1)
0.15
0 -5 0.7 0.05
0.5
DETAIL A
DETAIL A
SCALE: 14
TYPICAL
4229169/E 09/2024
NOTES:
per ASME Y14.5M.
3. Reference JEDEC registration MS-026.
www.ti.com
PNA0080A TQFP - 1.2 mm max height
SYMM
80 61
80X (1.45)
1
60
80X (0.2)
76X (0.4) SYMM
(11.4)
(R0.05) TYP
20 41
21 40
(11.4)

EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN
ALL AROUND

OPENING SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS
4229169/E 09/2024
NOTES: (continued)

6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
PNA0080A TQFP - 1.2 mm max height
SYMM
80 61
80X (1.45)
1
60
80X (0.2)
76X (0.4) SYMM
(11.4)
(R0.05) TYP
20 41
21 40
(11.4)

SCALE:8X
4229169/E 09/2024
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
PM0064A SCALE 1.400
LQFP - 1.6 mm max height
10.2
B
9.8
NOTE 3
64 49
PIN 1 ID
1 48
10.2 12.2
TYP
9.8 11.8
NOTE 3
16 33
17 32
A
0.27
60X 0.5 64X
0.17
4X 7.5 0.08 C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25 (1.4) 1.6 MAX

GAGE PLANE
0 -7 0.75 0.05 MIN

0.45
DETAIL A
DETAIL A
SCALE: 14
TYPICAL
4215162/A 03/2017
NOTES:
per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
PM0064A LQFP - 1.6 mm max height
SYMM
64 49
64X (1.5)
1
48
64X (0.3)
SYMM
60X (0.5) (11.4)
(R0.05) TYP
16 33
17 32
(11.4)

EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN
ALL AROUND

OPENING SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)

7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
PM0064A LQFP - 1.6 mm max height
SYMM
64 49
64X (1.5)
1
48
64X (0.3)
SYMM
60X (0.5) (11.4)
(R0.05) TYP
16 33
17 32
(11.4)

SCALE:8X
4215162/A 03/2017
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
RSH0056G SCALE 2.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
7.1
B A
6.9
PIN 1 INDEX AREA

0.25
45 0.15
7.1
6.9
(0.17)
(0.175)
DETAIL A
A35.000
1.0
0.8 TYPICAL
C
SEATING PLANE
0.05 0.08 C
0.00
2X 5.2
SYMM
EXPOSED (0.1) TYP
THERMAL PAD 15 28
14 29
SYMM 57
2X 5.2 5.3 0.1
1 42
52X 0.4 0.225
56X
43 0.125
56
PIN 1 ID 0.1 C A B
(45 X 0.3) 0.65
56X 0.05 C
0.45
SEE DETAIL A
4229539/B 08/2023
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
RSH0056G VQFN - 1 mm max height
( 5.3)
SYMM
56 43 SEE SOLDER MASK
56X (0.75) DETAIL
56X (0.2)
1
42
(1.12) TYP
52X (0.4)
(R0.05) TYP (1.28) TYP

SYMM 57
(6.65)
( 0.2) TYP
VIA
14 29
15 28
(1.28) TYP (1.12)
TYP
(6.65)

EXPOSED METAL SHOWN
SCALE: 12X
0.05 MIN
0.05 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK
EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING
NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4229539/B 08/2023
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
RSH0056G VQFN - 1 mm max height
(0.64) TYP (1.28) TYP
56 43
56X (0.75)
56X (0.2)
1
42
52X (0.4) (1.28) TYP
57 (0.64) TYP
SYMM (6.65)
(R0.05) TYP
16X (1.08)
14 29
15 28
SYMM 16X
(1.08)
(6.65)

BASED ON 0.100 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 57
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4229539/B 08/2023
NOTES: (continued)
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TMS320F28P550SJ, TMS320F28P559SJ-Q1

SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

TMS320F28P55x Real-Time Microcontrollers

– Three Programmable Gain Amplifiers (PGAs) – 80-pin TQFP [PNA suffix]

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• Body electronics & lighting • Renewable energy storage

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3.1 Functional Block Diagram

GS0-GS3 RAM NPU

Figure 3-1. Functional Block Diagram

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Embedded Real-time Analysis and Diagnostic (ERAD) - Type 2 1

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Table 4-1. Device Comparison (continued)

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Table 4-1. Device Comparison (continued)

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5 Pin Configuration and Functions

Figure 5-1. 128-pin PDT Thin Quad Flatpack (Top View)

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Figure 5-2. 100-Pin PZ Low-Profile Quad Flatpack (Top View)

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Figure 5-3. 80-Pin PNA Thin Quad Flatpack (Top View)

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Figure 5-4. 64-Pin PM Low-Profile Quad Flatpack (Top View)

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5.2 Pin Attributes

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Table 5-1. Pin Attributes (continued)

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Table 5-1. Pin Attributes (continued)

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Table 5-1. Pin Attributes (continued)

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Table 5-1. Pin Attributes (continued)

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Table 5-1. Pin Attributes (continued)

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Table 5-1. Pin Attributes (continued)

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Table 5-1. Pin Attributes (continued)

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Table 5-1. Pin Attributes (continued)

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