CompEng 361 - Homework 1 - Solutions
CompEng 361 - Homework 1 - Solutions
1. Consider three different processors P1, P2, and P3 executing the same instruction set.
P1 has a 3 GHz clock rate and a CPI of 1.2. P2 has a 2.6 GHz clock rate and a CPI of
1.0. P3 has a 4.25 GHz clock rate and has a CPI of 3.
CPU Cycles / CPU Time = Clock Rate therefore CPU Cycles = Clock Rate ⨉ CPU Time
P1 Cycles = (3.0e9 cycles / sec) ⨉ (10 secs) = 3.0e10 cycles
P2 Cycles = (2.6e9 cycles / sec) ⨉ (10 secs) = 2.6e10 cycles
P3 Cycles = (4.25e9 cycles / sec) ⨉ (10 secs) = 4.25e10 cycles
c. We are trying to reduce the execution time by 30% but this leads to an increase
of 20% in the CPI. What clock rate should we have to get this time reduction?
(CPU Time new) / (CPU Time old) = (Instructions ⨉ CPI new ⨉ Cycle Time new) / (Instructions
⨉ CPI old ⨉ Cycle Time old)
since the instructions are the same in both cases (same program) we have some cancelation
and can reorganize as:
1 / (Cycle Time new) = (CPU Time old) / (CPU Time new) ⨉ (CPI new)/(CPI old) ⨉ 1 / (Cycle
Time old)
Clock Rate new = (CPU Time old) / (CPU Time new) ⨉ (CPI new)/(CPI old) ⨉ (Clock Rate old)
Clock Rate new = (1 / (1 - .3)) ⨉ (1.2 ⨉ CPI old) / ( CPI old) ⨉ (Clock Rate old)
Clock Rate new = 1.43 ⨉ 1.2 ⨉ (Clock Rate old) = 1.71 ⨉ (Clock Rate old)
2. Consider two different implementations of the same instruction set architecture. The
instructions can be divided into four classes according to their CPI (class A, B, C, and
D). P1 with a clock rate of 2.25 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate
of 3.5 GHz and CPIs of 2, 2, 2, and 3. Given a program with a dynamic instruction count
of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50%
class C, and 20% class D,
a. Find the average CPI for each program given that the processor has a clock
cycle time of 1 ns.
b. Assume the compiled programs run on two different processors. If the execution
times on the two processors are the same, how much faster is the clock of the
processor running compiler A’s code versus the clock of the processor running
compiler B’s code?
CPU Time = (Insts A ⨉ CPI A) / Clock Rate A = (Insts B ⨉ CPI B) / Clock Rate B
(Clock Rate A)/(Clock Rate B) = (Insts A ⨉ CPI A) / (Insts B ⨉ CPI B)
= ((1.15e9 insts)(1 cpi)) / ((1.6e9 insts)(1.09 cpi)) = 0.624
c. A new compiler is developed that uses only 6.0E8 instructions and has an
average CPI of 1.1. What is the speedup of using this new compiler versus using
compiler A or B on the original processor?
CPU Time = Instructions ⨉ CPI ⨉ Cycle Time = (6.0e9 insts)(1.1 cycles/inst)(1 ns)
= 0.66 secs
CPU A speedup = 1.15 secs / 0.66 secs = 1.74 speedup
CPU B speedup = 1.75 secs / 0.66 secs = 2.65 speedup
4. Assume a 15 cm diameter wafer has a cost of 13.5 dollarbucks, contains 74 dies, and
has 0.020 defects/cm2. Assume a 21 cm diameter wafer has a cost of 16 dollarbucks,
contains 110 dies, and has 0.031 defects/cm2.
c. If the number of dies per wafer is increased by 10% and the defects per area unit
increases by 15%, find the die area and yield.
For A, we now have 81.4 dies/wafer and area per die = 2.18 cm^2
Yield A = 1/(1 + ((0.023)(2.18/2))^2 = 95.17%
For B, we now have 121 dies/wafer and area per die = 2.86 cm^2
Yield B = 1/(1 + (0.03565)(2.86/2))^2 = 90.53%
d. Assume a fabrication process improves the yield from 0.92 to 0.95. Find the
defects per area unit for each version of the technology given a die area of
200mm2.
5. For the following C statement, what is the corresponding RISC-V assembly code?
Assume that the variables i and j are assigned to registers t1 and t2, respectively.
Assume that the base address of the arrays A and B are in registers t3 and t4,
respectively, and assume that the elements of both arrays are 4-byte words.
B[8] = A[i-j];
6. Translate the following C code to RISC-V. Assume that the variables i and j are
assigned to registers t1 and t2, respectively. Assume that the base address of the
arrays A and B are in registers t3 and t4, respectively, and assume that the elements of
both arrays are 4-byte words.
7. Provide the type and RISC-V assembly language instruction for the following binary
value:
lw a0, 32(sp)
a0 = x10 and sp = x2