VLSI

 Briefly explain working of FPGA with suitable diagram.

FPGA (Field-Programmable Gate Array)

An FPGA is a type of integrated circuit that can be programmed or reprogrammed by the

user to perform a wide range of logical operations. Unlike fixed-function integrated circuits
like ASICs (Application-Specific Integrated Circuits), FPGAs offer flexibility, allowing
designers to implement custom hardware functionality after manufacturing.

Key Features of FPGA

1. Field-Programmable:
o The user can program or reconfigure the FPGA to meet specific application
requirements using a hardware description language (HDL) like VHDL or
Verilog.
2. Gate Array Architecture:
o Contains an array of programmable logic blocks (PLBs), routing resources,
and I/O blocks interconnected to form custom digital circuits.
3. Reconfigurability:
o Can be reprogrammed multiple times, making FPGAs ideal for prototyping,
research, and systems requiring updates or modifications.
4. Parallel Processing:
o Unlike CPUs or GPUs, FPGAs allow parallel execution of tasks, enabling
faster computation for certain applications.

Structure of FPGA

1. Logic Blocks:
o The core of the FPGA, each logic block can perform basic logic functions
such as AND, OR, XOR, and NOT.
o Composed of look-up tables (LUTs), flip-flops, and multiplexers.
2. Routing Resources:
o Programmable interconnects allow connections between logic blocks.
o Routing resources enable flexibility in how logic blocks are wired together.
3. Input/Output (I/O) Blocks:
o Interface between the FPGA and the external environment.
o Configurable for different voltage levels and communication standards.
4. Clocking Resources:
o Dedicated hardware for clock distribution, including phase-locked loops
(PLLs) and clock managers, ensuring synchronized operation across the chip.
5. Configurable Memory:
o Embedded block RAM (BRAM) and distributed RAM for temporary data
storage.
o Often includes memory interfaces for external DRAM or SRAM.
6. Specialized Blocks:
o Some FPGAs include hardware for specialized functions such as:
 Digital Signal Processing (DSP) blocks.
  High-speed transceivers for communication.
 Hard processor cores for hybrid CPU-FPGA systems.

Programming an FPGA

FPGAs are programmed using Hardware Description Languages (HDLs) such as:

 VHDL (Very High-Speed Integrated Circuit Hardware Description Language).

 Verilog.

Applications of FPGA

1. Prototyping and Development:

o Used for testing and validating hardware designs before committing to ASIC
production.
2. Signal Processing:
o Ideal for real-time digital signal processing tasks such as filtering, modulation,
and encoding.
3. High-Performance Computing (HPC):
o Accelerates compute-intensive tasks like machine learning, image processing,
and cryptographic algorithms.
4. Communication Systems:
o Implement protocols, data routing, and encoding/decoding in networks.
5. Embedded Systems:
o Used in hybrid CPU-FPGA systems for tasks requiring specialized hardware
and software integration.
6. Industrial Automation:
o Implement control systems, robotics, and real-time monitoring applications.

Advantages of FPGA

1. Flexibility:
o Reconfigurable for a variety of applications.
2. Parallel Processing:
o Can process multiple operations simultaneously, improving performance.
3. Cost-Effective Prototyping:
 o Eliminates the need for expensive ASIC fabrication during development.
4. Rapid Deployment:
o Faster implementation compared to designing a custom ASIC.
5. Reusability:
o Can be reprogrammed for different applications.

Disadvantages of FPGA

1. Power Consumption:
o Higher than ASICs due to dynamic reconfiguration and general-purpose
routing.
2. Cost:
o Unit cost is higher compared to ASICs for large-scale production.
3. Complex Design:
o Requires expertise in HDL and FPGA toolchains.
4. Speed:
o Slower than ASICs for specific tasks due to general-purpose architecture.

Conclusion

FPGAs provide an excellent balance between flexibility, performance, and development cost,
making them indispensable in modern electronics for prototyping, low-volume production,
and applications requiring custom hardware solutions.
  Compare FPGA and CPLD devices.

Comparison of FPGA and CPLD

FPGA (Field-Programmable Gate Array) and CPLD (Complex Programmable Logic

Device) are both programmable logic devices (PLDs) used for implementing digital circuits.
While they share similarities, they differ significantly in architecture, application, and
capabilities.

Key Differences

Feature FPGA CPLD

Based on a fine-grained architecture Based on a coarse-grained
with a large number of small logic architecture with a smaller
Architecture
blocks connected via programmable number of larger logic blocks
interconnects. (macrocells).
High density with tens of thousands Lower density, typically up to a
Density
to millions of logic gates. few thousand logic gates.
Flash-based (non-volatile),
Configuration SRAM-based (volatile), requiring
retaining configuration after
Technology external configuration on power-up.
power-off.
Highly flexible, ideal for
implementing complex systems with Less flexible, suited for simpler
Programmability
custom logic and specialized logic applications and glue logic.
functionalities.
Typically faster for complex designs
Simpler interconnects result in
due to advanced routing resources
Speed lower propagation delay for
and dedicated hardware (e.g., DSP
small designs.
blocks).
Lower power consumption due to
Power Higher power consumption,
simpler architecture and flash
Consumption especially in SRAM-based FPGAs.
memory.
Higher cost, especially for high- Lower cost, making them ideal
Cost density and high-performance for simpler, low-cost
devices. applications.
Highly scalable, supporting advanced
Limited scalability due to
Scalability features like high-speed transceivers,
architectural constraints.
embedded processors, and DSPs.
Can be reconfigured dynamically
Reconfiguration is static and less
Reconfiguration (runtime reconfiguration supported in
flexible compared to FPGAs.
some models).
Suitable for complex designs such as
Used for simpler tasks like
high-performance computing,
Applications interfacing, glue logic, and small
machine learning, and communication
state machines.
systems.
Requires more advanced tools like Simpler tools like Xilinx ISE or
Development Tools Xilinx Vivado, Intel Quartus, or Atmel’s tools, easier for
similar, along with expertise in HDL. beginners.
When to Use FPGA?

 For complex and high-performance designs requiring parallel processing.

 Applications like signal processing, image recognition, and custom processor
development.
 Situations where reconfigurability is crucial.

When to Use CPLD?

 For simpler designs like interfacing, control logic, or state machines.

 Applications where non-volatility is important, and configuration must persist after
power-off.
 Designs with a tight budget and low power requirements.
  What is CMOS ring oscillator? Explain in brief. (3, 5, 7 stage)

CMOS Ring Oscillator

A CMOS ring oscillator is a simple and commonly used circuit that generates a periodic
oscillating signal without requiring any external clock input. It is constructed using a chain of
CMOS inverters connected in a closed loop, where the output of the last inverter is fed back
to the input of the first inverter.

Structure of a CMOS Ring Oscillator

 It consists of an odd number of CMOS inverters connected in a feedback loop.

 The number of inverters determines the oscillation frequency.
 Each inverter introduces a propagation delay, and the total delay in the loop dictates
the oscillation period.

Diagram

(inverters in odd number with feedback)

Working Principle

1. The odd number of inverters ensures that the circuit has an overall inverting
characteristic (a 180° phase shift).
2. When the output of the last inverter is fed back to the input of the first inverter, the
circuit continuously toggles between high and low logic levels, generating an
oscillating signal.
3. The oscillation frequency is determined by the total delay in the loop:

f=1/(2⋅n⋅tp) where:

o n = Number of inverters in the loop.

o tp = Propagation delay of each inverter.

Key Characteristics

1. Oscillation Frequency:
o Depends on the number of inverters and the propagation delay of each
inverter.
o Higher the number of inverters, lower the frequency.
2. Power Consumption:
o Consumes dynamic power due to constant switching activity.
3. Simplicity:
o Easy to design and widely used as a test structure for evaluating the
performance of CMOS processes.

Applications

1. Frequency Synthesis:
 oUsed in phase-locked loops (PLLs) and clock generation circuits.
2. Process Monitoring:
o Oscillation frequency can provide insights into the propagation delay, which
depends on fabrication parameters like transistor size, temperature, and supply
voltage.
3. Random Number Generation:
o Ring oscillators are used in random number generators by exploiting the jitter
in the oscillation signal.
4. Voltage-Controlled Oscillators (VCOs):
o A variable supply voltage can tune the oscillation frequency for applications
like frequency modulation.

Advantages

 Simple and compact circuit.

 Useful for on-chip clock generation and testing.

Disadvantages

 Limited frequency stability.

 Sensitive to supply voltage and temperature variations.

The CMOS ring oscillator is a fundamental building block in VLSI circuits, offering insights
into device and circuit performance while being versatile in its applications.
  Define following VLSI design concepts – hierarchy, regularity, modularity, locality, Noise
Margin and channel length modulation, Delay- time.

VLSI Design Concepts

1. Hierarchy

 Definition: Hierarchy is the process of dividing a large, complex system into smaller,
more manageable sub-systems or modules.

2. Regularity

 Definition: Regularity refers to the repeated use of uniform structures or patterns in

the design.

3. Modularity

 Definition: Modularity is the design principle where a system is divided into

independent, interchangeable modules.

4. Locality

 Definition: Locality refers to the principle of placing related components or

subsystems physically close to each other to minimize interconnect delay and power
consumption.

5. Noise Margin

 Definition: Noise margin is the maximum noise voltage that can be added to a signal
without causing an error in the output. It ensures the reliability of digital circuits.

6. Channel Length Modulation (CLM)

 Definition: Channel length modulation occurs in MOSFETs when the effective 7.

Delay-Time

 Definition: Delay-time is the time taken by a signal to propagate through a circuit or

from input to output.
 Types:
1. Propagation Delay (tpt_p): Time taken for the output to reach 50% of its
final value after the input changes.
2. Rise Time (trt_r): Time taken for a signal to transition from 10% to 90% of
its maximum value.
3. Fall Time (tft_f): Time taken for a signal to transition from 90% to 10% of its
maximum value.
  Derive: VIH, VIL, VOL, VOH, VTH, NML, NMH
 Compare Semi-custom and Full custom VLSI design style

Comparison of Semi-Custom and Full-Custom VLSI Design Styles

Aspect Semi-Custom Design Full-Custom Design

A design style where pre-designed and A design style where every
pre-verified components (e.g., standard element, including logic gates
Definition
cells, macros) are used along with custom and layouts, is designed from
design. scratch.
Limited flexibility as pre-designed cells High flexibility; designer has full
Flexibility
constrain customization. control over every detail.
Requires significantly more time
Requires less time and effort since
Design Effort and effort due to the need to
standard libraries are used.
create all components.
Moderate performance, depending on the High performance, as the design
Performance quality of the standard cells and their can be optimized for specific
placement/routing. applications.
Lower, as the design can be
Power Generally higher due to suboptimal
highly optimized for power
Consumption layouts and routing overhead.
efficiency.
Higher development cost due to
Lower development cost since it uses pre-
Cost the need for extensive design and
designed components and tools.
verification.
Time-to- Shorter time-to-market due to the reuse of Longer time-to-market because
Market pre-verified components. of the detailed design process.
Suitable for moderately complex designs Suitable for highly complex or
Design
like application-specific integrated circuits performance-critical designs like
Complexity
(ASICs). microprocessors or GPUs.
Relies heavily on intellectual property Limited reuse; designs are
Reuse of IP
(IP) blocks and libraries. typically application-specific.
Used in designs where time and cost are Used for performance-critical
Applications critical, like consumer electronics or and high-volume products, like
industrial controllers. CPUs or GPUs.

Summary of Key Points

 Semi-Custom Design:
o Balances time, cost, and performance.
o Primarily uses standard cells, IP blocks, and predefined macros.
o Ideal for ASICs and applications where faster development is necessary.
 Full-Custom Design:
o Focuses on maximum performance, power efficiency, and area optimization.
o Every component, including the layout, is designed manually for precision.
o Best suited for designs where performance and efficiency are critical, like
high-end processors.
  Discuss VLSI design flow in brief
 Y- Chart (7 marks)
 Explain LOCOS technique used for device isolation and state its advantages over the Etched
Field Oxidation technique.
 Fabrication of nMOS
 What is reliability of the chip? List the 4 major causes for chip reliability problems

Reliability of a Chip

Chip reliability refers to the ability of a semiconductor device to perform its intended
function accurately over its expected lifetime under specified operating conditions. Reliable
chips minimize failures, ensuring consistent performance, safety, and functionality in various
applications, including consumer electronics, automotive systems, and aerospace.

4 Major Causes for Chip Reliability Problems

1. Thermal Issues
o Cause: Excessive heat generation due to high power density, poor thermal
management, or inadequate cooling.
2. Electrical Stress
o Cause: Overvoltage, electrostatic discharge (ESD), or high electric fields
during operation.
3. Environmental Factors
o Cause: External conditions like humidity, radiation, and contamination.
4. Process and Material Defects
o Cause: Imperfections during fabrication, such as lithography errors, material
impurities, or defective packaging.

Other Contributing Factors

 Aging Effects:
o Bias Temperature Instability (BTI): Degradation of the transistor threshold
voltage over time due to prolonged stress.
o Time-Dependent Dielectric Breakdown (TDDB): Gradual breakdown of
gate oxides under constant electric fields.
 Mechanical Stress:
o Poor chip-packaging integration leading to physical damage under operational
stress.
  What is substrate bias effect? Explain the substrate bias effect in nMOS and pMOS devices.

Substrate Bias Effect

The substrate bias effect, also known as the body effect, is a phenomenon in MOSFETs
where the threshold voltage (VTHV_{TH}) of the device changes due to a difference in
potential between the substrate (body) and the source terminal. This effect arises because the
source-substrate voltage (VSBV_{SB}) modifies the depletion region and, consequently, the
surface potential.

Key Insight:

 A larger VSB increases VTH, making it harder to turn the MOSFET on.

Substrate Bias Effect in nMOS

1. Structure:
o In an nMOS transistor, the substrate is typically p-type, and the source and
drain are n-type regions.
2. Biasing:
o If the substrate (p-type) is connected to a voltage lower than the source (n-
type), VSB>0V_{SB} > 0.
o This increases the depletion region width and the effective threshold voltage.
3. Impact:
o A higher threshold voltage means the device requires a larger gate-to-source
voltage (VGSV_{GS}) to turn on.
o Reduced drive strength and slower switching speed.

Substrate Bias Effect in pMOS

1. Structure:
o In a pMOS transistor, the substrate is typically n-type, and the source and
drain are p-type regions.
2. Biasing:
o If the substrate (n-type) is connected to a voltage higher than the source (p-
type), VSB>0V_{SB} > 0.
o This increases the depletion region width and the effective threshold voltage
(in magnitude).

o A higher ∣VTH∣|V_{TH}| means the device requires a larger ∣VGS∣|V_{GS}|

3. Impact:

(negative) to turn on.

o Similar effects as in nMOS: reduced drive strength and slower operation.

Comparison of Body Effect in nMOS and pMOS

Aspect nMOS pMOS

Substrate Type p-type n-type
 Aspect nMOS pMOS
Bias Condition VSB> VSB>0
VTH increases
Threshold Voltage Change (
with VSB.
Requires higher
Performance Impact Requires higher (
VGS to turn on.
  Switching Power Dissipation of CMOS Inverters.

Switching Power Dissipation in a CMOS Inverter

Switching power dissipation occurs in a CMOS inverter due to the charging and discharging
of the load capacitance (CLC_L) during transitions between logic levels (from HIGH to
LOW and vice versa). It is the dominant form of power dissipation in CMOS circuits under
typical operating conditions.

Mechanism of Switching Power Dissipation

1. Charging Phase:
o When the input switches from LOW to HIGH, the NMOS transistor turns ON,
and the PMOS transistor turns OFF.
o The load capacitor (CLC_L) is charged through the PMOS transistor to
VDDV_{DD}, consuming energy from the power supply.
2. Discharging Phase:
o When the input switches from HIGH to LOW, the PMOS transistor turns ON,
and the NMOS transistor turns OFF.
o The load capacitor discharges through the NMOS transistor to ground.

Energy Dissipation During Switching

 Energy Dissipated per Transition: The energy drawn from the power supply during
a charging event is:

Echarge=CLVDD2E_{charge} = C_L V_{DD}^2

o Half of this energy is stored in the capacitor (Estored=12CLVDD2E_{stored}

= \frac{1}{2} C_L V_{DD}^2).
o The other half is dissipated as heat in the PMOS transistor.
 During discharging, the stored energy in CLC_L is dissipated as heat in the NMOS
transistor:

Edischarge=12CLVDD2E_{discharge} = \frac{1}{2} C_L V_{DD}^2

 Total Energy Dissipation per Cycle: For a full charge-discharge cycle:

Etotal=Echarge+Edischarge=CLVDD2E_{total} = E_{charge} + E_{discharge} =

C_L V_{DD}^2

Switching Power Dissipation Expression

If the inverter operates at a switching frequency (ff) and a fraction of the clock cycle where
switching occurs is the activity factor (α\alpha), the switching power dissipation is:

Pswitching=αfCLVDD2P_{switching} = \alpha f C_L V_{DD}^2

Where:
  PswitchingP_{switching}: Switching power dissipation,
 α\alpha: Activity factor (fraction of clock cycles during which switching occurs,
typically α≤1\alpha \leq 1),
 ff: Clock frequency,
 CLC_L: Load capacitance,
 VDDV_{DD}: Supply voltage.

Key Insights

1. Proportional to Frequency: Switching power increases linearly with the clock

frequency. Higher operational frequencies lead to more frequent charging and
discharging of the load capacitance.
2. Proportional to VDD2V_{DD}^2: Switching power is highly sensitive to the supply
voltage. Reducing VDDV_{DD} significantly reduces switching power, which is a
critical factor in low-power design.
3. Impact of Activity Factor: The activity factor (α\alpha) determines how often a node
switches. Nodes with low activity factors dissipate less power.

Advantages of CMOS Inverters Regarding Switching Power

 No Static Power Dissipation: In ideal CMOS circuits, static power dissipation is

negligible because there is no direct current path between VDDV_{DD} and ground
during steady states.
 Low Power at Low Frequencies: At low frequencies or low switching activity,
switching power dissipation is minimal.
Packaging Technologies Used for VLSI Chips

Below are the main packaging technologies used for VLSI chips:

1. Dual In-line Package (DIP)

2. Surface Mount Device (SMD)

3. Ball Grid Array (BGA)

4. Chip-on-Board (COB)

5. Package-on-Package (PoP)

6. Flip-Chip

7. Wire Bonding

8. Wafer-Level Packaging (WLP)

9. Through-Silicon Via (TSV)

10. System-in-Package (SiP)

  Write short note on Complimentary pass transistor logic (CPL)

Complementary Pass Transistor Logic (CPL)

Complementary Pass Transistor Logic (CPL) is a design methodology in digital circuits

that utilizes pass transistors instead of traditional pull-up and pull-down networks (as in
CMOS logic) for implementing logic functions. CPL is known for its high speed and efficient
implementation of certain logic functions, especially in arithmetic circuits.

Key Features of CPL

1. Pass Transistor Logic:

o CPL circuits use NMOS and PMOS transistors as switches to pass logic
signals from input to output.
o Logic levels are transmitted directly through the transistors without relying on
full voltage swings.
2. Complementary Inputs:
o CPL requires both true and complement forms of the input signals to ensure
proper operation.
3. Differential Signaling:
o CPL outputs are usually generated in pairs (true and complement), reducing
noise sensitivity and improving signal integrity.
4. Static CMOS Inverter:
o A CMOS inverter is often added at the output stage to restore the full voltage
swing and ensure compatibility with subsequent stages.

Advantages of CPL

1. High Speed:
o Pass transistor logic results in faster switching speeds due to the reduced
number of transistors in the critical path.
2. Lower Power Consumption:
o CPL circuits consume less power in certain configurations because the
dynamic power dissipation is reduced.
3. Compact Design:
o CPL uses fewer transistors than traditional CMOS logic for implementing
complex functions, leading to smaller chip area.
4. Efficient Arithmetic Functions:
o Well-suited for implementing arithmetic circuits such as adders and
multiplexers.

Disadvantages of CPL

1. Voltage Degradation:
o Pass transistors may not pass the full voltage levels (VDDV_{DD} or 00),
leading to signal degradation and reduced noise margins.
2. Complexity in Complementary Signals:
o Requires complementary inputs, increasing the overhead in circuit design.
3. Leakage Current:
 o Increased leakage due to the use of pass transistors can impact low-power
designs.
4. Static Power Consumption:
o More static power dissipation compared to pure CMOS designs, particularly in
low-power applications.

Applications of CPL

 Arithmetic logic units (ALUs)

 Multiplexers and demultiplexers
 XOR and XNOR gates
 Adders and subtractors in digital arithmetic circuits
  What is the need of Scaling? Mention the merits and demerits of constant voltage scaling.
 Explain Gradual Channel Approximation (GCA), with help of that derive current voltage
equations for nMOS transistor.

Gradual Channel Approximation (GCA)

The Gradual Channel Approximation (GCA) is a simplification used in the analysis of

MOSFETs to derive their current-voltage (I−V) characteristics. It assumes that the electric
field along the channel (longitudinal field) varies slowly compared to the electric field
perpendicular to the channel (vertical field). This assumption simplifies the complex behavior
of the MOSFET channel into a manageable mathematical framework.

Key Concepts of GCA

1. Electric Fields in a MOSFET:

o The MOSFET channel has two types of electric fields:
 Vertical Electric Field (EyE_y): Created by the gate-to-channel
voltage (VGSV_{GS}).
 Longitudinal Electric Field (ExE_x): Created by the drain-to-source
voltage (VDSV_{DS}).
o In GCA, EyE_y (vertical) is much stronger than ExE_x (longitudinal).
2. Gradual Change Assumption:
o The channel potential (V(x)V(x)) varies gradually from the source to the drain.
o This allows the channel to be treated as a series of infinitesimally small MOS
capacitors.
3. Mathematical Formulation:
o The GCA assumes that the vertical electric field dominates the device
behavior, which simplifies solving the Poisson equation for charge
distribution.

Steps in Applying GCA

1. Charge Distribution in the Channel:

o The charge density Q(x)Q(x) at a point along the channel is proportional to the
gate voltage and inversely proportional to the channel voltage:
Q(x)=−Cox[VGS−V(x)−VTH]Q(x) = -C_{ox} \left[ V_{GS} - V(x) -
V_{TH} \right] where:
 CoxC_{ox}: Gate oxide capacitance.
 VGSV_{GS}: Gate-to-source voltage.
 V(x)V(x): Potential at a point xx along the channel.
 VTHV_{TH}: Threshold voltage.
2. Current Flow:
o The current IDI_D is related to the drift of charge carriers:
ID=Wμ∣Q(x)∣dV(x)dxI_D = W \mu \left| Q(x) \right| \frac{dV(x)}{dx} where:
 WW: Width of the transistor.
 μ\mu: Mobility of carriers.
3. Integration:
 o By integrating IDI_D from the source (x=0,V(x)=0x = 0, V(x) = 0) to the
drain (x=L,V(x)=VDSx = L, V(x) = V_{DS}), the current-voltage relationship
is derived:
 Linear Region (VDS<VGS−VTHV_{DS} < V_{GS} - V_{TH}):
ID=μCoxWL[(VGS−VTH)VDS−12VDS2]I_D = \mu C_{ox} \
frac{W}{L} \left[ (V_{GS} - V_{TH})V_{DS} - \frac{1}{2}
V_{DS}^2 \right]
 Saturation Region (VDS≥VGS−VTHV_{DS} \geq V_{GS} -
V_{TH}): ID=μCoxW2L(VGS−VTH)2I_D = \frac{\mu C_{ox} W}
{2L} (V_{GS} - V_{TH})^2

Assumptions in GCA

1. Long-Channel Device:
o GCA is valid for long-channel devices where the channel length (LL) is
significantly larger than the depletion region width.
2. Weak Longitudinal Field:
o The longitudinal electric field is small compared to the vertical field.
3. Uniform Mobility:
o Carrier mobility (μ\mu) is constant and does not depend on the electric field.

Advantages of GCA

1. Simplifies the analysis of MOSFET behavior, enabling analytical solutions for I−VI-
V characteristics.
2. Provides accurate results for long-channel MOSFETs under most operating
conditions.

Limitations of GCA

1. Short-Channel Effects:
o GCA becomes less accurate for short-channel MOSFETs where ExE_x is
comparable to EyE_y.
o Modern submicron devices experience velocity saturation, drain-induced
barrier lowering (DIBL), and other effects that GCA does not account for.
2. Non-Uniform Mobility:
o Variations in carrier mobility due to scattering or high electric fields are not
considered.

Applications of GCA

 Used in traditional MOSFET models for circuit simulation and understanding

transistor operation.
 Forms the basis for understanding regions of operation (linear, saturation) in
MOSFETs.

Conclusion
The Gradual Channel Approximation is a cornerstone of MOSFET modeling for long-
channel devices, providing essential insights into their behavior. However, for advanced
short-channel devices in modern VLSI, more sophisticated models are needed to capture
additional effects.

 Explain the behaviour of MOS device under external bias with the help of energy band
diagrams and derive the relationship for maximum depletion width at oxide-semiconductor
surface. (3 times)
 Draw and discuss: The circuit diagram of domino CMOS logic gate. (3 times)
 Voltage Transfer Characteristics of resistive load inverter and CMOS inverter (also NML and
NMH explaination)
 Circuits:
o SR latch using NAND

o SR latch using NOR

o Clocked SR latch using NOR

o D latch (with 2 inverter and 2 CMOS TG)

o 2 input NAND-NOR

o 2 input MUX
 Stick diagram & Euler approach
  Draw circuit of CMOS inverter. Derive VIH , VIL ,VOL and VOH for CMOS inverter.

CMOS Inverter Circuit

A CMOS inverter is the simplest logic gate built using CMOS technology. It consists of two
complementary MOSFETs:

 A p-channel MOSFET (PMOS) at the top (connected to VDDV_{DD}).

 An n-channel MOSFET (NMOS) at the bottom (connected to GNDGND).

The input is connected to the gates of both transistors, and the output is taken from the
connection between the drain terminals of the two transistors.

Circuit Diagram

VDD (Supply Voltage)

|
PMOS
|
|---- Output (Vout)
|
NMOS
|
GND (Ground)

Key Parameters to Derive

1. VOHV_{OH}: Maximum output voltage (Logic High).

2. VOLV_{OL}: Minimum output voltage (Logic Low).
3. VIHV_{IH}: Input voltage at which the output starts transitioning from high to low.
4. VILV_{IL}: Input voltage at which the output starts transitioning from low to high.

Operation of CMOS Inverter

1. Input Low (Vin=0V_{in} = 0):

o The NMOS transistor is OFF, and the PMOS transistor is ON.
o The output is pulled up to VDDV_{DD}.
o Vout=VOH=VDDV_{out} = V_{OH} = V_{DD}.
2. Input High (Vin=VDDV_{in} = V_{DD}):
o The NMOS transistor is ON, and the PMOS transistor is OFF.
o The output is pulled down to GNDGND.
o Vout=VOL=0V_{out} = V_{OL} = 0.
3. Transition Region (VIL<Vin<VIHV_{IL} < V_{in} < V_{IH}):
o Both NMOS and PMOS are partially ON, and the output is in the process of
transitioning between VOLV_{OL} and VOHV_{OH}.
Expressions for VOH,VOL,VIH,VILV_{OH}, V_{OL}, V_{IH}, V_{IL}

1. VOHV_{OH} (Logic High Output Voltage):

The output voltage is high when Vin=0V_{in} = 0, and the PMOS is fully ON while NMOS
is OFF.

 VOH=VDDV_{OH} = V_{DD}.

2. VOLV_{OL} (Logic Low Output Voltage):

The output voltage is low when Vin=VDDV_{in} = V_{DD}, and the NMOS is fully ON
while PMOS is OFF.

 VOL=0V_{OL} = 0.

3. VIHV_{IH} (High Input Voltage Threshold):

VIHV_{IH} is the input voltage at which the output starts transitioning from high
(VOHV_{OH}) to low (VOLV_{OL}).

At this point:

 The NMOS begins to conduct significantly, and the PMOS starts to turn OFF.
 Assuming equal mobility (μn=μp)(\mu_n = \mu_p) and threshold voltages
(Vtn=∣Vtp∣)(V_{tn} = |V_{tp}|), VIHV_{IH} can be approximated as:

VIH≈VDD−∣Vtp∣.V_{IH} \approx V_{DD} - |V_{tp}|.

4. VILV_{IL} (Low Input Voltage Threshold):

VILV_{IL} is the input voltage at which the output starts transitioning from low
(VOLV_{OL}) to high (VOHV_{OH}).

At this point:

 The PMOS begins to conduct significantly, and the NMOS starts to turn OFF.
 Similarly, under balanced conditions:

VIL≈Vtn.V_{IL} \approx V_{tn}.

Resistive Load Inverter Circuit

The circuit of a resistive load inverter consists of:

1. Resistive Load (RLR_L) connected between the supply voltage (VDDV_{DD}) and
the output.
2. NMOS Transistor with:
o Gate connected to the input (VinV_{in}),
o Drain connected to the output (VoutV_{out}),
o Source connected to ground.

Here’s the schematic:

VDD
|
R_L
|
+--- Vout
|
NMOS
|
GND

Key Points to Derive Parameters

 When the NMOS is OFF, Vout=VDDV_{out} = V_{DD} (logic HIGH,

VOHV_{OH}).
 When the NMOS is ON, the output voltage depends on the current through the load
resistor (RLR_L) and the NMOS transistor's operating region.

1. VOH (Output High Voltage)

 VOH is the maximum output voltage when the NMOS is OFF.

 In this case, there is no current through RL, so: VOH=VDD

2. VOL (Output Low Voltage)

 VOL is the output voltage when the NMOS is ON, and the transistor operates in
saturation or linear region.

3. VIH (Input High Voltage)

 VIH is the maximum input voltage at which the inverter still recognizes the input as
LOW.
 It is determined when the NMOS just begins to turn ON (VGS=Vin=Vth).

4. VIL (Input Low Voltage)

 VIL is the minimum input voltage at which the inverter starts transitioning to LOW
output.
  It is found when the NMOS transitions from linear to saturation.

Simplifications

For practical derivations, additional assumptions (like neglecting body effect, or assuming
Vin equals VGS may be applied based on operating conditions. If you'd like, I can work out
specific numerical examples. Let me know!