Register Transfer

Language and
Microoperations
Unit-2
 Contents:
1. Register Transfer Language
2. Register Transfer
3. Bus and Memory Transfers
4. Arithmetic Microoperations
5. Logic Microoperations
6. Shift Microoperations
7. Arithmetic Logic Shift Unit
8. Instruction codes
9. Computer Registers
10. Computer Instructions
11. Instruction Cycle
12. Memory-Reference Instructions
13. Input-Output and Interrupt
14. Stack Organization
15. Instruction Formats
16. Addressing Modes
17. Data Transfer and Manipulation
18. Program Control
19. Reduced Instruction Set Computer (RISC)
1. Register Transfer Language
SIMPLE DIGITAL SYSTEMS
Combinational and sequential circuits can be used to create
simple digital systems.
These are the low-level building blocks of a digital computer.
Simple digital systems are frequently characterized in terms
of
the registers they contain, and
the operations that they perform.

Typically,
Operations are performed on the data in the registers.
Information is passed between registers.
Microoperations(1)
The operations on the data in registers are called
microoperations.
The functions built into registers are examples of
microoperations
Shift
Load
Clear
Increment
…
Microoperations (2)
An elementary operation performed (during one clock
pulse), on the information stored in one or more
registers.

Regist AL 1 clock
ers U cycle
(R) (f)

R ← f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …
Organization of a Digital System

The internal organization of a computer is defined as

1. Set of registers and their functions.
2. Microoperations (Set of allowable microoperations
provided by the organization of the computer).
3. Control signals that initiate the sequence of
microoperations (to perform the functions).
Register Transfer Level
Viewing a computer, or any digital system, in this
way is called the register transfer level.
This is because we’re focusing on
The system’s registers
The data transformations in them, and
The data transfers between them.
Register Transfer Language
Rather than specifying a digital system in words, a specific
notation is used called register transfer language.
For any function of the computer, the register transfer
language can be used to describe the (sequence of)
microoperations.
Register transfer language
A symbolic language.
A convenient tool for describing the internal organization of digital
computers.
Can also be used to facilitate the design process of digital systems.
2. Register Transfer
Registers are designated by capital letters, sometimes followed by
numbers (e.g., A, R13, IR)
Often the names indicate function:
MAR- memory address register
PC - program counter
IR - instruction register

Registers and their contents can be viewed and represented in

various ways.
A register can be viewed as a single entity:

MA
Registers may also be represented showing
R the bits of data they contain
Register Transfer contd..
Designation of a
register
- a register
- portion of a
register
Common - a bit
waysof of
a drawing the block diagram of a
register Showing individual
Regist register
bits
er
R
7 6 5 4 3 2
1 1 0 1 0
5 1 8 7 0
R 5 PC( PC(
Numbering of
2 Subfiel H) L)
bits ds
Register Transfer contd..
Copying the contents of one register to another is a
register transfer.
A register transfer is indicated as
R2 ← R1

In this case the contents of register R1 are copied (loaded) into

register R2.
A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse.
Note that this is a non-destructive; i.e. the contents of R1 are
not altered by copying (loading) them to R2.
Register Transfer contd..
A register transfer such as

R3 ← R5

Implies that the digital system has

The data lines from the source register (R5) to the destination
register (R3).
Parallel load in the destination register (R3).
Control lines to perform the action.
Register Transfer contd..
Often actions need to only occur if a certain condition is true
This is similar to an “if” statement in a programming language.
In digital systems, this is often done via a control signal, called
a control function.
If the signal P is 1, the action takes place
This is represented as:
P: R2 ← R1
Which means “if P = 1, then load the contents of register R1 into
register R2”, i.e., if (P = 1) then (R2 ← R1).
Hardware Implementation Of Controlled Transfers
Implementation of controlled
transfer
P: R2 ←
R1
Block Contr P Loa
R Clo
ol d
diagram Circuit
2 n ck
R
1

Timing t t
+
diagram Cloc 1
k
Loa
d Transfer occurs
here

The same clock controls the circuits that generate the control function and the
destination register.
Registers are assumed to use positive-edge-triggered flip-flops.
Simultaneous Operations
If two or more operations are to occur simultaneously, they
are separated with commas.
P: R3 ← R5,, MAR ← IR
Here, if the control function P = 1, load the contents of R5 into
R3, and at the same time (clock), load the contents of register
IR into register MAR.
Basic Symbols For Register Transfers

Symbol Description
s
Capital letters Examples
Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register
R2(0-7), R2(L)
Arrow ← Denotes transfer of information R2 ←
R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A←
B, B ← A
Connecting Registers
In a digital system with many registers, it is impractical to
have data and control lines to directly allow each register to
be loaded with the contents of every possible other
registers.
To completely connect n registers  n(n-1) lines.
This is not a realistic approach to use in a large digital system

Instead, take a different approach

Have one centralized set of circuits for data transfer .bus
Have control circuits to select which register is the source,
and which is the destination.
3. Bus and Bus Transfer
Bus is a path(of a group of wires) over which information is
transferred, from any of several sources to any of several
From a register to bus: BUS ←
destinations.
R Register Register Register Register
A B C D

Bus
lines

Register Register Register Register

1A 2 3 4 B 2
1 3 4 1C 2 3 4 1D 2 3 4

B1 C 1 D 1 B2 C 2 D 2 B3 C 3 D 3 B4 C 4 D 4

0 0 0 0
4 4 4 4
MU
x1 MU
x1 MU
x1 MU
x1
X X X X
x
sele
cty

4-line
bus
Bus and Memory Transfers
Register Register Register Register
A B C D

Bus

. Register
lines
Register Register Register
D 1
3 2 C 1
3 2 B 1
3 2 A 1
3 2
0 0 0 0
D3 D 2 D 1 D 0 C3 C2 C1 C0 B3 B 2 B 1 B 0 A3 A2 A1 A0

D 3 C 3 B3 A 3 D 2 C 2 B2 A 2 D 1 C 1 B1 A 1 D 0 C 0 B0 A 0

3 2 1 3 2 1 3 2 1
3 2 1 S0
S0 0 S0 0 S0 0
0
MUX MUX MUX MUX S1
S1 S1 S1
3 2 1 0

4-Line Common Bus

Bus and Memory Transfers: Three-State Bus Buffers
A bus system can be constructed with three-state buffer
gates instead of multiplexers.
A three-state buffer is a digital circuit that exhibits three
states: logic-0, logic-1, and high-impedance (Hi-Z)

Output Y=A if C=1

High-impedance if
C=0

Control input C

Normal input A Output B

Three-State Buffer
Bus and Memory Transfers: Three-State Bus Buffers cont.

C=1

Buffer
A B A B

C=0

Open
A A Circuit
B B
Bus and Memory Transfers: Three-State Bus Buffers cont.

S1 0
Selec Bus line for bit 0
t S0 1
2×4 A0
Decoder 2
Enable E
3

B0

C0

Bus line with three-state

buffer (replaces MUX0 in the D0
previous diagram)
Bus Transfer In RTL
Depending on whether the bus is to be mentioned explicitly
or not, register transfer can be indicated as either

R2 ←
or R1

BUS ← R1, R2 ←
BUS
In the former case the bus is implicit, but in the latter, it is
explicitly indicated
Memory (RAM)
Memory (RAM) can be thought as a sequential circuits
containing some number of registers
These registers hold the words of memory
Each of the r registers is indicated by an address
These addresses range from 0 to r-1
Each register (word) can hold n bits of data
Assume the RAM contains r = 2k words. It needs thedata input
following
lines
n data input lines n

n data output lines address

lines k
k address lines RA
Rea
A Read control line d M
Wri uni
A Write control line te
t n
data output
lines
Bus and Memory Transfers: Memory Transfer
Memory read : Transfer from memory
Memory write : Transfer to memory
Data being read or written is called a memory word (called
M).
It is necessary to specify the address of M when writing
/reading memory.
This is done by enclosing the address in square brackets
following the letter M.
Memory Read
To read a value from a location in memory and load it into
a register, the register transfer language notation looks
like this: R1 ←
M[MAR]]

This causes the following to occur

The contents of the MAR get sent to the memory address lines.
A Read (= 1) gets sent to the memory unit.
The contents of the specified address are put on the memory’s output
data lines.
These values are sent over the bus to be loaded into register R1.
Memory Write

To write a value from a register to a location in memory looks

like this in register transfer language:

M[MAR] ←
R1
This causes the following to occur
The contents of the MAR get sent to the memory address lines.
A Write (= 1) gets sent to the memory unit.
The values in register R1 get sent over the bus to the data input lines of
the memory.
The values get loaded into the specified address in the memory.
Summary Of R. Transfer Microoperations
A← B Transfer content of reg. B into reg. A
AR ← DR(AD) Transfer content of AD portion of reg. DR into reg.
AR
A ← constant Transfer a binary constant into reg. A
ABUS ← R1, Transfer content of R1 into bus A and, at the same
time,
R2 ← ABUS Transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR ← M Memory read operation: transfers content of memory
word
specified by AR into DR
M ← DR Memory write operation: transfers content of DR into
memory
word specified by AR
4. Arithmetic Microoperations
The microoperations most often encountered in digital
computers are classified into four categories:
Register transfer microoperations
Arithmetic microoperations (on numeric data stored in
the registers)
Logic microoperations (bit manipulations on non-numeric
data)
Shift microoperations
Arithmetic Microoperations cont.
The basic arithmetic microoperations are:
addition
subtraction
increment
decrement
shift
Addition Microoperation:

R3 R1+R2

Subtraction Microoperation:

R3 R1-R2 (or)
1’s complement
R3 R1+ R2 +1
Arithmetic Microoperations cont
One’s Complement Microoperation:

R2 R2

Two’s Complement Microoperation:

R2 R2+1

Increment Microoperation:

R2 R2+1

Decrement Microoperation:

R2 R2-1
Summary of Typical Arithmetic Micro-Operations
Operations Description

R3 ← R1 + R2 Contents of R1 plus R2 transferred to

R3
R3 ← R1 - R2 Contents of R1 minus R2 transferred
to R3
R2 ← R2 Complement the contents of R2
R2 ← R2+ 1 2's complement the contents of R2
(negate)
R3 ← R1 + R2+ 1 subtraction
R1 ← R1 + 1 Increment
R1 ← R1 - 1 Decrement
Arithmetic Microoperations: Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0

4-bit binary adder (connection of

FAs)
Arithmetic
. Microoperations: Binary Adder-
Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

4-bit adder-subtractor
Arithmetic Microoperations : Binary Adder-Subtractor
For unsigned numbers, this gives A – B if A≥B or the 2’s
complement of (B – A) if A < B.
(example: 3 – 5 = -2= 1110)
For signed numbers, the result is A – B provided that there is
no overflow. (example : -3 – 5= -8)
1101
1011 +
1000 C3 1, if overflow
V=
C4 0, if no
overflow
Overflow detector for signed
numbers
Arithmetic Microoperations Binary Incrementer
A3 A2 A1 A0 1

x y x y x y x y

HA HA HA HA

C S C S C S C S

C4 S3 S2 S1 S0

4-bit Binary Incrementer

Binary Incrementer can also be implemented using a counter.

A binary decrementer can be implemented by adding 1111 to
the desired register each time.
Arithmetic Microoperations Arithmetic Circuit

This circuit performs seven distinct arithmetic operations

and the basic component of it is the parallel adder.
The output of the binary adder is calculated from the
following arithmetic sum:

D = A + Y + Cin
Arithmetic Microoperations : Arithmetic Circuit cont.
A3 A2 A1 A0
1 0 B B S1 S0 1 0 B B S1 S0 1 0 B B S1 S0 1 0 B B S1 S0
3 3 2 2 1 1 0 0

3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0

4×1 MUX 4×1 MUX 4×1

Figure A
4×1
MUX MUX

Y3 X3 Y2 X2 Y1 X1 Y0 X0
C3 C2 C1
FA FA FA FA Ci
n

Cout D3 D2 D1 D0

4-bit Arithmetic Circuit

Arithmetic Circuit
C
S
iS
1
n
0
A X C
0 S
S
1
4 0 0
FC
D
0
B 00 Y
0 1
2
3
Mx 0
A1
A U1 X C
1 S
1X
S 4 1
Y
1
FC
D
1
B 00
1 x
1 2M 1
A2
3
A
2 S
U1 X
2
C
2 D
1 4 FC
00 X
S 2
B Y
2 x
1
3 M A3
2 2

A
3
U1
S 4
X
3
C
3 D
B 00 X
S
1
Y FC 3

2 x
1M
3
3
3
A4 Co
0 1 U1 ut

X
S1 S0 Cin Y Output Microoperation
0 0 0 B D = A + B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D = ATransfer A
1 0 1 0 D = A + 1 Increment A
1 1 0 1 D = A - 1 Decrement A
1 1 1 1 D = ATransfer A
5. Logic Microoperations
Specify binary operations on the strings of bits in registers
Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data.
useful for bit manipulations on binary data .
useful for making logical decisions based on the bit value.
There are,16 different logic functions that can be defined over two
binary input variables

A B F0 F1 F2 … F13 F14
F015 0 0 0 0 … 1
1 1
0 1 0 0 0 … 1
1 1
1 0 only
However, most systems 0 0implement
1 … four of these
AND (∧), OR (∨), 0
XOR 1 1
(⊕), Complement/NOT
1 1 0 1 0 …
The others can be created from combination of these.
1 0 1
 List of Logic Microoperations
- 16 different logic operations with 2 binary variables.

x 00 Boolea Micro-
Na
1 1 n Operatio
me
y 01 Functi ns
0 1 0 0 0 0 on F0 = 0 F←0 Clear
0001 F1 = xy F ← A ∧ B AND
0010 F2 = xy' F ← A ∧ B’
0011 F3 = x F←A
Transfer A
0100 F4 = x'y F ← A’∧ B
0101 F5 = y F←B
Transfer B
0110 F6 = x ⊕ y F←A⊕B Exclusive-
OR
0111 F7 = x + y F←A∨B OR
1000 F8 = (x + y)' F ← (A ∨ B)’ NOR
1001 F9 = (x ⊕ y)' F ← (A ⊕ B)’ Exclusive-
NOR
1010 F10 = y' F ← B’
Complement B
1011 F11 = x + y' F←A∨B
Truth tables for1 16
1 0 functions
0 F12 =ofx'2 variables
F← A’ the corresponding 16 logic micro-
and
Complement A
Logic Microoperations

OR Microoperation
Symbol: ∨, +
Gate:

Example: 1001102 ∨ 10101102 = 11101102

OR
OR
P+Q: R1 R2+R3, R4 R5 ∨R6

AD
D
 Logic Microoperations

AND Microoperation
Symbol: ∧
Gate:
Example: 1001102 ∧ 10101102 = 00001102
 Logic Microoperations

Complement (NOT) Microoperation

−
Symbol:
Gate:
Example: 10101102 = 01010012
 Logic Microoperations

XOR (Exclusive-OR) Microoperation

Symbol: ⊕
Gate:
Example: 1001102 ⊕ 10101102 = 11100002
Hardware Implementation Of Logic Microoperations
Ai
0
Bi

1
4X Fi
MU
1
2 X

3 Sele
ct
S1
S0

Function
S1 table
Outp μ-
S00 0 Fut= A ∧ B AND
operation
0 1 F=A ∨ B OR
1 0 F=A⊕B XOR
1 1 F = A’
Complement
Applications Of Logic Microoperations
Logic microoperations can be used to manipulate individual bits
or a portions of a word in a register
Consider the data in a register A. In another register, B, is bit
data that will be used to modify the contents of A

Selective-set A← A+B
Selective-complement A← A⊕B
Selective-clear A ← A • B’
Mask (Delete) A← A•B
Clear A← A⊕B
Insert A ← (A • B) + C
Compare A← A⊕B
...
Selective Set

In a selective set operation, the bit pattern in B is used to

set certain bits in A

1 1 0 0 At
1 0 1 0B
1 1 1 0 At+1 (A ← A + B)

If a bit in B is set to 1, that same position in A gets set to

1, otherwise that bit in A keeps its previous value
Selective Complement
In a selective complement operation, the bit pattern in B is
used to complement certain bits in A

1 1 0 0 At
1 0 1 0B

0 1 1 0 At+1 (A ← A ⊕ B)

If a bit in B is set to 1, that same position in A gets

complemented from its original value, otherwise it is
unchanged
Selective Clear

In a selective clear operation, the bit pattern in B is used

to clear certain bits in A.
1 1 0 0 At
1 0 1 0B

0 1 0 0 At+1 (A ← A ⋅ B’)

If a bit in B is set to 1, that same position in A gets set to

0, otherwise it is unchanged.
Mask Operation

In a mask operation, the bit pattern in B is used to clear

certain bits in A.
1 1 0 0 At
1 0 1 0B

1 0 0 0 At+1 (A ← A ⋅ B)

If a bit in B is set to 0, that same position in A gets set to

0, otherwise it is unchanged.
Clear Operation
In a clear operation, if the bits in the same position in A
and B are the same, they are cleared in A, otherwise they
are set in A

1 1 0 0 At
1 0 1 0B

0 1 1 0 At+1 (A ← A ⊕ B)
Insert Operation
Step1: mask the desired bits
Step2: OR them with the desired value
Example: suppose R1 = 0110 1010, and we desire to
replace the leftmost 4 bits (0110) with 1001 then:

Step1: 0110 1010 A before

0000 1111 B (mask)
0000 1010 A After

Step2: 0000 1010 A before

1001 0000 B (insert)
 R1 = 1001 1010
6. Shift Microoperations
There are three types of shifts
Logical shift
Circular shift
Arithmetic shift

What differentiates them is the information that goes into

the serial input.

A right shift operation

A left shift operation
Seri
al
inpu
t

Seri
al
inpu
t
Logical Shift
In a logical shift the serial input to the shift is a 0.
A right logical shift operation:

A left logical shift operation:

In a Register Transfer Language, the following notation is

used
shl for a logical shift left
shr for a logical shift right
Examples:
R2 ← shr R2
R3 ← shl R3
 Circular Shift
In a circular shift the serial input is the bit that is shifted out of the other
end of the register.
A right circular shift operation:

A left circular shift operation:

In a RTL, the following notation is used

cil for a circular shift left
cir for a circular shift right
Examples:
R2 ← cir R2
R3 ← cil R3
 Arithmetic Shift
An arithmetic shift is meant for signed binary
numbers (integer).
An arithmetic left shift multiplies a signed number by
two.
An arithmetic
R n- R n- right shift divides a signed
R number
R by
1 2 1 0
two.

si
gn
A right arithmetic shift operation:
bi
t

0
si
gn
A left arithmetic shift operation:
bi
t
Arithmetic Shift

In a RTL, the following notation is used

ashl for an arithmetic shift left

ashr for an arithmetic shift right

Examples:

R2 ← ashr R2

R3 ← ashl R3
Arithmetic Shifts
Shifts a signed binary number to the left or right
An arithmetic shift-left multiplies a signed binary
number by 2:
ashl (00100): 01000

An arithmetic shift-right divides the number by 2.

ashr (00100) : 00010

An overflow may occur in arithmetic shift-left, and

occurs when the sign bit is changed (sign reversal).
Shift Microoperations
Example: Assume R1=11001110, then:
Arithmetic shift right once : R1 = 11100111
Arithmetic shift right twice : R1 = 11110011
Arithmetic shift left once : R1 = 10011100
Arithmetic shift left twice : R1 = 00111000
Logical shift right once : R1 = 01100111
Logical shift left once : R1 = 10011100
Circular shift right once : R1 = 01100111
Circular shift left once : R1 = 10011101
Hardware Implementation Of Shift Microoperations
0 for shift right
Serial Sele
input (down)
ct
(IR) 1 for shift left (up)

S
MU H
0 0
1 X

A
0 S
A H
1 0 MU
X 1
A 1
2
A
3 S
MU H
0 2
1 X

S
MU H
0 3
1 X

Serial
input
(IL)
Arithmetic Logic Shift Unit
S
S
3 Ci
S
2
S
1
0
Arithmet Di
icCircu
it Sele
ct
0 4 x Fi
Ci 1 MU
+ 2 1
1 3 X
Ei
Logi
Bi
Ai
Circu
c
it s
Ai
A-i sh
hr
+
1 l
1

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 01 F=A+1 Increment A
0 0 0 10 F=A+B Addition
0 0 0 1 1 F=A+B+1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with
borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F = A-1 Decrement A
0 0 1 1 1 F = A TransferA
0 1 0 0 X F = A∧B AND
0 1 0 1 X F = A ∨B OR
0 1 1 0 X F = A⊕B XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into
F
Basic Computer Organization And Design

• Instruction Codes

• Computer Registers
• Computer Instructions
• Instruction Cycle
• Memory Reference
Instructions
• Input-Output and Interrupt
8. Instruction Codes
Instruction Code:
It is a group of bits that instruct the computer to perform a
specific operation.
Opco Add
de ress
Operation code : Instruction
Format
The operation code of an instruction is a group of bits that
define such as
add
subtract
multiply
shift
complement.
 The Basic Computer

The Basic Computer has two components, a processor and

memory
The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in memory

Each word is 16 bits long Memo

ry
4096X
1 1 1 0 16
5Opco 2 1 Add Instructio
de Instructionress ns
(program
Format )Operan
1 0
5 Binary ds
operand
(data)
Processor
Fig: Stored program register
organization (accumulator
or AC)
Instruction Format
A computer instruction is often divided into two parts
An opcode (Operation Code) that specifies the operation for that instruction
An address that specifies the registers and/or locations in memory to use for that
operation

In the Basic Computer, since the memory contains 4096 (= 212)

words, we needs 12 bit to specify which memory address this
instruction will use

1 1 1 1 0
5 Opcode
4 2 1 Addre
I
ss
Addressing mode Instruction
Format

In the Basic Computer, bit 15 of the instruction specifies the

addressing mode (0: direct addressing, 1: indirect addressing)
Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode.
10. Basic Computer Instructions
Basic Computer Instruction
Format

Memory-Reference Instructions (OP-code = 000 ~

110) 15 1 0
14
I Opco 2 Add
de 1 ress
1
Register-Reference Instructions (OP-code = 111, I =
0)
1 1 0
50 1 2 Register
1 1 1 operation
Input-Output Instructions
1 (OP-code =111, I =
1)
1 1 0
51 1 2 I/O
1 1 1 operati
1 on
Basic Computer Instructions
Hex Code
Symbol I=0 I=1
Description
AND 0xxx 8xxx AND memory word
to AC
ADD 1xxx 9xxx Add memory word
to AC
LDA 2xxx Axxx Load AC from
memory
STA 3xxx Bxxx Store content of AC
into memory
BUN 4xxx Cxxx Branch
unconditionally
BSA 5xxx Dxxx Branch and save
return address
ISZ 6xxx Exxx Increment and skip
if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is
positive
SNA 7008 Skip next instr. if AC is
negative
SZA 7004 Skip next instr. if AC is
zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
 Instruction Set Completeness
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function
that is known to be computable.
Instruction
Types
Functional Instructions
- Arithmetic, logic, and shift instructions

- ADD, CMA, INC, CIR, CIL, AND, CLA

Transfer Instructions
- Data transfers between the main
memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
11. Instruction Cycle
In Basic Computer, a machine instruction is executed in
the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction
After an instruction is executed, the cycle starts again at step 1, for
the next instruction.
Note: Every different processor has its own (different) instruction
cycle .
Fetch and Decode
• Fetch and T0: AR ← PC (S0S1S2=010, T0=1)
Decode T1: IR ← M [AR], PC ← PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7 ← Decode IR(12-14), AR ← IR(0-11), I ←
IR(15)
T S
1 Bu
T S
2
s
0 S
1
Memo
ryun
0 7
it Add
R ress
ea
Ad 1
R
L
DP 2
C
I
IN 5
RR
L Cl
Common
D
bus oc
k
Determine The Type Of Instruction
Start
SC ←
0

A ←P T
R C 0 T
I ← M[AR P ← PC 1
],
R C + T
Decode Opcode in
A ← IR(0-
IR(12-14), I← 1
IR( 2
R 11), 15)
(Register or I/O) = 0 (Memory-
=1 D reference)
(I/O) =0 7 (indirect) =0
=1 I (register) =1 I (direct)
T T
T ← M[A 3 T
Exec Exec 3 A Nothi
input-
ute 3 register-
ute R R] ng 3
instructi instructi
S ← 0 S ← 0
output reference
on
C
on Exec
memory-
T
C ute
instructi
reference 4
S ←0
on
C
D'7IT3: AR ← M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 Register Reference Instructions
Register Reference Instructions are identified
when - D = 1, I = 0
7
- Register Ref. Instr. is specified in b0 ~ b11
of IR
- Execution starts with timing signal T3
r = D7 I′T3 => Register Reference
Instruction
Bi = IR(i)
r: , i=0,1,2,...,11
SC ← 0
CLArB11: AC ← 0
CLE rB10: E← 0
CMA rB9: AC ← AC’
CME rB8: E ← E’
CIR rB7: AC ← shr AC, AC(15) ← E, E ← AC(0)
CIL rB6: AC ← shl AC, AC(0) ← E, E ← AC(15)
INC rB5: AC ← AC + 1
SPA rB4: if (AC(15) = 0) then (PC ← PC+1)
SNA rB3: if (AC(15) = 1) then (PC ← PC+1)
SZA rB2: if (AC = 0) then (PC ← PC+1)
SZErB1: if (E = 0) then (PC ← PC+1)
HLT rB0: S ← 0 (S is a start-stop flip-flop)
 12. Memory Reference Instructions
Operat
Sym ion Symbolic
bol
AND Decod
ACDescription
D0 ← AC ∧ M[AR]
er
ADD D1 AC ← AC + M[AR], E ← Cout
LDA D2 AC ← M[AR]
STA D3 M[AR] ← AC
BUN D4 PC ← AR
BSA D5 M[AR] ← PC, PC ← AR + 1
ISZ D6 M[AR] ← M[AR] + 1, if M[AR] + 1 = 0 then PC ←
PC+1
- The effective address of the instruction is in AR and was placed there
during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU
cycle
AND to AC
- The execution of MR instruction starts with T4
D0T4: DR ← M[AR] Read operand
D0T5: AC ← AC ∧ DR, SC ← 0 AND with AC
ADD to AC
D1T4: DR ← M[AR] Read operand
D1T5: AC ← AC + DR, E ← Cout, SC ← 0 Add to AC and store carry
in E
Memory Reference Instructions
LDA: Load to AC
D2T4: DR ← M[AR]
D2T5: AC ← DR, SC ← 0
STA: Store AC
D3T4: M[AR] ← AC, SC ← 0
BUN: Branch Unconditionally
D4T4: PC ← AR, SC ← 0
BSA: Branch and Save Return
Address
M[AR] ← PC, PC ← AR + 1
Memory, PC, Memory, PC
AR2at 0time
B T4 1 after
2 execution
0 B 1
PC 0 Next S 3 0 Next
2 S 3
= instruction
A 5 1 instruction
A 5
21
AR 1 2
= 1 Subro PC 3 Subro
1
135 3 utine = 5 utine
6 136
1 B 1 1 B 1
UMe 3 UMe 3
Nmor 5 Nmor 5
Memory Reference Instructions
BSA:
D5T4: M[AR] ← PC, AR ← AR + 1
D5T5: PC ← AR, SC ← 0
ISZ: Increment and Skip-if-Zero
D6T4: DR ← M[AR]
D6T5: DR ← DR + 1
D6T4: M[AR] ← DR, if (DR = 0) then (PC ← PC + 1),
SC ← 0
Flowchart For Memory Reference Instructions
Memory-reference
instruction
AN AD LD ST
D D A A
D 4 D1 4 D2 4 D3 4
0
T T T T
DR ← DR ← DR ← M[AR] ←
M[AR] M[AR] M[AR] ACSC ←
0
D0 5 D1 5 D2 5
AC ← AC ∧ T T T
AC ← AC + AC ←
DR SC ← DR
E← SC ←
DR
0 Cout
SC ← 0
0
BU B I
N S S
D4 4 A D5 4 Z D6 4
T T T
PC ← M[AR] ← DR ←
AR ←
SC PC ← AR
AR M[AR]
0 +1
D5 5 D6 5
T T
PC ← DR ← DR
AR
SC ← +1
0
D6 6
T
M[AR] ←
If (DR =
DR
0)
then (PC ← PC
+ 1)
SC ←
0
Basic Computer Instructions
Hex Code
Symbol I=0 I=1
Description
AND 0xxx 8xxx AND memory word
to AC
ADD 1xxx 9xxx Add memory word
to AC
LDA 2xxx Axxx Load AC from
memory
STA 3xxx Bxxx Store content of AC
into memory
BUN 4xxx Cxxx Branch
unconditionally
BSA 5xxx Dxxx Branch and save
return address
ISZ 6xxx Exxx Increment and skip
if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is
positive
SNA 7008 Skip next instr. if AC is
negative
SZA 7004 Skip next instr. if AC is
zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
13. Input-Output And Interrupt
A Terminal with a keyboard and a
Printer
Input-Output
Configuration Input- Ser Computer
termi communicat
ial registers
output
nal ioninterfa
ce
Recei and
Print interfa OUT
flip-flops FG
ver
er ce R O
A
C
Transmit
Keybo interfa INP F
INPR Input register - 8 bits ard ter
ce R G
OUTR Output register - 8 bits Serial Communications
I
FGI Input flag - 1 bit Parallel Communications
Path
FGO Output flag - 1 bit Path
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial

information
- The serial info. from the keyboard is shifted into
INPR
- The serial info. for the printer is stored in the
OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
Input-Output Instructions
D7IT3 = p
IR(i) = Bi, i = 6, …,
11

p: SC ← 0 Clear SC
INP pB11: AC(0-7) ← INPR, FGI ← 0 Input char. to AC
OUT pB10: OUTR ← AC(0-7), FGO ← 0 Output char. from
AC
SKI pB9: if(FGI = 1) then (PC ← PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC ← PC + 1) Skip on
output flag
ION pB7: IEN ← 1 Interrupt enable on
IOF pB6: IEN ← 0 Interrupt enable off
Program-Controlled Input/Output

Program-controlled
I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
 Interrupt Initiated Input/Output
- Open communication only when some data has to be passed
--> interrupt.
- - The I/O interface, instead of the CPU, monitors the I/O
device.
- When the interface founds that the I/O device is ready for
data transfer,
it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the
* IEN (Interrupt-enable flip-
task
flop)
-itcan
is doing,
be set branches to by
and cleared theinstructions.
service routine to process the
data- when cleared, the computer cannot be
transfer, and then returns to the task it was performing.
interrupted.
 Flowchart For Interrupt Cycle
R=
Instruction Interrupt Interrupt f/f
= =
cycle R cycle
0 1

Fetch and Store return

in
instructio
decode address
M[0] ←
location 0
ns PC

Execu =
IE
instructio
te 0
N = Branch to
ns
=
1 location
PC 1 ←
F 1
1
G =
I 0 IEN ←0
=
FG R←
1
O = 0
R
←1 0

- The interrupt cycle is a HW implementation of a branch and save return

address operation.
- At the beginning of the next instruction cycle, the instruction that is read
from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine.
- The instruction that returns the control to the original program is "indirect
Register Transfer Operations In Interrupt Cycle
Me
Before mor After interrupt
interrupt
0 y 0 cycle 2
1 0 BU 1 PC 0 BU5 1
N 1 =1 N 6 1
Ma 2 Ma 2
2 Progr
in 2 Progr
in
PC =5 am 0 25 am 0
25615 155
1 I/ 16 I/
2 Progr
O 2 Progr
O
0 am 0 am
1 BU 0 1 BU 0
N N
Register Transfer Statements for Interrupt Cycle
- R F/F ← 1 if IEN (FGI + FGO)T0′T1′T2′
⇔ T0′T1′T2′ (IEN)(FGI + FGO): R ← 1
- The fetch and decode phases of the instruction cycle
must be modified ➔Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
14. A Stack Machine
A Stack machine has a stack as
Processo a part of the processor state
r
typical operations:
stac Mai
k n
Stor
: e push, pop, +, *, ...
Instructions like + implicitly
specify the top 2 elements of
the stack as operands.
push
a push b c c po b
b a ➔ b p a
➔ a ➔

5/28/2021
 Register Stack Organization
Stack
- Very useful feature for nested subroutines, nested interrupt
services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP sta Addre
- Only PUSH and POP operations are applicable
Register ck ss6
Fla
3
Stack FUL gs EMPT
L Y

Stack 4
pointer
S C 3
6P B 2
bits A 1
Push, Pop 0

operations D
R

PUS PO
H P
SP ← SP + 1 DR ← M[SP]
M[SP] ← DR SP ← SP − 1
If (SP = 0) then (FULL ← 1) If (SP = 0) then
(EMPTY ← 1)
Memory Stack Organization
10
Progra 00
P
Memory with Program, C
(instruction
m
s)
Data, Da
A (operand
ta
and Stack Segments R s)
S 30
P sta 00
ck
39
39
97
39
98
- A portion of memory is used as a stack with a 99
40
40
00
processor register as a stack pointer. 01
Stack grows
In this
- PUSH: SP ← SP - 1 direction

M[SP] ← DR
- POP: DR ← M[SP]

- Most computers do not provide hardware to check stack overflow (full

SP ← SP + 1
stack) or underflow (empty stack)  must be done in software
Reverse Polish Notation
Arithmetic Expressions: A
+B A + B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
- The reverse Polish notation is very suitable
for stack manipulation

Evaluation of Arithmetic
Expressions
Any arithmetic expression can be expressed in parenthesis-
free
Polish notation, including reverse Polish notation

(3 * 4) + (5 * 6) ⇒ 34*
56*+

6
4 5 5 3
3 3 1 1 1 0
1 4
2 2 2 2 2
3 4 * 5 6 * +
Processor Organization
In general, most processors are organized in one of 3 ways

Single register (Accumulator) organization

Basic Computer is a good example.
Accumulator is the only general purpose register.

General register organization

Used by most modern computer processors.
Any of the registers can be used as the source or destination for
computer operations.

Stack organization
All operations are done using the hardware stack.
For example, an OR instruction will pop the two top elements from the
stack, do a logical OR on them, and push the result on the stack.
 15. Instruction Format
Instruction
Fields OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a
processor register(s)
Mode field - determines how the address field is to be
interpreted (to get effective address or the operand)
The number of address fields in the instruction format
depends on the internal organization of CPU.
The three most common CPU organizations:

Single accumulator organization:

ADDX /* AC ← AC + M[X] */
General register organization:
ADDR1, R2, R3 /* R1 ← R2 + R3 */
ADD R1, R2 /* R1 ← R1 + R2 */
MOV R1, R2 /* R1 ← R2 */
ADD R1, X /* R1 ← R1 + M[X] */
Stack organization:
PUSH X /* TOS ← M[X] */
ADD
Three, and Two-Address Instructions
Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1 ← M[A] + M[B] */
ADD R2, C, D /* R2 ← M[C] + M[D] */
MUL X, R1, R2 /* M[X] ← R1 * R2 */
- Results in short programs
- Instruction becomes long (many bits)
Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1 ← M[A] */
ADD R1, B /* R1 ← R1 + M[A] */
MOV R2, C /* R2 ← M[C] */
ADD R2, D /* R2 ← R2 + M[D] */
MUL R1, R2 /* R1 ← R1 * R2 */
MOV X, R1 /* M[X] ← R1 */
One and Zero-Address Instructions
One-Address
Instructions
- Use an implied AC register for all data
- Program to evaluate X = (A + B) * (C
manipulation
+ D) : LOAD A /* AC ← M[A] */
ADD B /* AC ← AC + M[B] */
STORE T /* M[T] ← AC */
LOAD C /* AC ← M[C] */
ADD D /* AC ← AC + M[D] */
MUL T /* AC ← AC * M[T] */
STORE X /* M[X] ← AC */
Zero-Address
Instructions
- Can be found in a stack-organized
-computer
Program to evaluate X = (A + B) * (C
+ D) :
PUSH A /* TOS ← A */
PUSH B /* TOS ← B */
ADD /* TOS ← (A + B) */
PUSH C /* TOS ← C */
PUSH D /* TOS ← D */
ADD /* TOS ← (C + D) */
MUL /* TOS ← (C + D) * (A + B) */
POPX /* M[X] ← TOS */
The
End