1.

Write Verilog code using concurrent signal assignment

statement for the following and test it on FPGA kit.
a) Full adder using operators

module fulladder_operators(a,b,c,s,co);

input a,b,c;

output s,co;

assign s=a^b^c;

assign co=(a&b)|(b&c)|(a&c);

endmodule

waveform:
b) 3:8 decoder with active low output using operator

module decodr3_8(input a,b,c, output [0:7]y);

assign y[0] = ((~a)&(~b)&(~c));

assign y[1] = ((~a)&(~b)&(c));

assign y[2] = ((~a)&(b)&(~c));

assign y[3] = ((~a)&(b)&(c));

assign y[4] = ((a)&(~b)&(~c));

assign y[5] = ((a)&(~b)&(c));

assign y[6] = ((a)&(b)&(~c));

assign y[7] = ((a)&(b)&(c));

endmodule

waveform:
c) 4x1 MUX using operator

module mux4to1o(s0,s1,a,b,c,d,y);

input s0,s1,a,b,c,d;

output y;

wire x0,x1,x2,x3,s0b,s1b;

assign s0b=~s0;

assign s1b=~s1;

assign x0=s0b&s1b&a;

assign x1=s0b&s1&b;

assign x2=s0&s1b&c;

assign x3=s0&s1&d;

assign y=x0|x1|x2|x3;

endmodule

WAVEFORM
d) Boolean expressions using operators

module boolean_exp( input a,b,c,output f1,f2);

assign f1 =(!a*c)+(!b);

assign f2 = (a+!b)*!c;

endmodule

waveform:
e) bit Full Adder using gates

module fulladdr (x,y,z,sum,car);

input x,y,z;

output sum,car;

wire s1,s2,s3;

xor(sum,x,y,z);

and(s1,x,y);

and(s2,x,z);

and(s3,y,z);

or(car,s1,s2,s3);

endmodule

waveform:
f) 3to8 decoder using gates

module mux4_1(input a,b,c,d,s0,s1,output y);

wire A,B,C,D,E,F;

not(A,s1);

not(B,s0);

and(C,a,A,B);

and(D,b,A,s0);

and(E,c,s1,B);

and(F,d,s1,s0);

or(y,C,D,E,F);

endmodule

Waveform:
g) 4:1 mux using gate

module mux4_1(input a,b,c,d,s0,s1,output y);

wire A,B,C,D,E,F;

not(A,s1);

not(B,s0);

and(C,a,A,B);

and(D,b,A,s0);

and(E,c,s1,B);

and(F,d,s1,s0);

or(y,C,D,E,F);

endmodule

Waveform:
h) boolean expression using gate

module boolean_exp( input a,b,c,output f1,f2);

wire aabar,bbar,cbar,s0,s1,s2,s3,s4,w0,w1,w2,w3,w4;

not(abar,a);

not(bbar,b);

not(cbar,c);

//f1 function

and(s0,abar,bbar,cbar);

and(s1,abar,bbar,c);

and(s2,abar,b,c);

and(s3,a,bbar,cbar);

and(s4,a,bbar,c);

or(f1,s0,s1,s2,s3,s4);

//f2 function

or(w0,a,b,cbar);

or(w1,a,bbar,c);

or(w2,a,bbar,cbar);

or(w3,abar,b,cbar);

or(w4,abar,bbar,cbar);

and(f2,w0,w1,w2,w3,w4);

endmodule

waveform:
2.Write Verilog code using (a)conditional signal assignment
statement (b)sequential statements and test it on FPGA kit.
a) Full Subtractor using conditional statement

module FullSubb(input a,b,c,output diff,bor);

wire [2:0]ip;

assign ip = {a,b,c};

assign{diff,bor} = (ip==3'b000)?2'b00:

(ip==3'b001)?2'b11:

(ip==3'b010)?2'b11:

(ip==3'b011)?2'b01:

(ip==3'b100)?2'b10:

(ip==3'b101)?2'b00:

(ip==3'b110)?2'b00:

2'b11;

endmodule

waveform:
b) 3x8 Decoder using conditional statement

module decdr3_8(input a,b,c,output [0:7]y);

assign y =({a,b,c} == 3'b000) ? 8'b01111111:

({a,b,c} == 3'b001) ? 8'b10111111:

({a,b,c} == 3'b010) ? 8'b11011111:

({a,b,c} == 3'b011) ? 8'b11101111:

({a,b,c} == 3'b100) ? 8'b11110111:

({a,b,c} == 3'b101) ? 8'b11111011:

({a,b,c} == 3'b110) ? 8'b11111101:

8'b11111110;

endmodule

Waveform:
c) 4x1 MUX using conditional statement

module mux4_1(input a,b,c,d,s0,s1,output y);

assign y = ({s0,s1} == 2'b00) ? a :

({s0,s1} == 2'b01) ? b :

({s0,s1} == 2'b10) ? c :

d;

endmodule

waveform:
d) boolean expression using conditional statement

module boolean_exp( input a,b,c,output f1,f2);

assign {f1,f2} = ({a,b,c}==3'b000) ? 2'b11:

({a,b,c}==3'b001) ? 2'b10:

({a,b,c}==3'b010) ? 2'b00:

({a,b,c}==3'b011) ? 2'b10:

({a,b,c}==3'b100) ? 2'b11:

({a,b,c}==3'b101) ? 2'b10:

({a,b,c}==3'b110) ? 2'b01:

2'b00;

endmodule

waveform:
e) full substractor using sequential statement

module FullSubb(input a,b,c,output reg diff,bor);

wire [2:0]ip;

assign ip = {a,b,c};

always @(ip)

begin

case (ip)

3'b000 : begin diff = 0;bor = 0; end

3'b001 : begin diff = 1;bor = 1; end

3'b010 : begin diff = 1;bor = 1; end

3'b011 : begin diff = 0;bor = 1; end

3'b100 : begin diff = 1;bor = 0; end

3'b101 : begin diff = 0;bor = 0; end

3'b110 : begin diff = 0;bor = 0; end

3'b111 : begin diff = 1;bor = 1; end

default: begin diff = 0;bor = 0;end

endcase

endmodule

waveform:
f) 3:8 Decoder using sequential statement

module decdr3_8(input a,b,c,output reg [0:7]y);

always@(a or b or c)

begin

case({a,b,c})

3'b000 : y = 8'b01111111;

3'b001 : y = 8'b10111111;

3'b010 : y = 8'b11011111;

3'b011 : y = 8'b11101111;

3'b100 : y = 8'b11110111;

3'b101 : y = 8'b11111011;

3'b110 : y = 8'b11111101;

3'b111 : y = 8'b11111110;

endcase

end

endmodule

waveform:
g) 4:1 mux using sequential statement

module mux4_1(input a,b,c,d,s0,s1,output reg y);

always@(a or b or c or d or s0 or s1)

begin

case({s0,s1})

2'b00 : y = a;

2'b01 : y = b;

2'b10 : y = c;

2'b11 : y = d;

endcase

end

endmodule

waveform:
h) boolean expression using sequential statement

module boolean_exp( input a,b,c,output reg f1,f2);

always @ (a or b or c)

begin

case({a,b,c})

3'b000 : {f1,f2} = 2'b11;

3'b001 : {f1,f2} = 2'b10;

3'b010 : {f1,f2} = 2'b00;

3'b011 : {f1,f2} = 2'b10;

3'b100 : {f1,f2} = 2'b11;

3'b101 : {f1,f2} = 2'b10;

3'b110 : {f1,f2} = 2'b01;

3'b111 : {f1,f2} = 2'b00;

endcase

end

endmodule

waveform:
3.Write Verilog code and test it on FPGA kit.
a) Signed and unsigned adder

module sign_unsign_adder(a,b,c,d,signSum,unSignSum);

input [7:0] a,b;

input signed [7:0] c,d;

output [7:0] unSignSum;

output signed [8:0] signSum;

assign unSignSum = a+b;

assign signSum = c+d;

endmodule

WAVE FORM
b) 1-bit comparator

module comparator(a,b,aGb,aLb,aEb);

input a,b,c;

output aGb,aLb,aEb;

assign aGb=a & ~b;

assign aLb=~a & b;

assign aEb= a&b | ~a & ~b;

endmodule

WAVEFORM
c) 8-bitcomporator
module comp8bit (a,b,agb,aeb,alb);
input [7:0]a,b;
output agb,aeb,alb;
reg agb,aeb,alb;
always@(a,b)
begin
if(a>b)
begin
agb=1; aeb=0; alb=0;
end
else if(a<b)
begin
alb=1; agb=0; aeb=0;
end
else
begin
aeb=1; alb=0; agb=0;
end
end
endmodule

WAVEFORM
d) T-Flip Flop
module tffmy(clk,pr,clr,t,q,qb);
input clk,pr,clr,t;
output q,qb;
reg q;

initial
begin
q=1'b0;
end
always@(posedgeclk)
begin
if(pr)
begin
q=1'b1;
end
else if(clr)
begin
q=1'b0;
end
else if(t)
begin
q=~q;
end
end
assign qb=~q;
endmodule

WAVEFORM
e) D-Flip Flop

module dffmy(clk,pr,clr,d,q,qb);
input clk,pr,clr,d;
output q,qb;
reg q;
initial
begin
q=1'b0;
end
always@(posedgeclk)
begin
if(pr)
begin
q=1'b1;
end
else if(clr)
begin
q=1'b0;
end
else
begin
q=d;
end
end
assign qb=~q;
endmodule

WAVEFORM
 4. Write Verilog program for the following using component
statements and test it on FPGA kit
a) Parallel Adder using full adder as component

module padder4 (a,b,cin,cout,sum);

input [3:0] a,b;

input cin;

output [3:0]sum;

output cout;

wire [4:0] c;

assign c[0] = cin;

fulladd n1(a[0],b[0],c[0],sum[0],c[1]);

fulladd n2(a[1],b[1],c[1],sum[1],c[2]);

fulladd n3(a[2],b[2],c[2],sum[2],c[3]);

fulladd n4(a[3],b[3],c[3],sum[3],c[4]);

assign cout = c[4];

endmodule

WAVEFORM
b) 4 bit asynchronous up counter using T flipflop as component

module counter4(clk,pr,clr,t,q,qb);

input clk,pr,clr,t;

output [3:0] q,qb;

tffmy t1 (clk,pr,clr,t,q[0],qb[0]);

tffmy t2 (q[0],pr,clr,t,q[1],qb[1]);

tffmy t3 (q[1],pr,clr,t,q[2],qb[2]);

tffmy t4 (q[2],pr,clr,t,q[3],qb[3]);

endmodule

WAVEFORM
c) 3-bit Johnson counter using D flip flop as component

module johnson4bit(clk,pr,clr,q,qb);

input clk,pr,clr;

output [3:0]q,qb;

dffmy d1(clk,pr,clr,qb[3],q[0],qb[0]);

dffmy d2(clk,pr,clr,q[0],q[1],qb[1]);

dffmy d3(clk,pr,clr,q[1],q[2],qb[2]);

dffmy d4(clk,pr,clr,q[2],q[3],qb[3]);

//dffmy d1(clk,1'b0,1'b0,qb[3],q[0],qb[0]);

//dffmy d2(clk,1'b0,1'b0,q[0],q[1],qb[1]);

//dffmy d3(clk,1'b0,1'b0,q[1],q[2],qb[2]);

//dffmy d4(clk,1'b0,1'b0,q[2],q[3],qb[3]);

Endmodule

WAVEFORM
5.Write Verilog code for the following and test it on FPGA kit
a) BCD to seven segment display decoder

module BCD_SSD(input e,input [3:0]BCD,output [6:0] SSD_out);

assign SSD_out= ({e,BCD}==5'b00000)?7'b0000001:

({e,BCD}==5'b00001)?7'b1001111:

({e,BCD}==5'b00010)?7'b0010010:

({e,BCD}==5'b00011)?7'b0000110:

({e,BCD}==5'b00100)?7'b1001100:

({e,BCD}==5'b00101)?7'b0100100:

({e,BCD}==5'b00110)?7'b0100000:

({e,BCD}==5'b00111)?7'b0001111:

({e,BCD}==5'b01000)?7'b0000000:

({e,BCD}==5'b01001)?7'b0000100:7'b0000001;

Endmodule

WAVEFORM
 b) To display message on LCD display, Line 1 : BEC Line 2 : ECE

module LCD_static(clr,clk,rw,rs,lcdon,bklon,en,db);
input clr,clk;
output rw,rs,lcdon,bklon;
output en;
output [7:0] db;
reg rw,rs,en;

reg [7:0] db;

parameter a=0, b=1, c=2, d=3,

wr_dt1=4,wr_dt2=5,wr_dt3=6,shift=7,wr_dt4=8,wr_dt5=9,wr_dt6=10,nowork=11,dis_cont=
12;
reg [3:0] current;
reg [25:0] count;

assign lcdon=1'b1;
assign bklon=1'b1;

//frequency divider
always@(posedge clk)
begin
if (clr) count<=0;
else
begin
count<=count+1'b1;
en<=count[22];
end
end

always@(posedge en)
begin
if (clr) current <= a;
else
begin
case ( current )
a: begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00111000;//C8 //functionset 2 lines & 5x7 matrix 001 DL N F 00
current<=b;
end
b : begin
current <= c;
rs<=1'b0;
rw<=1'b0;
db<=8'b00001110;//0E
end //--diplay on/off control 00001DCB
c :begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000001; //01 // -- clear diplay screen
end
d : begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000110;//06 //-- Entry mode set 000001 I/D SH
current<=dis_cont;
end
dis_cont :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b10000110;//86 cursor at 1st line & 6th position (set DDRAM Address)1 AC6 to AC0
current<=wr_dt1;
end
wr_dt1 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000010; // -- B
current<=wr_dt2;
end
wr_dt2 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=wr_dt3;
end
wr_dt3 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=shift;
end//
shift : begin
rs<=1'b0;
rw<=1'b0; //-- force cursor to 2nd line & 6th
db<=8'b11000110;//C6 //-- position 1 AC6 to AC0
current<=wr_dt4;
end
wr_dt4 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; //-- E
current<=wr_dt5;
end
wr_dt5 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=wr_dt6;
end
wr_dt6 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=nowork;
end
nowork :begin
//rs<=1'b0;
//rw<=1'b0;
current<=nowork;
end
default:current<=a;

endcase
end
end
endmodule
c) To run message from left to right on LCD display, Line 1 : BEC Line 2 :ECE
module LCD_static_L_R(clr,clk,rw,rs,lcdon,bklon,en,db);
input clr,clk;
output rw,rs,lcdon,bklon,en;
output [7:0] db;
reg rw,rs,en;
reg [7:0] db;
parameter a=0, b=1, c=2, d=3,
wr_dt1=4,wr_dt2=5,wr_dt3=6,shift=7,wr_dt4=8,wr_dt5=9,wr_dt6=10,nowork=11,dis_cont
=12;
reg [3:0] current;
reg [25:0] count;

assign lcdon =1'b1;

assign bklon =1'b1;
//frequency divider
always@(posedge clk)
begin
if (clr ) count<=0;
else
begin
count<=count+1'b1;
en<=count[23];
end
end

always@(posedge en)
begin
if (clr ) current <= a;
else
begin case ( current )
a: begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00111000; //functionset 2 lines & 5x7 matrix 001 DL N F 00
current<=b;
end
b : begin
current <= c;
rs<=1'b0;
rw<=1'b0;
db<=8'b00001110;
end //--diplay on/off control 00001DCB
c :begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000001; // -- clear diplay screen
end
d : begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000110; //-- Entry mode set 000001 I/D SH
current<=dis_cont;
end
dis_cont :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b10000110; // --cursor at 1st line & 6th position (set DDRAM Address) 1
AC6 to AC0
current<=wr_dt1;
end
wr_dt1 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000010; // -- B
current<=wr_dt2;
end
wr_dt2 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=wr_dt3;
end
wr_dt3 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=shift;
end//
shift : begin
rs<=1'b0;
rw<=1'b0; //-- force cursor to 2nd line & 6th
db<=8'b11000110; //-- position 1 AC6 to AC0
current<=wr_dt4;
end
wr_dt4 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; //-- E
current<=wr_dt5;
end
wr_dt5 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=wr_dt6;
end
wr_dt6 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=nowork;
end
nowork :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00011000;
current<=nowork;
end
default: current <= a;
endcase
end
end

endmodule
 d) To run message from right to left on LCD display, Line 1 : BEC Line 2 :ECE
module LCD_static_R_L(clr,clk,rw,rs,lcdon,bklon,en,db);
input clr,clk;
output rw,rs,lcdon,bklon,en;
output [7:0] db;
reg rw,rs,en;
reg [7:0] db;
parameter a=0, b=1, c=2, d=3,
wr_dt1=4,wr_dt2=5,wr_dt3=6,shift=7,wr_dt4=8,wr_dt5=9,wr_dt6=10,nowork=11,dis_cont=
12;
reg [3:0] current;
reg [25:0] count;

assign lcdon =1'b1;

assign bklon =1'b1;

//frequency divider
always@(posedge clk)
begin
if (clr ) count<=0;
else
begin
count<=count+1'b1;
en<=count[23];
end
end

always@(posedge en)
begin
if (clr ) current <= a;
else
begin case ( current )
a: begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00111000; //functionset 2 lines & 5x7 matrix 001 DL N F 00
current<=b;
end
b : begin
current <= c;
rs<=1'b0;
rw<=1'b0;
db<=8'b00001110;
end //--diplay on/off control 00001DCB

c :begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000001; // -- clear diplay screen
end
d : begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000110; //-- Entry mode set 000001 I/D SH
current<=dis_cont;
end
dis_cont :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b10000110; // --cursor at 1st line & 6th position (set DDRAM Address) 1
AC6 to AC0
current<=wr_dt1;
end
wr_dt1 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000010; // -- B
current<=wr_dt2;
end
wr_dt2 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=wr_dt3;
end
wr_dt3 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=shift;
end//
shift : begin
rs<=1'b0;
rw<=1'b0; //-- force cursor to 2nd line & 6th
db<=8'b11000110; //-- position 1 AC6 to AC0
current<=wr_dt4;
end
wr_dt4 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; //-- E
current<=wr_dt5;
end
wr_dt5 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=wr_dt6;
end
wr_dt6 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=nowork;
end
nowork :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00011100;
current<=nowork;
end

default: current <= a;

endcase
end
end

endmodule
e) To display and blink message every one second on LCD display, Line 1 : BEC Line 2 :
ECE

module LCD_static_Blink(clr,clk,rw,rs,lcdon,bklon,en,db);
input clr,clk;
output rw,rs,lcdon,bklon,en;
output [7:0] db;
reg rw,rs,en;
reg [7:0] db;
parameter a=0, b=1, c=2, d=3,
wr_dt1=4,wr_dt2=5,wr_dt3=6,shift=7,wr_dt4=8,wr_dt5=9,wr_dt6=10,nowork=11,dis_cont=
12,nowork1=13;
reg [3:0] current;
reg [25:0] count;

assign lcdon =1'b1;

assign bklon =1'b1;

//frequency divider
always@(posedge clk)
begin
if (clr ) count<=0;
else
begin
count<=count+1'b1;
en<=count[23];
end
end

always@(posedge en)
begin
if (clr ) current <= a;
else
begin case ( current )
a: begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00111000; //functionset 2 lines & 5x7 matrix 001 DL N F 00
current<=b;
end
b : begin
current <= c;
rs<=1'b0;
rw<=1'b0;
db<=8'b00001110;
end //--diplay on/off control 00001DCB

c :begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000001; // -- clear diplay screen
end
d : begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000110; //-- Entry mode set 000001 I/D SH
current<=dis_cont;
end
dis_cont :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b10000110; // --cursor at 1st line & 6th position (set DDRAM Address) 1
AC6 to AC0
current<=wr_dt1;
end
wr_dt1 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000010; // -- B
current<=wr_dt2;
end
wr_dt2 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=wr_dt3;
end
wr_dt3 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=shift;
end//
shift : begin
rs<=1'b0;
rw<=1'b0; //-- force cursor to 2nd line & 6th
db<=8'b11000110; //-- position 1 AC6 to AC0
current<=wr_dt4;
end
wr_dt4 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; //-- E
current<=wr_dt5;
end
wr_dt5 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000011; //-- C
current<=wr_dt6;
end
wr_dt6 :begin
rs<=1'b1;
rw<=1'b0;
db<=8'b01000101; // -- E
current<=nowork;
end
nowork :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00001000;
current<=nowork1;
end
nowork1 :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00001100;
current<=nowork;
end
default: current <= a;
endcase
end
end

endmodule
6. Write Verilog code for the following and test it on FPGAkit

a) 4-bit up/down counter with parallel load and display result on LEDS
module updown_counter_4bit (Out, In, S, C, F, Clk);
input [3:0]In;
output [3:0]Out;
input S,C,F,Clk;
reg [3:0]Out;

always @(negedge Clk)

begin
if (S==1'b1)
Out=In; // parallel load
else if (C==1'b1)
Out=4'b0000;// clear

else if(F==1'b1)
Out=Out+1'b1;// up counter
else
Out=Out-1'b1;// down counter
end

endmodule

waveform
 b) BCD up counter and display the result on seven segmentdisplays
module BCD_counter_4bit (SSD_out,Out, In, S, C, Clk);
input [3:0]In;
output [3:0]Out;
input S,C,Clk;
reg [3:0]Out;
output [6:0]SSD_out;
reg [6:0]SSD_out;

always @(negedge Clk)

begin
if (S==1'b1)
Out=In; // parallel load
else if (C==1'b1)
Out=4'b0000;// clear

else begin
Out=Out+1'b1;// up counter
if(Out==4'b1010)
Out=4'b0000;
end
end
always@(Out)
begin
case (Out)
4'b0000 : begin SSD_out=7'b0000001; end
4'b0001 : begin SSD_out=7'b1001111; end
4'b0010 : begin SSD_out=7'b0010010; end
4'b0011 : begin SSD_out=7'b0000110; end
4'b0100 : begin SSD_out=7'b1001100; end
4'b0101 : begin SSD_out=7'b0100100; end
4'b0110 : begin SSD_out=7'b0100000; end
4'b0111 : begin SSD_out=7'b0001111; end
4'b1000 : begin SSD_out=7'b0000000; end
4'b1001 : begin SSD_out=7'b0000100; end
default:begin SSD_out=7'b0000001;end
endcase
end
endmodule
Waveform:
c) 00 to 99 up counter and display result on LCD
module LCD_BCD_00_99(clr,clk,rw,rs,lcdon,bklon,en,db);
input clr,clk;
output rw,rs,lcdon,bklon,en;
output [7:0] db;
reg rw,rs,en,clk1;
reg [7:0] db;

parameter a=0, b=1, c=2, d=3, wr_dt1=4,wr_dt2=5,wr_dt3=6,dis_cont=7;

reg [3:0] current;

reg [25:0] count;
reg [3:0] d1,d0;
reg [7:0] dig1,dig0;

assign lcdon =1'b1;

assign bklon =1'b1;

//frequency divider
always@(posedge clk)
begin
if (clr ) count<=0;
else
begin
count<=count+1'b1;
en<=count[21];
clk1<=count[23];
end
end

always@(posedge clk1)
begin

if(clr==1'b1)
begin
d0=4'b0000;
d1=4'b0000;
end
else
begin
d0=d0+1;
if(d0==4'b1010)
begin
d0=4'b0000;
d1=d1+1;
if(d1==4'b1010)
begin
d0=4'b0000;
d1=4'b0000;
end
end
end
end
always@(posedge en)
begin
if (clr ) current <= a;
else
begin case ( current )
a: begin
rs<=1'b0;
rw<=1'b0;
db<=8'b00111000; //functionset 2 lines & 5x7 matrix 001 DL N F 00
current<=b;
end
b : begin
current <= c;
rs<=1'b0;
rw<=1'b0;
db<=8'b00001110;
end //--diplay on/off control 00001DCB
c :begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000001; // -- clear diplay screen
end
d : begin
current <= d ; rs<=1'b0;
rw<=1'b0;
db<=8'b00000110; //-- Entry mode set 000001 I/D SH
current<=dis_cont;
end
dis_cont :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b10000111; // --cursor at 1st line & 6th position (set DDRAM Address)
1 AC6 to AC0
current<=wr_dt1;
end
wr_dt1 :begin
rs<=1'b1;
rw<=1'b0;
db<=dig0; // -- B
current<=wr_dt2;
end
wr_dt2 :begin
rs<=1'b0;
rw<=1'b0;
db<=8'b10000110; // dig0
current<=wr_dt3;
end
wr_dt3 :begin
rs<=1'b1;
rw<=1'b0;
db<=dig1; //dig1
current<=dis_cont;
end//
default: current <= a;
endcase
end
end
always@(d0)
begin
case (d0)
4'b0000:begin dig0<= 8'b00110000; end
4'b0001:begin dig0<= 8'b00110001; end
4'b0010:begin dig0<= 8'b00110010; end
4'b0011:begin dig0<= 8'b00110011; end
4'b0100:begin dig0<= 8'b00110100; end
4'b0101:begin dig0<= 8'b00110101; end
4'b0110:begin dig0<= 8'b00110110; end
4'b0111:begin dig0<= 8'b00110111; end
4'b1001:begin dig0<= 8'b00111000; end
default:begin dig0<= 8'b00110000; end
endcase

end
always@(d1)
begin
case (d1)
4'b0000:begin dig1<= 8'b00110000; end
4'b0001:begin dig1<= 8'b00110001; end
4'b0010:begin dig1<= 8'b00110010; end
4'b0011:begin dig1<= 8'b00110011; end
4'b0100:begin dig1<= 8'b00110100; end
4'b0101:begin dig1<= 8'b00110101; end
4'b0110:begin dig1<= 8'b00110110; end
4'b0111:begin dig1<= 8'b00110111; end
4'b1001:begin dig1<= 8'b00111000; end
default:begin dig1<= 8'b00110000; end
endcase
end
endmodule
 d) 4-bit SISO shift register display result on LEDs

module shift_reg (D, Qout,Lshift,CLK,clr, Ld, Sh, Shiftin);

parameter N = 4;
output[N:1] Qout;//paralle output
input[N:1] D;//paralle input
input CLK,clr;
input Ld;//parallel load
input Sh;//shift enable
input Shiftin,Lshift;
reg[N:1] Q;
reg[N:1] shifter;
assign Qout = Q ;
//Left and right shift stored in shifter register
always@(posedge CLK or Lshift)
begin
if(Lshift)
shifter = {Q[N - 1:1], Shiftin} ; //left shift register
else
shifter = {Shiftin, Q[N:2]} ; //right shift register
end
always @(posedge CLK)
begin
if(clr)
Q<=4'b0000;
else if (Ld == 1'b1)
begin
Q <= D ; //parallel load
end
else if (Sh == 1'b1) //shift enabled
begin
Q <= shifter ;
end
end
endmodule
Waveform:
7. Draw the state diagram and write Verilog code for Sequence
Detector to detect the sequence 1010. Consider the overlapping of
the sequence. System takes one bit as input and produces one-bit
output.

module seq1010(clr,d,clk,y);
input clr,d,clk;
output y;
reg [2:0] state;
reg [2:0] nstate;
reg y;

always @(clr or posedge clk)

begin
if (clr==1'b1)
begin
nstate=3'b000;
state=3'b000;
end
else
state=nstate;
end
always@(state or d)

begin
case (state)
3'b000:
begin
y=1'b0;
if (d == 1'b1)
nstate = 3'b001;
else
nstate =3'b000;
end
3'b001:begin
y=1'b0;
if (d == 1'b0)
nstate = 3'b010;
else
nstate =3'b001;
end

3'b010:begin
y=1'b0;
if (d == 1'b1)
nstate = 3'b011;
else
nstate =3'b000;
end

3'b011:begin
y=1'b0;
if (d == 1'b1)
nstate = 3'b001;
else
nstate =3'b100;
end
3'b100:begin
y=1'b1;
if (d == 1'b1)
nstate = 3'b011;
else
nstate =3'b000;
end
default :nstate = 3'b000;
endcase
end
endmodule

Waveform:
8 Write Verilog test bench to automate programs/design
a) Fulladder
Design:
module FUlladderprimitive(a,b,c,s,cout);
input a,b,c;
output cout,s;
wire s0,s1,s2;
xor (s,a,b,c);
and (s0,a,b);
and (s1,a,c);
and (s2,c,b);
or (cout,s0,s1,s2);
endmodule

Test bench:
module testbench_FUlladderprimitive();
reg a,b,c;
wire s,cout;

FUlladderprimitive t1(a,b,c,s,cout);//DUT

initial
begin

// Dump waves

$dumpfile("dump.vcd");
$dumpvars(1);

$monitor("a:%b,b:%b, c:%b,s:%b,cout:%b",a,b,c,s,cout);

a=1'b0;b=1'b0;c=1'b0;
#10
a=1'b0;b=1'b0;c=1'b1;
#10
a=1'b0;b=1'b1;c=1'b0;
#10
a=1'b1;b=1'b0;c=1'b1;
#10
a=1'b1;b=1'b1;c=1'b1;
#10
#80 $finish;
end
endmodule
b) 3:8 decoder with active lowoutput
Design:
module decodr3_8(input a,b,c, output [0:7]y);
assign y[0] = ((~a)&(~b)&(~c));
assign y[1] = ((~a)&(~b)&(c));
assign y[2] = ((~a)&(b)&(~c));
assign y[3] = ((~a)&(b)&(c));
assign y[4] = ((a)&(~b)&(~c));
assign y[5] = ((a)&(~b)&(c));
assign y[6] = ((a)&(b)&(~c));
assign y[7] = ((a)&(b)&(c));
endmodule

Testbench:
module testbench_decodr3_8();
reg a,b,c;
wire [0:7]y;
decodr3_8 t1 (a,b,c,y);
initial
begin
//dump waves

$dumpfile("dump.vcd");
$dumpvars(1);
$monitor("a:%b,b:%b,c:%b,y:%b",a,b,c,y);
a=1'b0;b=1'b0;c=1'b0;
#80 $finish;
end
always #40 a=~a;
always #20 b=~b;
always #10 c=~c;
endmodule
c) 4:1 MUX
Design:
module mux41c (s0,s1,a,b,c,d,y);
input s0,s1,a,b,c,d;
output y;

assign y= (s0) ? (s1? d: c) ://true

( s1 ? b: a);//false
endmodule

Testbench:

module test_mux41if;
reg s0,s1,a,b,c,d;
wire y;
mux41c t1(s0,s1,a,b,c,d,y);

initial
begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);
$display("input option1");
{s0,s1}=2'b00;{d,c,b,a}=4'b0001;
#10;
display;
$display("input option2");
{s0,s1}=2'b01;{d,c,b,a}=4'b0010;
#10;
display;
$display("input option3");
{s0,s1}=2'b10;{d,c,b,a}=4'b0100;
#10;
display;
$display("input option4");
{s0,s1}=2'b11;{d,c,b,a}=4'b1000;
#10;
display;
#1;$finish;
end
task display;
#1 $display("s0:%0b,s1:%0b,a:%0b,b:%0b,c:%0b, d:%0b, y:%0b",
s0,s1,a,b,c,d,y);
endtask
endmodule
d) for 4-bit up/down counter with parallel load

Design:
module updown_counter_4bit (Out, In, S, C, F, Clk);
input [3:0]In;
output [3:0]Out;
input S,C,F,Clk;
reg [3:0]Out;
always @(negedge Clk)
begin
if (S==1'b1)
Out=In; // parallel load
else if (C==1'b1)
Out=4'b0000;// clear
else if(F==1'b1)
Out=Out+1'b1;// up counter
else
Out=Out-1'b1;// down counter
end
endmodule

Testbench:
module test_dffmy;
reg [3:0]In;
wire [3:0]Out;
reg S,C,F,Clk;

updown_counter_4bit t1(Out, In, S, C, F, Clk);

initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);
Clk=0;C=0;S=1;F=0;In=4'b0011;
#20;
C=1;S=0;F=0;In=4'b0011;
display;
#40;
C=0;S=0;F=0;In=4'b0011;
#20;
C=0;S=1;F=0;In=4'b0011;
display;
#20;
C=0;S=0;F=1;In=4'b0011;
display;
#160 $finish;
end
always #5 Clk = ~Clk;

task display;
#1 $display("Clk:%0b, In:%0b, S:%0b, C:%0b,F:%0b,Out:%0b",
Clk,In, In, S, C, F, Out);
endtask
endmodule