Nguyễn Ngọc Hưng - 20226044

Báo cáo Computer Architecture

Lab 11

Assignment 1:

.eqv IN_ADDRESS_HEXA_KEYBOARD 0xFFFF0012

.eqv OUT_ADDRESS_HEXA_KEYBOARD 0xFFFF0014

.text
main:
# Load the addresses for input and output of the keypad
li t1, IN_ADDRESS_HEXA_KEYBOARD # Address to select row
li t2, OUT_ADDRESS_HEXA_KEYBOARD # Address to read key press
li t3, 0x08 # Start with row 0x08
li t4, 0x0f

polling:
# Poll the selected row
slli t3, t3, 1 # Get to next row
rem t3, t3, t4 # Return to row 1
sb t3, 0(t1) # Set the expected row (must reassign every time)
lb a0, 0(t2) # Read the scan code of the key pressed

print:
# Print the scan code (hexadecimal)
li a7, 34 # Syscall to print integer in hex
ecall

sleep:
# Sleep to avoid overwhelming the simulation tool
li a0, 100 # Sleep for 100ms
li a7, 32 # Syscall for delay
ecall

back_to_polling:
j polling # Loop back to polling

Explanation of the Code

1. Addresses:
◦ IN_ADDRESS_HEXA_KEYBOARD (0xFFFF0012): Pick row.
◦ OUT_ADDRESS_HEXA_KEYBOARD (0xFFFF0014): Used to read the key
scan code. If no key is pressed, it returns 0x00.

1

 2. Polling Process:
◦ Mỗi 100ms, subroutine polling sẽ "hỏi" giá trị địa chỉ phím được nhấn

3. Upgrade:

li t4, 0x0f
polling:
slli t3, t3, 1 # Get to next row
rem t3, t3, t4 # Return to row 1

◦ The program has been modi ed so it the current row is (t3 << 1) % 15
so it’s a cycle of 0x01 —> 0x02 —> 0x04 —> 0x08 —> 0x01 —> …

Assignment 2:

How It Works

1. Initialization:
◦ The ISR (handler) is set up to handle interrupts.
◦ External interrupts are enabled for the keypad using uie and ustatus.
◦ The keypad is con gured to generate an interrupt when any key is pressed.
2. Main Program:

◦ The CPU enters an in nite loop (loop) where it executes nop. It simulates a
scenario where the CPU can perform other tasks, but in this case, it does
nothing signi cant.
3. Interrupt Handling:

◦ When a key is pressed, the interrupt is triggered:

▪ The CPU jumps to the ISR (handler) de ned at the address stored
in utvec.
▪ The ISR saves the current CPU state, prints a message ("Someone's
pressed a button."), and restores the CPU state.
▪ The CPU resumes the main program (loop).

2

fi
fi
fi
fi
fi
 Assignment 3:

Key Steps in the Code

1. Main Program

• Counter (s0):
◦ The counter increments in each iteration and its value is printed using syscall
1.
• Delay:
◦ The main program sleeps for 300ms between iterations to avoid overwhelming
the console.
2. Interrupt Con guration

• ISR Address:
◦ The address of the ISR (handler) is loaded into the utvec register.
• Enable Interrupts:
◦ Global and external interrupts are enabled via the ustatus and uie
registers.
• Keypad Interrupt:
◦ The keypad is con gured to generate an interrupt when any key is pressed.
3. Interrupt Service Routine (ISR)

• Context Saving:
◦ The registers (a0, a7, t1, t2) used in the ISR are saved on the stack.

• Message Display:

◦ A message ("Key scan code:") is printed to indicate a key press.

• Key Scan Code:

◦ The scan code of the pressed key is retrieved from the
OUT_ADDRESS_HEXA_KEYBOARD.
◦ This scan code is printed in hexadecimal format using syscall 34.

• Context Restoration:
◦ The saved registers are restored, and the stack is deallocated.

• Return:
◦ The ISR concludes with a uret instruction, returning control to the main
program.

Expected Behavior

• The program continuously prints a sequence of numbers (e.g., 1, 2, 3, ...) every

300ms.
• When the user presses one of the keys (C, D, E, F):

3

fi
fi
 1. A message "Key scan code:" is displayed.
2. The scan code of the key is printed (e.g., 0x28 for D).

Assignment 4:

Key Steps in the Code

1. Main Program

• Timer Con guration:

◦
The timer is set to trigger an interrupt every 1000ms (1 second) by writing a
comparison value to TIMER_CMP.
◦ After each timer interrupt, this value is updated for the next interval.
• Keypad Interrupt Con guration:

◦ The keypad is con gured to generate interrupts when any key is pressed.
• In nite Loop:

◦
The main program does nothing meaningful (nop) and only demonstrates that
interrupts are handled independently.
2. ISR (Interrupt Service Routine)

• Context Saving:
◦ The registers used in the ISR (a0, a1, a2, a7) are saved on the stack to
prevent data corruption.
• Interrupt Classi cation:
◦ The cause of the interrupt is determined by reading the ucause register.
◦ The value is masked to exclude the interrupt bit and matched with
MASK_CAUSE_TIMER or MASK_CAUSE_KEYPAD.
• Timer Interrupt Handling:
◦ Prints the message "Time interval!".
◦ Updates the timer comparison value to schedule the next interrupt.
• Keypad Interrupt Handling:
◦ Prints the message "Someone has pressed a key!".
• Context Restoration:
◦ The saved registers are restored, and control is returned to the main program.

Expected Behavior

• The program prints "Time interval!" every 1 second due to the timer
interrupt.
• When a key is pressed, the program prints "Someone has pressed a
key!".

4

fi
fi
fi
fi
fi
 5

 Assignment 5:

Explanation of the Code

1. Setting Up Exception Handling

• utvec Register:

◦ The program sets the address of the exception handler (catch) in the
utvec register using csrrw.
• Global Interrupt Enable:

◦ By setting the UIE bit (bit 0) in the ustatus register, exceptions are
enabled.
2. Try Block

• The try section deliberately triggers an exception by attempting an invalid memory

access (lw zero, 0). This operation attempts to load a value from an invalid
memory address (0x0), causing a load access fault.
3. Exception Handler (Catch Block)

• When an exception occurs:

◦ The CPU jumps to the handler (catch).

◦ The handler prints the message "Exception occurred." using
syscall 4.
• Redirect Execution:

◦ After handling the exception, the program resumes execution at the

finally block by updating the uepcregister with the address of
finally.
4. Finally Block

• The finally section performs cleanup or program termination.

• In this case, the program exits gracefully using syscall 10.

6

 Assignment 6:

.data
message: .asciz "Software interrupt triggered due to overflow.\n"
no_interrupt_msg: .asciz "No interupt"
.text
main:
# Set up the interrupt service routine
la t0, handler # Load address of ISR
csrrw zero, utvec, t0 # Set ISR address in utvec

# Enable software interrupts

li t1, 0x1 # USIP bit (bit 0)
csrrs zero, uie, t1 # Enable software interrupts in uie

# Enable global interrupts

csrrsi zero, ustatus, 0x1 # Enable global interrupts (UIE bit in
ustatus)

# Initialize values for addition

li t1, 0x7fffffff # Maximum positive signed integer
li t2, 1 # Value to add (causes overflow)

# If 2 inputs have different sign then they can't overflow

xor t3, t1, t2
bltz t3, no_overflow

# Perform addition and check for overflow

add t3, t1, t2 # t3 = t1 + t2
xor t3, t3, t1 # Check if results have different sign
from input
bltz t3, trigger_interrupt # If signs are different then it has
overflow

no_overflow:
# If no overflow, print success and exit
li a7, 4 # Syscall to print string
la a0, no_interrupt_msg
ecall

li a7, 10 # Syscall to exit program

ecall

trigger_interrupt:
# Trigger software interrupt by setting USIP bit in mip
li t1, 0x1 # USIP bit (bit 0)
csrrs zero, uip, t1 # Set software interrupt pending in uip

# -----------------------------------------------------------------
# Interrupt Service Routine (ISR)
# -----------------------------------------------------------------
handler:
# Save context
addi sp, sp, -8
sw a0, 0(sp)

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 sw a7, 4(sp)

# Display interrupt message

li a7, 4 # Syscall to print string
la a0, message
ecall

# Restore context and exit

lw a7, 4(sp)
lw a0, 0(sp)
addi sp, sp, 8

li a7, 10 # Exit program

ecall

Key Steps in the Code

1. Setting Up the ISR

• The address of the ISR (handler) is loaded into the utvec register.
• Software interrupts are enabled by setting the USIP bit (bit 0) in the uie register.
• Global interrupts are enabled by setting the UIE bit (bit 0) in the ustatus register.
2. Integer Over ow Detection

•Two integers are added:

◦ t1 is initialized with the maximum positive value for a signed 32-bit integer
(0x7FFFFFFF).
◦ t2 is initialized with 1.
• The result (t3) is checked:
◦ If the result is negative (bltz), an over ow has occurred, and a software
interrupt is triggered.
3. Triggering a Software Interrupt

• To trigger the interrupt, the USIP bit (bit 0) in the uip register is set.
4. ISR Execution

• When the interrupt occurs:

◦ The CPU jumps to the ISR (handler).
◦ The ISR saves the context, prints the message "Software interrupt
triggered due to overflow.", and exits the program.

8

fl
fl
 CONCLUSION (NO CHATGPT):

1. What is Polling?

• Trong mối quan hệ CPU và IO devices thì Polling giống việc: CPU - thứ
đảm nhiệm việc process được chạy, phải đồng thời chủ động 'hỏi' về
trạng thái của IO devices (sau mỗi khoảng thời gian).

2. What is Interrupt?

• Cùng trong mối quan hệ trên thì Interrupt giống việc: CPU chỉ cần đảm
nhiệm việc chạy process, còn IO devices nếu có thay đổi về trạng thái thì
chính nó sẽ chủ động thông báo cho CPU.

3. What is Interrupt Service Routine?

• Chương trình khi bị interrupt sẽ bị ngăn không cho chạy tiếp mà phải
chạy một đoạn subroutine để xử lí lệnh interrupt trước khi được chạy
tiếp.

4. What are the advantages of Polling?

• Thiết lập quá trình polling rất đơn giản, phù hợp cho những chương trình
không đòi hỏi độ phức tạp cao.

5. What are the advantages of Interrupt?

• Sự phức tạp của nó đem lại sự hiệu quả về mặt hiệu năng khi không
phải tiêu tốn tài nguyên CPU.

• Có thể tạo ra những subroutine để xử lí lệnh interrupt một cách linh hoạt
hơn.

6. Distinguish between Interrupt, Exception and Trap?

• Interupt: Là interrupt do phần cứng gây ra, cụ thể là những thiết bị IO và

CPU

• Exception: Là interrupt phần mềm gây ra bởi một điều kiện bất kì.

• Trap: Là một loại interrupt phần mềm gây ra bởi những những lỗi điển hình
như là (breakpoint, divide by 0, invalid memory access).

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