Demux 1 8 1 4
Demux 1 8 1 4
module demux_21(
input sel,I,
output Y0,Y1
);
endmodule
//Testbench Code
initial begin
// Initialize Inputs
sel = 0;
I = 0;
end
endmodule
module demux_1_to_4(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);
endmodule
initial begin
// Initialize Inputs
d = 1;
s0 = 0;
s1 = 0;
#100;
end
endmodule
//1:8 demux
module demux_81_1(
input in,s0,s1,s2,
output d0,d1,d2,d3,d4,d5,d6,d7
);
module demux_8_1_test;
// Inputs
reg in;
reg s0;
reg s1;
reg s2;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;
demux_81_1 uut (
.in(in),
.s0(s0),
.s1(s1),
.s2(s2),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
// Initialize Inputs
in = 0;
s0 = 0;
s1 = 0;
s2 = 0;
#100;
in = 1;
s0 = 0;
s1 = 1;
s2 = 0;
#100;
#100;
in = 1;
s0 = 1;
s1 = 1;
s2 = 0;
#100;
end
endmodule