Place and Route

1. PnR Flow:

2. Inputs of PnR:
• Netlist(.V)
• Updated SDC(Standard Design Constraints)
• .lib (Liberty or Library file)
• .lef(Library Exchange Format)
• TLU+ (Table Look Up)
• Captable File
• UPF(Unified Power Format).
3. DEF (Design Exchange Format):
DEF File is a text file which consist of :
• Placement info
• Pin Locations
• Metal Blockages
• Orientation
• Macro Placement Info
4. UPF (Unified Power Format):
UPF contains :
• supply set definition,
• power domain definition,
• power switch definition
• retention cell definition
• level shifter cell definition and other low power related definition.
5. TLU(Table Look Up):
It is a table containing wire capacitance at different net length and spacing. contain RC
coefficients for specific technology.
6. Manufacturing Deviations:
Minimum spacing rules to be followed to consider manufacturing deviations,
otherwise adjacent nets gets shorted if the deviation on the adjacent nets is opposite.
7. Pitch:
The distance between the centre to centre of the metal is called as pitch.
8. Offset:
Offset is the distance between the core and first metal layer.
9. Core:
A 'core' is the section of the chip where the fundamental logic of the design is placed.
10.Die:
Die is the combination of core area and I/O pad area.
11.Package:
The package is a case that surrounds the circuit material to protect it from corrosion
or physical damage and allow mounting of the electrical contacts connecting it to the
printed circuit board (PCB).
12.I/O Pads:
• Input/ Output circuits (I/O Pads) are intermediate structures connecting internal
signals from the core of the integrated circuit to the external pins of the chip
package.
• Typically I/O pads are organized into a rectangular Pad Frame.
• The input/output pads are spaced with a Pad Pitch.
13.I/O Voltage:
The Voltage which powers the I/O Pads.
14.Core Voltage:
Core voltage is the voltage which powers the Logic Blocks ,logic cells in the core area.
15.OBUF:
Output Buffer is used to drive the signal from the design to the external output pads.
16.IBUF:
Input Buffer is used to drive the signal from the external pads to the design.
17.Level Shifters:
Level Shifters (LS) are special standard cells used in Multi Voltage designs to covert one
voltage level to another.
18.STD.Cell Utilization:
The ratio of the total std. cell area to the core area is known as std. cell utilization.
19.Core Utilization:
The Ratio of the std.cell area, macro area and blockage are to the total core area.

𝑆𝑡𝑑. 𝑐𝑒𝑙𝑙 𝑎𝑟𝑒𝑎 + 𝑀𝑎𝑐𝑟𝑜 𝑎𝑟𝑒𝑎 + 𝐵𝑙𝑜𝑐𝑘𝑎𝑔𝑒

𝐶𝑜𝑟𝑒 𝑈𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛 =
𝑇𝑜𝑡𝑎𝑙 𝐶𝑜𝑟𝑒 𝐴𝑟𝑒𝑎
25.Aspect Ratio:
It is the Ratio of the Height of the core and the Width of the core.
𝐻𝑒𝑖𝑔ℎ𝑡 𝑜𝑓 𝑡ℎ𝑒 𝑐𝑜𝑟𝑒
𝐴𝑠𝑝𝑒𝑐𝑡 𝑅𝑎𝑡𝑖𝑜 =
𝑊𝑖𝑑𝑡ℎ 𝑜𝑓 𝑡ℎ𝑒 𝑐𝑜𝑟𝑒
26. Abutting:
In Abutting type design there will be no space between the two blocks. So that these
blocks touch each other.
27. PG Mesh:
Each of these stripes run both vertically and horizontally at regular interval then this is
called power mesh.
30. Site:
The smallest unit of placement where the smallest cell can be placed is called as SITE.
31. IA:
A via is an electrical connection that establishes the connectivity between two layers.
32. Follow Pin:
A follow pin connects VDD and VSS pins of all std. Cells to the power mesh.
33. SSO Analysis:
34. Timing Driving Placement:
Tool tries to place the standard cells along timing critical path close together to reduce
net RC and meet setup timing.
35. Congestion driven placement:
Tool tries to spread the cells where the density of cells are more for the reduction of
congestion.
36. Core Limited Design:
Core logic dictates the die dimension is called core limited design.
37. Pad Limited Design:
I/O pads dictates the die dimension is called pad limited design.
38. Design Partitioning:
Partitioning is a process of dividing the chip into small blocks. This is done mainly to
separate different functional blocks and also to make placement and routing easier.
39. Manufacturing Grid :
The minimum metal length that can be manufactured is called manufacturing grid.
40. Routing Tracks:
Routing Tracks are imaginary lines that tools would divide the whole routing area. Tool
use these tracks as a reference for routing the nets. While routing tool will route such
that routing tracks falls exactly to center of the route.
41. Macro:
Macros are the memory cells. There are two types of macro:
• Hard Macro (Placement is Fixed)
• Soft Macro (Can be moved while optimizing the design).
42. Fly-line Analysis:
Fly line analysis is the virtual lines which shows the connections between the blocks,
While doing manual floor planning.
43. Floorplan Guidelines:

• All the macros should be placed at periphery of the core boundaries but not at the
center of the core.
• Macros are to be placed such that pins must face towards the core area.
• Macros should not contain criss crossing.
• There must be a space between two macros.
• The space between a macro and core boundary is = (Total no. of pins/No. of vertical
layers) x pitch
• Halo should be specified around the macros.
• Notches should be avoided.
44. Types of Blockages:
Blockages are used to avoid the congestion in our design. There are 2 types of
blockages
• Placement Blockage.
(a) Soft Blockage:
This Blockage allows only optimization cells to be place in it.
(b) Partial Blockage:
It allows only specified percentage of cells to be placed.
(c) Hard Blockage:
It does not allow any cells to be placed.
• Routing Blockage.
It allows only some specified metal layers inside the blockage.
45. Stack Via and Via Array

• A stacked via consists of multiple vias layered directly on top of each other.
• Array vias are used for connecting wide wires where the required cut size would
exceed the maximum cut size of the simple via.
 ARRAY VIA

STACK VIA

46. Halo:
Halo is special hard blockage around the macro which blocks the placement of std.
cells near the macro.
47. Physical Cells:
These cells are not present in the design netlist. if the name of a cell is not present in
the current design, it will consider as physical only cells. they do not appear on timing
paths reports they are typically invented for finishing the chip.
48. Tap Cells:

• Used to avoid the latch.

• It creates low impedance path between the VDD and VSS.
• Well tap connects N-Well to VDD and P-Sub to VSS.
• It is place in pre-placement stage.

CMD : addWellTap -cell FILL1 -cellInterval 60 -fixedGap -InrowOffset 30 -

StartRowNUM 2 -SkipRow 1 -Prefix WELLTAP

49. Tie Cells:

• Used to connect constant High and Constant Low.

• Its Creates high impedance path between power rail & gate of cell.
• It is placed in placement stage

CMD : addTieHiLo -cell “NAME” -Prefix “NAME”

50. END CAP cells:

• Used to avoid cell damage which are placed at core boundary & to main row
continuity.
• These are placed at pre-placement stage.

CMD: addEndCap -preCap FILL1 -PostCap FILL1 -Prefix ENDCAP.

51. De Cap cells:

• Used to fix IR issue in power grid.

• These cells are placed between VDD and VSS.
• These are placed at power planning stage.

CMD: addDecapCellCandidates DECAP10 10

addDeCap -totCap 1000 -cells DECAP 10 DECAP 9

52. Spare Cells:

• Used to fix bugs in functionality at the time of tape out.

• These cells are connected to VDD and VSS through the Tie Cells.
• Generally, we use 2-3% of spare cells in design.
• These are placed at placement
CMD: SpecifySpareGate -Cell “NAME”
stage.
53. Filler Cells:

• Used to maintain N-well continuity.

• These are placed after the routing stage.

CMD: addFiller -Cell “FILL1” -Prefix “FILLER”

54. Double Cut Via:

If two vias are provided for each connection point, such via is called a "double-cut via".
55. Redundant Via:
The occurrence of via defects Increases due to the shrinking size in integrated circuit
manufacturing Redundant via insertion is an effective and recommended method to
reduce the yield loss caused by via failures In this paper we introduce the redundant
via allocation problem for layer partition based redundant via insertion methods
56. Cell Padding:

• Cell padding is used to avoid the congestion caused by high pin density cells. For
these cells we reserve some site by using cell padding technique.
• Cell padding is done for specified cell name in the design.
57. Instance Padding:

• This is done for particular instance in the design.

58. Scaling factor:
To co-relate the delays between PnR tool and signoff tool we are using scaling factors.
By using scaling. factors co-relation differences are included in advance in PnR tool. So
that in sign-off tools the timing and RC values almost match with final sign-off quality
tools. Hence the iterations are reduced.
59. Trail Route:
Trial Route will give idea on routing congestion at early stage so that one can avoid
iterations and save timing.
60. Gcell:
The chip is divided into small blocks. These small blocks are called routing bin. The size
of the routing bin depends on the algorithm the tool uses. Each routing bin is also
called a GCELL.The size of this gcell depends on the tool.Each gcell has a finite number
of horizontal and vertical tracks.
61. Over-Commiting:
If tool uses already used routing tracks, then it is called Over-Comitting.
62. Congestion:
When the number of routing tracks available for routing in a given location is less than
the number necessary, the area is considered congested and hence, is termed as
congestion.
63. Area Reclamation:
It is optimizing area without affecting timing.
Ex: Replacing high drive strength with low drive strength cells where ever possible.
64. CTS:
The process of distributing the clock to all sequential elements and balancing the
minimum skew is called CTS.
65. Goals Of CTS:

• Minimum Skew
• Minimum latency
• DRV’s
66. Leaf Pin:
The flop pin where the cts stops balancing the skew is known as leaf pin.
67. Root Pin:
The start point of the clock is called root pin.
68. Clock Insertion Delay:
The delay between the source of the clock signal and the flip-flop clock pin is known
as Clock Insertion Delay.

69. Through Pin:

All clock pins of a generated clock flop.
70. Macro Model:
We specify the Insertion delay inside the macro as macro model for proper balancing
the skew.
71. Rise Skew:
It is the max difference of all the arrival times of the clock signal at the leaf pin inputs
as measured from rising edge at the clock root.
72. Fall Skew:
It is the max difference of all the arrival times of the clock signal at the leaf pin inputs
as measured from falling edge at the clock root.
73. Trigger Edge:
It is based on all the arrival times of the clock signal at the leaf pin input.
74. Bogus I/O Slack:
After CTS In to Reg paths slacks would get improved by the amount of clock insertion
delay and reg to out timing get deteriorated by the amount equal to clock insertion
delay.
75. Exclude Pin:
Exclude pin are clock tree endpoints that are excluded from clock tree timing
calculation and optimization. The tool considers exclude pins only in calculation and
optimizations for design rule constraints. During CTS, the tool isolates exclude pins
from the clock tree by inserting a guide buffer before the pin or these pins are need
not to be considered during the clock tree propagation.
Example - Non clock input pin of sequential cell.
76. Float pin:
Float pins are clock pins that have special insertion delay requirements and balancing
is done according to the delay [Macro modelling]. This is same as sync pin but internal
clock latency of the pin is taken into consideration while building the clock tree. To
adjust the clock arrival for specific endpoints with respect to all other endpoints.
Example - Clock entry pin of hard macros.
77. Stop pin:
Stop pins are the endpoints of clock tree that are used for delay balancing. In CTS, the
tool uses stop pins in calculation & optimization for both DRC and clock tree timing.
Example - Clock sink are implicit stop pins.
 The clock signal should not propagate after reaching the stop/sync. This pin needs to
be considered for building the clock tree.
78. Detail Route:

• Detailed routing follows up with the track routed net segments and performs
the complete DRC aware and timing driven routing.
• It is the final routing for the design built after the CTS and the timing is freeze
• Filler Cells are adding before Detailed Routing
• Detail Routing is done after analyze the cause for congestion in the design, add
density screen or change floorplan etc.
79. Max_dept :
This parameter indicates no. of logic levels that tool can trace through before CTS is
done.

80. RC Corners:
RC Corners are the wire delay corners which we use for timing analysis
• RC_Worst
• RC_Best
• C_Worst
• C_Best
81. SPEF(Standard Parasitic Extraction Format):

• SPEF mainly contains extracted RC values of every single net in the design.
• It is the input to the STA where we can get accurate RC delays of the net.
82. Design Modes:

• MBIST MODE
• JTAG MODE
• SCAN SHIFT MODE
• SCAN CAPTURE MODE
 • FUNCTIONAL MODE.
83. Rise and Fall Glitch:
Whenever one net switches from low to high and other neighbouring net is supposed
to remain constantly low, will get affected by the switching net due to the mutual
capacitance in that case we have a rising glitch on it.

Whenever one net switches from high to low and other neighbouring net is supposed
to remain constantly high, will get affected by the switching net due to the mutual
capacitance in that case we have a falling glitch on it.
84. Increase in Cell Delay (Factors):

• Input Skew
• Library Setup Time
• Operating Conditions
• Wire Load Models
• Input Transition
• Output load Capacitance.
85. Glitch Analysis:

• Glitch analysis depends upon the height because of this height it could be safe
or unsafe.
• If the glitch height is in between Vol and Vil then it is safe.
• If the glitch height is in between Vih and Voh then it is unsafe.
• If the glitch is in between undefined region then it is unpredictable.
• The glitch height depends upon the factors
➢ Coupling Capacitance
𝐶𝑚
ℎ𝖺
𝐶1+𝐶2

1
𝐶𝑚 𝖺
𝐷
➢ In lower node technologies the distance(D) Cm So the height(h) is
more. So the glitch will be in unsafe.
 • Aggressor drive strength is more, the slew rate is faster, higher the crosstalk.
• Victim drive strength is more, lower the crosstalk.

86. Delay Analysis:

The sole distinction between crosstalk delay and crosstalk noise is that the nets are not
at steady state values and some switching activities are occurring on both the victim
and aggressor nets. The propagation orientation of the aggressor and victim nets
influences crosstalk delay. This causes either a slower or quicker transition of victim
nets.
87. Dishing:
This refers to an increase in the surface topography of a composite structure, primarily
due to the difference in CMP removal rate between the two (or more) materials of the
composite. The dishing occurs in the material component with a higher removal rate.
88. Erosion:
The SiO2 Erosion is defined as the difference in the SiO2 thickness before and after the
polish step.
http://www.vlsi-expert.com/2015/08/dishing-and-erosion-cmp.html
89. Clock Tree Jitter:
It can be defined as “deviation of a clock edge from its ideal location.”
90. Load Splitting:

• Load Splitting is the technique which adds the buffer in high fanout nets and
divides the load.
• For max_tran violation we use this technique to reduce it.
91. DRC(Design Rule Check):
Design Rule Checking (DRC) verifies as to whether a specific design meets the
constraints imposed by the process technology to be used for its manufacturing.
92. Module Constraints Types: Guide, Fence, Region
Sometimes we need to place a particular group of standard cells or modules in a
particular area (box).
93. Fence:

• The fence is assigned with certain cells in the design.

• A fence does not allow the assigned cell to sit outside the box defined.
• A fence does not allow the other cells to sit inside the box also. So the area is
exclusively reserved for the assigned cells.
• It is a hard constraint
94. Region:

• The region is assigned with certain cells in the design.

• A region does not allow the assigned cell to sit outside the box defined.
• It may cause congestion in the area assigned if not chosen the area wisely.
• The only difference between the region and the fence is that it allows the other
cells to sit inside the box.
• It is a hard constraint
95. Guide:

• The guide is assigned to certain cells in the design

• The guide allows to assigned cell sit outside the box
• It also allows the other cells to sit inside the box.
• It is a soft constraint.
 Sign-off:
1. Latch Up:

Latchup refers to short circuit/low impedance path formed between power and
ground rails in an IC leading to high current and damage to the IC. It occurs due to
interaction between parasitic pnp and npn transistors. The structure formed by these
resembles a Silicon Controlled rectifier (SCR).

2. Antenna Effect:

The oxide layer is often only a few molecules thick, and if enough charge builds up,
the thin oxide layer breaks down, damaging or even completely destroying the MOSFET.
This accumulation of charge is usually, and misleadingly, called the antenna effect.

𝑀𝑒𝑡𝑎𝑙 𝐴𝑟𝑒𝑎
𝐴𝑛𝑡𝑒𝑛𝑛𝑎 𝑅𝑎𝑡𝑖𝑜 =
𝐺𝑎𝑡𝑒 𝐴𝑟𝑒𝑎
3. Electro Migration:
Electromigration is the movement of atoms based on the flow of current through
a material. If the current density is high enough, the heat dissipated within the material
will repeatedly break atoms from the structure and move them. This will create both
‘vacancies’ and ‘deposits’. The vacancies can grow and eventually break circuit
connections resulting in open-circuits, while the deposits can grow and eventually
close circuit connections resulting in short-circuit.
• Here the vacancies are called voids.
• The deposits are called hillocks.

4. IR Drop:
IR drop is the voltage drop in the metal wires constituting the power grid before
it reaches the power pins of the standard cells. It becomes very important to limit the
IR drop as it affects the speed of the cells and overall performance of the chip. There
are two types of IR drops:
• Static - Vstatic_drop = Iavg x Rwire [Iavg are all factors of leakage currents ]
• Dynamic - Vdynamic_drop = L (di/dt) [current L is due to switching current]
5. Cross Talk:

Crosstalk is a phenomenon that occurs when a signal carried on one net of a

transmission system causes an undesirable effect in another net, due to coupling
capacitance formed between them. The net which is effected is called victim net, the
net which effects is called Aggressor.
6. Overshoot and Undershoot:

If a signal voltage level goes above the VDD value is called Overshoot.
If a signal voltage level goes below the VSS value is called Undershoot.
7. ECO Flow:

Engineering change order (ECO) refers to a practice in the VLSI design flow to
accommodate specification changes, to rectify functional errors, or to fix non-
functional design requirements, such as timing and power, with minimal disturbance
to the existing implementation, to save as much as possible the already-spent
optimization efforts.
8. Metal Density Check:

Density check is performed to check the even density through out the chip which
required for manufacturing process to ensure the mechanical sturdiness of the chip to
achieve planarity during CMP (Chemical Mechanical Polishing). Different density
checks verify the overall density of each metal and densities per unit area.
9. Why the Metal Fill is required?

If there is lot of gap between the routed metal layers (empty tracks), during the
process of Etching the etching material used will fall more in this gap due to which
Over Etching of existing metal occurs which may create opens. So in order to have
uniform Metal Density across the chip, Dummy Metal is added in these empty tracks.