Index

Marks Awarded-Day to Day

activities
Sign of

Performing the

Completion of
Record Work
the

Attendance
Knowledge
experiment

(5 Marks)

(5 Marks)
(5 Marks)
Technical
(5 Marks)
S.No Date Name of the experiment Faculty
with
Date

10

Max. Marks Sign of the

Internal Calculation Marks Awarded Faculty
Average of Day to day Activity 20
Mini Project 10
Model Exam 10
Assignment/Simulation 10
Total 50

Sign of the Student Sign of Lab Incharge

Format no.: LA 12b Rev.No: 0.0 Rev.Date : 08.11.23

Exp 1 Modelling and Sources of Power Consumption

Aim
To write SPICE code for Modelling of Inverter, AND gate and estimate the power
consumption

Theory
SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose circuit
simulator which is used as an essential computer-aided design (CAD) tool for circuit design.
SPICE has three built-in MOSFET models:
 LEVEL 1 (MOS1) is described by a square-law current-voltage characteristic
 LEVEL 2 (MOS2) is a detailed analytical MOSFET model, and
 LEVEL 3 (MOS3) is a semi-empirical model.
Both MOS2 and MOS3 include second-order effects such as the
i. short-channel threshold voltage,
ii. subthreshold conduction,
iii. scattering-limited velocity saturation, and
iv. Charge-controlled capacitances.

The LEVEL 1 Model Equations:

The equivalent circuit structure of the LEVEL I MOSFET model in SPICE is shown in Fig.
1.

The parasitic source and drain resistances are represented by the resistors RD and Rs.
The voltage-controlled current source ID determines the steady-state current-voltage
behaviour of the device
The voltage- controlled (nonlinear) capacitors connected between the terminals represent the
parasitic oxide-related and junction capacitances.
The source-substrate and the drain-substrate junctions, which are reverse-biased under
normal operating conditions, are represented by ideal diodes in this equivalent circuit.
The nominal channel (gate) length is L and the channel width is W.
Effective channel length Leff is defined as the distance on the surface between the two (source
and drain) diffusion regions.
The equations used for the LEVEL 1 n-channel MOSFET model in SPICE are as follows

Linear region:
K′ 𝑊
ID = 2 . .[2.(VGS-VT)VDS-V2DS].(1+λVDS ) for VGS≥ VT and VDS <VGS -VT
𝐿𝑒𝑓𝑓

Saturation Region
K′ 𝑊
ID = 2 . .(VGS-VT)2 .(1+λ.VDS ) for VGS≥ VT and VDS≥VGS -VT
𝐿𝑒𝑓𝑓

Threshold Voltage:
VT =VT0 + ϒ .( 2∅F +VSB - 2∅F )

Effective Channel Length:

Leff = L- 2.LD
Ɛ𝑜𝑥
K’ = μ. C ox’ where Cox =𝑡𝑜𝑥
2.Ɛ𝑠𝑖.𝑞.𝑁𝐴
ϒ=
𝐶𝑜𝑥
𝑘𝑇 𝑛𝑖
2∅F = 2 𝑞 .ln 𝑁𝐴

Capacitance Models
Gate Oxide Capacitances
SPICE uses a simple gate oxide capacitance model that represents the charge storage effect
by three nonlinear two-terminal capacitors: CGB, CGS, and CGD. The geometry information
required for the calculation of gate oxide capacitances are: gate oxide thickness TOX,
channel width W, channel length L, and the lateral diffusion LD. This information is to be
provided by the user in the respective device description line. The capacitances CGBO,
CGSO, and CGDO, which are specified in the .MODEL statement, are the overlap
capacitances between the gate and the other terminals outside the channel region.The zero-
bias depletion capacitances associated with the bottom junction (CJ) and the sidewall
junctions (CJSW) are found as
𝜀𝑠𝑖 .𝑞 . 𝑁𝐴.𝑁𝐷 1
Cj0 = .∅0
2 𝑁𝐴+𝑁𝐷

𝜀𝑠𝑖 .𝑞 . 𝑁𝐴(𝑠𝑤 ).𝑁𝐷 1

Cj0SW =xj. .∅0
2 𝑁𝐴(𝑠𝑤 )+𝑁𝐷
The gate overlap capacitances per unit length (CGSO and CGDO) are calculated as:
Cgso=CGDO=Cox . LD
Example
1. Simple Inverter

.INCLUDE „../models‟
* This line includes the model file
.DC VIN 0 5 .1
.OPT POST
** Sources ***********
VD VDD 0 5V
VIN IN 0 0
** Inverter Netlist *****
M1 VDD VDD OUT 0 N315 W=5U L=1.2U
M2 OUT IN 0 0 N315 W=10U L=1.2U
.END

2. The top view of an n-channel MOSFET is shown in the figure below. The process
parameters for this device are: NA = 1015 cm-3 NA (sidewall) = 2.1x1016 cm-3 ND = 1020 cm-3 xj
= 0.8µm tox = 600 Ao LD = 0.5 µm The zero-bias threshold voltage is measured as 0.85 V,
and k' is determined to be 45 µA/ V2. The channel length modulation coefficient is A = 0.05.
The source, drain, gate, and substrate nodes of the device are labelled by node numbers 4, 6,
12, and 7, respectively. Prepare the device description line and the .MODEL line for SPICE
simulation. Use the LEVEL 1 model, and avoid conflicting parameter definitions.

M1 6 12 4 7 NM1 W-5U L3U LD-0.5U AS-37.5P P8-25U

+ AD-94.5P PD-43U
.MODEL NMI NMOS (VTO=0.85 P=45U LAMBDA=0.05 GAMMA-
0.32
+ PHI=0.58 PB=0.878 CJ=9.7E-5 CJBW=3.56E-10
+ CGSO=2.87E-10 CGDO=2.87E-10 MJ=0.5
+ MJSW=0.5)
3. AND Gate:

Procedure:
1. Draw the schematics using Digital Schematic Circuit designing software (DSCH
Microwind)
2. Connect the input and output devices to the schematic
3. Save the file
4. Go to File and choose “ make verilog file”.
5. Open Microwind and compile ( choose compile verilog file with .txt extension)
6. Run the program to obtain power estimation.
Output:

Result:
Exp 2 Power estimation at different design levels

Aim
To write Verilog HDL code for Multiplexer in dataflow & gate level and obtain the power
estimation.

Theory:
Example 1:
Multiplexer is a combinational circuit that has maximum of 2n data inputs, „n‟ selection lines
and single output line. One of these data inputs will be connected to the output based on the
values of selection lines.
Truth Table:
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Boolean Expression: Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

Circuit diagram:

Power consumption is dependent on both the physical structures on the chip and the mode of
operation. Simulation tools support the switching activity information needed for power
optimization and power analysis. This information needs to be provided before running
generic synthesis. Switching activity can be annotated into the compiler by loading a .vcd,
.saif, or .tcf file. The functional simulation is carried out to generate the toggle count format
file (.tcf, .saif, or switching activity) by running the testbench on the RTL or synthesized
gate-level netlist. The toggle count format (.tcf) file contains switching activity in the form of
the toggle count information and the probability of the net or pin to be in the logic 1 state.
Synthesis tools propagate the switching activities throughout the design.
Example 2:
Seven segment displays are the output display device that provides a way to display
information in the form of text or decimal numbers. It is widely used in digital clocks, basic
calculators, electronic meters, and other electronic devices that display numerical
information. It consists of seven segments of light-emitting diodes (LEDs) which are
assembled like numerical 8.

Digit A B C D E F G
0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 1
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 0
5 1 0 1 1 0 1 1
6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 0
9 1 1 1 1 0 1 1

Procedure
1. Open the ISE Project Navigator and create a new project. After entering a project
name and location, you'll be prompted for the project properties. Set the properties
and make ISE Simulator as your Simulator.
2. Click Next, and create a new Verilog Module. Choose the inputs and outputs for the
module, click Next and Finish.
3. Run the Check Syntax process (under Synthesize) to make sure your code is entered
correctly, and save your design.
4. Right-click on filename.v in the Sources window and choose New Source. Select
Verilog Test Fixture (not Verilog Module) and give your file a name such as
"test_filename". Click Next, and you'll be prompted to associate the file with a
module; choose filename, click Next, then click Finish. The file will be added to your
project.
5. ISE creates a skeleton test fixture (a.k.a. testbench) for you. The module is
instantiated as the "unit under test" (uut).
6. Run functional simulations using Verilog simulations tool.
 7. The .tcf generated by running simulation on the RTL is used as an input for accurate
power analysis in synthesis.

Program:
Example 1: 4x1 MUX - Dataflow Model
module mux4x1(
input s0,
input s1,
input a,
input b,
input c,
input d,
output y
);
assign y = (a & (~s1) & (~s0)) |(b & (~s1) & s0) |(c & s1 & (~s0)) |(d & s1 & s0);
endmodule

Gate Level
module mux4x1_gate_level (
input a,
input b,
input c,
input d,
input s0,
input s1,
output y
);
wire n1, n2, n3, n4, n5, n6;
not (n1, s1);
not (n2, s0);
and (n3, a, n1, n2);
and (n4, b, n1, s0);
and (n5, c, s1, n2);
and (n6, d, s1, s0);
or (y, n3, n4, n5, n6);
endmodule

Example 2:
module sevensegment (input [3:0] data,
output reg [6:0] segments);
always @ ( * ) // * is short for all signals
case (data) // case statement
0: segments = 7'b111_1110; // when data is 0
1: segments = 7'b011_0000; // when data is 1
 2: segments = 7'b110_1101;
3: segments = 7'b111_1001;
4: segments = 7'b011_0011;
5: segments = 7'b101_1011;
6: segments = 7‟b111_1111;
7: segments = 7‟b111_0000;
8: segments = 7‟b111_1111;
9: segments = 7‟b111_1011;
default: segments = 7'b000_0000; // required
endcase
endmodule

Output for Dataflow Model

Output for Gate level Model

Output of Seven Segment Display

Result
Exp 3 Power optimization for combinational circuits

Aim
To write Verilog HDL code for a full adder using dataflow, gate level and behavioural model
and estimate the power.

Theory:
A full adder adds two binary numbers with a carry-in and produces a 2 bit output. The lower
order bit of the resultant is known as Sum, whereas the higher order bit is named Cout.

Truth Table:
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Boolean Expression
S = A ^ B ^ Cin
Cout = A·B + B·Cin + A·Cin

Gate Implementation:
Procedure:
1. Open the ISE Project Navigator and create a new project. After entering a project
name and location, you'll be prompted for the project properties. Set the properties
and make ISE Simulator as your Simulator.
2. Click Next, and create a new Verilog Module. Choose the inputs and outputs for the
module, click Next and Finish.
3. Run the Check Syntax process (under Synthesize) to make sure your code is entered
correctly, and save your design.
4. Right-click on filename.v in the Sources window and choose New Source. Select
Verilog Test Fixture (not Verilog Module) and give your file a name such as
"test_filename". Click Next, and you'll be prompted to associate the file with a
module; choose filename, click Next, then click Finish. The file will be added to your
project.
5. ISE creates a skeleton test fixture (a.k.a. testbench) for you. The module is
instantiated as the "unit under test" (uut).
6. Run functional simulations using Verilog simulations tool.
7. The .tcf generated by running simulation on the RTL is used as an input for accurate
power analysis in synthesis.

Program
Dataflow :
module full_adder(input a, b, cin, output S, Cout);
assign S = a ^ b ^ cin;
assign Cout = (a & b) | (b & cin) | (a & cin);
endmodule

Test Bench
module tb_top;
reg a, b, c;
wire s, c_out;
full_adder fa(a, b, c, s, c_out);
initial begin
$monitor("At time %0t: a=%b b=%b, cin=%b, sum=%b, carry=%b",$time, a,b,c,s,c_out);
a = 0; b = 0; c = 0; #1;
a = 0; b = 0; c = 1; #1;
a = 0; b = 1; c = 0; #1;
a = 0; b = 1; c = 1; #1;
a = 1; b = 0; c = 0; #1;
a = 1; b = 0; c = 1; #1;
a = 1; b = 1; c = 0; #1;
a = 1; b = 1; c = 1;
end
endmodule
Expected Output:
At time 0: a=0 b=0, cin=0, sum=0, carry=0
At time 1: a=0 b=0, cin=1, sum=1, carry=0
At time 2: a=0 b=1, cin=0, sum=1, carry=0
At time 3: a=0 b=1, cin=1, sum=0, carry=1
At time 4: a=1 b=0, cin=0, sum=1, carry=0
At time 5: a=1 b=0, cin=1, sum=0, carry=1
At time 6: a=1 b=1, cin=0, sum=0, carry=1
At time 7: a=1 b=1, cin=1, sum=1, carry=1

Gate Level
module full_adder(
input a,
input b,
input cin,
output s,
output cout,
wire p,q,r
);
xor (p,a,b);
and (r,a,b);
xor (sum,p,cin);
and (q,p,cin);
Or (cout,q,r);
endmodule

Test Bench
initial begin
// Initialize Inputs
a = 0;b = 0;cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; a = 0;b = 0;cin = 1;
#100; a = 0;b = 1;cin = 0;
#100; a = 0;b = 1;cin = 1;
#100; a = 1;b = 0;cin = 0;
#100; a = 1;b = 0;cin = 1;
#100; a = 1;b = 1;cin = 0;
#100; a = 1;b = 1;cin = 1;
end
Expected Output:

Behavioral Model
full_adder(input wire A, B, Cin, output reg S, output reg Cout);
always @(A or B or Cin)
begin
case (A | B | Cin)
3'b000: begin S = 0; Cout = 0; end
3'b001: begin S = 1; Cout = 0; end
3'b010: begin S = 1; Cout = 0; end
3'b011: begin S = 0; Cout = 1; end
3'b100: begin S = 1; Cout = 0; end
3'b101: begin S = 0; Cout = 1; end
3'b110: begin S = 0; Cout = 1; end
3'b111: begin S = 1; Cout = 1; end
endcase
end

Result:
 Exp 4 Power optimization for sequential circuits

Aim
To write Verilog HDL code for a D flipflop, FSM, Upcounter and estimate the power.

Theory:

Example 1:
A finite-state machine (FSM) is an abstract mathematical model of computation used to
design sequential logic circuits. Each FSM consists of three separate parts: next state logic,
state register, output logic

A finite-state machine for binary divisibility by 3 is given as example. This is a FSM that
accepts strings formed with input alphabet {0, 1}. It accepts exactly those strings that are a
numeral representing a multiple of 3 in binary, least-significant digit first.

Procedure
1. Open the ISE Project Navigator and create a new project. After entering a project
name and location, you'll be prompted for the project properties. Set the properties
and make ISE Simulator as your Simulator.
2. Click Next, and create a new Verilog Module. Choose the inputs and outputs for the
module, click Next and Finish.
3. Run the Check Syntax process (under Synthesize) to make sure your code is entered
correctly, and save your design.
4. Right-click on filename.v in the Sources window and choose New Source. Select
Verilog Test Fixture (not Verilog Module) and give your file a name such as
"test_filename". Click Next, and you'll be prompted to associate the file with a
module; choose filename, click Next, then click Finish. The file will be added to your
project.
 5. ISE creates a skeleton test fixture (a.k.a. testbench) for you. The module is
instantiated as the "unit under test" (uut).
6. Run functional simulations using Verilog simulations tool.
7. The .tcf generated by running simulation on the RTL is used as an input for accurate
power analysis in synthesis.

Program
Example 1
module flop_D (input clk,
input reset,
input en,
input [3:0] d,
output reg [3:0] q);
always @ (posedge clk. negedge reset)
begin
if (reset == „0‟) q <= 0; // when reset
else if (en) q <= d; // when en AND clk
end
endmodule

Example 2
module up_counter(input clk, reset, output[3:0] counter );
reg [3:0] counter_up;
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up <= 4'd0;
else
counter_up <= counter_up + 4'd1;
end
assign counter = counter_up;
endmodule

Test Bench
module upcounter_testbench();
reg clk, reset;
wire [3:0] counter;
up_counter dut(clk, reset, counter);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule

Expected Output:

Example 3
module divideby3FSM (input clk, input reset, output q);
reg [1:0] state, nextstate;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
always @ (posedge clk, posedge reset) // state register
if (reset) state <= S0;
else state <= nextstate;
always @ (*) // next state logic
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S0;
default: nextstate = S0;
endcase
assign q = (state == S0); // output logic
endmodule
Expected Output:

Result
Exp 5 Power optimization for RT and algorithmic levels.

Aim
To write Verilog HDL code for a Arithmetic Logic Unit and estimate the power.

Theory:
An 8-bit arithmetic logic unit (ALU) is a combinational circuit which operates on two 8-bit
input based on opcode. The ALU performs common arithmetic (addition, subtraction,
multiplication, division) and logic (AND, INV, XOR, and OR) functions. The opcode will tell
the ALU which operations to perform. If the processor is n-bit then ALU will perform the
operation on n-bit operand. The length of the opcode given to the ALU will decide the
maximum number of operations performed.

S.no Op Code Operation

1 000 Addition
2 001 Subtraction
3 010 Multiplication
4 011 Division
5 100 And
6 101 Or
7 110 Invert
8 111 x-or

Procedure:
1. Open the ISE Project Navigator and create a new project. After entering a project
name and location, you'll be prompted for the project properties. Set the properties
and make ISE Simulator as your Simulator.
2. Click Next, and create a new Verilog Module. Choose the inputs and outputs for the
module, click Next and Finish.
3. Run the Check Syntax process (under Synthesize) to make sure your code is entered
correctly, and save your design.
4. Right-click on filename.v in the Sources window and choose New Source. Select
Verilog Test Fixture (not Verilog Module) and give your file a name such as
"test_filename". Click Next, and you'll be prompted to associate the file with a
module; choose filename, click Next, then click Finish. The file will be added to your
project.
5. ISE creates a skeleton test fixture (a.k.a. testbench) for you. The module is
instantiated as the "unit under test" (uut).
6. Run functional simulations using Verilog simulations tool.
7. The .tcf generated by running simulation on the RTL is used as an input for accurate
power analysis in synthesis.
Program
//8-bit arithmetic and logical unit
module alu(
input [2:0]opcode,
input [7:0]OperandA,OperandB,
output reg [7:0]result
);
always @(*)begin
case(instruction)
3'b000:
result = Operand A + B;
3'b001:
result = Operand A - B;
3'b010:
result = Operand A / B;
3'b011:
result = Operand A * B;
3'b100:
result = Operand A & B;
3'b101:
result = Operand A | B;
3'b110:
result = ~Operand A;
3'b111:
result = Operand A ^ OperandB;
default:
result = 0;
endcase
end
endmodule

Testbench
module alu_tb;
reg [2:0]instruction;
reg [7:0]A,B;
wire [7:0]result;
alu uut(instruction,A,B,result);
integer i;
initial begin
A = 50; B = 10; instruction = 0;
for(i = 1; i < 8; i = i+ 1)begin
#10
instruction = i;
end
#10
$finish();
End

Expected Output

Result