2023 IEEE International Conference on Quantum Software (QSW)

Influence of HW-SW-Co-Design
on Quantum Computing Scalability
Hila Safi Karen Wintersperger Wolfgang Mauerer
Siemens AG, Technology Siemens AG, Technology Technical University of
Technical University of Munich, Germany Applied Sciences Regensburg
2023 IEEE International Conference on Quantum Software (QSW) | 979-8-3503-0479-4/23/$31.00 ©2023 IEEE | DOI: 10.1109/QSW59989.2023.00022

Applied Sciences Regensburg [email protected] Siemens AG, Technology

Munich, Germany Regensburg/Munich, Germany
[email protected] [email protected]

Abstract—The use of quantum processing units (QPUs) Quantum algorithms in general have the potential to im-
promises speed-ups for solving computational problems. Yet, prove both, the quality and performance of approximate solu-
current devices are limited by the number of qubits and suffer tions to NP-complete problems [5]. QAOA (Quantum Approx-
from significant imperfections, which prevents achieving quan-
tum advantage. To step towards practical utility, one approach is imate Optimisation Algorithm) is a particularly well-known
to apply hardware-software co-design methods. This can involve and widely studied quantum algorithm for finding approximate
tailoring problem formulations and algorithms to the quantum solutions to combinatorial optimisation problems. However,
execution environment, but also entails the possibility of adapting among other factors, current quantum hardware limitations
physical properties of the QPU to specific applications. In this restrict the potential of using QAOA to solve problems of prac-
work, we follow the latter path, and investigate how key figures—
circuit depth and gate count—required to solve four cornerstone tical interest. Quantum computers face different challenges; for
NP-complete problems vary with tailored hardware properties. instance they are limited to a relatively small number of qubits,
Our results reveal that achieving near-optimal performance typically ranging from around 50 to 400. Scaling quantum
and properties does not necessarily require optimal quantum computers to large numbers of qubits is a difficult engineering
hardware, but can be satisfied with much simpler structures problem that also heavily depends on the specific hardware
that can potentially be realised for many hardware approaches.
Using statistical analysis techniques, we additionally identify an
platform. Another problem is that quantum computers are
underlying general model that applies to all subject problems. susceptible to noise and distortions from their environment
This suggests that our results may be universally applicable to and suffer from imperfections in the control signals [6], both
other algorithms and problem domains, and tailored QPUs can leading to errors in the operations performed on the qubits,
find utility outside their initially envisaged problem domains. and limited decoherence times.
The substantial possible improvements nonetheless highlight the
importance of QPU tailoring to progress towards practical
Changes to the hardware architecture can influence the
deployment and scalability of quantum software. connectivity between qubits, the coherence time, and the gate
Index Terms—quantum computing, software engineering, error rates. These modifications impact the performance and
hardware-software co-design, quantum algorithm performance resource requirements of quantum algorithms, such as the
analysis, scalability of quantum applications number of gates needed to execute the quantum circuit, the
number of measurements required and the amount of memory
I. I NTRODUCTION and time needed to store and manipulate quantum states. In
this paper, we consider the effects of such hardware improve-
NP-Complete problems are of great interest in computer sci- ments on four NP- complete problems: Travelling Salesperson
ence and mathematics, as many industrial problems belong to (TSP), Number Partitioning (NumPart), Maximum Cut (Max-
this complexity class. They are believed to be computationally Cut) and Maximum 3-Satisfiability (Max3Sat).
intractable for classical computers, at least in the worst case. This is of particular importance in the current era of
This means that for large instances of these problems, it may noisy, intermediate-scale quantum (NISQ) computers, which
not be possible to find a solution in a reasonable amount of is expected to last for at least several years (possibly even
time using any known algorithm. Industrial use-cases already decades) until fault-tolerant, perfect quantum computing be-
benefit from approximating optimisation. These problems can comes feasible. Yet, there is an increasing interest in util-
be rewritten as NP-optimisation (NPO) problems and also ising NISQ devices in high- performance computing (HPC)
include combinatorial elements to represent each problem [1], scenarios, and tailoring NISQ devices to problems is seen as
[2]. In practice, there exist heuristics and approximation algo- a possible or even necessary of stepping towards practically
rithms that can be used to find good near-optimal solutions to relevant quantum speedups and advantage. As properties of
some NP-complete problems by choosing a trade-off between quantum algorithms depend on QPU (hardware) properties [7],
performance and result quality, albeit it is known that problems hardware-software co-design can help to address some of the
exist that defy such techniques [3], [4]. key challenges of current quantum devices [8]. By designing

979-8-3503-0479-4/23/$31.00 ©2023 IEEE 104

DOI 10.1109/QSW59989.2023.00022
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algorithms and programs optimised for these limitations, it with minimal gate-overhead. The ansatz is compared to other
may be possible to surpass result quality of more generic designs using the example of VQE for quantum chemistry
approaches. It is also an important and promising approach calculations. Furthermore, Linke et al. [15] assert that co-
to optimise the performance and efficiency of quantum com- designing quantum applications for specific purposes is crucial
puting systems by putting both the hardware and software to successfully utilise quantum computers in the near future.
component as a cohesive unit. The focus of this paper is They reach this conclusion by comparing identical quantum
to examine the impact of hardware-software co-design on algorithms on two different hardware platforms.
quantum computing scalability. We use numerical experiments
to explore the potential for co-design using a hybrid quantum III. C ONTEXT AND F OUNDATIONS
algorithm (QAOA) applied so several subject problems. The In the following, we lay some foundations necessary to un-
quantum circuits are compiled to different types of simulated derstand our approach and rationale behind the experiments..
hardware backends, which are extended from the topology of
the IBM-Q devices. A. Quantum Optimisation with QAOA
The paper is augmented by a reproduction package [9], QAOA is a widely used variational hybrid quantum algo-
which is available for download (link in PDF).1 Some sup- rithm on NISQ hardware developed by Fahri et al. in 2014 [5].
porting material that we could not present in the main text is The algorithm has shown promising results on small-scale
available on the supplementary website. quantum devices for several optimisation problems, including
The rest of this work is structured as follows. Section II the MaxCut problem, TSP [16], or similar problems [17]. As
reviews related work. Following in Sec. III, we explain the quantum hardware continues to improve, QAOA and other
principles behind our approach, and also elaborate on proper- quantum optimisation algorithms are expected to play an
ties of the subject problems. Results from numerical experi- increasingly important role in solving real-world problems.
ments, conducted in Sec. IV, are analysed in Sec. V, which 1) Algorithm: QAOA produces approximate solutions for
also presents a general model that universally describes all combinatorial optimisation problems, which are described by
subject problems. Finally, Sec. VII discusses the consequences a problem Hamiltonian Hp . The algorithm consists of several
of our findings, together with an outlook on future research layers of parameterised unitary operators U (β, γ). As the
directions. number of layers p ≥ 1, p ∈ N increases, the quality of
the approximation improves [5]. First, the quantum register is
II. R ELATED W ORK initialised in a well-defined state and after applying the unitary
QAOA has been studied as a promising approach to solve operators, the expectation value of Hp is measured in the final
combinatorial optimisation problems. Several previous works state. The parameters β, γ of the quantum circuit are optimised
have focused on optimising QAOA for available quantum by classical methods such that the expectation value of Hp is
hardware. The main challenges in this context are the limited minimised.
number of qubits and the high error rates of current quantum Each layer consists of two different kinds of unitaries,
devices. To address these challenges, different approaches U (βi ) = eiβHB and U (γi ) = eiγHP . The algorithm applies
have been proposed, such as the use of hardware-software a mixer Hamiltonian, typically a Pauli-X operator, to each
co-design, error mitigation techniques [10], hardware-efficient qubit using the U (βi ) = eiβHB unitary. This is followed by
ansätze [5] or hybrid classical-quantum optimisation [11]. a combination of single qubit Z−rotations RZ (γi ) and two-
Lotshaw et al. [12] discuss the impact of problem sizes and qubit rotation gates RZZ (γi ) composing the U (γi ) = eiγHP
complexity on QAOA performance and resource requirements unitary. Multiple layers of this process correspond to a dis-
on contemporary hardware, and also analyse scalability of the cretized time evolution governed by the Hamiltonians HP and
algorithm under different hardware topologies. Furthermore, HB . The algorithm’s initial state is usually the ground state
Wille et al. [13] address the challenge of mapping quantum of HB , prepared using Hadamard gates H. To optimise the
circuits to the topology of targeted architectures and present a objective function, the quantum circuit is executed multiple
tool for tackling this problem. Some works have focused more times, and the qubits are measured in the computational
on designing quantum hardware that is optimised for specific basis. The mean of the expectation values of HP for each
quantum algorithms. For example in the work of Kandala et measurement outcome is minimised by the classical optimiser,
al. [14], a superconducting quantum processor was optimised and the optimal solution is derived as the state or bit string
for the variational quantum eigensolver (VQE) algorithm. The with the lowest energy expectation value in the probability
paper shows that this approach can significantly reduce the distribution obtained from the final set of parameters. The
number of gates required to implement VQE on the hard- algorithm determines the minimum value of the objective func-
ware. In [8], an architecture design-flow for superconducting tion specified in quadratic unconstrained binary form (QUBO).
quantum computers is proposed that finds a trade-off between A classical algorithm that can efficiently sample the output
optimisation of the processor’s yield rate and a mapping distribution of QAOA even for p = 1, cannot exist based on
reasonable complexity-theoretic assumptions. This indicates
1 We will place this material on a long-term stable, DOI-compliant location the possibility of quantum advantage, but practical utility on
for the accepted version of this paper. real-world problems require further investigations [7].

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B. Translation of algorithms to quantum hardware readout techniques, the infrastructure requirements (e.g., if
cooling with a cryostat is needed) and the properties relevant
When programming a quantum algorithm, initially no re- for mapping between logical and physical circuits, such as
strictions on the type of gates being used or the interaction the number of qubits, the native gate set and the connectivity
between qubits is made. However, to execute a certain quan- are different for each type of QPU. This means that the
tum algorithm on a specific hardware backend, it needs to be performance of a quantum algorithm usually heavily depends
compiled [18] to the properties of the backend, which is also on the type of hardware that it is running on.
called transpilation [19]. The most important properties of a
quantum computer that influence the transpilation of circuits
C. Problem selection
are the size of the backend, that is, the number of qubits
available, their geometric arrangement and connectivity, and In this paper, we focus on problems that belong to com-
the native gate set. For the actual execution of the circuit, plexity class NP-Complete (NPC), as it contains practically
also other factors such as the fidelities of gate operations, relevant problems that, assuming the usually uncontended
initialization and measurement as well as the decoherence and P ̸= NP hypothesis, cannot be efficiently solved on a classical
gate operation times play an important role. machine, and are in most instances also hard to approximate,
The connectivity measures the number of other qubits one as is textbook knowledge [24].
qubit can interact with, and thus the ability to perform a two- A decision problem p is in NPC if a solution can be
qubit gate operation between them. If a two-qubit gate needs determined by a non-deterministic Turing machine in polyno-
to be executed between qubits which are not connected, a mial time (i.e., p ∈ NP), and is additionally NP-hard, which
S WAP gate can be applied to swap the states of two qubits. means that any other problem in NP can be reduced to p
The geometric layout and connectivity of the QPU can be in polynomial time. We investigate the fundamental MaxCut,
depicted by a graph with nodes representing the qubits and NumPart, TSP and Max3Sat problem.
edges connecting two qubits if an interaction between them is 1) Maximum Cut: Given an undirected graph G = (V, E)
possible. Analogously, the circuit that is executed can also be composed of vertices V and the set of edges E, the objective
represented by a graph, which has an edge between two nodes, is to partition the vertices into two disjoint sets, S and T, while
if a two-qubit gate is performed between the corresponding maximising the number of edges that cross the partition:
qubits. The transpilation process maps this circuit graph to the
hardware graph, while taking into account further restrictions, X
max (2xi xj − xi − xj ), (1)
such as the native gate set. xi,j
(i,j)∈E
Due to the decomposition of gates into the native gate
set of the hardware as well as the insertion and further where xi is a binary variable that takes the value 1 if vertex
decomposition of S WAP gates, the transpiled circuit contains Vi lies in the first subset S and 0 if it lies in the second subset
more gates in total. This is crucial in the current NISQ-era, T.
as each gate introduces an error, and thus the quality of 2) Number Partitioning: Let x1 , x2 . . . , xn be a set of
the results is expected to drop with a growing number of positive integers. The objective is to divide the set into two
operations. Moreover, the circuit depth is increased, which subsets S and T, while minimising the difference between the
measures the maximum length of the circuit accounting for sums of the two non-empty subsets
parallel execution of gates, as well as the overall runtime of
the algorithm, due to the finite execution time of each gate. The n
X n
X
!2
available quantum computers only have a limited decoherence min ai xi − ai (1 − xi ) , (2)
xi
time, in which operations can be performed, that should not i=1 i=1
be exceeded by the algorithm runtime.
where xi = 1 if ai is assigned to subset S and xi = 0 if
Thus, to increase the performance of quantum algorithms on
ai is assigned to subset T. Note that we minimise the square
near-term quantum computers, the number of gate operations
of the expression, since a QUBO formulation is not able to
should be minimised. This could be achieved by designing
represent the alternative of absolute values.
optimised algorithms or by increasing the connectivity of the
hardware. 3) Travelling Salesperson: Given a set of n cities
1, 2, . . . , n, the travelling salesperson problem determines the
The ability to modify these properties depends on the
shortest path, whilst starting and ending at the same city and
type of the QPU being used. Today, several different types
visiting each location exactly once
of quantum computing hardware exist, which differ by the
physical implementation of qubits. The two states |0⟩ and |1⟩ n n
can be encoded in various different ways such as the naturally
X X
min ci,j xi,j , (3)
occurring discrete energy levels of single ions or atoms, the xi,j
i=1 j̸=i,j=1
effective energies of superconducting circuit elements or in
the spatial modes of single photons, to just name a few [20]– where xi,j = 1 if the path goes from city i to city j and
[23]. Along with the choice of qubits, also the control and xi,j = 0 otherwise.

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 4) Maximum 3-Satisfiability: Given a set of m clauses hand, MAX-SNP consists of optimisation problems that can be
1, 2, . . . , m , each consisting of three Boolean variables or expressed as a Boolean formula in conjunctive normal form,
their negations, Max3Sat seeks to find an assignment of truth where each clause is a disjunction of at most k literals. The
values to the variables that satisfies the maximum number of main difference between these complexity classes lies in the
clauses. The objective function can be expressed as follows: available approximation algorithms [26].
m
1 X X
3 IV. E XPERIMENTS
max wi xi,j , (4) A. Setup
xi,j m i=1 j=1
In this work, the quantum circuits are designed and tran-
where wi is the weight of clause i, ci is the number of spiled using Qiskit [27]. We study the QAOA-circuits for sev-
literals in clause i that are satisfied by the assignment, and m eral instances of the four problems described above after being
is the total number of clauses. transpiled to hardware backends with different properties. As
We selected this set of problems for two reasons, one of a starting point, a backend with 127 qubits is chosen that
which is that they represent significant industrial use cases as- matches the geometric layout and connectivity of the current
sociated with them. MaxCut has various industrial applications IBM-Q devices, the so-called heavy-hex-geometry [28]. The
in network optimisation and clustering. Amongst other things native gate set corresponds to that of IBM-Q, containing the
it is used for targeted advertising, recommendation systems following gates: Rotation RZ, phase shift SX, Pauli (Not)
as well as identifying the ideal placement, for instance, for X, and controlled X (C–X). In principle, also the influence of
hospitals or subway stations to extend and improve infras- noise on the transpilation process could be modelled in Qiskit,
tructures. NumPart can be used for load balancing. The goal which is, however, not in the scope of this work.
could be to divide a set of tasks among machines in a way We investigate the depth and number of S WAP gates of the
that minimises the differences in workload. It can also help to transpiled circuits depending on the connectivity and size of
find an optimal division of orders among workers. The TSP the backend. The circuit depth measures the overall length of
is well known and is commonly applied in the logistics and the circuit, taking into account also parallel execution of gates.
transportation industry [25]. Just as importantly, Max3Sat is The S WAP gate counts are derived by mapping each circuit a
used in the design of digital circuits, where the goal is to second time using an extended native gate set including the
minimise the number of gates needed to implement a logic S WAP gate. This prevents the latter from being decomposed
function, thus reducing the overall complexity of the circuit. into other gates.
This can help save costs and leads to a better performance. It The connectivity of the backend is measured in terms of a
is worth noting that many other NP-Complete problems have connectivity density
similar applications in various industrial settings.
NC
The other reason to chose this set of problems is that c= , (5)
decision problems are less common in industrial use-cases than NC,max
approximate optimisation problems. For example, in the case with NC denoting the total number of edges in the hardware
of the travelling salesperson one could ask ”what are possible graph and NC,max = N (N − 1)/2 the maximal number of
short routes”. Accepting for small deviations from optimal edges for N qubits. While c = 1 describes a device with
solutions can lead to significant savings in time and effort for all-to-all connectivity such as in ideal simulations, the heavy-
many problems, which usually is a more desirable outcome in hex-geometry has a connectivity density of c ≈ 1.8%. This
practical applications [1]. This particular problem set contains value corresponds to each qubit having on average 2.27 nearest
problems from three different complexity classes when de- neighbours. In the experiments presented below, the connec-
scribed as NP (nondeterministic polynomial time) problems— tivity density is increased by randomly adding connections
APX-Complete, NPO-Complete and MAX-SNP. This helps us between pairs of qubits until the desired value is reached. The
compare the scalability within the same complexity class, as average number of nearest neighbours per qubit grows linearly
well as across different complexity classes. with the connectivity density.
D. Complexity classes in NP optimisation problems B. Problem Mapping
APX-complete problems are considered to be the hardest All problems in NP can be reduced to Quadratic Uncon-
problems to approximate within a constant factor in poly- strained Binary Optimisation (QUBO) problems. The QUBO
nomial time, assuming P ̸= NP. MaxCut belongs to this formulations in this work follows the Ising formulations given
complexity class. NPO-complete problems include the TSP by Lucas [29].
and NumPart problem. These problems are characterised by 1) Maximum Cut: MaxCut can be cast using binary vari-
the task of finding an optimal solution that satisfies a set ables xi , where xi = 1 indicates that node i belongs to the
of constraints, and are at least as hard as the hardest deci- first subset, and xi = 0 indicates that it belongs to the second
sion problems in NP. Unlike APX-complete problems, NPO- subset. If an edge connecting nodes i and j is part of the
complete problems may not have a constant-factor approxi- cut, then one of xi and xj is equal to zero and the other one
mation algorithm that runs in polynomial time. On the other is equal to one, resulting in Hij = (xi + xj − 2xi xj ) being

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 Maximum 3-SAT Maximum Cut
8
6
4 # Qubits
2 6
Circuit Depth [k, sqrt]

9
16

Number Partitioning Travelling Salesperson 36

8 49
6
64
4
2 81
100

0% 25% 50% 75% 100% 0% 25% 50% 75% 100%

Connectivity Density
Fig. 1. Span of achievable circuit depths for the subject problems in different sizes, plotted over varying degrees of connectivity. Data points for each density
are slightly displaced horizontally to make point ranges visible; connecting lines do not provide a fit to the data, but are only used to guide the eye.

1, whereas Hij equals 0 if xi = xj . The goal is to find the following Hamiltonian:

MaxCut by maximising the sum of Hij over all edges of the N N
graph or in other words minimising the sum over −Hij . The
X X
HC = cij xi,k xj,k+1 (8)
optimal solution is the ground state of the Hamiltonian i,j∈E,i̸=j k=1
X where ci,j is the distance between nodes i and j; xi,k is
HP = (2xi xj − xi − xj ) (6)
a binary variable that is equal to 1 if node i is visited at
(i,j)∈E
position k in the tour (and 0 otherwise); and N denotes the
which serves as the objective function for the QAOA algorithm total number of nodes in the TSP instance. The sum over k
to find the minimum solution. enforces the ordering of the nodes in the tour. Note that xi,N +1
Setup: The MaxCut problem graphs G = (V, E) were is equivalent to xi,1 , so the tour loops back to the starting node
characterised by their number of nodes N = |V |, and the and in our case ci,j = cj,i . To ensure that each city is visited
graph density d, defined as the ratio of the number of edges exactly once in the tour and that at each position in the tour
|E| to the maximum possible number of edges |Emax | in a there is exactly one city, the corresponding penalty terms are
clique comprising |V | nodes. The value of d ranges from 0 added to comprise the final Hamiltonian:
to 1 and is set to d = 0.7 for the experiments in this work. n
X N
X n
X N
X
Each node in the graph is represented by one qubit, so the H=A (1 − xj,k )2 + A (1 − xj,k )2 ) + HC , (9)
problem size given in numbers of qubits directly corresponds j=1 k=1 k=1 j=1
to the number of nodes. where A controls the strength of the penalty.
2) Number Partitioning: NumPart can be reformulated as Setup: The TSP problem graphs were represented as a
a QUBO problem using binary variables xi where xi = 1 complete, undirected graph (so ci,j = cj,i ), where the nodes
indicates that ai belongs to subset S and if xi = 0, ai belongs represent the cities and the edges represent the distances be-
to subset T. The objective is given by the Hamiltonian tween them. A randomly generated distance matrix determines
n n
the distances between the cities. For N nodes, we have N 2
qubits and a N × N distance matrix. The graph density for
X 2 X 2
HP = ai xi − ai (7)
TSP is defined analogously to MaxCut and also set to d = 0.7.
i=1 i=1
4) Maximum 3-Satisfiability: To formulate this problem as
which represents the difference between the sums of S and T. a QUBO, we introduced three binary variables yi , yj and yk ,
The goal is to find the minimum value of the Hamiltonian, where each variable can take the value 0 or 1. The Hamiltonian
which corresponds to the optimal partitioning of the set. for this problem is given by
Setup: The NumPart problem was generated as a list of Xm
1
length n ∈ N. Each number was generated randomly, and the H= (1 − (yi + yj + yk − 1) (10)
2
corresponding field index is represented by one qubit. i=1

3) Travelling Salesperson: The objective function of the where m is the number of clauses. The Hamiltonian is min-
TSP, describing the total length of the tour, is given by the imised when the number of satisfied clauses is maximised.

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 Setup: The values for each variable were generated ran- a uniform generation mechanism, but vary with instance size
domly. The number of clauses added to the number of vari- and characteristics of the individual instances.
ables equals the number of qubits necessary to represent our As one of our goals is to understand the effects of varying
QUBO formulation. In our experiments we use a fixed number degrees of connectivity in (hypothetical) QPUs, first consider
of 3 variables per clause. According to Figure 6, the ratio Fig. 1, which shows the achievable circuit depths for a given
between the number of clauses and number of variables has degree of (extended) connectivity for the subject problems
little to no effect on the circuit depth, suggesting it can be in various instance sizes given by the amount of required
disregarded in the experiments. qubits. Since mapping between logical and physical circuits
is performed by a stochastic algorithm, we obtain a range of
C. Circuit Mapping depths for varying connectivity densities and qubit count. Data
The hardware backend is described by a connectivity graph points in Figure 1 represent mean values over 20 compilation
given in the form of tuples and a native gate set. The transpila- runs. It is immediately apparent that even small increases in
tion process in Qiskit consists of several steps: First, the circuit circuit depth over the base connectivity of IBMQ’s heavy hex
is optimised, for instance by combining several single-qubit topology lead to considerable reduction of the circuit depth
gates into a single one. Then, all gates which do not belong to in a similar way for all of the problem types considered
the native gate set, such as gates with more than 2 qubits, are here. Likewise result variability increases considerably towards
decomposed into the native gate set. The next step is to find smaller degrees of connectivity. Both, strength of variability
an optimal placement of the logical qubits in the circuit to the and circuit depth, converge for densities exceeding 25%.
physical qubits of the hardware, which corresponds to a direct Figure 2 shows the amount of S WAP gates that are required
mapping of the problem (or algorithm) graph to the hardware for a given connectivity density (we address the inset in
graph. Thereby, S WAP gates are inserted, if necessary, and the Sec. V-B below). Since S WAP gates are necessary to bring
mapping is determined to minimise the number of S WAP gates. qubits into physical adjacency when multi-qubits operations
For the circuits presented here, the standard mapping method must be applied on topologically not adjacent qubits, they can
of Qiskit has been used, which includes a stochastic placement be seen as overhead that arises from restricted connectivity
of S WAP gates. After the mapping, the inserted S WAP gates are densities. As the figure shows, zero S WAP gates are required
being translated into the native gate set (if necessary), and the when the density reaches 1.0, as the need to logically move
circuit is optimised once more, accounting e.g., for possible qubits by swapping them around in the circuit does not
concatenations of gates. arise in this case. Similar to circuit depth, we can observe a
The aggressiveness of depth optimisation varies between steep decline in S WAP gate count with increasing connectivity
four levels [19] (level n includes all measures of levels k < n): density, and a plateauing of the count form densities of about
• 0 (off): Map without optimisation. 30% onwards.
• 1 (light): Collapse adjacent gates that cancel each other.
B. Statistical Modelling
• 2 (medium): Noise-adaptive layout, gate cancellation
based on gate commutation relationships. While it is obvious from Figures 1 and 2 that even slightly
• 3 (heavy): Replace blocks of gates with (different, yet
improved connectivity density results in substantial reductions
semantically equivalent) optimised gate sequences. on circuit depth independent of the specific problem, it is
pertinent to further characterise this empirical observation.
Our numerical experiments were performed at optimisation
To find simple models that accurately describe the observed
level 2, which provides a good trade-off between result opti-
phenomena, we fit statistical models to the available data.
mality and required computational effort. This choice is further The sharp decrease of circuit depth with increasing connec-
justified in Section VI. tivity density, modelled in general by a functional dependency
V. E VALUATION of the form d(ϱ) = fP (ϱ) (where P denotes specialisation for a
specific problem) suggests an inverse (f (ϱ) ∼ 1/ϱ) or negative
We commence to discuss the outcomes of our numerical
exponential (f (ϱ) ∼ exp(−ϱ)) relationship. The empirical
experiments in the following, and then find common patterns
results for these ansätze (linear univariate regression [30] for
in the data using statistical analysis techniques.
the inverse relationship, non-linear regression [31] for the
A. Numerical Results negative exponential), together with a linear regression fit
1) Circuit Depth and S WAP gate Count: The depth of based on a Box-Cox transformation [32] of the data,2 is shown
quantum circuits is analogue to classical runtime—the more in Fig. 3. Visually, it is obvious that the linear regression based
gates are involved in a circuit, the longer a quantum compu- approaches result in a sub-optimal match between model and
tation takes—, but also key to understanding the capabilities data, whereas the negative exponential ansatz
of NISQ machines, as increasingly deep circuits are subject to d(ϱ) = R∞ + (R0 − R∞ ) · e− exp(δ)·ϱ (11)
growing amounts of noise and decoherence, eventually leading
2 The transformation uses a maximum-likelihood estimate to determine
to entirely stochastic results that do not provide information
an optimal non-linear transformation to minimise the standard deviation of
about the problem at hand. Recall that quantum circuits regression residuals, which could suggest desirable other forms of functional
generated for specific problem formulations are produced by dependencies than the two considered variants.

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 49 81 Maximum 3-SAT Number Partitioning
# Qubits Problem
64 100 Maximum Cut Travelling Salesperson

R0 δ R∞
6
# Swap Gates [k]

10000
7500

Estimate [sqrt]
5000
4 2500

2 0
25 50 75 100
# Qubits

0
0% 25% 50% 75% 100%
Connectivity Density
Fig. 2. Outer: Empirical observation of S WAP gate count decrease with increasing connectivity density (points), together with fits obtained by the negative
exponential model (solid lines) for the subject problems. Inset: Corresponding model coefficients.

Box-Cox Inverse R0 is the (extrapolated) circuit depth estimate for vanishing

Type connectivity density at ϱ = 0, offset by R∞ . Coefficient
Exponential Measured
δ represents the natural logarithm of the exponential rate
Maximum 3-SAT Maximum Cut constant, and characterises the speed of decline with increasing
2.5
3 connectivity density.
2.0
1.5 2 Maximum 3-SAT Number Partitioning
Problem
1.0 Maximum Cut Travelling Salesperson
Circuit Depth [k]

0.5 1
Coefficent R0 δ R∞
0.0
Number Partitioning Travelling Salesperson
Coefficient Estimate [log]

3
4
1000
3 2
100
2
1
1 10

0% 25% 50% 75% 100% 0% 25% 50% 75% 100%

Connectivity Density 1

Fig. 3. Comparing models (inverse, Box-Cox, negative exponential; solid 25 50 75 100

lines) against the empirically measured data (points). The graph shows # Qubits
problem instances each requiring 64 qubits; graphs for other sizes exhibit Fig. 4. Coefficients for the non-linear negative exponential fit described by
similar characteristics and are available on the supplementary website. Eq. 11 to the circuit depths for all subject problems over varying instance
sizes. Connecting lines have no significance, and are only used to guide the
eye.
describes the data very well.3 Based on the data for each
subject problem, parameters R0 , R∞ and δ are obtained Consider Figure 4, which summarises the evolution of
for varying connectivity densities. R∞ denotes the horizontal model parameters for the circuit depth with increasing instance
asymptote towards large values of the connectivity density, sizes for all subject problems. Note that for each problem and
instance size, we numerically compute circuit depths for a
3 A straightforwards logarithmic transformation of the data, which would range of connectivity densities, and then fit Eq. 11 to the data.
allow us to deploy a simpler linear univariate regression model, does not Consequently, each combination of problem and instance size
produce satisfactory results; while the variation of the decay constant is small delivers three parameters. The evolution of these parameters
across instance sizes for each subject problem, it is nonetheless large enough
to warrant different bases for each log transformation, which would need to with increasing instance sizes is shown in the figure.
be estimated in a prior modelling step. Apart from some smaller variations for NumPart, the rate

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constant δ is stable across instance sizes—that means that bus, either directly via tuning their frequencies in and out of
exponential improvements in circuit depth with increasing con- resonance with the bus [36], or indirectly via additional flux
nectivity density are achieved nearly uniformly across the full qubits [34], which are variably tuned. The latter architecture
spectrum of instance sizes. As gains are mostly independent has the advantage of lower cross-talk and longer coherence
of the problem, we hypothesise that this behaviour holds as a times, since the data qubits can be operated at their optimal
general law for QAOA-based approaches. Circuit depths in the frequencies. Other ideas include using sparse connections but
limits of zero and full connectivity, obviously increase with with non-trivial topologies, extending the architecture to 3D
increasing problem size. It is however important to observe or using long cables to connect distant qubits [22]. With the
that the evolution is also very similar across subject problems, quantum bus setup proposed in [34], the connectivity could
again hinting at a general property of QAOA circuits. theoretically be increased such that two-qubit-gates can be
The inset in Fig. 2 can be interpreted similarly, except performed between all pairs of qubits, superseding the inser-
that we use S WAP gate counts instead of circuit density as tion of S WAP gates at all. Nevertheless, realising such a setup
dependent quantity for the model in Eq. 11. Since it is an a- with only an intermediate connectivity, as suggested by our
priori invariant that the S WAP gate count needs to reach zero findings, will in any case benefit the practical implementation.
for full connectivity (qubits do not need to be swapped around In general, increasing the number of connections between
if interactions between any possible pair can be implemented qubits can lead to a higher probability for crosstalk. This term
natively), we fit a restricted form of Eq. 11 where the asymp- describes unwanted interaction between qubits or between
tote R∞ is constrained to vanish. The obtained parameters qubits and the control signals, which means that a gate pulse
show even better agreement across subject problems than for can effect other than the target qubit(s) or local gate operations
the circuit depth, which can be explained by the fact that are disturbed by other gate operations applied in parallel.
S WAP gates constitute “overhead” gates to compensate for These effects are especially detrimetal for implementing error
connectivity deficiencies. As our results show, this impacts correction, which assumes that gate errors only affect the state
all problems equally. Yet, the observed exponential decrease of the target qubits. For superconducting qubits, crosstalk can
with increasing connectivity density underlines that even small be reduced by using qubits with tunable frequencies (see [34])
changes have substantial impact on QC utility. and / or tunable couplers to switch connections dynamically
on and off. In addition, optimizing the pattern of tunable
C. Implications for Co-Design qubit frequencies and gate schedules via software can also
In the previous section we have seen that the circuit depth as lead to substantial improvements [37]. On the other hand,
well as the number of inserted S WAP gates is already reduced architectures with fixed-frequency qubits and fixed couplers
by a significant amount when increasing the connectivity like IBM-Q that do not allow for such optimisation suffer from
density to intermediate values of about 30%. This value fewer sources of noise. In this case, optimised gate schedules
increases slightly with the problem size, but does not depend are being used to minimise crosstalk [38].
on the problem type, as shown in Fig. 4. Overall, we can state Quantum computers based on cold neutral atoms and
that full connectivity is not essential to decrease the resource Rydberg-interactions already feature a higher connectivity of
requirements for the considered QAOA circuits. about 1:10 to 1:20 in 2D- and 3D-layouts [21], which would
In general, a quantum computing device with connectivity correspond to c ≈ 8-16% for the heavy-hex-based layout.
density between 10% to 50% would be an appropriate choice The connectivity can be further increased by using higher
for all of the four problem types. The S WAP gate overhead energy levels for the Rydberg interaction, which, however,
might be reduced further, if also the geometric layout of might lead to a higher susceptibility to noise and become tech-
the hardware graph directly matches that of the problem nically challenging. Another approach is shuttling of atoms
graph, opposed to randomly adding connections as done in during the computation to allow for two-qubit-gates between
this work. A connectivity density of c = 10% corresponds arbitrary pairs of qubits [39]. In general, crosstalk is quite
to each qubit being connected to 15 nearest neighbours on low for neutral atom qubits [40], [41], since their distances
average, for c = 50% this increases to 64 neighbours. Apart can be made large enough to avoid unwanted excitations of
from the reduced number of gates in the circuit, a higher spectator qubits. Also, increasing the qubit connectivity is not
qubit connectivity is desirable for implementing efficient error- necessarily related to higher crosstalk for this platform.
correction schemes which in turn require a lower overhead in In contrast to the two previous examples, trapped ion
the number of physical qubits needed to encode a logical qubit, quantum computers are characterized by an all-to-all connec-
such as low-density parity check (LDPC) codes [22], [33]. tivity, which means that two-qubit gates can be performed
The connectivity of currently available quantum comput- between each pair of qubits, but also up to 20 qubits can
ers depends on the type of quantum hardware being used. be entangled [42]. On the other hand, ion trap setups are
Architectures based on superconducting qubits, such as the more difficult to scale to larger numbers of qubits. The
devices built by IBM and Google, are currently limited to most common technique stores ions in a linear string and is
nearest neighbour connectivity (so c ≈ 3.2%) [15], [34], [35]. limited to qubits numbers in the range of 50. This has to be
There exist several ideas to increase the connectivity. One compared to superconducting qubits and neutral atoms, which
common approach is to couple several qubits to a quantum currently offer up to ≈ 400 [43] and ≈ 100 [21], [39] qubits,

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respectively, and, in the latter case, are also easier to scale. Ion 1) Influence of Mapping Optimisation: Since the circuit
strings with larger number of ions are expected to suffer from mapping (transpilation) problem is known to be NP-complete
lower gate speeds, higher crosstalk and background noise [44]. by itself (see, e.g., [48]), it is unavoidable to use approximation
To realise trapped-ion devices with larger number of qubits, techniques that cannot guarantee optimal results in feasible
mainly two different approaches exist: coupling several linear time, and therefore require precise characterisation. In partic-
traps via photonic interconnects or shuttling of ions in a 2D ular, there is the risk that the technical choice of optimisation
trap. While the first approach is more simple to realise, it is level could impact our general conclusions; likewise, different
affected by higher crosstalk due to residual illumination of compiler/mapping approaches could influence behaviour.
ions which are not targeted by a gate operation. Crosstalk can Consider Figure 5, which compares mapping results with
be reduced by careful design of pulse sequences or improved different optimisation levels for medium and large problem
laser focusing, as well as by using refocusing schemes [45]. instances requiring 25 and 100 qubits for the TSP (identical
While the first option can be broadly attributed to the software observations can be made for the other subject problems). All
domain, the latter two options are deeply intertwined with the levels follow the exponential decrease pattern, with relatively
core physical realisation of QPUs. small improvements of optimisation level 3, although it is also
Finally, to find the most suitable platform for a quantum clear that the highest optimisation level does not guarantee
program, a trade-off between several properties such as the smallest circuits, neither averaged nor overall. As the highest
connectivity, number of qubits or error-rates has to be made. optimisation level implies considerably increased simulation
times (days instead of hours), we find our choice of optimisa-
VI. T HREATS TO VALIDITY tion level 2 justified. While there are many other approaches
A. External Validity to circuit compilation that we cannot compare in detail in the
Our scope is limited to the Qiskit compiler and the base scope of this work, the results of Salm et al. [46], together with
topology of IBM-Q devices. It is important to note that using results that take differences for mapping practical problems
different compilers may result in varying circuit properties between the most widespread compilers into account [49],
(see Salm et al. [46]), which means that our findings may indicate that the risk of observing a qualitatively different
not be applicable to other compilers. Additionally, different scaling behaviour is absolute minor, though.
topologies may yield different outcomes. Furthermore, we 2) Influence of Instance Properties: Quantum circuits for a
only consider QAOA. There are other (variational) quantum given problem are constructed using a uniform mechanism
algorithms as well as different types of the QAOA algorithms, that depends on problem size, but also on the properties
that tackle NP optimisation problems [47]. While it is possible of the instance itself. As the observed exponential decrease
to model the impact of noise on the transpilation process in in circuit depth might depend on the latter properties, we
Qiskit, which would effect the circuit depth, it falls outside explore a varying set of parameters for problem MAX-3SAT.
the scope of this work [48]. Boolean satisfiability is known to exhibit marked differences in
computational complexity depending on the ratio α = |C|/|V |
B. Internal Validity between the number of variables |V | and clauses |C| (see,
Our observations rely on controlled numerical experiments e.g., Refs [50]). Fig. 6 shows how the circuit depth decreases
that depend on explicit parameters, but may also be influenced with increasing connectivity density for random instances of
by confounding factors. In the following, we consider various the problem that are constrained to a given value of α. We
possible confounding factors, and find that they pose moderate scan across values of α that represent regions where instances
to no risk to the validity of our study. are either trivially to solve by guessing (α ∈ [0, 3.5]) or
finding contradictory assignments that show non-solubility
Optimisation Level 1 2 3 (α ∈ [4.9, 11]), as well as the region around α ≈ 4.2 that
is known to contain computationally hard problem instances.
0.6
The inset shows that all three model coefficients R0 , R∞
0.5
and δ as given in Eq. 11 are are in good agreement with
Circuit Depth [k]

0.4
25

0.3 a constant value for each across the whole spectrum of α,

0.2 indicating no influence of the specific instance. Consequently,
6 we deem this risk minor to negligible. For this particular
assessment, it was not necessary to test other problem sizes,
4
100

as α determines the complexity of the Max3Sat problem.

2 3) Influence of Backend Size: Our numerical experiments
are performed using a constant backend size of 127 qubits, so
0.013895
0.03 0.05 0.1 0.2 0.4 0.5 0.6 0.8 0.9 1
Connectivity Density the ratio of the problem size to the backend size varies. If the
problem is much smaller than the backend, several mappings
Fig. 5. Distribution of circuit depth for two instance sizes (25 and 100
qubits) over connectivity density for varying optimisation levels obtained with
of logical to physical qubits are possible. We empirically study
the Qiskit compiler 0.41.1, see the replication package on the supplementary whether this influences the circuit depth by uniformly scaling
website for details) for the travelling salesperson problem. the backend size, while retaining the connectivity structure

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 For none of the problems, the exponential decrease for
0.64 1.25 4.14
Ratio α = |C| increasing connectivity density changes; there is practically
|V | 0.89 2.6 8 no influence of the increased backend size for Max 3-SAT
and TSP. For MaxCut and NumPart, the asymptotes vary
R0 δ R∞ moderately depending on backend size, yet the differences
600
are only relevant for connectivity densities exceeding 50%.

Coefficient [k]
Circuit Depth

1.00 However, since the models overestimate the connectivity den-

0.75
400 0.50 sities compared to empirical observations, we err—if at all—
0.25
0.00 on the side of caution. These observations are also backed
3 6 9 by the regression model coefficients, whose distribution for
200
α each subject problem is shown in the inset. Especially the rate
parameter is extremely narrowly distributed, which means that
the exponential decrease with increasing connectivity density
0% 25% 50% 75% 100% is independent of the base backend size. Consequently, we
Connectivity Density deem this threat minor.
Fig. 6. Empirically observed circuit depth degradation for MAX-3SAT on VII. D ISCUSSION & O UTLOOK
36 variables, with varying degrees of α (outer plot; see the main text for an
explanation of this parameter), and the coefficients obtained for Eq. 11 (inset). In conclusion, our results show that an all-to-all connectivity
The outer plot shows mean circuit depths obtained with 20 samples per data is not necessary to achieve near-optimal circuit depth for
point and omit ranges to reduce visualisation clutter, while the model fit is
obtained from the full data set. Connecting lines are used to guide the eye. all subject problems. Even small changes to the density can
lead to significant improvements, particularly across different
problem sizes and types. Lower connectivity between qubits,
Maximum 3-SAT Number Partitioning lower circuit depth and lower gate counts can help scale
Problem quantum systems, as the number of interactions between
Maximum Cut Travelling Salesperson
qubits, the number of quantum gates required to execute algo-
rithms and the overall complexity of the system is decreased.
[6, 4] [6, 6] [8, 5]
Backend Size Therefore it becomes easier to maintain coherence and reduce
[6, 5] [8, 4] [8, 6]
the probability of errors and decoherence, which are crucial
6 factors in building scalable quantum computing systems [51].
Coefficient [k]

6 We have identified an underlying effective model, which ex-

4
hibits an exponential decrease in circuit depth with increasing
Circuit Depth [k]

2
4 0 connectivity uniformly across all instance sizes. This suggest
R∞ δ R0 that our findings may be applicable to other problem domains.
Our results also point towards the construction of better
2 problem-adapted QPUs as a possible step towards practical
applications of quantum computing. The fact that all problems
demonstrate a consistent exponential decrease in circuit depth
0 as connectivity density rises is a highly encouraging and
0% 25% 50% 75% 100% promising observation. This trend is true for all investigated
Connectivity Density problems. Further research is required to explore the full
potential of our findings and understand the optimal topologies
Fig. 7. Empirical observations for circuit depth for problems with constant
size of 36 qubits with varying backend sizes (geometrically extrapolated as well as the effects on scalability for specific problems and
from the IBM-Q heavy-hex backend), together with nonlinear regression problem classes. This includes a comprehensive analysis of the
fits of the model in Eq. 11 (we augment the empirical observations with a effects of noise and different topology layouts. Moreover, it
slight horizontal jitter to reduce overplotting. Inset: Distribution of regression
coefficients. is important to incorporate more refined physical models that
better capture the physical trade-offs involved. Finally, it is
important to emphasise the importance of hardware-software
of the heavy-hex geometry, which is composed of a certain co-design for achieving scalability in quantum computing. As
number of rows and columns containing interconnected rings. we continue to explore new algorithms and applications, it will
Figure 7 shows circuit depths for varying backend sizes, whose be necessary to develop hardware and software in tandem to
geometry has been consistently extended from the IBM-Q ensure that they are optimised for each other.
Washington architecture with 127 qubits. Backend sizes are Acknowledgements This work is supported by the German
specified in the form [n, m], where n denotes the number of Federal Ministry of Education and Research within the funding
rows, and m the number of columns (details in the replication program Quantentechnologien – von den Grundlagen zum
package on the supplementary website). This creates backends Markt, contract number 13N16092.
ranging from 143 (6 × 4) to 297 (8 × 6) qubits.

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