Ay 2023-24 Digital Design and Computer Organization-Lab Manual-Part-2
Ay 2023-24 Digital Design and Computer Organization-Lab Manual-Part-2
INTRODUCTION
❖ Introduction to the Multisim Interface
Multisim is the schematic capture and simulation application of National Instruments Circuit Design
Suite, a suite of EDA (Electronics Design Automation) tools that assists you in carrying out the major steps in
the circuit design flow. It provides a virtual environment for designing, testing, and simulating electronic circuits.
Multisim allows users to create schematic diagrams, simulate circuit behavior, and analyze circuit performance.
Multisim is designed for schematic entry, simulation, and feeding to downstage steps, such as PCB layout.
Element Description
1 Menu Bar Contains the commands for all functions.
2 Component Toolbar Contains buttons that you use to select components from the
Multisim database for placement in your schematic.
3 Standard Toolbar Contains buttons for commonly-performed functions such as Save,
Print, Cut, and Paste.
4 Main Toolbar Contains buttons for common Multisim functions.
5 Place Probe Toolbar Contains buttons that you use to place various types of probes on
the design. You can also access Probe Settings from here.
6 In-Use Toolbar Contains a list of all components used in the design.
7 Simulation Toolbar Contains buttons for starting, stopping and pausing simulation.
8 Workspace This is where you build your designs.
9 View Toolbar Contains buttons for modifying the way the screen is displayed.
10 Instruments Toolbar Contains buttons for each instrument.
Installation steps are given below: Install Multisim by obtaining the software from National
Instruments and following the provided installation instructions.
1. Launch Multisim and choose to create a new project or open an existing one from the start
page.
2. Create a new project by giving it a name and choosing a save location.
3. Within the project, create a schematic by clicking "New" and selecting "Schematic."
4. Build your circuit on the schematic canvas by dragging components from the library and
connecting them with wiring tools.
5. Optionally, add virtual instruments like oscilloscopes or multimeters to visualize and analyze
your circuit during simulation.
6. Simulate your circuit by clicking on the "Simulate" tab, choosing the simulation type,
adjusting settings, and clicking "Run."
7. Analyze simulation results using built-in instruments, graphs, and charts to understand circuit
behavior.
8. Optionally, transfer your schematic to NI Ultiboard for PCB layout by clicking "Transfer to
Ultiboard."
9. Save your project periodically, export simulation results or other data as needed, and close
Multisim when finished.
Standard Toolbar
The Standard toolbar contains buttons for commonly performed functions. Its buttons are
described below:
Components Toolbar
The buttons in the Components toolbar are described below. Each button will launch the place
component browser (Select a Component browser) with the group specified on the button pre-selected.
Simulation Toolbar
The Simulation toolbar contains buttons used during simulation.
OVERVIEW OF HDL
Hardware Description Languages (HDLs) are specialized programming languages used for the design,
modeling, and simulation of digital circuits and systems. HDLs allow engineers to describe the behavior
and structure of electronic circuits at various levels of abstraction. Here is an overview of HDLs:
Purpose of HDLs:
1. Digital Circuit Design: HDLs are primarily used for designing digital circuits, including
processors, memory units, controllers, and other digital components.
2. Simulation: HDLs facilitate the simulation of digital circuits before actual implementation,
helping designers to verify functionality and detect potential issues.
3. Synthesis: HDLs support synthesis tools that convert high-level hardware descriptions into
low-level representations suitable for implementation on programmable devices like FPGAs or
ASICs.
Types of HDLs:
1. Verilog: Verilog is one of the most widely used HDLs. It supports both behavioral and
structural modeling and is used for simulating and synthesizing digital circuits.
2. VHDL (VHSIC Hardware Description Language): VHDL is another popular HDL used for
modeling digital circuits. It was developed by the U.S. Department of Defense and is known
for its strong type-checking and suitability for complex systems.
Levels of Abstraction:
1. Behavioral Modeling: Describes the functionality of a circuit without specifying its structure.
It includes high-level constructs like processes, tasks, and functions.
2. Structural Modeling: Describes a circuit in terms of its components and their interconnections.
FPGAs, alternative to the custom ICs, can be used to implement an entire System On one Chip (SOC).
The main advantage of FPGA is ability to reprogram. User can reprogram an FPGA to implement a
design and this is done after the FPGA is manufactured. This brings the name “Field Programmable.”
Custom ICs are expensive and takes long time to design so they are useful when produced in bulk
amounts. But FPGAs are easy to implement within a short time with the help of Computer Aided
Designing (CAD) tools.
XILINX FPGA
Xilinx logic block consists of one Look Up Table (LUT) and one Flip-flop. An LUT is used to
implement number of different functionality. The input lines to the logic block go into the LUT and
enable it. The output of the LUT gives the result of the logic function that it implements and the output
of logic block is registered or unregistered output from the LUT.
PROCEDURE:
The Procedure to be followed for Software and Hardware Programs are as follows:
Step 1: Go to Start Menu All Programs Xilinx ISE 13.1i and Select Project Navigator.
Step 2: Go to File Menu and select Close project to close previously opened project if any, and then
Select New Project.
Step 3: Enter the Project name and location and Select the Top level module type as HDL.
Step 4: Select the Device family and Device name as Spartan3, pin density TQ144, -5 for FPGA.
Step 5: Right click on the source file and select new source followed by Verilog module and Give the
file name same as the name of the entity.
Step 6: Define the ports used and their respective directions in the next window that opens.
Step 7: Write the architecture body and the generics etc. in the incomplete Verilog code that opens and
save the file after completion of editing.
Step 8: Go to the Process view window and right click on the Synthesize - XST and Select Run. Correct
the errors if any.
Step 9: Select and Right click the source file and click on the New Source tab and then select the Test
Bench Waveform and give the appropriate file name for the same.
Step 10: Make the alterations in the Clock information and initial length of the test bench if needed.
Step 11: Set or Reset the inputs as required and save the test bench waveform file.
Step 12: Go to Process view and under Xilinx ISE Simulator Right click on the Simulate Behavioral
model to see the output for the input conditions.
Step 13: Make the appropriate connections between the PC and the FPGA kit for the observation of
outputs in the FPGA kit and for other Hardware Programming.
Step 14: Select and Right click the source file and click on the New Source tab and then select the
Implementation Constraints file and give the appropriate file name for the same.
Step 15: Go to Process view and under User Constraints, double click on the Edit Constraints (Text).
Step 16: Write the code for the user constraints file as required and save the same.
Step 17: Select the main source file and right click on the Implement design in the process view window
and select run.
Step 18: Right click on the Generate Programming file in the process view window and select run.
Step 19: Under the Generate Programming file tab, right click on the Configure device (Impact) and
click on the Run option.
Step 20: Select the appropriate mode and make changes in the jumper settings of the FPGA Kit as
required, select the appropriate. BIT extension file in the pop up window.
Step 21: Right click on the Chip picture in the pop up window and Select “Program”. Debug the errors
if it is there. Set the conditions for the inputs using Dip switch and observe the outputs.
EXPERIMENT NO – 01
Aim: Given a 4-variable logic expression, simplify it using appropriate technique and simulate the
same using basic gates.
Objectives:
1. Simplify 4-variable logic expression for efficient design.
2. Simulate using basic gates for practical verification and optimization.
Theory:
SUM OF PRODUCT:
The short form of the sum of the product is SOP, and it is one kind of Boolean
algebra expression. In this, the different product inputs are being added together. The product
of inputs is Boolean logical AND whereas the sum or addition is Boolean logical OR. Before
going to understand the concept of the sum of products
Procedure:
1. Open Multisim software on your computer.
2. Click on "File" and select "New" to create a new schematic.
3. Drag and drop components from the component toolbar onto the workspace.
4. Connect the components using wires.Specify values and properties for components.
5. Add a power supply to the circuit. Connect it appropriately (Vcc and GND).
6. Double-click on components to open their properties.
7. Set parameters, such as resistor values, capacitor values, etc.
8. Click on "Simulate" in the toolbar.
9. Set simulation parameters like start time, stop time, and time step.
10. Add instruments to measure and observe circuit behavior.
11. Click on the "Run" button (play icon) to start the simulation.
12. Observe and analyze waveforms and measurements from the instruments. Check for correct
circuit behavior.
13. If unexpected results occur, review the circuit, component values, and connections. Make
necessary adjustments and rerun the simulation.
14. Save your schematic and simulation results.
15. Document the circuit design, simulation parameters, and observed behavior.
16. Export simulation results or circuit diagrams for sharing or further analysis.
Simulation Output:
Answer: Multisim allows users to create and simulate electronic circuits virtually, enabling
them to test the functionality and performance of the circuits without the need for physical
components. This aids in the design and validation process.
Answer: Simplifying a logic expression reduces the number of gates needed, leading to more
efficient and faster circuits.
Answer: Identify minterms, group adjacent 1s in the K-map, find the minimal sum-of-
products (SOP) expression, and then apply any additional simplifications.
Answer: AC + AD + BC + BD
Answer: Don't care conditions represent input combinations for which the output value is not
critical. Utilizing don't care conditions allows for further optimization during simplification.
EXPERIMENT NO – 02
Design a 4 bit full adder and subtractor and simulate the same using basic gates.
Aim: To design a 4 bit full adder and subtractor and simulate the same using basic gates.
Objectives:
1. Design a 4-bit full adder and subtractor circuit in Multisim using basic gates.
2. Simulate the circuit to analyze and verify correct functionality, considering various input
scenarios.
Theory:
The addition and subtraction operations can be combined into one circuit with one common binary
adder by including an exclusive-OR gate with each full-adder.
• When M = 1, we have B 1 = 𝐵̅ and C0 = 1. The B inputs are all complemented and a 1 is added
through the input carry. The circuit performs the operation A + (the 2’s complement of B)= A –B
• The exclusive-OR with output V is for detecting an overflow.
The binary adder–subtractor circuit with outputs C and V is shown in Fig. 4.13. If the two binary
numbers are considered to be unsigned, then the C bit detects a carry after addition or a borrow
after subtraction. If the numbers are considered to be signed, then the V bit detects an overflow. If
V = 0 after an addition or subtraction, then no overflow occurred and the n -bit result is correct. If
V = 1, then the result of the operation contains n + 1 bits, but only the rightmost n bits of the number
fit in the space available, so an overflow has occurred. The 1n + 12 th bit is the actual sign and has
been shifted out of position.
Equipment / components required:
Procedure / activity:
1. Open Multisim software on your computer.
2. Click on "File" and select "New" to create a new schematic.
3. Drag and drop components from the component toolbar onto the workspace.
4. Connect the components using wires.Specify values and properties for components.
5. Add a power supply to the circuit. Connect it appropriately (Vcc and GND).
6. Double-click on components to open their properties.
7. Set parameters, such as resistor values, capacitor values, etc.
8. Click on "Simulate" in the toolbar.
9. Set simulation parameters like start time, stop time, and time step.
10. Add instruments to measure and observe circuit behavior.
11. Click on the "Run" button (play icon) to start the simulation.
12. Observe and analyze waveforms and measurements from the instruments. Check for correct
circuit behavior.
13. If unexpected results occur, review the circuit, component values, and connections. Make
necessary adjustments and rerun the simulation.
14. Save your schematic and simulation results.
15. Document the circuit design, simulation parameters, and observed behavior.
16. Export simulation results or circuit diagrams for sharing or further analysis.
Simulation Output:
HALF ADDER
FULL ADDER
HALF SUBSTRACTOR
FULL SUBSTRACTOR
Results & conclusions: Simulated 4-bit full adder and subtractor in Multisim, verified correct
outputs, efficient gate use, and stable performance. Achieved accurate, optimized, and versatile circuit
design.
3. How many control inputs are there in a 4-bit full subtractor for each XOR gate used?
2
Answer: Basic gates include AND gates, XOR gates, and OR gates.
8. How would you simulate the 4-bit full adder and subtractor using basic gates in a
software tool like Multisim or similar?
Answer: Create a schematic in the simulation tool, instantiate the required basic gates (AND,
XOR, OR), and interconnect them according to the design of the 4-bit full adder and
subtractor. Apply appropriate inputs and observe the outputs.
9. How many XOR gates are required for the sum output in a 4-bit full adder?
Answer: Four XOR gates are required for generating the sum outputs in a 4-bit full adder.
10. Can you identify any challenges or considerations when designing a 4-bit full
subtractor?
Answer: One consideration is managing borrow inputs for each bit subtraction, and careful
handling of borrow propagation to ensure accurate subtraction results.
EXPERIMENT NO – 03
Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.
Aim: To design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.
Objectives:
1. Implement Verilog for simple circuits using structural, data flow, and behavioral models.
2. Verify designs through simulation for functionality and performance assessment.
Theory:
As mentioned previously, the module is the basic building block for modeling hardware with the
Verilog HDL. The logic of a module can be described in anyone (or a combination) of the
following modeling styles:
FIGURE 3.1: Relationship of Verilog constructs to truth tables, Boolean equations, and
schematics
• Dataflow modeling using continuous assignment statements with the keyword assign.
o Dataflow modeling is used mostly for describing the Boolean equations of
combinational logic.
• Behavioral modeling using procedural assignment statements with the keyword always.
o behavioral modeling that is used to describe combinational and sequential circuits
at a higher level of abstraction.
Combinational logic can be designed with truth tables, Boolean equations, and schematics; Verilog has
a construct corresponding to each of these “classical” approaches to design: user-defined primitives,
continuous assignments, and primitives, as shown in Fig. 3.1. There is one other modeling style, called
switch-level modeling. It is sometimes used in the simulation of MOS transistor circuit models, but not
in logic synthesis. We will not consider switch-level modeling.
Procedure / activity:
1. Open a Xilinx IDE, close old projects.
2. Create a new project through the project navigator icon.
3. Add VHDL/Verilog new source to the project depending on the user requirement.
4. Select the Verilog HDL mode.
5. Assign the inputs and outputs for the system to design.
6. And write the code as given below for the functionality.
7. Synthesize the code and correct the syntax errors if any.
8. Isim Simulator and Behavioral check syntax the Simulation behavioral model.
9. Observe the output timing waveform and verify it with the truth table.
Verilog code:
Structural- Data Flow- Behavioural Model-
module logicg(a, module ldataflow(a, module logicgB(a,
b,y0,y1,y2,y3,y4,y5,y6); b,y0,y1,y2,y3,y4,y5,y6); b,y0,y1,y2,y3,y4,y5,y6);
input a,b; input a,b; input a,b;
output y0,y1,y2,y3,y4,y5,y6; output y0,y1,y2,y3,y4,y5,y6; output y0,y1,y2,y3,y4,y5,y6;
not g1(y0,a); assign y0=!a; reg y0;
and g2(y1,a,b); assign y1=a&b; reg y1;
or g3(y2,a,b); assign y2=a|b; reg y2;
nand g4(y3,a,b); assign y3=!(a&b); reg y3;
nor g5(y4,a,b); assign y4=!(a|b); reg y4;
xor g6(y5,a,b); assign y5=a^b; reg y5;
xnor g7(y6,a,b); assign y6=!(a^b); reg y6;
endmodule endmodule always @(a,b)
begin
y0=!a;
y1=a&b;
y2=a|b;
y3=!(a&b);
y4=!(a|b);
y5=a^b;
y6=!(a^b);
end
endmodule
Simulation Output:
Results & conclusions: The Verilog code for simple circuits using structural, Data flow and
Behavioral model are verified.
EXPERIMENT NO – 04
Aim: To Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half
and Full Subtractor.
Objectives:
1. Create Verilog HDL for Binary Adder-Subtractor, including Half and Full Adder, Half and Full
Subtractor.
2. Validate functionality through simulation for accurate arithmetic operations in digital systems.
Theory:
Adder is a combinational digital circuit that is used for adding two numbers. A typical adder circuit
produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Adder circuits are of
two types: Half adder and Full adder.
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called
a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the
carry bit, C.
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry
bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits,
A and B, and a carry-in bit Cin, is called a full-adder.
Subtractor is a combinational digital circuit that is used for subtracting two numbers. A typical
subtractor circuit produces a diff bit (denoted by D) and a borrow bit (denoted by B)as the output.
Subtractor circuits are of two types: Half subtractor and Full subtractor.
Half Subtractor: A combinational logic circuit that performs the subtraction of two data bits, A and B,
is called a half-adder. Subtraction will result in two output bits; one of which is the diff bit, D, and the
other is the borrow bit, B.
Full Subtractor: A combinational logic circuit that subtractor two data bits, A and B and a borrow in
bit, is called full subtractor.
Half Adder
Half Subtractor
Full Adder
Full Subtractor
Procedure / activity:
1. Open a Xilinx IDE, close old projects.
2. Create a new project through the project navigator icon.
3. Add VHDL/Verilog new source to the project depending on the user requirement.
4. Select the Verilog HDL mode.
5. Assign the inputs and outputs for the system to design.
6. And write the code as given below for the functionality.
7. Synthesize the code and correct the syntax errors if any.
8. Isim Simulator and Behavioral check syntax the Simulation behavioral model.
9. Observe the output timing waveform and verify it with the truth table.
Verilog code:
Half Adder- Half Substractor-
module halfadder(a,b,sum,carry); module HS(a,b,diff,borrow);
input a,b; input a,b;
output sum,carry; output diff,borrow;
assign diff=a^b;
assign sum=a^b;
assign borrow=!(a)&b;
assign carry=a&b; endmodule
endmodule
Full Adder- Full Substractor-
module FA(a,b,c,sum,carry); module FS(a,b,c,diff,borrow);
input a,b,c; input a,b,c;
output sum,carry; output diff,borrow;
assign sum=a^b^c; assign diff=a^b^c;
assign carry=(a&b)||(b&c)||(c&a); assign borrow=((!a)&b)|(b&c)|((!a)&c);
endmodule endmodule
.sum(sum), .diff(diff),
.carry(carry) ); .borrow(borrow) );
initial begin initial begin
a = 0; b = 0; #100; a = 0; b = 0; #100;
a = 0; b = 1; #100; a = 0; b = 1; #100;
a = 1; b = 0; #100; a = 1; b = 0; #100;
a = 1; b = 1; #100; a = 1; b = 1; #100;
end end
endmodule endmodule
Simulation Output:
Half Adder-
Half Substractor-
Full Adder-
Full Substractor
Results & conclusions: The Verilog code for adders and subtractors are verified.
Ans: A Half Adder adds two binary digits (bits) and produces a sum and a carry-out. It lacks the
ability to handle a carry-in from a previous stage.
6. How does a Half Subtractor handle the case when the minuend is smaller than the
subtrahend?
Ans: In such cases, the Half Subtractor produces a difference without a borrow-out, signifying that
no borrowing is required for the subtraction.
7. Explain the significance of the carry-in and borrow-in signals in Full Adders and Full
Subtractors.
Ans: The carry-in (Cin) in Full Adders and the borrow-in in Full Subtractors represent inputs from
the previous stage, allowing these circuits to operate on multiple bits.
EXPERIMENT NO – 05
Theory: BCD or Binary coded decimal is a way of representing decimal digits in binary form.
Generally 4 bits are used to represent values 0 to 9.
BCD BCD
Decimal Digit Decimal Digit
8421 8421
0 0000 5 0101
1 0001 6 0110
2 0010 7 0111
3 0011 8 1000
4 0100 9 1001
A BCD adder, takes in two BCD numbers as inputs, and outputs a BCD digit along with a carry output.
If the sum of the BCD digits is less than or equal to 9, then we don't have a problem. But if its greater
than 9, we have to convert it into BCD format. This is done by adding 6 to the sum and taking only the
least significant 4 bits. The MSB bit is output as carry.
Consider the below BCD addition:
1001 + 1000 = 10001
9 + 8 = 17
The output 17 is more than 9. So we add 6 to it. So we get,
17+6 = 23 (in binary 23 is 10111)
Now the least significant 4 bits (which is "0111") represent the units digit and the MSB(4th bit which
is '1') bit represents the tens digit. Since the range of input is 0 to 9, the maximum output is 18. If you
consider a carry it becomes 19. This means at the output side we need a 4 bit sum and a 1 bit carry to
represent the most significant digit. These binary numbers are listed below
The condition for a correction and an output carry can be expressed by the Boolean Function
C = K + Z8Z4 + Z8Z2
When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next
stage. A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in Figure
below.
Logic Diagram:
For multiple digit addition, you can connect the carry_out to the carry input of the next adder. A simple
cascading network of these small adders is enough to realize the multiple digit BCD addition.
Equipment:
• Computer with Modelsim SoftwareSpecifications:
• HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
• Softwares: Modelsim - 5.7c, Xilinx - 14.1i.
Procedure:
3. Add VHDL/Verilog new source to the project depending on the user requirement.
4. Select the Verilog HDL mode.
5. Assign the inputs and outputs for the system to design.
6. And write the code as given below for the functionality.
7. Synthesize the code and correct the syntax errors if any.
8. Isim Simulator and Behavioral check syntax the Simulation behavioral model.
9. Observe the output timing waveform and verify it with the truth table.
module deciadder(a,b,carry_in,sum,carry);
//declare the inputs and outputs of the module with their sizes.
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
//always block for doing the addition
always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9)
begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0];
end
else
begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
module deciadder_tb;
reg [3:0] a;
reg [3:0] b;
reg carry_in;
wire [3:0] sum;
wire carry;
deciadder uut (.a(a), .b(b), .carry_in(carry_in), .sum(sum), .carry(carry));
initial begin
// Initialize Inputs
a = 9;
b = 6;
carry_in = 0;
#100;
end
endmodule
Simulation waveform:
Results & conclusions: The Verilog code for Decimal adder is simulated and verified.
6. How does the addition process differ between binary and decimal adders?
Ans: Decimal addition involves carrying over to the next decimal place when the sum exceeds
9, while binary addition carries over when the sum exceeds 1.
EXPERIMENT NO – 06
Design Verilog program to implement Different types of multiplexer like 2:1, 4:1
and 8:1.
Aim: Design Verilog program to implement Different types of multiplexers like 2:1, 4:1 and 8:1.
Objectives:
1. Develop Verilog program for 2:1, 4:1, 8:1 multiplexer design.
2. Validate through simulation for accuracy and efficiency in circuit implementation.
Theory:
➢ A multiplexer (or data selector, abbreviated as MUX) has a group of data inputs (2n) and a group
of control inputs (n) (also called as select inputs).
➢ The control inputs are used to select one of the data inputs and connect it to the output terminal.
2:1 Multiplexer
➢ A 2 to 1 multiplexer has 2 data inputs, 1 select input and 1 output.
Truth Table:
Select (S) Output (Z)
0 I0
1 I1
➢ The logic equation for the 2-to-1 MUX can be written as:
𝐙 = 𝐒̅𝐈𝟎 + 𝐒𝐈𝟏
Logic Diagram:
Logic Diagram:
8:1 Multiplexer
➢ An 8 to 1 multiplexer has 8 data inputs, 3 select inputs and 1 output. 8 to 1 MUX selects one of
eight data inputs using three select inputs
𝐙 = 𝐒̅𝟐 𝐒̅𝟏 𝐒̅𝟎 𝐈𝟎 + 𝐒̅𝟐 𝐒̅𝟏 𝐒𝟎 𝐈𝟏 + 𝐒̅𝟐 𝐒𝟏 𝐒̅𝟎 𝐈𝟐 + 𝐒̅𝟐 𝐒𝟏 𝐒𝟎 𝐈𝟑 + 𝐒𝟐 𝐒̅𝟏 𝐒̅𝟎 𝐈𝟒 + 𝐒𝟐 𝐒̅𝟏 𝐒𝟎 𝐈𝟓 + 𝐒𝟐 𝐒𝟏 𝐒̅𝟎 𝐈𝟔
+ 𝐒𝟐 𝐒𝟏 𝐒𝟎 𝐈𝟕
Procedure / activity:
1. Open a Xilinx IDE, close old projects.
2. Create a new project through the project navigator icon.
3. Add VHDL/Verilog new source to the project depending on the user requirement.
4. Select the Verilog HDL mode.
5. Assign the inputs and outputs for the system to design.
6. And write the code as given below for the functionality.
7. Synthesize the code and correct the syntax errors if any.
8. Isim Simulator and Behavioral check syntax the Simulation behavioral model.
9. Observe the output timing waveform and verify it with the truth table.
Verilog code:
2:1 MUX 4:1 MUX 8:1 MUX
module two_to_one_MUX module four_to_one_MUX module eight_to_one_MUX
(I0,I1,S,Y); (I1,I2,I3,I4,S1,S2,Y); (I1,I2,I3,I4,I5,I6,I7,I8,S1,S2,S3,Y);
input I0; input I1,I2,I3,I4; input I1,I2,I3,I4,I5,I6,I7,I8;
input I1; input S1,S2; input S1,S2,S3;
input S; output Y; output Y;
output Y;
wire S_bar,w1,w2; assign assign Y=((!S1)&(!S2)&(!S3)&I1)
not g1(S_bar,S); Y=((!S1)&(!S2)&I1)|((!S1 |((!S1)&(!S2)&S3&I2)|((!S1)&S2&
and (w1,I0,S_bar); )&(S2)&I2)|(S1&(!S2)&I3 (!S3)&I3)|((!S1)&S2&S3&I4)|(S1
and (w2,I1,S); )|(S1&S2&I4); &(!S2)&(!S3)&I5)|(S1&(!S2)&S3
or (Y,w1,w2); endmodule &I6)|(S1&S2&(!S3)&I7)|(S1&S2&
endmodule S3&I8);
endmodule
Simulation Output:
2:1 MUX
4:1-MUX
8:1 MUX
7. Can Verilog code for a 2:1 multiplexer be reused for a 4:1 multiplexer? Why or why not?
Ans: Some code can be reused, but adjustments are needed for the increased number of inputs.
8. How does the complexity of a multiplexer circuit increase with the number of inputs?
Ans: The complexity of a multiplexer circuit increases linearly with the number of inputs, leading to
more logic gates and connections.
EXPERIMENT NO – 07
Aim:
To Design Verilog program to implement Different types of De-multiplexer like 1:2, 1:4 and 1:8.
Objectives:
1. Implement Verilog program for 1:2, 1:4, 1:8 Demultiplexer designs.
2. Verify functionality through simulation for accuracy and performance assessment.
Theory:
A De-multiplexer is a combinational circuit that has only 1 input line and 2N output lines. Simply, the
multiplexer is a single-input and multi-output combinational circuit. The information is received from
the single input lines and directed to the output line. On the basis of the values of the selection lines,
the input will be connected to one of these outputs. De-multiplexer is opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2n outputs. So, there is a total of 2n possible
combinations of inputs. De-multiplexer is also treated as De-mux.
1×2 De-multiplexer: In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1
selection lines, i.e., S0, and single input, i.e., A. Based on the selection value, the input will be connected
to one of the outputs. The block diagram and the truth table of the 1×2 multiplexer are given below.
1×4 De-multiplexer: In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and
Y3, 2 selection lines, i.e., S0 and S1 and single input, i.e., A. Based on the combination of inputs which
are present at the selection lines S0 and S1, the input be connected to one of the outputs. The block
diagram and the truth table of the 1×4 multiplexer is given below.
Block Diagram: Truth Table:
1×8 De-multiplexer: In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y0, Y1, Y2,
Y3, Y4, Y5, Y6, and Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of
the combination of inputs which are present at the selection lines S0, S1 and S2, the input will be
connected to one of these outputs. The block diagram and the truth table of the 1×8 de-multiplexer
is given below.
Block Diagram: Truth Table:
Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A
Logical circuit of the above expressions is given below:
Procedure / activity:
1. Open a Xilinx IDE, close old projects.
2. Create a new project through the project navigator icon.
3. Add VHDL/Verilog new source to the project depending on the user requirement.
4. Select the Verilog HDL mode.
5. Assign the inputs and outputs for the system to design.
6. And write the code as given below for the functionality.
7. Synthesize the code and correct the syntax errors if any.
8. Isim Simulator and Behavioral check syntax the Simulation behavioral model.
9. Observe the output timing waveform and verify it with the truth table.
Verilog code:
1:2 DEMUX 1:4 DEMUX 1:8 DEMUX
module demux12_BM(S0,A,Y); module module
input A, S0; one_four_demux_BM(S,A,Y); one_eight_demux_BM(S,A,Y);
wire A, S0; input A; input A;
wire A; wire A;
output [1:0] Y;
input [1:0] S; input [2:0] S;
reg [1:0] Y; wire [1:0] S; wire [2:0] S;
always @ (A or S0) output [3:0] Y; output [7:0] Y;
begin reg [3:0] Y; reg [7:0] Y;
case(S0)
1'b0: Y={A,1'b0}; always @(A or S) begin always @(A or S)
default: Y={1'b0, A}; begin
case(S)
endcase
1'b00: Y= {A,3'b000}; case(S)
end 1'b01: Y= {1'b0, A,2'b00}; 0: Y={A,7'b0000000};
endmodule 1'b10: Y= {2'b00, A,1'b0}; 1: Y= {1'b0, A,6'b000000};
default: Y= {3'b000, A}; 2: Y= {2'b00, A,5'b00000};
endcase 3: Y= {3'b000, A,4'b0000};
end 4: Y= {4'b0000, A,3'b000};
endmodule 5: Y= {5'b00000, A,2'b00};
6: Y= {6'b000000, A,1'b0};
default: Y= {7'b0000000, A};
endcase
end
endmodule
Simulation Output:
1:2 DEMUX
1:4 DEMUX
1:8 DEMUX
EXPERIMENT NO – 08
Design Verilog program for implementing various types of Flip-Flops such as SR,
JK and D
Aim: To design and simulate Verilog modules for three different types of flip-flops (SR, JK, and D)
using behavioral modeling. The program should demonstrate the functionality and behavior of these
flip-flops under various input conditions.
Objectives:
• Implement Verilog modules for SR, JK, and D flip-flops using behavioral modeling. Develop
a testbench to simulate the behavior of the implemented flip-flops.
• Apply different input conditions to the flip-flops in the testbench to observe their responses.
• Verify that the flip-flops exhibit the expected sequential logic behavior, such as state changes
and toggling.
Theory:
Flip-flops are synchronous bitable devices. The term synchronous means the output changes state
only when the clock input is triggered. That is, changes in the output occur in synchronization with
the clock. A flip-flop circuit has two outputs, one for the normal value and one for the complement
value of the stored bit. Since memory elements in sequential circuits are usually flip-flops, it is worth
summarizing the behavior of various flip-flop types before proceeding further. Flip-flops can be
divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response
invoked by different value of input signals. The four types of flip-flops are defined in the Table 8.1.
Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its
characteristic equation or excitation table. All flip-flops have output signals Q and Q'.
Q Q(next) D
D D Q(next) 0 0 0
0 0 Q(next) = D 0 1 1
1 1 1 0 0
1 1 1
Logic diagram
Procedure:
1. Open a Xilinx IDE, close old projects.
2. Create a new project through the project navigator icon.
3. Add VHDL/Verilog new source to the project depending on the user requirement.
4. Select the Verilog HDL mode.
5. Assign the inputs and outputs for the system to design.
6. And write the code as given below for the functionality.
7. Synthesize the code and correct the syntax errors if any.
8. Isim Simulator and Behavioral check syntax the Simulation behavioral model.
9. Observe the output timing waveform and verify it with the truth table.
Verilog code:
1. SR Flip-Flop 2. JK Flip Flop 3. D Flip Flop
module srlax( module JK_FF( module D_FF(
input wire S, input wire j, input wire D,
input wire R, input wire k, output reg Q,
input output reg Q, output reg Q, output wire Q_bar
output wire Q_bar ); output wire Q_bar ); );
always @(S, R) begin
if (S && ~R) always @(j, k) begin always @(D) begin
Q <= 1'b1; if (j && ~k) if (D==0)
else if (~S && R) Q <= 1'b1; Q <= 0;
Q <= 1'b0; else if (~j && k) else
else if (S==0 && R==0) Q <= 1'b0; Q <= 1;
Q <= Q; else if (j==0 && k==0) end
else if (S==1 && R==1) Q <= Q;
Q <= 1'bz; else if (j==1 && k==1) assign Q_bar = ~Q;
end Q <= !Q; endmodule
assign Q_bar = ~Q; end
endmodule assign Q_bar = ~Q;
endmodule
2. JK Flip Flop
3. D Flip Flop