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Assignment 1 dsd

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Assignment 1 dsd

Uploaded by

Uzair Ashfaq
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© © All Rights Reserved
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Assignment #01

Assignment
Submitted By
NAME Registration Number
Abdullah Ahsan FA20 - EEE-027 /ATD

For the course

DSD
Semester Fall 2023
Supervised by:
Dr. Shahid Nawaz Khan

Department of Electrical & Computer Engineering


COMSATS University Islamabad – Abbottabad Campus
Using (a) case and (b) if statement, write an HDL description of an 8-bit arithmetic
logic unit (ALU). The circuit has a three bit select bus (Sel), 8-bit input data-paths
A[7:0] and B[7:0], an 8-bit output data-path y[7:0], and perform the arithmetic
and logical operations
module ALU( reg [3:0] sel;
input wire [7:0] A,B, wire [7:0] out;
input wire [3:0] S, ALU alu1(.A(in1),.B(in2),.S(sel),.Y(out));
output reg [7:0] Y initial
); begin
always @(A,B,S) in1=8'b00011011;
if (S==000) in2=8'b00000001;
Y=8'b00000000; sel=3'b000;
else if (S==001) #10 sel=3'b001;
Y=(A & B); #10 sel=3'b010;
else if(S==010) #10 sel=3'b011;
Y=(A|B); //CHANGING THE INPUT +5
else if(S==011) in1=8'b00100000;
Y=(A^B); in2=8'b00000110;
else if (S==100) #10 sel=3'b100;
Y=(A+B); #10 sel=3'b101;
else if(S==101) #10 sel=3'b110;
Y=(A-B); //CHANGING THE INPUT -5
else if(S==110) in1=8'b00010110;
Y=~(A); in2=8'b00000000;
else if(S==111) #10 sel=3'b111;
Y=(A*B); #10 sel=3'b000;
Endmodule #10 sel=3'b001;
Testbench: #10 $stop;
module tb_ALU; end
reg [7:0] in1, in2; endmodule
Result:

Write a Verilog code for 4x1 Multiplexer using (CLO-1)


a. Conditional operator + assign statement.
b. Procedural Statements (If, Else)
c. By instantiating 2to1 Multiplexers (write code of 2to1 Mux and then use it to
design 4to1 Mux)
d. Write test bench and include Modelsim simulation results for (a) and (b) and (c)
parts.
Part a.
module Mux4_1( reg [1:0] sel;
input wire [3:0] I, wire out;
input wire [1:0] S, Mux4_1 Mu(.I(inp),.S(sel),.Y(out));
output wire Y initial
); begin
assign Y=(S==2'b00)? I[0]: inp=4'b0101;
(S==2'b01)? I[1]:
(S==2'b10)? I[2]: sel=2'b00;
(S==2'b11)? I[3]: #10 sel=2'b01;
I[3]; #10 sel=2'b10;
#10 sel=2'b11;
endmodule #10 $stop;
TestBench: end
module tb_Mux4_1; endmodule
reg [3:0] inp;
Results :

Part b:
module muxbyif( reg [1:0] sel;
input wire [3:0] I, wire out;
input wire [1:0] S, muxbyif Mu(.I(inp),.S(sel),.Y(out));
output reg Y initial
); begin
always @ (I,S) inp=4'b0101;
if (S==2'b00)
Y=I[0]; sel=2'b00;
else if (S==2'b0) #10 sel=2'b01;
Y=I[1]; #10 sel=2'b10;
else if (S==2'b10) #10 sel=2'b11;
Y=I[2]; #10 $stop;
else if(S==2'b11) end
Y=I[3]; endmodule

endmodule
Testbench
module tb_muxbyif;
reg [3:0] inp;
Result:

Part c.
module mux_4to1 initial
( begin
input wire [1:0] a,b, in1= 4'b0000; in2=4'b0000; selec=1'b1;
input wire sel, #15 in1= 4'b0011; in2=4'b1100; selec=1'b1;
output wire [1:0] f #15 in1= 4'b1010; in2=4'b0101; selec=1'b1;
); #15 in1= 4'b1000; in2=4'b0111; selec=1'b1;
#15 in1= 4'b0110; in2=4'b1001; selec=1'b1;
mux_2to1 #15 in1= 4'b1111; in2=4'b1111; selec=1'b1;
m0(.f(f[0]),.sel(sel),.a(a[0]),.b(b[0])); #15 $stop ;
mux_2to1 end
m1(.f(f[1]),.sel(sel),.a(a[1]),.b(b[1]));

endmodule

module tb_4bmux;
reg [3:0] in1,in2;
reg selec;
wire [3:0] out;

mux_4to1
m1(.a(in1),.b(in2),.sel(selec),.f(out));
Result:

Question 3
The binary-coded-decimal (BCD) format uses 4 bits to represent 10 decimal digits.
For example, (259)10 is represented as "0010 _0101_1001" in BCD format. A
BCD incrementor adds 1 to a number in BCD format. For example, after
incrementing, “0010_0101_100 1 " (i.e., 25910) becomes "0010 _0110 _0000"
(i.e., 26010). (CLO-1)
a. Design a three-digit 12-bit incrementor and derive the code.
b. Derive a testbench and use simulation to verify operation of the code.
Code:
module BCD_incrementor( if (in[11:8] < 4'b1001)
input [11:0] in, out[11:8] = in[11:8] + (in[7:4] == 4'b1001);
output reg [11:0] out); else
always @* out[11:8] = 4'b0000;
begin end
if (in[3:0] < 4'b1001) endmodule
out[3:0] = in[3:0] + 4'b0001;
else
out[3:0] = 4'b0000; module BCD_incrementor_tb;
if (in[7:4] < 4'b1001) reg [11:0] in;
out[7:4] = in[7:4] + (in[3:0] == 4'b1001); wire [11:0] out;
else BCD_incrementor DUT ( .in(in),.out(out));
out[7:4] = 4'b0000; initial begin
#15 in = 12'b001010010001; // Test case 1
#15 $stop in = 12'b001001011001;
Result

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