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problem sheet2

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aryabanda189
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GOKARAJU RANGARAJU

Institute of Engineering and Technology


(Autonomous Institute under JNTU Hyderabad)
II B Tech I Semester – 2017-18 – GR15 Regulation
DIGITAL LOGIC DESIGN
Problem Sheet 2 – Unit II (Gate Level Minimization)

Syllabus: Gate-Level Minimization: The Map method, Four-variable map, Five-


Variable map, Product of Sum’s simplifications, Don’t care conditions, NAND and NOR
implementation, other two level implementations, Exclusive-OR Function.

1. Simplify the following Boolean functions using three – variable maps:


a) F(x,y,z)=∑(0,2,6,7) b)F(A,B,C)=∑(0,2,3,4,6)
b) F(x,y,z)=∑(0,1,2,3,7) d) F(x,y,z)=∑(3,5,6,7)
2. Simplify the following Boolean functions using three – variable maps:
a) F(x,y,z)=∑(0,1,5,7)
b) F(A,B,C)=∑(1,2,3,6,7)
c) F(x,y,z)=∑(0,1,6,7)
d) F(x,y,z)=∑(0,1,3,4,5)
3. Simplify the following Boolean expressions using three-variable maps:
a) xy+x’y’z’+x’yz’ b) x’y’+yz+x’yz’
c) x'y + yz' + y'z' d) xyz + x'y'z + xyz’

4. Simplify the following Boolean expressions using karnaugh maps:


a) F(x,y,z)=∑(2,3,6,7)
b) F(A,B,C,D)=∑(4,6,7,15)
c) F(A,B,C,D)=∑(3,7,11,13,14,15)
d) F(w,x,y,z)=∑(2,3,12,13,14,15)
e) F(w,x,y,z)=∑(1,4,5,6,7)
f) F(w,x,y,z)= ∑(0,1,5,8,9)
5. Simplify the following Boolean expression using four-variable maps:
(a) w’z+xz+x’y+wx’z
(b) C’D+A’B’C+ABC’+AB’C
(c) AB’C+B’C’D’+BCD+ACD’+A’B’C+A’BC’D
(d) xyz+wy+wxy’+x’y
6. Simplify the following Boolean functions using five variable maps:
(a) F(A, B, C, D, E) = ∑ (0, 1, 4, 5, 16, 17, 21, 25, 29)
(b) F(A, B, C, D, E) = A'B'CE' + B'C'D'E' + A'B'D' + B'CD' + A'CD + A'BD
7. Simplify the following Boolean function to product of sum form:
(a) F =∑ (0, 1, 2, 5, 8, 10, 13)
(b) F = ∏(1, 3, 5, 7, 13, 15)
(c) F = ∏ (1, 3, 6, 9, 11, 12, 14)
8. Give three possible ways to express the following Boolean function with eight or fewer
literals.F=B’C’D’+AB’CD’+BC’D+A’BCD
9. Simplify the following Boolean expressions, together with the don’t care conditions d,
and then express the simplified function in sum of minterms form:
(a) F(x,y,z) =∑ (2,3,4,6,7), d(x,y,z)= =∑ (0,1,5)
(b) F(A,B,C,D) =∑ (0,6,8,13,14), d(A,B,C,D)= ∑(2,4,10)
(c) F(A,B,C,D) =∑ (4,5,6,7,12,13,14), d(A,B,C,D)= ∑(1,9,11,15)
(d) F(A,B,C,D) =∑ (1,3,8,10,15), d(A,B,C,D)= ∑(0,2,9)
10. Simplify the following functions, and implement them with two level NAND gate
circuits:(a) F(A,B,C,D)= A’B’C+AC+ACD+ACD’+A’B’D’+B’CD
(b) F(A,B,C,D)= AB+A’BC+A’B’C’D
(c) F(A,B,C,D)=A’B+A+C’+D’
(d) F(A,B,C)= (A’+B’+C’)(A’+B’)(A’+C’)
11. Draw a NAND logic diagram that implements the complement of the following
function F(A,B,C,D)= ∑(0,1,2,3,8,9,10,12)
12. Simplify the following Boolean functions, and implement with two level NOR gate
circuits:(a) F(w,x,y,z)= ∑(1,2,13,14)
(b) F(x,y,z)=[(x+y)(x’+z)]’
13. Draw the multi level NOR and multilevel NAND circuits for the following
expression: F = (AB' + CD')E + BC(A + B)
14. Draw the multi level NAND circuit for the following expression: w(x+y+z)+xyz
15. Derive the circuits for a three bit parity generator and four bit parity checker using the
parity bit.

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