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1
COMBINATIONAL LOGIC
1.1 INTRODUCTION:
The digital system consists of two types of circuits, namely
Combinational circuits
Sequential circuits
Combinational circuit consists of logic gates whose output at any time is
determined from the present combination of inputs. The logic gate is the most basic
building block of combinational logic. The logical function performed by a
combinational circuit is fully defined by a set of Boolean expressions.
Sequential logic circuit comprises both logic gates and the state of storage
elements such as flip-flops. As a consequence, the output of a sequential circuit
depends not only on present value of inputs but also on the past state of inputs.
A combinational circuit consists of input variables, logic gates, and output
variables. The logic gates accept signals from inputs and output signals are generated
according to the logic circuits employed in it. Binary information from the given data
transforms to desired output data in this process. Both input and output are obviously
the binary signals, i.e., both the input and output signals are of two possible states,
logic1 and logic 0.
For n number of input variables to a combinational circuit, 2n possible
combinations of binary input states are possible. For each possible combination, there
is one and only one possible output combination. A combinational logic circuit can
1.2 Combinational Logic
be described by m Boolean functions and each output can be expressed in terms of n

input variables.
Figure 1.1 Block diagram of a combinational logic circuit

DESIGN PROCEDURE:
Any combinational circuit can be designed by the following steps of design
procedure.
The problem is stated.
Identify the input and output variables.
The input and output variables are assigned letter symbols.
Construction of a truth table to meet input -output requirements.
Writing Boolean expressions for various output variables in terms of input
variables.
The simplified Boolean expression is obtained by any method of
minimization algebraic method, Karnaugh map method, or tabulation
method.
A logic diagram is realized from the simplified boolean expression using logic
gates.
The following guidelines should be followed while choosing the preferred form
for hardware implementation:
The implementation should have the minimum number of gates, with the gates
used having the minimum number of inputs.
There should be a minimum number of interconnections.
Limitation on the driving capability of the gates should not be ignored.
BASIC LOGIC GATES:
Logic gates are electronic circuits that can be used to implement the most
elementary logic expressions, also known as Boolean expressions. The logic gate is the
Digital Principles and Computer Organization 1.3
most basic building block of combinational logic.

There are three basic logic gates, namely the OR gate, the AND gate and the NOT
gate. Other logic gates that are derived from these basic gates are the NAND gate, the
NOR gate, the EXCLUSIVE- OR gate and the EXCLUSIVE-NOR gate.
GATE SYMBOL OPERATION TRUTH TABLE
NOT gate (Invertion),

NOT producesan inverted output
pulse for a given input pulse.
(7404)
AND gate performs logical

multiplication. The output is
HIGH only when all the inputs
AND
are HIGH. When any of the
(7408) inputs are low, the output is
LOW.
OR gate performs logical

addition. It produces a HIGH
on the output when any of the
OR
inputs are HIGH. The output is
(7432) LOW only when all inputs are
LOW.
It is a universal gate. When

anyof the inputs are LOW, the
output will be HIGH. LOW
NAND
output occurs only when all
(7400) inputs are HIGH.
It is a universal gate. LOW

output occurs when any of its
input is HIGH. When all its
NOR
inputs are LOW, the output is
(7402) HIGH.
EX- OR The output is HIGH only when

(7486) odd number of inputs is HIGH.
The output is HIGH only when

EX- even number of inputs is
NOR HIGH.
Or when all inputs are zeros.
1.2 REPRESENTATION OF LOGIC FUNCTIONS

The logic functions and structure of a combinational logic block is represented
by three different ways:
1. Truth table
2. Logic gates
3. Boolean functions
1.2.1 Truth table

A truth table is a table which shows the input-output relationship of
combinational logic functions using logic 1 for true and logic 0 for false. A typical truth
table for a logic function withthree inputs X, Y and Z and a single output F is shown in
table.
X Y Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
Any combinational logic can be represented by truth tables but, in some cases the
table became too large.
1.2.2 Logic gates

The circuit details of a combinational logic block are determined by logic gates.
Logic gates are simple circuits that can be wired together to implement any
Combinational Logic function.
Basic Logic Gates
There are three basic logic gates each of which performs a basic logic function, they
are called NOT, AND and OR. All other logic functions can ultimately be derived from
combinations of these three. For each of three basic logic gates a summary is given
including the logic symbol, the corresponding truth table and the Boolean expression.
The NOT gate
The NOT gate is unique in that it only has one input. The logic symbol of NOT
gate is shown in Figure 1.2.
Fig. 1.2 Logic Symbol

The input to the NOT gate A is inverted i.e., the binary input state of 0 gives an
output of 1 andthe binary input state of 1 gives an output of 0.
A is known as or alternatively as the complement of A.
The truth table for the NOT gate appears as below:

Table 1.1 Truth Table
The AND gate

The AND gates has two or more inputs. The output from the AND gate is 1 if and
only if all of the inputs are 1, otherwise the output from the gate is 0. The AND gate is
drawn as shown in Figure 2.3.
Fig. 1.3: Logic Symbol

The output from the AND gate is written as A . B
The truth table for a two-input AND gate is given below:
A TRUTH TABLE A- B
B
0 0 0
0 1 0
1 0 0
1 1 1
The OR gate
The OR gate has two or more inputs. The output from the OR gate is 1 if any of
the inputs is 1. The gate output is 0 if and only if all inputs are 0. The OR gate is drawn
as shown in Figure 2.4.
Fig. 1.4 : Logic Symbol

The output from the OR gate is written as A + B.

The truth table for a two-input OR gate is given below:
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
Other Logic Gates

The three basic logic gates can be combined to provide more complex logical
functions. Four important logical functions are described here, namely NAND, NOR,
XOR and XNOR. In each case a summary is given including the logic symbol for that
function, the corresponding truth table and the Boolean expression.
The NAND gate
The NAND gate has two or more inputs. The output from the NAND gate is 0 if
and only if all of the inputs are 1 otherwise the output is 1. Therefore the output from the
NAND gate is the NOT of A AND B (also known as the complement or inversion of A-
B ). The NAND gate is shown in Figure 1.5 where the small circle immediately to the
right of the gate on the output line is known as an invert bubble.

The output from the NAND gate is written as . The Boolean expression
reads as NAND The truth table for a two-input NAND gate is given below:
A B
0 0 1
0 1 1
1 0 1
1 1 0
The NOR gate

The NOR gate has two or more inputs. The output from the NOR gate is 1 if and
only if all of the inputs are 0, otherwise the output is 0. This output behaviour is the NOT
of A OR B. The NOR gate is drawn as shown in Figure 1.6.
Fig. 1.6: NOR-Logic Symbol

The output from the NOR gate is written as A+B which reads
The truth table for a two-input NOR gate is given below:
A B
0 0 1
0 1 0
1 0 0
1 1 0
The Exclusive-OR (XOR) gate

The exclusive-OR or XOR gate has two or more inputs. For a two-input XOR the
output is similar to that from the OR gate except it is 0 when the both inputs are 1. This
cannot be extended to XOR gates comprising 3 or more inputs however.
In general, an XOR gate gives an output value of 1 when there are an odd number
truth table for a 3-input XOR gate below illustrates
this point.
The XOR gate is drawn as shown in Figure 1.7.
Fig. 1.7: XOR-Logic Symbol

The output from the XOR gate is written as which reads OR
The truth table for a two-input XOR gate looks like
For a 3-input XOR gate with inputs A, B and C the truth table is given by
The Exclusive-NOR (XNOR) gate

The exclusive-NOR or XNOR gate has two or more inputs. The output is
equivalent to inverting the output from the exclusive-OR gate described above. Therefore an
equivalent circuit would comprise an XOR gate, the output of which feeds into the input
of a NOT gate.
In general, an XNOR gate gives an output value of 1 when there are an even number
of on the inputs to the gate. The truth table for a 3-input XNOR gate below illustrates
this point.
The XNOR gate is drawn using the same symbol as the XOR gate with an invert
bubble on the output line as is illustrate in Figure 1.8.

The output from the XNOR gate is written as which reads XNOR
The truth table for a two-input XNOR gate looks like

For a 3-input XNOR gate with inputs A, B and C the truth table is given by
A B C
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
UNIVERSAL GATES
NAND Gate as a Universal Gate
The NAND gate is said to be a universal gate because any digital system can be
implemented with it. The implementation of AND, OR and NOT operations with NAND
gates is shown in Figure 1.9 and EX-OR operations with NAND gates is shown in Figure
1.10.
Fig. 1.9: Implementation of basic gates using NAND

Exclusive OR with NAND
Fig. 1.10: Implementation of EX-OR gate

NOR Gate as a Universal Gate
The NOR gate is called a universal gate because combinations of it can be used to
accomplish all the basic functions. The implementation of basic gates using NOR gate is
shown in Figure 1.11.
Fig. 1.11: Implementation of Basic gates using NOR

Example 1.1: Draw the logic circuit using basic gates for the function
Example 1.2: Reduce the given combinational logic circuit to a minimum form.
Solution:
Applying theorem an Boolean algebra,
The simplified circuit is,

1.2.3 Boolean functions

In 1854 George Boole introduced a systematic treatment of logic and developed
for this purpose, an algebraic system called as Boolean algebra. His variables took on the
values of TRUE and FALSE. Later, Claude Shannon showed how to map Boolean
algebra to digital circuits.
Boolean algebra has collection of laws apply to Boolean expressions called
Boolean laws or Boolean theorems. These are simple algebraic equalities that are known
to be true. The Boolean expressions are manipulated through successive application of
these laws. The table shows the most important Boolean laws:
TABLE 1.8: Boolean Theorems
Example 1.3:
W = ABC + CAB + BAC
= ABC + ABC + ABC (Theorem 1a)
= ABC + ABC (Theorem 3b)
= ABC
Example 1.4:
Example 1.5:
Example 1.6:
Y = AB + A(B + C) + B(B + C)
= AB + AB + AC + BB + BC
= AB + AB + AC + B + BC (BB = B)
= AB + AC + B + BC (AB + AB = AB)
= AB + AC + B (B + BC = B)
= AC + B (B + BA = B)
Example 1.7:
Simplify the following Boolean expression to a minimum number of literals: (Dec
2011)
1.2.3.1 Boolean rules for simplification

Boolean algebra finds its most practical use in the simplification of logic circuits.
To translate a logic function into symbolic (Boolean) form, and apply certain
algebraic rules to the resulting equation to reduce the number of terms and/or arithmetic
operations, the simplified equation may betranslated back into circuit form a logic circuit
performing the same function with fewer components. If equivalent function may be
achieved with fewer component, the result will be increased reliability and decreased cost
of manufacture.
To this end, there are several rules of Boolean algebra presented in this section for
use in reducing expressions to their simplest forms. The identities and properties already
reviewed in this chapter are very useful in Boolean simplification, and for the most part
bear similarity to many identities and
shown in this section are all unique to Boolean mathematics.
Rule 1:
Fig. 1.12: Logic diagram for A + AB = A

This rule may be proven symbolically by factoring an A out of the two terms,
then applying the rules of A + 1 = 1 and 1A = A to achieve the final result:
A + AB
Factoring A out of both terms

A(1 + B)
Applying identity B + 1 = 1
A(1)
Applying identity 1A = A
A
Rule 2: (Dec. 2005)
Fig. 1.13: Logic diagram for A +AB =A +B
Rule 3:
Fig. 1.14: Logic diagram (A + B) (A + C) = A + BC

And, the corresponding proof:
Example 1.8: Simplify the expression AB + BC(B + C)
Fig. 1.15: Logic diagram
The final expression, B(A + C), is much simpler than the original, yet performs the
same function. The truth tables for these two expressions should be identical.
Fig. 1.16: Simplified function diagram
1.3 SUM-OF-PRODUCTS METHOD

The logical sum of those fundamental products that produce output 1's in the truth
table. The corresponding logic circuit is an AND-OR circuit or the equivalent NAND-
NAND circuit.
For example, is a standard sum of products of A, B and
C are the only variables pertaining to the logic. Note that this expression is not in simplest
form because we can write,
This simplified expression is a sum of products; but not a standard sum of

products.
The logic expression corresponding to a given truth table can be written in a
standard sum-of- products form of writing one product term for each input combination
that produces an output of 1. These product terms are ORed together to create the standard
sum of products.
TABLE 1.9: SOP table
We note that F is 1 when A = 0, B = 0 and C = 1 , so this particular combination

makes the outputof an AND gate equal to 1 when and roman and C are all equal to
1. Thus is one product term. Similarly other two product terms are is and
is. Thus the standard sum-of-products form is,
Consider the truth table given in Table 1.10.

TABLE 1.10: Design Truth Table
Figure 1.17 shows the AND-OR logic circuit and Figure 1.18 shows the NAND-
NAND circuit for the expression.
Fig. 1.17: AND-OR circuit

Fig. 1.18: NAND-NAND circuit
Example 1.9:
Suppose a truth table has a low output for the first three input conditions: 000, 001
and 010. If all other outputs are high, what is the product-of-sum (POS) form?
Solution:
Example 1.10:
Suppose a 3 variable truth table has a high output for these input conditions:
000,010, 100 and 110. What is the sum-of-product (SOP) form?
Solution:
Example 1.11:
Convert the Boolean expressions to SOP form.
(a) AB + B(CD + EF) = AB + BCD + BEF
(b) (A + B) (B + C + D) = AB + AC + AD + BB + BC + BD
(c)
1.4 PRODUCT-OF-SUMS METHODS

The logical product of those fundamental sums that produce output in the
truth table. Thecorresponding logic circuit is an OR-AND circuit or the equivalent NOR-
NOR circuit.
TABLE 1.11: POS table
A B C Y
0 0 0
0 0 1 1
0 1 0 1
0 1 1
1 0 0 1
1 0 1 1
1 1 0
1 1 1 1
Y = 0, when A = 0, B = 1 and C = 1 . So this particular combination makes the

output of an OR gate equal to 0, when and Thus is on sum
term. Similarly other two sum terms are A + B + C and . Thus the standard
product of sum form is,
Figure 1.19 Shows the OR-AND logic circuit and Figure 1.20 shows the NOR-NOR
logic circuit for this expression.
Fig. 1.19: OR-AND circuit

Fig. 1.20: NOR-NOR circuit

Theorems:
Two theorems that are an important part of Boolean algebra were proposed by
DeMorgan.
The first theorem states that the complement of a product is equal to the sum of
the complements.
=
he second theorem states that the complement of a sum is equal to the product of the
complements.
(A+ =
Consensus Theorem:
In simplification of Boolean expression, an expression of the form
BC, the term BC is redundant and can be eliminated to form the equivalent expression
AB+
is stated as,
AB+ BC = AB+
The dual form of consensus theorem is stated as,
(A+B) (B+C) = (A+B)
BOOLEAN FUNCTIONS:
Minimization of Boolean Expressions:
The Boolean expressions can be simplified by applying properties, laws and
theorems of Boolean algebra.
Simplify the following Boolean functions to a minimum number of literals:
1. x
= xy [ ]
= 0 + xy [ x+ 0 = x ]
= xy.
2.
= x + xy + [ x+ xy= x]
=
= x+ y (1) [ x+ = 1]
= x+ y.
3. (x+ y)
= x.x+ xy+
= xy+ 0 [ x. x= 0]; [ y.
= x (1+
= x (1) [ 1+y= 1 ]
= x.
4. xy + yz.
+ yz( x+ [ 1]
= xy + + xyz +
Re-arranging,
= xy + xyz +
= xy (1+ z) + (1+y) [1+y= 1]
= xy+
5. xy+ yz+
= xy+ z ( y+
= xy+ z ( 1 ) [ = 1]
= xy+ z.
6. (x+ y) z) (y+ z)
= (x+ y) z) [ dual form of consensus theorem,
(A+ B) (B+ C) = (A+ B) C) ]
7.
=y( x) + [ x (y+ z) = xy+ xz ]
=y(1)+ = 1]
= y+ [ x+ ]
=
8. x+
= x (1+
= x (1) + [ 1+ x = 1 ]
= x+ [ x+ ]
= x+ y.
9. AB + (AC)' + (AB + C)
= AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + 0+ AB'CC [B.B' = 0]
= AB + (AC)' + AB'C [C.C = 1]
= AB + A' + C' +AB'C [(AC)' = A' + C']
= AB + C' + AB' + = +
= A' + B+ + AB = + B]
Re- arranging,
= A' B+ C' + AB = + B]
= A' B+ C'
= A' +1+ [ A+ 1= 1]
=1
10. (x+ y)
= yx+ y.y
= xy+ y [ x. x= x]
=y( x+ 1)
= y( 1 ) [ 1+ x = 1 ]
= y.
11. xy+ xyz+ xy (w+ z)
= xy ( 1+ z+ w+ z)
= xy ( 1 ) [ 1+ x = 1 ]
= xy.
12. xy+ xyz+
= xy ( 1+
= xy ( 1 ) + [ 1+ x = 1 ]
= xy+
= y ( x+ ) [ x+ = x+ y]
= y ( x+ z ).
13. xyz+
= xy (z+ +
= xy+ [ 1]
= x(y+ [ x+ = x+ y]
= x(y+ z)
14.
= y)+ y)
= [ x+
= x)
= [ x+
15.
= 1) +
= [ 1+ x = 1 ]
= (y+
= [ x+
=x
=x [
16. wxz
= y)+ wxz
= (1)+ wxz [ 1]
= wxz
= w)
= xz. [ x+
17.
= +
= (1) (1)+ [ 1]
=
= +
= + [ x+
= +
= [
18. + +
= +
= + + = x]
= + +
=0+ + + [x. 0]
Re-arranging,
= + +
= (y+
= (y+ [ x+
= (y+x) [ x+ = x+ y]
19. xy+ x (y+ z) + y (y+ z)
= xy+ xy+ xz+ yy+ yz
= xy+ xz+ y+ yz [x+ x= x]; [x. x= x]
= xy+ xz+ y [x+ xy= x]
= y+ xz [x+ xy= x]
20. [ (z+ wy) + z
=[ z
=[ z [x. 0]
= z+
= [x. x= x]
=
= (1) [ x+
21. xyz
= yz
= yz (1) + (x+ + [ x+
= yz+ (1) + [ x+
= yz+
= yz+ xz)
= x) [ y]
=
22.
=[
=[ [x+ x= x]
= [ y]
= [ x+
=[ [ 1+ x = 1 ]
= 0.
23. [
=
=
=
= [x+ x= x]
=
= y]
= [x+ xy = x]
=
= [x+ xy = x]
= [x+ xy = x]
24. xy+
= xy+
= xy+ (x+ z) = x]
= xy+
= xy+ [x. x= x]
= xy+ [1+ z]
= xy+ [1] [ 1+ x = 1 ]
= xy+
= x( y+
= x [1] [ 1]
= x.
25. [(
= [ x( (y+
=[ (y+ y]
= [ x(
=[ xy+ [x. x= x]
=[( [x+ xy = x]
=[ (xz
=[
=[ = x]
=[ [ (x+ y) (x+ z)= x+ yz]
=[
= [ 1+ [ 1]
= [ 1+ x = 1 ]
= 0.
26. [
=[
= [ xy. xy. z+
= [ 0+ xyz+ 0]
= [ xyz+
= (
=(
=( y+ z). = x]
27. (x+ y) z)
= (x+ y) z)
= (x+ z) (y. (xz x]
= (x+ y) z)
=(
= ( 0+ xz+ yz)
= (xz+ yz)
= xz. yz.
= 0 [x. [x. x= x]
= z)
(1) [ 1+ x = 1 ]
28. Y= (1, 3, 5, 7)
= xyz
= + xz(
= (1)+ xz (1) [ x+
xz
= z( x)
= z (1) [ 1]
= z.
1.5 KARNAUGH MAPS

A Karnaugh map is a graphical representation of a truth table that can be used to
reduce a logic circuit to its simpliest terms. The size of the Karnaugh map depends on the
amount of inputs that are listed in the truth table. An example of a three variable Karnaugh
Map is shown below:
The terms withing a Karnaugh Map are obtained by combining the row and
column boolean expression that are shown at the top and left margins of the Karnaugh
Map. Each combined term within the Karnaugh Map corresponds to a single line of inputs
in a truth table. Terms that have a line over them corresponds to a low or zero input. Terms
without any marking corresponds to a high or 1input.
1.5.1 Constructing a Karnaugh Map

(1) Two variable maps:
(2) Three variable maps:

(3) Four variable maps
Pairs, Quads and Octets

Pairs
Pair eliminates are variable and its complements.
Pair of 1's horizontally and vertially adjacent.
Quads: A quad is a group of four that are horizontally or vertially adjacent

Octet: An octet is a group of eight

An octet eliminates three variables and their complements.
1.5.2 Karnaugh Map Simplifications

Encircle octets first, the quads second and the pairs last.
Overlapping Groups: It is possible to use the same 1 more than once.

It is valid to encircle the as shown below. But the isolated 1 results in a more
complicated equation.
Rolling the map
Visualize the picking up the karnaugh map and rolling it so that the left side
touches the rightside. By doing so, the two pairs can be realised as Quad.
The quad has the equation,
Proof: To show whether the rolling is valid or not.
Rolling and Overlapping: It is possible to overlap and roll the map to get large groups.
Eliminating Redundant Groups

Redundant group is a group whose are already used by other groups. The
redundant group is eliminated as shown in below figure.
1.5.3 Care Condition

In some digital system, certain output conditions never occur during normal
operation. Thereforecorresponding output never appears. Since the output never appears
X truth table.
Solution:
1. Given the truth table, draw a Karnaugh map with other cares.
2. Enclose the actual on the Karnaugh map in the largest groups you can find by
treating the cares
3. After the actual have been included in groups, disregard the remaining
cares byvisualizing them
Example:
Here cares are of no help. The best way is, encircle the isolated 1, while
treating caresas
1.6 MINIMIZATION OF KARNAUGH MAPS

The rules for reducing Karnaugh Maps are as follows:
All of the are called minterms.
can be reduced in groups of 2, 4 and 8.
Minterms that are next to each other horizontally or vertically, can be grouped
together.
Minterms that have been grouped in a Karnaugh Map, can be reduced to the
boolean terms that are common with all the terms in the group.
Minterms that cannot be grouped together, cannot be reduced.
Use a minterm for grouping more than once.
All must be accounted for.
Example 1.12:
Determine the Karnaugh Map and reduced boolean equation for the truth table
shown in Table 1.12.
TABLE 1.12: Truth Table
Without reduction the Boolean Equation for the above truth table is:
Each minterm corresponds to an instance in the truth table when the output is high.
The KarnaughMap for the above truth table, with the allowed groupings are shown below:
The map shows two groupings that cover each minterm. Each of these groupings
will reduce toone term.
The two terms that are grouped together reduces to . This is because
and arecommon to both terms.
The four terms and and and that are grouped together
reduces to C. This is because is the only input common to all four terms.
Therefore the boolean equation
1.6.1 Simplification of Sum of Product Expression

The procedure to simplify the SOP expression using K-map as follows:
Plot the K-map and enter the in those cells corresponding to the combinations
for which function value is 1.
Check the K-map for adjacent 1's and encircle those which are not adjacent to
any other 1's.
Check for those 1's which are adjacent to only one other 1 and encircle such pairs.
A group must contain either 1,2,4,8 or 16 ones (1's), which are all powers of two.
Combine any pairs necessary to include any 1's that have not yet been grouped.
Form the simplified expression by summing product terms of all the groups.
The minterms for variable and standard product terms and represented by 2
variable K map, 3 variable K-map and 4 variable K-map are shown in Figure 1.22.
Fig.1.22: Representation of functions in the Map

Example 1.13:
Simplify the following SOP expression on a Karnaugh Map.
Solution:
The expression is evaluated as follows:
Example 1.14:
Simplify the SOP by using K-map
Y = m(0,1,3,7)
Example 1.15:
Simplify the expression
Solution:
Example 1.16:
Simplify the Boolean expression using K map
Solution:
The given expression is not a standard SOP form. First convert this non-standard
SOP to standard SOP and then simplify the expression using K-map.
Example 1.17:
Use a K map to minimize the following SOP expression:
Solution:
Example 1.18:
F= m(0,2,4,5,6,7,8,10,11,12,14,15)
Solution:
Example 1.19:
Simplify the expression using K-map
Example 1.20:
Simplify the following SOP expression on a K-map
Solution:
The SOP expression is obviously not in standard form because each product term
does nothave 4 variables. The first and second term are both missing 2 variables, the third
term is missing one variable and the rest of the terms are standard. First expand the terms
by including all combinations of the missing variables numerically as follows:
Repeated terms are cancelled under the rule A + A = A, therefore,
(0, 1, 8, 9 10, 11, 12, 13)
Example 1.21:
Simplify using K-map
F(A, B, C, D) m (7,8,9) + d (10,11,12,13,14,15)
Solution:
Note: Without cares,

With cares, F = A + BCD
Therefore, it is clear that, the advantage of using care terms is to get the
simplest expression.
Example 1.22:
Simplify using K-map
F(A, B, C, D) m (1,3,7,11,15) + d (0,2,5)
Solution:
(or)
Example 1.23:
Using the K-Map method, simplify the following Boolean function
F m (0,2,3,6,7) + d (8, 10, 11, 15) (April 2005)
Solution:
Example 1.24:
Simplify the following Boolean function F using Karnaugh map method.
F C, D 1, 4,5,6,12,14,15
Example 1.25:
Example 1.26:
Example 1.27:
Example 1.28:
Implement the switching function. (May 2012)
Example 1.29:
Example 1.30:
F(w, x, y, z) = m(0, 7, 8, 9, 10, 12) + d(2, 5, 13) (May 2013)
1.6.2 Simplification of Product of Sum expression

To simplify a POS expression, for each maxterm in the expression in, a has to
be entered in the
1 cells to get he minterm (SOP) expression. The simplified term corresponding to each
group can be obtained by the OR operation of the variables that are same for all cells of
that group. Here, a variable corresponding to to be represented in an
uncomplemented form.
Example 1.31:
Simplify, the POS expression using K map method.
F (0, 1, 4, 5, 6, 8, 9, 12, 13, 14)
Solution:
Example 1.32:
Simplify the POS expression
F = (0,6,7,8,12,13,14,15)
Example 1.33:
F(A, B, C, D) = M (4,5,6,7,8,12) . d(1,2,3,9,11,14)
Solution:
Example 1.34:
Simplify the POS expression,
F = M (0,3,4,7,8,10,12,14).d(2,6)
Example 1.35:
Determine the minterm sum of product form of the switching function.
F= (0,1,4,5,6,11,14,15,16,17,20,22,30,32,33,36,37,48,49,52,53,59,63)
(Dec. 2010)
Solution:
Fill up the K-map with the variable given
Four in each box form a group of 16 bits and their reduced function is .
Therefore
F= (0,1,4,5,6,11,14,15,16,17,20,22,30,32,33,36,37,48,49,52,53,59,63)
Example 1.36:
Minimize the following expression using Karnaugh map.
Example 1.37:
Simplify the following Boolean function F using Karnaugh map method.
Example 1.38:
Simplify F(A, B, C, D) = (0, 1, 2, 5, 8, 9, 10) in sum of products and product
ofsums using K-map. (Dec 2012)
Solution:
SOP:
POS:
Five Variable Map

The five-variable map consists of 2 four-variable maps with A, B, C, D and E.
Variable A distinguishes between the two maps, as indicated on the top of the diagram as
A = 0 and A = 1. Minterms 0 15 belong with A = 0 and minterms 16 31 with A = 1.
Example 1.39:
Simplify the Boolean expression:
F ( A, B, C, D, E) = (0, 2, 3, 4, 5, 6, 7, 11, 15, 16, 18, 19, 23, 27, 31)
In DE and terms, A is not included because the adjacent squares belong to

both A = 0 and A = 1.
In term, it is necessary to include because all the squares are associated
with A = 0.
Example 1.40:
Simplify the Boolean function
F ( A, B, C, D, E) = ( 0, 1, 4, 5, 16, 17, 21, 25, 29)
Example 1.41:
Find the minimal sum of product form for the following switching function:
Example 1.42:
Find the minimal sum of product expression for the following switching function:
1.7 IMPLEMENTAING COMBINATIONAL LOGIC

Any combinational circuit can be designed by following the design procedure
given below:
From the given word description of the problem, identify the number of input
variables and required output.
The variables input and output variables are assigned letter symbols.
Draw a truth table such that it completely describes the operation of the circuit
for differentcombinations of inputs.
Obtain the Boolean expression for each output using either algebraic or K-map
method.
Obtain the logic diagram.
In practical design method, some constraints are considered:
Minimum number of gates.
Minimum number of inputs to a gate.
Minimum propagation time of the signal through the circuit.
Minimum number of interconnections.
Limitations of the driving capabilities of each gate.
Example 1.43:
Design a combination logic circuit with three input variables that will produce a
logic 1 output when more than one input variables are logic 1.
Solution:
Number of Input variables = 3
Number of Output variables = 1
Let assign the letter symbols A, B and C Y
one output variable. The relationship between input variables and output variable is
tabulated in truth table as given in Table 1.13.
Table 1.13: Truth Table
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Using K map method, find the Boolean expression for Y.
Y = AB + AC + BC
Draw the logic diagram for Y = AB + AC + BC.
Fig. 1.23 : Logic diagram

Example 1.44:
Design a combinational logic circuit that has four inputs and one output. The
outputis high if both inputs A and B are high or both inputs C and D are high.
Solution:
The relationship between input variables (A, B, C, D) and output variable (Y) is
tabulated as shown in Table 1.14.
Table 1.14: Truth Table

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Using K map obtain the Boolean expression for output variable Y
Y=AB+CD
Draw the logic diagram for Y = AB + CD.
Fig. 1.24 : Logic diagram
1.8 ARITHMETIC CIRCUITS BASIC BUILDING

BLOCKS:
In this section, we will discuss those combinational logic building blocks that
can be used to perform addition and subtraction operations on binary numbers.
Addition and subtraction are the two most commonly used arithmetic operations, as
the other two, namely multiplication and division, are respectively the processes of
repeated addition and repeated subtraction.
The basic building blocks that form the basis of all hardware used to perform
the arithmetic operations on binary numbers are half-adder, full adder, half-subtractor,
full- subtractor.
Half-Adder:
A half-adder is a combinational circuit that can be used to add two binary bits.
It has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.
Fig. 1.25 Block schematic of half-adder

The truth table of a half-adder, showing all possible input combinations and
the corresponding outputs are shown below.
Table 1.15 Truth table of half-adder

Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
K-map simplification for carry and sum:
The first one representing the SUM output is that of an EX-OR gate, the second
one representing the CARRY output is that of an AND gate.
The logic diagram of the half adder is,
Fig. 1.26 Logic Implementation of Half-adder

Full-Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three
input bits. It consists of 3 inputs and 2 outputs.
Two of the input variables, represent the significant bits to be added. The third
input represents the carry from previous lower significant position. The block diagram
of full adder is given by,
Fig. 1.27 Block schematic of full-adder

The full adder circuit overcomes the limitation of the half-adder, which can
be used to add two bits only. As there are three input variables, eight different input
combinations are possible. The truth table is shown below,
Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
To derive the simplified Boolean expression from the truth table, the Karnaugh
map method is adopted as,
The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum, S = in + in + in + ABCin
Carry, Cout = AB+ ACin + BCin .
The logic diagram for the above functions is shown as,
Fig.1.28 Implementation of full-adder in Sum of Products

The logic diagram of the full adder can also be implemented with two half-
adders and one OR gate. The S output from the second half adder is the exclusive-
OR of Cin and the output of the first half-adder, giving
Sum = Cin (A B) [x y =
= Cin
= in + Cin
= in + Cin
= in + in + ABCin + in .
and the carry output is,
Carry, Cout = AB+ Cin
= AB+ in+ in
= AB (Cin+1) + in+ in [Cin+1= 1]
= ABCin+ AB+ in+ in
= AB+ ACin in
= AB+ ACin+ in
= AB (Cin+1) + ACin+ in [Cin+1= 1]
= ABCin+ AB+ ACin+ in
= AB+ ACin+ BCin (A
= AB+ ACin+ BCin.
Fig. 1.29 Implementation of full adder with two half-adders and an OR gate
Half -Subtractor:
A half-subtractor is a combinational circuit that can be used to subtract one
binary digit from another to produce a DIFFERENCE output and a BORROW output.
The BORROW output here specifies whether a has been borrowed to perform the
subtraction.
Fig. 1.30 Block schematic of half-subtractor

The truth table of half-subtractor, showing all possible input combinations and
the corresponding outputs are shown below.
Input Output
A B Difference (D) Borrow (Bout)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
K-map simplification for half subtractor:
The first one representing the DIFFERENCE (D)output is that of an exclusive-

OR gate, the expression for the BORROW output (Bout) is that of an AND gate with
input A complemented before it is fed to the gate.
The logic diagram of the half adder is,
Fig. 1.31 Logic Implementation of Half-Subtractor

Comparing a half-subtractor with a half-adder, we find that the expressions
for the SUM and DIFFERENCE outputs are just the same. The expression for
BORROW in the case of the half-subtractor is also similar to what we have for
CARRY in the case of the half-adder. If the input A, ie., the minuend is
complemented, an AND gate can be used to implement the BORROW output.
Full Subtractor:
A full subtractor performs subtraction operation on two bits, a minuend and a
subtrahend, and also takes into consideration whether a has already been borrowed
by the previous adjacent lower minuend bit or not.
As a result, there are three bits to be handled at the input of a full subtractor,
namely the two bits to be subtracted and a borrow bit designated as B in. There are
two outputs, namely the DIFFERENCE output D and the BORROW output Bo.
The BORROW output bit tells whether the minuend bit needs to borrow a from
the nextpossible higher minuend bit.
The truth table for full-subtractor is,

Inputs Outputs
A B Bin Difference(D) Borrow(Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-map simplification for full-subtractor:
The Boolean expressions for the DIFFERENCE and BORROW outputs are
given by the equations,
Difference, D = in+ in + in + ABB in Borrow,
Bout = in + BBin .
The logic diagram for the above functions is shown as,
Fig. 1.32 Implementation of full-adder in Sum of Products

The logic diagram of the full-subtractor can also be implemented with two
half- subtractors and one OR gate. The difference, D output from the second half
subtractor is the exclusive-OR of Bin and the output of the first half-subtractor, giving
Difference,
D = Bin (A B) [x y=
= Bin
= in + Bin
= in + Bin
in + in + ABBin + in .
and the borrow output is,
Borrow,
Bout = Bin
= Bin
ABBin+ in
= (Bin+1) + ABBin+ in [Cin+1= 1]
= in+ ABBin+ in
= BBin + in 1]
= BBin+ in
= (Bin+1) + BBin+ in [Cin+1= 1]

= in+ BBin+ in
= BBin+ in (B
= BBin+ in.
Therefore,
we can implement full-subtractor using two half-subtractors and OR gate as,
Fig. 1.33 Implementation of full-subtractor with two half-subtractors and an OR

gate
Binary Adder (Parallel Adder):
The 4-bit binary adder using full adder circuits is capable of adding two 4-bit
numbers resulting in a 4-bit sum and a carry output as shown in figure below.
Fig. 1.34 4-bit binary parallel Adder

Since all the bits of augend and addend are fed into the adder circuits
simultaneously and the additions in each position are taking place at the same time,
this circuit is known as parallel adder.
Let the 4-bit words to be added be represented by, A3A2A1A0= 1111 and
B3B2B1B0= 0011.
The bits are added with full adders, starting from the least significant position,
to form the sum it and carry bit. The input carry C0 in the least significant position
must be 0. The carry output of the lower order stage is connected to the carry input of the
next higher order stage. Hence this type of adder is called ripple-carry adder.
In the least significant stage, A0, B0 and C0 (which is 0) are added resulting
in sum S0 and carry C1. This carry C1 becomes the carry input to the second stage.
Similarly in the second stage, A1, B 1 and C1 are added resulting in sum S1 and
carry C2, in the third stage, A2, B2 and C2 are added resulting in sum S2 and carry
C3, in the third stage, A3, B3 and C3 are added resulting in sum S3 and C4, which
is the output carry. Thus the circuit results in a sum (S3S2S1S0) and a carry output
(Cout).
Binary Subtractor (Parallel Subtractor):
The subtraction of unsigned binary numbers can be done most conveniently
by means of complements. The subtraction A-
complement of B and adding it to A. The complement can be obtained by taking
the complement and adding 1 to the least significant pair of bits. The
complement can be implemented with inverters and a 1 can be added to the sum
through the input carry.
Fig.1.35 4-bit Parallel Subtractor

The circuit for subtracting A-B consists of an adder with inverters placed
between each data input B and the corresponding input of the full adder. The input
carry C0 must be equal to 1 when performing subtraction. The operation thus
the complement of B.
Parallel Adder/ Subtractor:
The addition and subtraction operation can be combined into one circuit with
one common binary adder. This is done by including an exclusive-OR gate with each
full adder. A 4-bit adder Subtractor circuit is shown below.
Fig.1.36 4-Bit Adder Subtractor

The mode input M controls the operation. When M= 0, the circuit is an adder
and when M=1, the circuit becomes a Subtractor. Each exclusive-OR gate receives
input M and one of the inputs of B. When M=0, we have B 0= B. The full adders
receive the value of B, the input carry is 0, and the circuit performs A plus B. When
M=1, we have 0=1. The B inputs are all complemented and a 1 is
added through the
complement of B. The exclusive-OR with output V is for detecting an overflow.
Decimal Adder (BCD Adder):
The digital system handles the decimal number in the form of binary coded
decimal numbers (BCD). A BCD adder is a circuit that adds two BCD bits and
produces a sum digit also in BCD.
Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output
sum cannot be greater than 9+ 9+1 = 19; the 1 is the sum being an input carry.
The adder will form the sum in binary and produce a result that ranges from 0 through
19.
These binary numbers are labeled by symbols K, Z8, Z4, Z2, Z1, K is the carry.
The columns under the binary sum list the binary values that appear in the outputs of
the 4-bit binary adder. The output sum of the two decimal digits must be represented
in BCD.
Binary Sum BCD Sum
K Z8 Z4 Z2 Z1 C S8 S4 S2 S1 Decimal
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 1 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19
In examining the contents of the table, it is apparent that when the binary sum is
equal to or less than 1001, the corresponding BCD number is identical, and therefore no
conversion is needed. When the binary sum is greater than 9 (1001), we obtain a non-
valid BCD representation. The addition of binary 6 (0110) to the binary sum converts
it to the correct BCD representation and also produces an output carry as required.
The logic circuit to detect sum greater than 9 can be determined by
simplifying the boolean expression of the given truth table.
To implement BCD adder we require:

4-bit binary adder for initial addition
Logic circuit to detect sum greater than 9 and
One more 4-bit adder to add 01102 in the sum if the sum is greater than 9 or
carry is 1.
The two decimal digits, together with the input carry, are first added in the top4- bit
binary adder to provide the binary sum. When the output carry is equal to zero, nothing
is added to the binary sum. When it is equal to one, binary 0110 is added to the binary
sum through the bottom 4-bit adder. The output carry generated from the bottom adder
can be ignored, since it supplies information already available at the output carry terminal.
The output carry from one stage must be connected to the input carry of the next
higher-order stage.
Fig. 1.37 Block diagram of BCD adder

1.9 MAGNITUDE COMPARATOR:
A magnitude comparator is a combinational circuit that compares two given
numbers (A and B) and determines whether one is equal to, less than or greater than
the other. The output is in the form of three binary variables representing the
conditions A = B, A>B and A<B, if A and B are the two numbers being compared.
Fig. 1.38 Block diagram of magnitude comparator

For comparison of two n-bit numbers, the classical method to achieve the
Boolean expressions requires a truth table of 22n entries and becomes too lengthy and
cumbersome.
2-bit Magnitude Comparator:
The truth table of 2-bit comparator is given in table below
Table 1.17 Truth table
Inputs Outputs
A3 A2 A1 A0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
K-map Simplification:
Logic Diagram:
Fig. 1.39 2-bit Magnitude Comparator

4-bit Magnitude Comparator:
Let us consider the two binary numbers A and B with four digits each. Write
the coefficient of the numbers in descending order as,
A = A3A2A1A0 B = B3 B2 B1 B0,
Each subscripted letter represents one of the digits in the number. It is
observed from the bit contents of two numbers that A = B when A 3 = B3, A2 = B2,
A1 = B1 and A0 = B0. When the numbers are binary they possess the value of either
1 or 0, the equality relation of each pair can be expressed logically by the equivalence
function as
Xi = AiBi + Ai i for i = 1, 2, 3, 4.
Or, Xi = (A or, Xi A B
Or, Xi = (AiBi + Ai i
where,
Xi =1 only if the pair of bits in position i are equal (ie., if both are 1 or both
are 0).
To satisfy the equality condition of two numbers A and B, it is necessary that
all Xi must be equal to logic 1. This indicates the AND operation of all Xi variables. In
other words, we can write the Boolean expression for two equal 4-bit numbers.
(A = B) = X3X2X1 X0.
The binary variable (A=B) is equal to 1 only if all pairs of digits of the two
numbers are equal.
To determine if A is greater than or less than B, we inspect the relative
magnitudes of pairs of significant bits starting from the most significant bit. If the
two digits of the most significant position are equal, the next significant pair of digits
is compared. The comparison process is continued until a pair of unequal digits is
found. It may be concluded that A>B, if the corresponding digit of A is 1 and B is 0.
If the corresponding digit of A is 0 and B is 1, we conclude that A<B. Therefore, we
can derive the logical expression of such sequential comparison by the following two
Boolean functions,
(A>B) = A3B3 3A2B2 3X2A1B1 3X2X1A0B0 (A<B)
= A3 3 +X3A2 2 +X3X2A1 1 +X3X2X1A0 0
The symbols (A>B) and (A<B) are binary output variables that are equal to 1
when A>B or A<B, respectively.
The gate implementation of the three output variables just derived is simpler
than it seems because it involves a certain amount of repetition. The unequal outputs
can use the same gates that are needed to generate the equal output. The logic diagram
of the 4-bit magnitude comparator is shown below,
The four x outputs are generated with exclusive-NOR circuits and applied to
anAND gate to give the binary output variable (A=B). The other two outputs use the
x variables to generate the Boolean functions listed above. This is a multilevel

implementation and has a regular pattern.
Fig.1.40 4-bit Magnitude Comparator

1.10 DECODERS:
A decoder is a combinational circuit that converts binary information from
input lines to a maximum of 2n unique output lines. The general structure of
decodercircuit is
The encoded information is presented as inputs producing 2n possible
outputs. The 2n output values are from 0 through 2n-1. A decoder is provided with
enable inputs to activate decoded output based on data inputs. When any one enable
input is unasserted, all outputs of decoder are disabled.
Fig.1.41 General structure of decoder

Binary Decoder (2 to 4 decoder):
binary input and a one activated output out of 2n
outputs. A binary decoder is used when it is necessary to activate exactly one of 2 n
outputs based on an n-bit input value.
Fig.1.42 2-to-4 Line decoder

Here the 2 inputs are decoded into 4 outputs, each output representing one of
theminterms of the two input variables.
Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
As shown in the truth table, if enable input is 1 (EN= 1) only one of the
outputs (Y0 Y3), is active for a given input.
The output Y0 is active, ie.,
Y0= 1 when inputs A= B= 0,
Y1 is active when inputs, A= 0 and B= 1,
Y2 is active, when input A= 1 and B= 0,
Y3 is active, when inputs A= B= 1.
3 to-8 Line Decoder:
A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7).
Based on the 3 inputs one of the eight outputs is selected.
The three inputs are decoded into eight outputs, each output representing one
of the minterms of the 3-input variables. This decoder is used for binary-to-octal
conversion. The input variables may represent a binary number and the outputs will
represent the eight digits in the octal number system. The output variables are mutually
exclusive because only one output can be equal to 1 at any one time. The output line
whose value is equal to 1 represents the minterm equivalent of the binary number
presently available in the input lines.
Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Fig. 1.43 3-to-8 line decoder

BCD to 7-Segment Display Decoder:
A seven-segment display is normally used for displaying any one of the
decimaldigits, 0 through 9. A BCD-to-seven segment decoder accepts a decimal digit
in BCD and generates the corresponding seven-segment code.
Each segment is made up of a material that emits light when current is passed
through it. The segments activated during each digit display are tabulated as
Table 1.18 Truth table

Logic Diagram:
Fig.1.44 BCD to 7-segment display decoder

Applications of decoders:
Decoders are used in counter system.
They are used in analog to digital converter.
Decoder outputs can be used to drive a display system.
1.11 ENCODERS:
An encoder is a digital circuit that performs the inverse operation of a decoder.
Hence, the opposite of the decoding process is called encoding. An encoder is a
combinational circuit that converts binary information from 2n input lines to a
maximum of unique output lines.
The general structure of encoder circuit is
Fig.1.45 General structure of Encoder

It has 2n
lines. It encodes one of the active inputs to a coded
encoder, the number of outputs is less than the number of inputs.
Octal-to-Binary Encoder:
It has eight inputs (one for each of the octal digits) and the three outputs that
generate the corresponding binary number. It is assumed that only one input has a
value of 1 at any given time.
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table. Output z is equal to 1, when the input octal digit is 1 or
3 or 5 or 7. Output y is 1 for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4,
5, 6 or 7. These conditions can be expressed by the following output Boolean functions:
z = D1+ D3+ D5+ D7
y = D2+ D3+ D6+ D7 x= D4+ D5+ D6+ D7
The encoder can be implemented with three OR gates. The encoder defined in
the below table, has the limitation that only one input can be active at any given time.
If two inputs are active simultaneously, the output produces an undefined combination.
For eg., if D3 and D6 are 1 simultaneously, the output of the encoder may be
111. This does not represent either D6 or D3. To resolve this problem, encoder
circuits must establish an input priority to ensure that only one input is encoded. If
we establish a higher priority for inputs with higher subscript numbers and if D3 and
D6 are 1 at the same time, the output will be 110 because D6 has higher priority than
D3.
Fig.1.46 Octal-to-Binary Encoder

Another problem in the octal-to- is

generated when all the inputs are 0; this output is same as when D0 is equal to 1. The
discrepancy can be resolved by providing one more output to indicate that atleast one
input is equal to 1.
Priority Encoder:
A priority encoder is an encoder circuit that includes the priority function. In
priority encoder, if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.
In addition to the two outputs x and y, the circuit has a third output, V (valid bit
indicator). It is set to 1 when one or more inputs are equal to 1. If all inputs are 0,
there is no valid input and V is equal to 0.
The higher the subscript number, higher the priority of the input. Input D3, has
the highest priority. So, regardless of the values of the other inputs, when D3 is 1, the
output for xy is 11.
D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0. The
output for D1 is generated only if higher priority inputs are 0, and so on down the
priority levels.
Truth table:
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
is replaced first by 0 and then by 1, we obtain all 16 possible input combinations. For
example, the third row in the table with X100 represents minterms 0100 and 1100.
The care condition is replaced by 0 and 1 as shown in the table below.
Modified Truth table:

Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
0 1 0 0
0 1 1
1 1 0 0
0 0 1 0
0 1 1 0
1 0 1 0 1 0 1
1 1 1 0
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1 1 1 1
1 0 1 1
1 1 0 1
1 1 1 1
The priority encoder is implemented according to the above Boolean functions.
Fig.1.47 Input Priority Encoder
1.12 MULTIPLEXERS
Multiplex means into A multiplexer is a combinational circuit with
many inputs but only one output. By applying control signals, we can steer any input to
n m signals and 1 output signal. Multiplexer is
called as data selector or because the output bit depends on the input data bit that is
selected. The block diagram of multiplexer is shown in Figure 1.48.
Fig 1.48
1.12.1 4-to-1 Line Multiplexer
A 4-to-1 line multiplexer has four (n) input lines, two (m) select lines and one
output line. The selection (control) lines decide the number of input lines. If the number
n 2m, then m select lines are required to select one of the n
input lines.
The logic symbol of a 4-to-1 multiplexer is shown in Figure 1.49. If has 4 input
lines (I0 to I3), two select lines (S0, S1) and a single output line. The function table of 4-
to-1 multiplexer is shown in Table 1.19.

TABLE 1.19: Function Table
Select Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
1. Y = I0 iff S1 = 0 , S0 = 0
2. Y = I1 iff S1 = 0, S0 = 1
3. Y = I2 iff S1 = 1 , S0 = 0
4. Y = I3 iff S1 = S0 = 1
The final expression for the data output,
Using this expression, the 4-to-1 multiplexer can be implemented using gates
Fig. 1.50 : Logic Diagram of 4-to-1 Multiplexer

1.12.2 16-to-1 Multiplexer
The 16-to-1 multiplexer has 16 data input lines , a single output line
(Y) and 4 select15lines (A, B, C, D) to select one of the 16 input lines. The truth table for
a 16-to-1 multiplexer is shownin Table 1.20.
For example, when ABCD = 0000, the upper AND gate is enabled while all other
AND gates are disabled. Therefore data bit D0 is transmitted to the output.
Y = D0
If D0 = 0, Y = 0
D0 = 1, Y = 1 i.e., Y depends only on the value of D0
When ABCD = 1111, Y = D15.
Thus the control bits (A, B, C, D) determines which of the input data bits is transmitted
to the output.
Figure 1.51 shows the logic diagram of 16-to-1 multiplexer.
TABLE 1.20: Truth Table of 16-to-1 MUX
Enable Select Inputs Output
E S3 S2 S1 S0 Y
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 X X X X 1
Fig. 1.51 : Logic diagram of 16-to-1 multiplexer

We can implement a 16-to-1 multiplexer using two 8-to-1 multiplexer as shown
in Figure 1.52.
To select one of the 16 inputs, 4 select lines (S3 S2 S1 S0) are required. Among
the 4 select lines(S2 S1 S0) are connected with 3 select inputs of both 4 to 1 multiplexers.
S3 is connected directly to E (Enable) input of MUX1 and it is connected through an NOT
gate to E input of MUX2. Therefore, when S3 = 0, MUX1 is selected and the inputs (D0
to D7) are multiplexed to the output and MUX2 is disabled. When S3 = 1, the MUX 1 is
disabled while MUX 2 is enabled and the inputs (D8 to D15) aremultiplexed to the output.
Fig. 1.52 : 16-to-1 Multiplexer using IC 74151
1.13 DEMULTIPLEXERS
Demultiplex means
circuit with one input and many outputs. By applying control signal, we can steer the input
signal to one of the output lines. Figure 1.53 shows the block diagram of demultiplexer. It
has 1 input signal, control signals and output signals.
Fig. 1.53 : Block diagram of demultiplexer

The select inputs (Control Signals) determine to which output the data input will
be connected. As the serial data is changed to parallel data, i.e., the input caused to appear
on one of n output lines, the demultiplexer is called data distributor or serial-to-
parallel converter.
1.13.1 1-to-4 Demultiplexer

A 1-to-4 demultiplexer has a single input (D), 4 outputs (Y0Y1Y2Y3) and two select
lines (S1S0).
The truth table of the 1 to 4 demultiplexer is shown in Table 1.21.
When S1S0 = 00, the data input is connected to output Y0.
When S1S0 = 01, the data input is connected to output Y1
When S1S0 = 10 , the data input is connected to output Y2
When S1S0 = 11, the data input is connected to output Y3

Y3 = S1S0D = D
Using these expressions, a 1-to-4 demultiplexer is implemented using AND gates
TABLE 1.21: Truth Table
Data Input Select Inputs Outputs
D S S0 Y3 Y2 Y1 Y0
D 0 0 0 0 0 D
D 0 1 0 0 D 0
D 1 0 0 D 0 0
D 1 1 D 0 0 0
(a) Logic Symbol
(b) Logic Diagram

Fig. 1.54: 1 to 4 multiplexer

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1

be described by m Boolean functions and each output can be expressed in terms of n

Figure 1.1 Block diagram of a combinational logic circuit

most basic building block of combinational logic.

NOT gate (Invertion),

AND gate performs logical

OR gate performs logical

It is a universal gate. When

It is a universal gate. LOW

EX- OR The output is HIGH only when

The output is HIGH only when

1.2 REPRESENTATION OF LOGIC FUNCTIONS

1.2.1 Truth table

1.2.2 Logic gates

Fig. 1.2 Logic Symbol

The truth table for the NOT gate appears as below:

The AND gate

Fig. 1.3: Logic Symbol

Fig. 1.4 : Logic Symbol

The output from the OR gate is written as A + B.

Other Logic Gates

Fig. 1.5: Logic Symbol

The NOR gate

Fig. 1.6: NOR-Logic Symbol

The Exclusive-OR (XOR) gate

Fig. 1.7: XOR-Logic Symbol

Table 1.6 Truth Table

The Exclusive-NOR (XNOR) gate

Fig. 1.8: Logic Symbol

The truth table for a two-input XNOR gate looks like

Fig. 1.9: Implementation of basic gates using NAND

Fig. 1.10: Implementation of EX-OR gate

Fig. 1.11: Implementation of Basic gates using NOR

Applying theorem an Boolean algebra,

The simplified circuit is,

1.2.3 Boolean functions

1.2.3.1 Boolean rules for simplification

Fig. 1.12: Logic diagram for A + AB = A

Factoring A out of both terms

Rule 2: (Dec. 2005)

Fig. 1.13: Logic diagram for A +AB =A +B

Fig. 1.14: Logic diagram (A + B) (A + C) = A + BC

Example 1.8: Simplify the expression AB + BC(B + C)

Fig. 1.15: Logic diagram

Fig. 1.16: Simplified function diagram

1.3 SUM-OF-PRODUCTS METHOD

This simplified expression is a sum of products; but not a standard sum of

We note that F is 1 when A = 0, B = 0 and C = 1 , so this particular combination

Consider the truth table given in Table 1.10.

Fig. 1.17: AND-OR circuit

Fig. 1.18: NAND-NAND circuit

1.4 PRODUCT-OF-SUMS METHODS

Y = 0, when A = 0, B = 1 and C = 1 . So this particular combination makes the

Fig. 1.19: OR-AND circuit

Fig. 1.20: NOR-NOR circuit

= (x+ z) (y. (xz x]

1.5 KARNAUGH MAPS

1.5.1 Constructing a Karnaugh Map