AStudyontheMemristor-basedNon-Volatile4TStaticRAMCell

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A Study on the Memristor-based Non-Volatile 4T Static RAM Cell
Conference Paper · June 2011
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A Study on the Memristor-based Non-Volatile
4T Static RAM Cell
Hae-Jun Seo†, Dong-keun Song, Ju-ho Lee, Mohamed G. Ahmed and Tae-Won Cho
College of Electrical and Computer Engineering, Chungbuk University, Korea
Gaeshin 12, Heungduk, Cheongju, Chungbuk, Korea
Tel: +82-43-261-2479, Fax: +82-43-266-2479
E-mail: [email protected]†
  D RON 
1. Introduction M(q)  ROFF 1 q (t )  . (3)

 D2 
SRAM is used where either low power or bandwidth, or where μD is the average dopant mobility (m2S-1V-1). To
both, are issues for system performance. However, data simulate memristor behaviour, we used the window function
retention introduces a key problem in SRAM since data is lost that is proposed by Biolek[4] as well as F(x)=1-(x-sgn(-i))2p,
when power is removed usually at power-down. The volatility where i is memristor current and sgn(i)=1 when i=0, and
characteristic of conventional SRAM increases the booting sgn(i)=0 when i<0. As a matter of fact, when the current is
time for systems utilizing SRAM either as their fast main positive, the doped region length, w, is expanding. The
memory or cache. memristor has long writing time [3] and therefore it cannot be
Introduction of non-volatile memory into the main memory implemented directly as a fast storage, however, its reading
or cache architectures can be an effective means to reduce time is almost the same as that of a conventional SRAM cell.
booting time and energy consumption. Memristor-based Therefore in this paper we propose a modified SRAM cell that
SRAM cell can be a promising circuit component that would incorporates memristor allowing the SRAM cell to retain data
allow conventional SRAM cells to retain data at power-down at power-down without the need for auxiliary circuitry. The
without the need for auxiliary circuitry. Memristor (memory- functionality and stability of the newly introduced cell have
resistor) was theorized by Leon Chua in 1971 and formalized been verified through a series of simulation.
by Kang [1,2] as a new fundamental circuit element.
Memristor consists of a thin nano layer (6 nm–8 nm) of 2. Non-volatile SRAM Cell
insulating TiO2 and a second Oxygen deficient nano layer of
TiO2-x sandwiched between two Pt nanowires [3]. The
The conventional SRAM cell is modified to implement the
electrical behaviour as a memory is determined by the
non-volatile functionality through replacement of the two
boundary between these two regions. It is based upon the
pMOS load transistors in SRAM cell by memristors as
principle where one part of the TiO2 nano layer receives
illustrated in Fig. 1(a), Fig.(b) SRAM cell when the power is
Oxygen ions (O2-) while other part of TiO2 nano layer loses
turned off to save the data on the latch of the memristor device
oxygen ions. A change in distribution of oxygen ions within
and two pull-down transistor and consists of two pass
TiO2 nano layer changes the resistance [3]. The voltage
transistor. Memristors show resistivity changes along the
/current relationship of the memristor defined as M(q), can be
direction of low frequency current flow below 50 KHz [3].
modeled as:
 w(t ) 
 w(t )  
v(t)  RON  ROFF 1   i (t )
 D 
 D   . (1)
where D is TiO2/ TiO2-x film thicknesses, RON is the

resistance for completely doped memristor, while ROFF is the
resistance for the undopped region. The width of the doped
region w(t) is given by:
RON (a) (b)
w(t)   D q (t ) . (2) Fig. 1 Structure of (a)Conventional SRAM cell (b)Non-
D
volatile SRAM cell with memristors.
For RON << ROFF that is the case in digital circuits, Eq. (1) For the forward direction it has around 100K ohms: let this
is modified to: state correspond to the high bias condition. It is also about 50
ohms for the reverse direction: this is defined to be the low
bias. Two load devices of a SRAM cell flow current in the
forward direction making memristors in the high bias state. By
making a cell discharge through power lines for power down
events, one of the memristors will flow current in the reverse
direction. The memristor will have the low bias state during
the power off period. The resistivity mismatch between the
two current paths is used for information storage. The
mismatch will bring back the data stored just before the power
down. When the power is on, the load device of the current
path having the low bias state will have higher voltage than
that of the other path having the high bias state. The latch
mechanism of the SRAM cell instantly recovers the original
data before the power down.
Circuit simulations examine the possibility of circuit
malfunction due to this resistivity mismatch. Typical load
devices of a 4T SRAM cell have 10 Mohms. About 2 to 3 %
changes may occur. The effect of the memristor resistivity Fig.3 Restore the saved data.
changes will be practically negligible.
More detailed work will show through figures the
relationship. Fig.2 the supply voltage (Vdd) is off work when
the data is stored is an illustration. The power is supplied to
the SRAM cell latch to 0 when converting from Vdd, SRAM
cell for read data written to the latch device is stored in
memristor. Fig.3 the power supply voltage (Vdd) if the data
being restored is a picture of an example behavior. Power to
the SRAM cell from 0 to Vdd, when converted to the left and
right internal resistance of the memristor device SRAM cell by
the difference of the value that was stored in the latch itself is
restored. Fig. 4 the supply voltage (Vdd) continue to be
available is an illustration of the operation. When continued
power supply status of memristor is reinitialized, the proposed
SRAM cell and a conventional SRAM cell to perform the
same operation. Finally, fig.5 PMOS transistor instead of a
pull-up resistor to write a full CMOS SRAM cell shows that
can be applied.
Fig.4 Memristor initialization and basic SRAM cell operation.
Fig.2 Data stored in SRAM cell.
Fig.5 Full CMOS SRAM cell using Memristor.

Fig. 6 Timing and simulation scenario. Fig. 8 4T-SRAM SNM and comparison of the proposed
circuit.
Fig. 7 Monte Carlo simulation results (M is memristors).

Fig.9 Cell ratio changes according to the variation of SNM.
3. Non-volatile Cell Circuit Simulation
node of the latch structure generates the resistivity differences.
Three types of circuit simulation have been used to verify Cell stability analysis shows good noise immunity. Presence of
the data recovery, SRAM cell functionality and robustness. unmatched resistivity does not impede the cell operating
The static noise margin issues cover the design spaces for margin. The noise margin analysis shows that the non-volatile
correct cell operation. Monte Carlo simulation addresses the design yields a sufficient operation range is based on the
robustness of the cell operation. The simulation assumes T=25 window function model [4].
°C and VDD=3.3 V employing HSPICE model parameter for Fig. 8 is simulation results whether SRAM cell operates
ML 0.18 um CMOS technology. stably. SRAM cell stability is defined as the ability to maintain
The timing scenario of data recovery and memory access stored data without any damage, even though supply voltage,
operations is based on the modified cell. Fig. 6, shows data temperature, process variation are changed or there is noise
recovery after the power down period in accordance with the signal. To increase the cell stability noise margin of SRAM
memristor resistivity. The recovered data is sent to the bit line cell should be higher as much as possible. Fig. 8 presents the
(BL) when the word line (WL) activates. The sense amp comparison of SNM(Static Noise Margin) between
activation signal SA enables the data to be sent to the output. conventional 4T SRAM cell and proposed non-volatile 4T
It also demonstrates the SRAM read and write operations. The SRAM cell. Simulation was executed as cell ration is 2. In the
subsequent write operation takes external data, written into the figure, the addition of memristor does not affect to SNM of
cell along with the word line (WL) activation. The read SRAM cell. Also, we can see that cell stability can be
operation follows yielding the read data on the output. increased by changing cell ratio as in fig. 9 when operation
The robustness analysis of the cell operation shows the has problem due to low SNM.
sufficient level of cell operating range as shown in Fig. 7. Table1. the last of the non-volatile random access memory
Monte Carlo simulation performed addresses the voltage cell configuration and the operating speed of the proposed
difference variations between the memristors. It confirms that circuit will compare the place. Looking at the table cell above
immediate data recovery is achieved by extremely small load the plot area of the proposed circuit sustaining the other non-
voltage differences of the latch structure. Note that this volatile random access memory, at least 66.6time faster than
voltage differences are obtained by the resistivity differences the read time, write/erase time is at least 33.3time faster that
of the two memristor components. Discharge from a storage you can see.
Table. 1 Non-volatile RAM cell and speed comparison of [8] Z. Biolek, D. Biolek, and V. Biolkova (2009) “SPICE Model of
the proposed circuit configuration. memristor with nonlinear dopant drift,” Radio engineering, vol.8,
no.2, pp.210-214.
FeRAM MRAM PRAM Memristor Proposed [9] E. Seevinck, F. J. List, and J Lohstroh (1987) “Static-Noise
Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State
Cell Circuits, vol.sc-22, no.5, pp.748-754.
1T1C 1T1R 1T1R 1M 4T2R2M
structure
Read
<45 <20 <60 <50 <0.3
time(ns)
Write
/Erase 10 20 60 <250 <0.3
time(ns)
4. Conclusion
The non-volatile memory cell described in this letter
employs memristor elements as storage devices. A
conventional SRAM cell is modified to accommodate the
memristor elements in its load devices. The current discharge
mechanism is added when the power is down so that the
memristors may change its resistivity. When the power of the
SRAM is turned on, the resistivity differences between the two
load devices bring back the data previously stored. A series of
simulation including Monte Carlo analysis for stability and
static noise margin analysis verified the robustness of the
design. Computer systems with non-volatile SRAM cells in its
main memory or cache experience substantially shorter
booting time, and thereby consume less power and energy.
References
[1] L. O. Chua, “Memristor -the missing circuit element,” IEEE
Transactions on Circuit Theory, vol.18, no.5, pp.507–519,
September, 1971.
[2] L. O. Chua, and S. M. Kang, “Memristive devices and systems,”

IEEE Transactions on Circuit Theory, vol.64, no.2, pp. 209–222,
February, 1976.
[3] D. B. Strukov, G. S. Snider, D. R. Stewart, R. S. Williams, “The

missing memristor found,” Nature International Weekly Journal of
Science, no. 453, pp. 80–83, May, 2008.
[4] Z. Biolek, D. Biolek, and V. Biolková, “SPICE Model of

memristor with nonlinear dopant drift,” Radioengineering, vol. 18,
no.2, pp. 210-214, June, 2009.
[5] S. Williams (2008) “How we found the missing memristor.”

IEEE SPECTRUM vol.45, PP.28-35.
[6] J. Borghetti, and R.S. Williams (2010) “memristive switches

enable stateful logic operations via material implication,” Nature, vol.
464.
[7] Hee-Bok kang, Young-jin park, Jae-Jin Lee, Jin-Hong Ahn, Man-
young Sung, and Young-Kwon Sung (2004) “Cell Signal
Distribution Characteritics For High Density FeRAM,” Journal of
Semiconductor technology and science, col.4, no.3, pp.222-227.
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A Study on the Memristor-based Non-Volatile 4T Static RAM Cell

Conference Paper · June 2011

Mohamed Gamal Ahmed Mohamed

The user has requested enhancement of the downloaded file.

1. Introduction M(q)  ROFF 1 q (t )  . (3)

where D is TiO2/ TiO2-x film thicknesses, RON is the

Fig.2 Data stored in SRAM cell.

Fig.5 Full CMOS SRAM cell using Memristor.

Fig. 7 Monte Carlo simulation results (M is memristors).

[2] L. O. Chua, and S. M. Kang, “Memristive devices and systems,”

[3] D. B. Strukov, G. S. Snider, D. R. Stewart, R. S. Williams, “The

[4] Z. Biolek, D. Biolek, and V. Biolková, “SPICE Model of

[5] S. Williams (2008) “How we found the missing memristor.”

[6] J. Borghetti, and R.S. Williams (2010) “memristive switches

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