Earlier electronic circuits

Huge bulky and non-reliable circuit

Connecting wires
Metal strips
• Integrated Circuit (IC):An integrated circuit (IC), also called a chip or microchip, is a miniaturized low-cost electronic circuit.
• It is composed up of semiconductor wafer (substrate) on which millions of active and passive components (small resistors,
capacitors, and transistors) fabricated together.
• An engineer at Texas Instrument named Jack Kilby invented the first integrated circuit.

Why need Integrated circuit:

We have discrete components, can make different circuits,
can make PCBs, right, then why to go for integrated circuit?
1. Miniaturization: equipment density would increase
2. Batch processing resulting in cost reduction
3. Improved system reliability due to elimination of
soldered joints
4. Better functional performance: millions of transistors on
one device rather than having lot of circuits
5. Increased operating speeds
6. Significant reduction in the power consumption
 IC 7400 IC 741
Total no of transistor=?, Total no of resistor=?, Total
No of NAND Gates=4 no of capacitor=?
No of transistor per
gate=4
Total no of transistor= 16
Size of chip in mm
•Difference in mounting •Single In-line Package (SIP)
method • Leads come out of one side of the package
•Difference in terminals and the leads are in a single row.
•Zig-zag In-line Package (ZIP)
• Leads come out of one side of the package
and the leads zig-zagged out.
•Dual In-line Package (DIP)
• Leads come out of two sides of the
package and leads exit downward.

Packages with leads coming out of two sides of

the package are often marked with SO(Small
Outline). Shape of lead:
•SOP: Gull-wing (L-shaped) type
•SOJ: J-lead type
•SON: Non-leaded (no lead) type: have electrode
pads

Packages with leads coming out of four sides of

the package are often marked with QF(Quad
Flat). Shape of lead:
•QFP: Gull-wing (L-shaped) type
•QFJ: J-lead type
•QFN: Non-leaded (no lead) type
Packages with terminals arranged in a grid
pattern from bottom of package are often marked
with GA (Grid Array). Shape of lead:
•PGA: Pin type
•LGA: Land type
•BGA: Solder Balls type
A particular IC is categorized as
1. Linear or Analog: Linear IC is one which is gives us continuously variable output on the basis of given input signal
level.
2. Digital IC: Digital IC is one which operates at only a few defined levels or states.

Analog signal change smoothly and continuously over Digital signal have only two values
a range f values between a maximum and miimum in
this case output is almost directly proportional to the
input.at is it varies linearly with the input.

Ex: Logic gates, Flip-flops, Shift registers,

counters, memories, processors
Ex: Op-amp, Voltage regulator
 IC packages
Metal Can Integrated Ceramic packages: Plastic packages
Circuit •Provides high reliability under •Plastic packages are lightweight, cost-
•Made using quality grade severe environmental conditions. effective, and suitable for high-volume
raw material •Offers excellent heat transfer automated manufacturing.
•Long lasting usage properties, suitable for high- •Suited for applications where hermetic
•Optimum functionality temperature applications. sealing is not a strict requirement.
•Suitable for applications requiring •Offers design flexibility for various forms
hermetic sealing and minimal and shapes.
gas/moisture permeability. Challenges of plastic packaging includes:
Challenges of ceramic packaging •Vulnerable to higher temperatures; some
include: chips can break down or melt plastic
•Ceramic packages are bigger packaging.
and heavier compared to plastic •Plastic packaging may absorb moisture,
packages. leading to issues like "popcorning" when
•Manufacturing and testing of exposed to high temperatures.
ceramic packages can add •Some chips may produce heat that affects
substantial cost. the stability of plastics
•Quartz windows are necessary
for certain applications, adding
complexity and cost.
Digital ICs: Digital ICs are further divided based on number of logic gates present per mm2
 IMPACT OF WAFER SIZE ON SEMICONDUCTOR INDUSTRY

• The standard silicon wafer size at present is 300mm (11.8/12 inch), although
the trend is growing in favor of larger sizes.
• This is mostly due to the higher productivity and efficiency that a larger
wafer size can provide.
• Larger wafer size indicates: Higher chip density per wafer – more IC
production in a single manufacturing run.
• Shifting to 450mm will allow gain in surface area of 125%. It should also
reduce operating costs by 20-30%.

Intel’s Chip Manufacturing 450mm Wafers

 Moore’s Law

• Intel co-founder Gordon Moore predicted a

doubling of transistors every year for the
next 10 years in his original paper
published in 1965.
which he updated in 1975
• Moore’s Law is the observation that the
number of transistors on an integrated
circuit will double every two years with
minimal rise in cost.

“Core i7 processors
approximately 1.7 billion transistors”
Types of Integrated Circuits
The most noticeable characteristic of an IC is its size. Built in a manner like the discrete components. The disadvantage of using
an IC is when a single component within an IC fails; the entire structure is replaced.

A. Monolithic IC
• It came form the Greek words “monos” meaning single and “lithos” meaning stone.
• Thus, it means single – stone or single solid structure.
• It is constructed within a single wafer of semiconductor material.
• Wafers are1/1000 inch obtained through a slicing process.
• Mask – a selective diffusion required in the formation of the various active and passive elements of an IC.
• Photolithographic process – selective etching of the SiO2 layer is accomplished through the use of this process.
• The wafer is first coated with a thin layer of photosensitive material, called photoresist.
• It uses ultraviolet light that can not penetrate the masking pattern.
B. Thick and Thin Film
• It is not formed within a semiconductor wafer but on the surface of an insulating substrate such as glass or an appropriate
ceramic material.
• Passive elements are used in thick and thin film.
• Active elements are added as discrete elements.
• The only difference between thin and thick film is the method employed for its formation.
• The thin film uses evaporation or cathode sputtering technique, while the thick film employs the silk screen technique
C. Hybrid IC
Hybrid IC is simply the combination of both monolithic and thick/thin filmintegrated circuit
The various processes used to fabricate IC’s using silicon planar technology:

1. Silicon wafer preparation.

2. Epitaxial growth.
3. Oxidation.
4. Photolithography.
5. Diffusion.
6. Ion implantation.
7. Isolation.
8. Metallization.
9. Assembly processing and packaging.
 Wafer Fabrication

1. Czochralski Crystal Growth Process

Four important subsystems:

Silicon in nature
1. Furnace: Crucible, susceptor and rotation mechanism,
heating element, power supply, and chamber.

2. Crystal-pulling mechanism: Seed shaft or chain, rotation

mechanism and seed chuck
3. Ambient control: Gas source, purge tube, flow control and
exhaust system
4. Control system: Sensors microprocessor and outputs
2. Float zone technique (FZ Technique)
Process flowing steps of shaping of ingot to wafer
A crystallographic orientation flat is also ground along the length of the ingot and defined by two types of flats:
Primary flat-defines specific crystal direction and act as a visual reference to the orientation of the wafer
Secondary flat-defines for identification of the wafer, dopant type and orientation

On viewing the wafers based on flats one can easily analysis the type of wafer
 Epitaxy

• The term epitaxy refers to the “Growth of a crystalline layer on (epi) the surface of a crystalline substrate and
crystallographic orientation of the substrate surface imposes a crystalline order (taxis) onto the growing film"
i.e. the grown film have a crystal structure with certain thickness. The grown film crystal structure may be differs from their
bulk so epitaxial deposition has facility to add and arrange atoms upon the crystal surface.
• Epitaxy is discriminated in two different kinds:
(i) Homoepitaxy growth in which the epitaxial layer and the substrate are of the same material. If grown film and substrate
have different lattice constants but same crystal lattices the film will be under strain with slightly different lattice constant than
in its own bulk. Some novel properties may occur due to the electronic hybridization at the interface. Mostly commercial
silicon epitaxy is Homoepitaxy.

(ii) Heteroepitaxy growth in which the epitaxial layer and substrate are of a different materials. The two crystal structure
should be very similar if single-crystal growth is to be obtain and a large number of defects are to be avoided at the epitaxial-
substrate interface
• Several epitaxial techniques are used to grow epitaxy layers of materials and compound semiconductors. The prominent
among these techniques are:
•Liquid Phase Epitaxy (LPE),
•Vapour Phase Epitaxy (VPE),
•Molecular Beam Epitaxy (MBE),
•Chemical Beam Epitaxy (CBE),
•Atomic Layer Epitaxy (ALE)
 Oxidation
• Silicon is unique among semiconductor materials and what makes it so popular is that silicon forms an excellent native
oxide, SiO2 with ease. This oxide is widely used as an insulator both in active devices such as MOSFETs and in the region
between the active devices, known as the field.
• It is privileged that silicon forms protective oxide easily.
• In oxidation process, a semiconductor or metal is converted to an oxide. In technology, oxidation of various materials plays
a role, but conversion of parts or fully of a semiconductor wafer into SiO2 is chief oxidation process. the process by which
a silicon dioxide is grown
• Thickness depend upon time and temperature
GROWTH RATE OF SILICON OXIDE LAYER
 Measurement of oxide thickness
The oxide thickness is an important parameter of the oxidation process, and thus many ways have been
developed to measure it. Several methods for estimating the thickness of an oxide are:
1. Physical determination of the oxide thickness requires the production of a step in the oxide. Typically
this is done with a mask followed by an etch. Hydrofluoric acid (HF) etches oxide at a much higher
rate than it etches silicon. Therefore, if a mask is applied to the wafer, the wafer immersed in HF, and
then the mask is removed, a step nearly equal to the oxide thickness will be left. This step can be
measured using a scanning electron microscope (SEM) if thickness is larger than 200 Å, or with a
transmission electron microscope (TEM) if it is not.
2. Surface profilometer: an instrument that measures surface topology by mechanically scanning a
needle stylus while it is in contact with the wafer. The deflection of the needle is measured,
amplified, and displayed as a function of position. Similarly, atomic force microscopy (AFM) can be
used to measure the step. Profilometry has the advantage that it makes no assumptions other than
the relative etch rates of the oxide and the silicon. Since part of the oxide must be etched to
determine the thickness, this test is destructive and generally requires the use of a dedicated test
wafer.
3. Simplest optical technique is to partially immerse the unmasked wafer in dilute HF until the oxide on
the submerged portion of the wafer is completely removed. Near the line between the etched and
unetched oxide, a slow grading of the thickness will be found. If this edge is examined under a
microscope a variety of colors will be seen starting from light brown. These colors are due to
interference between the incident and reflected light. By following the colors up to the top of the
oxide an approximate thickness can be found.
4. Ellipsometry technique: a polarized coherent beam of light that is reflected off the
oxide surface at some angle. Helium-Neon lasers are commonly used as a source. The
reflected light intensity is measured as a function of the polarization angle. To measure
refraction index and film thickness, reflected and incident intensity are compared and
change in polarization angle is measured. To do this definitively requires measurement at
more than one incidence angle or for more than one wavelength as more than one
thickness generates the same change in the light at any given angle or wavelength.
Variable angle spectroscopic ellipsometers systematically vary both angle and wavelength
and fit the data to a model to extract thickness and index. Ellipsometry has the
advantage of being nondestructive, although it often requires that the oxide be grown on
bare silicon.
5. Capacitance-Voltage (C-V) measurements: most sensitive methods of evaluating oxides. A metal film must be used as an
upper electrode. The wafer is used as a lower electrode. Assume for the moment that the substrate is doped p-type. On
application of negative voltage to the gate, additional holes are drawn to the Si–SiO2 interface. This process is known as
accumulation. Now assume that a small ac signal is added to the dc bias and the ac current is measured. The out of-phase
magnitude of current is proportional to the capacitance.
The device will be considered as parallel plate capacitor, if the diameter of the capacitor is very large compared to the oxide
thickness.
𝜀𝐴 𝜀 𝜀 𝐴
Then 𝐶𝑜𝑥 = 𝑡 = 𝑟𝑡 𝑜 where 𝜀𝑟 is the relative permittivity or dielectric constant of the oxide and 𝜀𝑜 is the permittivity of
𝑜𝑥 𝑜𝑥
free space.
 Oxide furnace
Batch process is used to grow thermal oxides in tube furnaces, i.e. manifold wafers are processed at the same time.
• In the context of process control, this becomes important as any change from required conditions would affect all wafers in
that batch and hence lead to overall cost increase.
• The furnace is designed to have a long flat zone in which the temperature can be controlled from 400°C to 1200°C
• One end of the furnace has provisions for the flow of pure dry oxygen or water vapour while the other end opens into a
vertical flow clean air bench where the wafers can be loaded into the reactor.
• The hood is designed to keep out particulate matter and minimize contamination during wafer loading.
• Gas flow, insertion and withdrawal of wafers as well as the furnace temperature are micro-processor controlled.
• The furnace temperature is ramped up and down several times to prevent thermal shock to the wafers and damage later.
• Utmost cleanliness is essential in wafer handling as well as in maintenance of the diffusion tube which must be cleaned at
intervals.
• In special cases the slotted quartz boat can be replaced by one made of polysilicon.
• For wafer having small sizes, typically 3” and 4” wafers, horizontal tube furnaces are utilized for oxidation.
• If wafer is of large size (common wafers are now 300 mm), horizontal furnaces are not practical. These occupies lot of
space. For large size wafers vertical diffusion furnaces are used. Vertical furnace is also known as diffusion furnace.
• Generally, oxygen (for dry oxidation) and steam (for wet oxidation) at the appropriate partial pressure (concentration) is
used as a source gas.
 OXIDATION TECHNIQUES
Various physical deposition methods are utilized to grow oxide layer. These methods are:
i) Physical vapor deposition: It is a process in which the target material is first vaporized or sputtering then condensed on
the substrate surface.
• There are no chemical reaction involve in the vicinity of substrate surface.
• In PVD the atoms or molecules in the vapor phase physically absorb on the surface of the substrate to form a solid
film which is normally amorphous in nature and can be converted to crystalline form on proper annealing ambient.
• PVD occurred at a very low pressure so that very few gas collision occur with surface reaction occur very rapidly and
very little rearrangement of atoms happens at the surface of wafer.
• Physical vapor deposition (PVD) technology fall into:
(a) Evaporation : It is one of the oldest techniques for depositing thin films.
A vapor is first generated by evaporating a source material in a vacuum chamber and then
transported from the source to the substrate and condensed to a solid film on the substrate
surface as shown in fig. The wafers are loaded into a high vacuum chamber that is
pumped with either a diffusion pump or a cryo pump. Diffusion-pumped systems
commonly have a cold trap to prevent the back streaming of pump oil vapors into the
chamber. The charge, or material to be deposited, is loaded into a heated container called
the crucible. It can be heated very simply by means of an embedded resistance heater
through external power supply. As the material in the crucible becomes hot, the charge gives
off a vapor. Since the pressure in the chamber is much less than 1 m.torr, the atoms of the
vapor travel across the chamber in a straight line until they strike a surface, where they
accumulate as a film.
b) Sputtering: Sputtering, unlike evaporation, is very well controlled and generally applicable to all
materials such as metals, insulators, semiconductors, and alloys film deposition in microelectronic
fabrication.
• Placed within a vacuum chamber, the target material and the substrate are subjected to a
voltage differential. This voltage setup designates the target as cathode while the substrate is
linked to anode
• Through ionization of a sputtering gas—commonly an inert gas like argon or xenon—
a plasma is generated.
• Inert gases are favored as sputtering gases due to their minimal reactivity with the target
material and process gases and their capacity to yield heightened sputtering and deposition
rates owing to their substantial molecular weight.
• Sputter deposition involves ejecting material from a target to a substrate through plasma
generated by inert gas, forming uniform thin films.
• Sputtering involves the ejection of surface atoms from an electrode surface by momentum
transfer from the bombarding ions to the electrode surface atoms.
• In a sputtering application, however, the plasma chamber must be arranged so that high energy ions strike a target containing
the material to be deposited. The target material must be placed on the electrode with the maximum ion flux.
• To collect as many of these ejected atoms as possible, the cathode and anode in a simple sputtering system are closely
spaced, often less than 15 cm.
• The gas pressure in the chamber is held at about 0.1 torr. This results in a mean free path of order hundreds of mm.
• Due to the physical nature sputtering can be used for depositing a wide variety of materials. In the case of elemental metals,
simple DC sputtering is usually favored due to its large sputter rates. When depositing insulating materials such as SiO2, an RF
plasma must be used.
 Photolithography

• Photolithography is the most complicated, expensive, and critical process in mainstream microelectronic fabrication.
• In IC technology, Lithography is the process of transferring pattern of design outline through mask to the surface of
semiconductor wafer which is covered through radiation-sensitive material known as photoresist.
• Lithography is the process of transferring patterns drawn on a mask to a thin layer of radiation sensitive material (resist)
covering the surface of the material to be etched (oxide or metal).
Basics of Photolithography
 MASKS

• IC fabrication is done by mass batch processing, where many copies of the same circuit
are deposited on a single wafer and many wafers at the same time.
• The number of wafers processed at one time is called the Lot whose size may vary between 20 to 200 wafers.
• Since each IC chip is square and the wafer is circular, the number of chips per wafer is :
“the number of complete squares of a given size that can fit inside a circle”.
• The photographic mask controls the location of all windows in the oxide layer and so areas over which a particular
diffusion step is effective.
• Each complete mask consists of a photographic plate on which each window is represented by a dense part and
remainder remains transparent.
• The patterns are generated using computer-aided design (CAD) systems whose output drives a pattern generator
that transfers the patterns directly to the photosensitive masks.
• Masks are typically made from fused silica i.e. glass covered with hard-surface materials such as Cr or Fe2O3.
• Mask substrate materials are chosen to comply with some mechanical and physical properties that can be
summarized as follows: transparency at the exposure wavelength, thermal expansion and flatness
• Low thermal expansion materials are required mainly for two reasons:
1. To minimize mask pattern placement errors induced by temperature variations that may happen during
the mask patterning process, and
2. To minimize wafer pattern placement errors induced by mask heating that may happen when the mask is
exposed to laser radiation in exposure tools.
 PHOTORESIST
• A photoresist is a radiation-sensitive compound that forms a Polymer film in
radiation.
• The film is photosensitive or capable or reacting with the photolysis product of
added compound so that the solubility in developer solution increases or
decreases significantly by exposure to UV radiation.
• According to the solubility changes that take place, photoresists are termed
negative or positive.
• Materials which are solidified, less soluble in a developer solution by radiance
produce a negative pattern of the mask and are called negative photoresists.
• Wherein positive resists, the exposed region becomes more soluble by radiance so
more readily removed in the developing process.
• The net result is that the patterns formed in the positive resist on the wafer are
same as those on the mask and the patterns etched are the reverse of the mask
patterns for negative resists as the exposed regions become less soluble.
• The change in solubility is due to a set of chemical reactions which occur as the
photon scatters and loses energy in the resist polymer material.

Figure: lithographic transfer

process.
 PATTERN TRANSFER

• The goal of pattern transfer is to transfer the sketches on the mask to the wafer surface.
• To achieve this, two phases are often performed when fabricating microelectronic devices.
• In the first phase, a photolithography process is used to transfer the pattern of the mask on the photoresist;
• And in the second phase, the thin-film removal is employed to copy the image on the photoresist on to the wafer
surface.
1. Wafer clean and prime: The first step of the photolithography is to clean the wafer because it might be contaminated
during the previous step. Then, a priming process is utilized to deposit a thin primer layer to wet the wafer surface that
enhance the adhesion between the photoresist and the wafer surface.
2. Photoresist coating: The wafer is coated with a liquid photo resist by a spin coating method. The spin speed and the
viscosity of photoresist material determine the final photoresist thickness, ranging from 0.6 to 1 mm.
3. Softbake: A softbake process is required to drive off most of the solvent in the photoresist material. The softbake
process is to place the wafer on a hot plate at a temperature of 90 to 100°C for about 30 seconds.
4. Alignment & Exposure: The mask is aligned to the correct location of wafer coated with the photoresist and then
exposed into a controlled UV light to transfer the mask image onto the photoresist surface as displayed
5. Post-exposure bake: A post develop bake of the photoresist pattern is a common method for stabilizing the printed
features to provide optimum performance at etch.
6. Development: Development is the critical step for creating the pattern in photo resist on the wafer surface. In this step,
the soluble regions are removed by developer chemicals, After development, the following two steps are often carried
out.
7. Hardbake: After development, the wafer needs to be baked again on a hot plate at a temperature of 100 to 130.C for
about 1 to 2 minutes to drive out the remaining solvent in the photoresist material. This step improves not only the
strength and adhesion but also the, etch and ion-implantation resistance of the photoresist.
8. Photoresist Stripping: The remaining part of the pattern transfer of the running example is completed by etching away
the silicon dioxide exposed and then removing the photoresist. Succeeding oxide etching and with the help of abrasion
process, the remaining resist is finally stripped off with a mixture of H2SO4 and H2O2. Finally a step of washing and drying
completes the required window in the oxide layer.

9. Pattern inspection: The closing step of the pattern transfer process is pattern inspection, which checks whether the
sketch on the mask correctly transported. The whole process is repeated again if the wafer fails in inspection test.
 Etching
• Thin-film removal, also known as thin-film etch or just etch for short, is the process of selectively removing the
unneeded (unprotected) material by a chemical (wet) or physical (dry) means.
• After a photoresist image has been fabricated on the surface of a wafer, the next process often involves transferring
that image into a layer under the resist by etching.
• In wet chemical etching processes where wafer is immersed in a solution that reacts with the exposed film to form
soluble by-products. Ideally, the photoresist mask is highly resistant to attack by the etching solution. Although still
used for noncritical processes, wet chemical etching is difficult to control, is prone to high defect levels due to solution
particulate contamination, cannot be used for small features, and produces large volumes of chemical waste.

ETCH PARAMETERS
• The most important parameters that govern which of etching process, wet etching or dry etching, is appropriate when
removing a specific thin film are etch rate, etch profile, selectivity, uniformity, and degree of anisotropy.
1. Etch Rate: Etch rate is a measure of the thickness removed per unit of time.
• It is usually a strong function of solution concentration and etching temperature.
• High etch rate is generally favorable due to a higher throughput which is generally desirable in a manufacturing
environment.
• Too high etch rate may render a process difficult to control.
• Desired etch rates commonly are hundreds or tens of nanometer per minute (nm/min).
• When a batch of wafers is etched simultaneously, etch rate can be less than the rate required for a single-wafer
etch process.
• Several related figures are equally important. Variation percentage of each rate through a wafer and wafer to
wafer is measured in terms.
2. Etch Profile
• Etch profile refers to the fraction of sidewall of the etched feature removed during an etching process.
• There are two basic etch profiles, as illustrated in figure.
• In an isotropic etch profile, all directions are etched at the same rate, leading to an undercut of the etched
material under the mask as in figure a.
• This results in the reduction of the actual width of a line such as a polysilicon or a metal wire.
• The other etch profile is called an anisotropic etch profile. In this profile, the etch rate is in only one direction
perpendicular to the wafer surface, as in figure b.

3. Selectivity
Selectivity means how much faster one material is etched than another under the same condition.
Selectivity (S) is defined as etch rate ratio of one material to another and is given by
𝑅1
𝑆=
𝑅2
Where R1 is etch rate of the material intended to be removed and R2 is the etch rate of the material not intended to be
removed. A particular process may be quoted as having a selectivity of 20 to 1 for polysilicon over oxide means that
polysilicon etches 20 times faster than oxide.
4. Uniformity
Uniformity is a measure of the capability of the etching process to etch evenly across the entire wafer surface.
For IC production lines, high uniform each rates are important.
Each rate uniformity is given by

(Maximun etch rate−Minimum etch rate)

Each rate uniformity (%) = × 100
(Maximum etch rate+Minimum etch rate)

5. Degree of Anisotropy
Degree of anisotropy Af is a measure of how rapidly an etchant removes material in different directions and can be given
by
𝑅𝑙
𝐴𝑓 = 1 −
𝑅𝑣
where 𝑅𝑙 is the lateral etch rate whereas 𝑅𝑣 is the vertical etch rate. For isotropic etch, 𝑅𝑙 is equal to 𝑅𝑣 and therefore Af =
0; for anisotropic etch, 𝑅𝑙 is equal to v 0 and therefore Af = 1.
 SILICON ETCHING

For silicon, mostly used etchants are the mixtures of nitric acid (HNO3) with hydrofluoric acid (HF) in water or acetic acid
(CH3COOH). The reaction is initiated by promoting silicon from its initial oxidation state to a higher oxidation state
Si + 2h+ Si2+

The holes (h+) are generated through the following autocatalytic process:
HNO3 + HNO2 2NO2- + 2h+ + H2O
2NO2– + 2H+ 2HNO2
Si2+ combines with OH– (produced by the dissociation of H2O) to form Si (OH)2 which later releases H2 to form SiO2:
Si(OH)2 SiO2 + H2
SiO2 then dissolves in HF;
SiO2 + 6HF H2SiF6 + H2O
The overall reaction can be written
Si (s) + HNO3 (l) + 6HF (l) H2SiF6 (l) + HNO2 (l) + H2O (l) + H2 (g)
 SILICON DIOXIDE ETCHING
• One of the most common etching processes is the wet etching of SiO in dilute solutions of hydrofluoric acid (HF).
2

• Common etchants are 6:1, 10:1, and 50:1, meaning 6, 10, or 50 parts (by volume) of water to one part HF. A 6:1 HF
solution will etch thermal silicon dioxide at about 1200 Å/min.
• Deposited oxides tend to etch much faster.
• The ratio of the deposited film etch rate in HF to that of thermal oxides is often taken as a measure of its density.
• Doped oxides such as phosphosilicate glass and borophosphosilicate glass etch faster yet, as the etch rate increases with
impurity concentration. Solutions of HF are extremely selective of oxide over silicon some etching of silicon does occur,
since the water will slowly oxidize the surface of the silicon and HF will etch this oxide
• Wet etching of oxide in HF solutions is, however, completely isotropic.
• The exact reaction pathway is complex and depends on the ionic strength, the solution pH, and the etchant solution. The
overall reaction for etching SiO is
2

SiO2 (s) + 6HF (l) H2 (g) + SiF6 (l) + 2H2O (l)

Since the reaction consumes HF, the reaction rate will decrease with time.
• To avoid this it is common to use HF with a buffering agent (BHF) such as ammonium fluoride (NH4F), which maintains a
constant concentration of HF through the dissolution reaction:
NH4F (s) NH3(g) + HF (l)
Where NH3 (ammonia) is a gas. Buffering also controls the pH of the etchant which minimizes photoresist attack.
 WET ETCHING PROCESS
The wet etching process is the earliest used etching process.
• It uses the chemical reaction between thin film and solvent to remove the thin film unprotected by photoresist.
• The wet etching process is commonly used to etch silicon dioxide, single-crystal silicon, silicon nitride, and metal.
• The wet etching process has high throughput compared to the dry etching process and is usually an isotropic process even
though it can also be anisotropic.
• Consequently, in modern deep submicron processes, it is not suitable for defining the line features.
• However, due to high selectivity, it still plays an important role in the cleaning of the wafer surface and thin-film removal,
such as silicon dioxide cleaning, residue removal, and the stripping of surface layers, such as the blanket thin film.
• So in wafer production process lapping and polishing process utilizes wet etching to produce damage-free optically flat
surface.
• Wafers are scrubbed and chemically cleaned to remove contamination that results from handling and storing before loading
to the chambers for thermal oxidation or epitaxial growth.
• Wet etching is used to outline patterns and windows in insulating materials for many discrete devices and ICs of relatively
large dimensions (> 3 μm). In IC processing, most chemical etchings proceed through dissolution of a materials in a solvent or
by transforming the material into a soluble compound that successively dissolves in the etching medium.
Wet chemical etching contains mainly three steps:
1. Transportation of reactants towards the reacting surface (e.g. by diffusion)
2. Chemical reactions on and at the surface
3. Transportation of the products from the surface (e.g. by diffusion)

Since all three steps must occur, the slowest one, called the rate-limiting step, determines the etch rate. Since it is generally
desirable to have a large, uniform, well-controlled etch rate, the wet etch solution is often agitated in some manner to assist
in the movement of etchant to the surface and the removal of the etch product. Some wet etch processes use a continuous
acid spray to ensure a fresh supply of etchant, but this comes at the cost of the production of significant amounts of chemical
waste. Wet etching can also have serious drawbacks such as a lack of anisotropy, poor process control, and excessive particle
contamination.
 DRY ETCHING PROCESS
• The dry etching (also called as plasma etching) process has gradually replaced the wet etching process for all
patterned etching processes since the feature size reached 3 μm in the late 1980s.
• Nowadays, because it has an excellent anisotropic profile and can generate very reactive chemical species, the
dry etching process has become the primary etch approach in semiconductor fabricating.
• It may remove the material through only chemical reactions using chemical reactive gases or plasma, by purely
physical methods such as sputtering and ion beam-induced etching, or with a combination of both chemical
reaction and physical bombardment.
• The dry etching process is commonly used to etch dielectric, single-crystal silicon, poly silicon, and metal, as well
as to strip photoresist.
 PLASMA ETCHING PROCESS
• Plasma is an ionized gas composed of ions, electrons, and neutral atoms or molecules with an equal amount of positive
and negative charge.
• Although plasma is neutral in a macroscopic sense, it behaves quite differently from a molecular gas, because it consists of
charged particles that can be influenced by applied electric and magnetic fields.
• To achieve the etching action, plasma provides energetic positive ions that are accelerated toward the wafer surface by a
high electric field.
• These ions physically bombard the unprotected wafer surface material, causing material to be ejected off the wafer surface.
• A plasma is produced when an electric field is applied across two electrodes between which a gas is confined at low
pressure, causing the gas to break down and become ionized
• Simple DC (direct current) power can be used to generate plasma, but insulating materials require AC (alternate current)
power to reduce charging.
• In plasma etching, an RF (radio frequency) field is usually used to generate the gas discharge.
• One reason for doing so is that the electrodes do not have to be made of a conducting material.
• The other reason is that electrons can pick up sufficient energy during field oscillation to cause more ionization by electron –
neutral atom collisions.
• As a result, the plasma can be generated at pressures
lower than 10-3 torr.
• A conceptual view of the plasma etching system is shown in fig.
• The free electrons released by photo-ionization or field emission from a negatively biased electrode create the
plasma.
• The free electrons gain kinetic energy from the applied electric field, and in the course of their travel through
the gas, they collide with gas molecules and lose energy.
• These inelastic collisions serve to further ionize or excite neutral species in the plasma via the following reaction
examples:
e- + AB A- + B++ e- (Dissociative attachment)
e- + AB A + B + e-(Dissociation)
e- + A A++ 2 e- (Ionization)
• Some of these collisions cause the gas molecules to be ionized and create more electrons to sustain the plasma.
• Therefore, when the applied voltage is larger than the breakdown potential, the plasma is formed throughout the
reaction chamber. Some of these inelastic collisions can also raise neutrals and ions to excited electronic states
that later decay by photoemission, thereby causing the characteristic plasma glow.
 Diffusion

• The selectively changing of electrical properties of silicon through the introduction of impurities commonly
referred to as dopants.
• Impurity atoms are introduced onto the surface of a silicon wafer and diffuse into the lattice because of their
tendency to move from regions of high to low concentration.
• The doping concentration decreases monotonically from the surface, and the in-depth distribution of the dopant is
determined mainly by the temperature and diffusion time.
• Diffusion of impurity atoms into silicon crystal takes place only at elevated temperature, typically 900 to 1200°C.
• Diffusion and ion implantation are the two key processes to introduce a controlled amount of dopants into
semiconductors and to alter the conductivity type.
• In modern state-of-the-art IC fabrication the required junction depths have become so shallow that dopants are
introduced into the silicon at the desired depth by ion implantation and any diffusion of the dopants is unwanted;
therefore diffusion has become a problem as opposed to an asset.
• Generally speaking, diffusion and ion implantation complement each other.
• For instance, diffusion is used to form a deep junction, such as an n-tub in a CMOS device, while ion implantation is
utilized to form a shallow junction, like a source / drain junction of a MOSFET.
 ATOMIC MECHANISMS OF DIFFUSION

• Impurity atoms utilized as dopants such as boron (B), phosphorus (P) and arsenic (As) occupy substitution
positions where the dopant atoms can contribute free electrons or holes to the silicon lattice
• The diffusion of impurities into a solid is basically the same type of process as occurs when excess carriers are
created non-uniformly in a semiconductor which cause carrier gradient.
• In each case, the diffusion is a result of random motion, and particles diffuse in the direction of decreasing
concentration gradient.
• The random motion of impurity atoms in a solid is, of course, rather limited unless the temperature is high.

There are mainly two types of physical mechanisms by which the impurities can diffuse into the lattice. They are:
1. Substitutional Diffusion
2. Interstitial Diffusion
 Substitutional Diffusion
• At high temperature many atoms in the semiconductor move out of their lattice site, leaving
vacancies into which impurity atoms can move.
• The impurities, thus, diffuse by this type of vacancy motion and occupy lattice position in the
crystal after it is cooled.
• Thus, substitution diffusion takes place by replacing the silicon atoms of parent crystal by
impurity atom.
• In other words, impurity atoms diffuse by moving from a lattice site to a neighboring one by
substituting for a silicon atom which has vacated a usually occupied site as shown in the figure.
• Substitutional diffusion mechanism is applicable to the most common diffusants, such as B, P
and As.
• These dopants atoms are too huge to fit into the interstices or voids, so the only way they can
enter the silicon crystal is to substitute for a Si atom.
• In order for such an impurity atom to move to a neighboring vacant site, it has to overcome
energy barrier which is due to the breaking of covalent bonds.
• The probability of its having enough thermal energy to do this is proportional to an exponential
function of temperature.
• Also, whether it is able to move is also dependent on the availability of a vacant neighboring site
and since an adjacent site is vacated by a Si atom due to thermal fluctuation of the lattice, the
probability of such an event is again an exponent of temperature.
• The jump rate of impurity atoms at ordinary temperatures is very slow, for example about 1
jump per 1050 years at room temperature.
• However, the diffusion rate can be speeded up by an increase in temperature.
 Interstitial Diffusion
• In such, diffusion type, the impurity atom does not replace the silicon atom, but instead moves into the interstitial voids
in the lattice.
• The main types of impurities diffusing by such mechanism are gold, copper, and nickel.
• Gold, particularly, is introduced into silicon to reduce carrier life time and hence useful to increase speed at digital IC’s.
• Because of the large size of such metal atoms, they do not usually substitute in the silicon lattice.
• To understand interstitial diffusion, let us consider a unit cell of the diamond lattice of the silicon which has five
interstitial voids.
• Each of the voids is big enough to contain an impurity atom.
• An impurity atom located in one such void can move to a neighboring void, as shown in the figure.
• In doing so it again has to surmount a potential barrier due to lattice this time, most neighboring interstitial sites are
vacant so the frequency of movement is reduced.
• The diffusion rate due to this process is very slow at room temperature but becomes practically acceptable at normal
operating temperature of around 1000°C.
• The diffusion rate due to interstitial movement is much greater than for substitutional movement. This is possible
because interstitial diffusants can fit in the voids between silicon atoms.
 Parameters which Affect Diffusion Profile

• Solid Solubility – In deciding which of the availability impurities can be used, it is essential to know if the number of atoms
per unit volume required by the specific profile is less than the diffusant solid solubility.
• Diffusion temperature – Higher temperatures give more thermal energy and thus higher velocities, to the diffused
impurities. It is found that the diffusion coefficient critically depends upon temperature. Therefore, the temperature
profile of diffusion furnace must have higher tolerance of temperature variation over its entire area.
• Diffusion time -Increases of diffusion time, t, or diffusion coefficient D have similar effects on junction depth as can be
seen from the equations of limited and constant source diffusions. For Gaussian distribution, the net concentration will
decrease due to impurity compensation, and can approach zero with increasing diffusion tunes. For constant source
diffusion, the net Impurity concentration on the diffused side of the p-n junction shows a steady increase with time.
• Surface cleanliness and defects in silicon crystal – The silicon surface must be prevented against contaminants during
diffusion which may interfere seriously with the uniformity of the diffusion profile. The crystal defects such as dislocation
or stacking faults may produce localized impurity concentration. This results in the degradation of junction characteristics.
Hence silicon crystal must be highly perfect.
DIFFUSION SYSTEMS
The choice of dopants in Si has been discussed. There are broadly 2 types of diffusion systems employed (i) open tube and
(ii) closed tube. There are some general requirements for diffusion systems. These are:
(a) The dopant remaining after diffusion should be capable of easily removed
(b) The diffusion process should not result in any damage to the surface
(c) The temperature control should provide a central flat zone with ±1/2℃ variation in Temperature.
(d) The system should be reproducible and capable of handling a large number of wafers simultaneously.
• A diffusion furnace is a carefully designed apparatus proficient of upholding uniform temperature between 600–1200°C
with a feedback controller.
• The diffusion tube made of high purity fused silica must be handled with great care, one tube and slice carrier being
used for each type of dopant to prevent contamination.
• The length of the tubes varies from 10 cm – 150 cm or more for industrial furnaces. For large tubes the insertion of the
carrier is done mechanically from one end, the other end being used for flow of gases and dopants.
• The temperature of the furnace is gradually ramped up from 600°C after insertion of the wafers with a programmed
temperature controller ramping up the temperature at a linear rate of 3–10°C/min. This is to avoid thermal shock to the
wafers as well as to the tube and components.
• In practice the diffusion tube is always kept above 600°C and never permissible to cool to room temperature to avoid
devitrification.
Fig: Gas source diffusion system
Fig: Liquid source diffusion system

Fig: Solid source diffusion system

 FICK’S LAWS OF DIFFUSION
The diffusion rate of impurities into semiconductor lattice depends on the following:
•Mechanism of diffusion
•Temperature
•Physical properties of impurity
•The properties of the lattice environment
•The concentration gradient of impurities
•The geometry of the parent semiconductor

• The behavior of diffusion particles is governed by Fick’s Law, which when solved for appropriate boundary conditions, gives
rise to various dopant distributions, called profiles which are approximated during actual diffusion processes.
• In 1855, Fick drew analogy between material transfer in a solution and heat transfer by conduction. Fick assumed that in a
dilute liquid or gaseous solution, in the absence of convection, the transfer of solute atoms per unit area in a one-dimensional
flow can be described by the following equation.

Where F is the rate of transfer of solute atoms per unit area of the diffusion flux density (atoms/cm2-sec),
N is the concentration of solute atoms (number of atoms per unit volume/cm3), and
x is the direction of solute flow.
t is the diffusion time, and
D is the diffusion constant (also referred to as diffusion coefficient or diffusivity) and has units of cm2/sec.
The above equation is called Fick’s First law of diffusion and states that the local rate of transfer (local diffusion rate) of solute per
unit area per unit time is proportional to the concentration gradient of the solute, and defines the
proportionality constant as the diffusion constant of the solute. The negative sign appears due to opposite direction of matter
flow and concentration gradient. That is, the matter flows in the direction of decreasing solute concentration.
• Ion implantation is an alternative to diffusion process which changes the physical and electronic properties of a material
by forcibly embedding different types of ions into the material.
• In diffusion process the transistor dimensions is not accurately controlled as the quantity of doping and the depth of
doping is not quite controllable. The constant miniaturization of device dimensions in integrated circuit needs precised
control on transistor dimensions.
• Ion implantation is a very prevalent process for VLSI because it arrange for more precise control of dopants (as compared
to diffusion).
• The main benefits over the diffusion are low temperature, more precise control and reproducibility of impurity doping,
and shallow implant. However, owing to high-energy bombardment causing damaged crystal lattice, Rapid thermal
annealing (RTA) at 400°C to 500°C is required to allow the implanted atom to stay at the right substitutional site, to repair
crystal damage, and drive-in the implanted atom.
• Ion implantation permits introduction of the dopant in silicon that is controllable, reproducible and free from undesirable
side effects.
 ION IMPLANTER

A schematic of an ion implanter is shown in figure. Basically, the ion implant system consists of several systems, which are gas
system, electrical system, vacuum system, control system, and beam line system. These systems will be discussed in details in
the following sub-sections.
1 Gas System
The basic requirement of an ion implanter is the source of ion of adequately high energy. Either a solid source is vaporized or
gas source is conventionally used to delivery material for the ion implanter. Arsine, phosphine, diborane, and boron
trifluoride (BF3) are gas sources and phosphorus pentoxide (P2O5) is a solid. The common gas sources are extremely toxic and
have been used in dilute mixture 15% in hydrogen gas in high pressure more than 400 psi cylinder. Owing to safety concern,
solid sources of elemental boron, arsenic or phosphorus are at time preferred. The main benefit of solid is that it can
be evaporated and implanted. New gas such as zeolite matrix which acts as a molecular sieve to absorb and store gas in
cylinder below atmospheric pressure reduces the risk of release and explosion.
2 Electrical System
High voltage and current electrical system is required for ion implanter. High voltage DC power is needed to accelerate ion.
Up to 200 kV DC power supply system is equipped in an implanter. The ion in the ion source is generated
either a hot filament or RF plasma system. The hot filament requires large
current and a few thousand volt bias power supply, whereas the RF ion source system needs a thousand watt of RF power.
The analyzer magnet needs a high
current to generate the magnetic field strong enough to deflect ion trajectory
and helps to select right ions and created ultra-pure ion beam.
3 Vacuum System
The beam line must be in high vacuum condition to minimize collision between energetic ions with neutral gas molecules
along the ion trajectory. Collision can cause ion scattering loss and creation of unwanted ion species for ion implantation. The
vacuum requirement is 10–7 torr for beam line system. The high vacuum requirement can be achieved by combining the
cryo-pump, turbo pump, and dry pump.
The dangerous gases are used in ion implantation. Thus, the exhaust of the vacuum system of ion implanter must be
separated from the exhaust of other systems. The exhaust gas needs to go through a burn box and a scrubber before it can
be released into the atmosphere. In the burn box, the combustible and
4 Control System
The ion implanter needs to precisely control the ion beam energy, current, and ion species. The implanter needs to control the
mechanical parts such the robot for wafer loading and unloading, and control wafer movement in order to achieve uniform
implantation across the wafer. The throttle valves are controlled according to the pressure setting point to maintain system
pressure.
5 Beam Line System
The ion beam line system is the most important part of an ion implanter. It consists of an ion source, extraction electrodes,
mass analyzer, post acceleration, plasma flooding system, and end analyzer.
5.1 Ion Source
Dopant ion is generated from ion source through ionization discharge of the atom or molecule of dopant vapor or gaseous
dopant chemical compound. The hot filament ion source is one of the most commonly used ion source. The thermal electron
hot filament is accelerated by the arc power supply to attain energy high enough to dissociate and ionize dopant gas molecule
or dopant atom. Magnetic field in the ion source forces the electron into gyro-motion, which helps electron to travel longer
distance and increase the probability of its collision with dopant molecule to generate more dopant ions. Other types of ion
source are RF ion source and microwave ion source. The RF ion source uses inductive coupling of the RF power to ionize the
dopant ions. The microwave ion source uses electron cyclotron resonance to generate plasma and ionized dopant ions.
5.2 Extraction
An extraction electrode with negative bias draws the positive ion out from the plasma in the ion source and accelerates it to
adequately high 50 keV energy. It is a requirement for ion to attain high energy before the analyzer magnetic field
can select the right type of ion species. When the dopant ions accelerate toward the extraction electrode, some of the ions pass
through the slit and continue to travel along the beam line. Dome hit the extraction electrode surface, which generates X-ray
and excites some secondary electrons. A suppression electrode with sufficiently lower electrical potential up to 10 kV than the
extraction electrode is used to prevent these electrons being accelerated back to the ion source that would cause damage. All
electrodes are shaped with a narrow slit through which ions are extracted as a collimated ion flux forming an ion beam.