Week 5 Review

Week 5
▪ Registers
▪ Counters
▪ Basics of state machines
▪ How to design state machines

Inputs State Output

Logic Logic

Flip-
Flops Outputs
 Registers
▪ An n-bit register: a bank of n flip-flops that share a
common clock.
▪ Registers store a multi-bit value.

D0 Q D1 Q D2 Q D15 Q
…
Q Q Q Q

Clk

▪ All bits written at the same time.

▪ Key building block of sequential systems and CPUs.
Load registers
D0 D1 D2 D3

D Q D Q D Q D Q
EN EN EN EN
Q Q Q Q
Write
Clk

▪ Write value in parallel

▪ Write-enable (write) signal controls if writing
or not.
Shift Registers
▪ A series of D flip-flops where output of flip-
flop i is connected to input of i+1
Sin D0 Q D1 Q D2 Q D15 Q

Q Q Q Q

Clk

▪ Load bits one bit at a time.

▪ Or implement parallel load.
▪ Useful to save space or when we want to shift.
Counters
▪ Basic idea…

one bit…
two bit…
three bits…
Counters
▪ Basic idea…

n
n
adder register
n
…00001
Clk
 Ripple Counter (async!)
1
Q0 Q1 Q2 Q3

T Q T Q T Q T Q

Q Q Q Q

C
Q0
Q1
Q2
Q3
 Synchronous Counter
Write

T Q T Q
T Q T Q Q2 Q3
Q0 Q1

Q Q
Q Q

Clk

▪ This is a synchronous counter, with a slight

delay.
Counters with Load
Load
Write
R0 R1

1 1
D Q 0 D Q
0

Q Q

Clk
Clear

▪ Counter with parallel load, write, and clear

(reset) inputs.
▪ Useful for countdowns and more.
Question
We want to build a change machine
▪ We can add either $0.05 or $0.10 at a time
▪ We want to keep track of the current amount
in the machine
▪ We can hold a maximum of $0.50
▪ Draw the state diagram
 For now, ignore the possibility of going over $0.50
Question Zero
5¢
Five
10¢ 5¢ 10¢
5¢
▪ How many flip- Ten
5¢
Fifteen
10¢ 10¢
flops would you 5¢
Twenty Twenty-Five
need to implement 5¢
10¢ 10¢
the following finite 5¢
Thirty Thirty-Five
state machine 10¢ 5¢ 10¢
(FSM)? Forty
5¢
Forty-Five
 11 states 5¢
10¢
 # flip-flops =
log2 (# of states) Fifty

 # flip-flops = 4
 Question Zero
5¢
Five
10¢ 5¢ 10¢
5¢
▪ Dealing with too Ten Fifteen
5¢
much money means 10¢
5¢
10¢

when we don’t accept Twenty Twenty-Five

5¢
any more coins. 10¢ 10¢
5¢
▪ New outputs tell Thirty
5¢
Thirty-Five
10¢ 10¢
machine what to do: 5¢
 A = 1 → reject 5c Forty Forty-Five
5¢
10¢
 B = 1 → reject 10c
Fifty
▪ Complete the state
machine for this
addition
 Question Zero
AB=00
5¢ Five
AB=00
10¢ 5¢ 10¢
Ten 5¢ Fifteen
▪ Dealing with too AB=00 AB=00
5¢
much money means 10¢
5¢
10¢
Twenty Twenty-Five
when we don’t accept AB=00 AB=00
5¢
any more coins. 10¢ 10¢
Thirty 5¢ Thirty-Five
▪ New outputs tell AB=00
5¢
AB=00
10¢ 10¢
machine what to do: 5¢
Forty Forty-Five
 A = 1 → reject 5c AB=00 AB=01
5¢
10¢
 B = 1 → reject 10c
Fifty
▪ Complete the state AB=11 10¢

machine for this 5¢,10¢

addition
Question: Barcode Reader
▪ When scanning UPC
barcodes, the laser
scanner looks for black
and white bars that
indicate the start of the code.
▪ If black is read as a 1 and white is read as a 0,
the start of the code has a 1010 pattern.
 Create a state machine that detects this pattern
Question: Barcode Reader
▪ Build a machine that
detects a 1010 pattern.

Input 0 0 0 1 0 1 0 0 0 0

Output 0 0 0 1 0 0 0

Input 0 0 0 1 0 1 0 1 0 1 0 0 0 0

Input 1 0 1 1 0 1 0 1 0
 Question: Barcode Reader
▪ Build a machine that
detects a 1010 pattern.
▪ We know how to build
a pattern recognizer:
 One state for each possible sequence of 4 bits.
 In other words, one FF per bit:
F0 last seen bit, F1 the bit before that, F2 for bit seen
before that, and F3.
▪ Can we do better than 4 FFs?
 Question: Barcode Reader
▪ The previous pattern recognizer:
state for each possible sequence of 4 bits.
 It essentially memorized
▪ Do you have another idea?
 Question: Barcode Reader
▪ The previous pattern recognizer:
state for each possible sequence of 4 bits.
 It essentially memorized
▪ Do you have another idea?
 How about a state that shows us where we are in the
pattern?

1 0 1 0

A B C D E
 Step #1: Draw state diagram

1 0 1 0

A
 Step #1: Draw state diagram
0 1
1
A

B 0
1 1
C
0 0
D
1
1 0 1 0 0
E

A B C D E
Step #1: … and outputs
0 1
1
A/0

B/0 0
1 1
C/0
0 0
D/0
1
E/1
0
 Step #2: State Table
Present Next
▪ Write state table with Z State
X Z
State

0 1
1
A/0
0
B/0
1 1
C/0
0 0
D/0
1
E/1
 Step #2: State Table
Present Next
▪ Write state table with Z State
X Z
State
▪ Output Z is determined A 0 0 A
A 1 0 B
by the current state. B 0 0 C
B 1 0 B
 Denotes Moore machine.
C 0 0 A
▪ Next step: allocate flip- C 1 0 D
D 0 0 E
flops values to each state. D 1 0 B
E 0 1 A
 How many flip-flops will
E 1 1 D
we need for 5 states?
 # flip-flops = log(# of states) 

→ We need 3 flipflops
Discussion!
▪ Wait a minute… we built a recognizer before!
▪ We needed 8 states to recognize 3-bit pattern.
▪ Now we need only 5 states for a 4-bit pattern
▪ Why?
0 1
1
A/0
B/0
0
1 1
C/0
0 0
D/0
1
E/1
Discussion!
▪ The 3-bit pattern recognizer is doing more!
 It is memorizing the last 3 bits.
 To recognize another pattern, simply set the output
of the relevant state to one.
 Even multiple patterns by the same machine.
▪ The 4-bit pattern recognizer can only recognize
one specific pattern.
 Different pattern → different state machine.
 To recognize n-bit pattern → need n+1 states.
Step #3: Flip-Flop Assignment
0 1
1 Unsafe!
A (might go through E)
▪ 3 flip-flops
B 0
needed here. 1
1
▪ Assign states C
0 0
carefully though! D
1
▪ Can’t simply do this: E
➢ A = 100 ➢B = 011 0

➢ C = 010 ➢D = 001
➢ E = 000
Why not?
Step #3: Flip-Flop Assignment
0 1
1
A

B 0
▪ Be careful of 1
1
race conditions. C
0 0
▪ Better solution: D
➢ A = 000 ➢B = 001 1
E
➢ C = 011 ➢D = 101 0
➢ E = 100
• Still has race conditions (C→D, C→A), but is safer.
• “Safer” is defined according to output behaviour.
• Sometimes, extra flip-flops are used for extra insurance.
 Step #4: Redraw State Table
Present Next
▪ We can now F2 F1 F0
State
X Z F2 F1 F0
State
construct the K-maps 0 0
A 0 0 0 0 A0 0
0 0
A 0 1 0 0 B0 1
for the state logic 0 0
B 1 0 0 0 C1 1
combinational circuit. 0 0
B 1 1 0 0 B0 1
0 1
C 1 0 0 0 A0 0
 Derive equations for each 0 1
C 1 1 0 1 D0 1
flip-flop value, given the 1 0
D 1 0 0 1 E0 0
1 0
D 1 1 0 0 B0 1
previous values and the
1 0
E 0 0 1 0 A0 0
input X. 1 0
E 0 1 1 1 D0 1
 Three equations total,
plus one more for Z (trivial for Moore machines).
Step 5: Circuit design
▪ Karnaugh map for F2:

F0·X F0·X F0·X F0·X

F2·F1 0 0 0 0

F2·F1 X X 1 0

F2·F1 X X X X

F2·F1 0 1 0 1

F2 = F1X + F2F0X + F2F0X

Step 5: Circuit design
▪ Karnaugh map for F1:

F0·X F0·X F0·X F0·X

F2·F1 0 0 0 1

F2·F1 X X 0 0

F2·F1 X X X X

F2·F1 0 0 0 0

F1 = F2F1F0X
Step 5: Circuit design
▪ Karnaugh map for F0:

F0·X F0·X F0·X F0·X

F2·F1 0 1 1 1

F2·F1 X X 1 0

F2·F1 X X X X

F2·F1 0 1 1 0

F0 = X + F2F1F0
Step 5: Circuit design
▪ Output value Z goes high for state E (100),
so the output expression is:
Z = F2F1F0

▪ Note: All of these expressions would be

different, given different flip-flop
assignments!
 Practice alternate assignments!
 Circuit
Clk
D Q
F0
Q

X
D Q
F1 Z
Q

D Q
F2
Q
 Circuit
Clk
D Q
F0
Q

X
D Q
F1 Z
Q

D Q
F2
Q
 Question: Mouse clicks
▪ Design a state machine
that takes in two signals:
 P is high if the user
is pressing the mouse button.
 M is high if the mouse is being moved.
▪ Based on the inputs, the state indicates
whether the user is clicking, double-clicking,
or dragging the mouse on the screen.
 Hint: you will need more states than that!

36
Question: Mouse clicks
Clicked

Dragging Neutral Released

Double
Clicked

37
 Question: Mouse clicks
10

Clicked
PM = 11 00
01
0X 10 00
1X
Neutral 01
Dragging Released

11 0x 0x

1x
11
Double
Clicked
10

▪ Transitions indicate the values of P and M.

▪ X means this transition happens for both 0 and for 1.
▪ Outputs depend on the state (Moore machine)
▪ Home exercise: build this FSM.
Week 6: Processor
Components
Microprocessors
▪ So far, we’ve been about
making devices, such
such as adders, counters
and registers.
▪ The ultimate goal is to make a
microprocessor, which is a digital device that
processes input, can store values and
produces output, according to a set of on-
board instructions.
Microprocessors
▪ Microprocessors are a
combination of the
units that we’ve
discussed so far:
 Registers to store values.
 Adders and shifters to process data.
 Finite state machines to control the process.
▪ Microprocessors have been the basis of all
computing since the 1970’s, and can be found
in nearly every sort of electronics.
 To get to this

Assembly Language

Processors
Arithmetic Finite State
Logic Units Machines
Devices Flip-flops
Circuits
Gates

Transistors

We build these
The Final Destination
The Final Destination
PCWriteCond
Control PCSource
PCWrite Unit
ALUOp
IorD
ALUSrcB
MemRead
ALUSrcA
MemWrite
RegWrite
MemtoReg
RegDst
IRWrite
Opcode

0
1
Shift left 2 2

Instruction
[31-26] Registers
0 Instruction Read reg 1 0
A
PC

Address [25-21] Zero

Read A 1
1 Instruction Read reg 2 data 1
Memory [20-16]
data ALU ALU
Instruction 0 result Out
Write [15-0]
data Write reg Read B 0
1 data 2
4 1 B
Instruction 2
Memory Register Write data
3
0
Memory 1
data
register Sign
extend Shift left 2
Deconstructing processors
▪ Simpler at a high level:

Controller
Thing

Storage Arithmetic
Thing Thing
The “Arithmetic Thing”
aka: the Arithmetic Logic Unit (ALU)
Arithmetic Logic Unit
▪ The first microprocessor
applications were calculators.
 Remember adders
and subtractors?
 These are part of a larger
structure called the arithmetic
logic unit (ALU).
 You made a simple one for lab 2 and 3!
▪ This larger structure is responsible for the
processing of all data values in a basic CPU.
 ALU inputs A B

▪ The ALU performs all of

the arithmetic operations S, Cin VCNZ
covered in this course so
far, and logical operations G
as well (AND, OR, NOT, etc.)
 Input S represents select bits (in this case, S2 S1 & S0)
that specify which operation to perform.
 For example: S2 is a mode select bit, indicating
whether the ALU is in arithmetic or logic mode
 The carry-in bit Cin is used in operations such as
incrementing an input value or the overall result.
ALU outputs A B

▪ In addition to the input

signals, there are output S, Cin VCNZ
signals V, C, N & Z which
indicate special conditions G
in the arithmetic result:
 V: overflow condition
 The result of the operation could not be stored in
the n bits of G, meaning that the result is incorrect.
 C: carry-out bit
 N: Negative indicator
 Z: Zero-condition indicator (result is zero)
The “A” of ALU
▪ To understand how the ALU does all of these
operations, let’s start with the arithmetic side.
▪ Fundamentally, this side is made of an adder /
subtractor unit, which we’ve seen already:
Y3 Y2 Y1 Y0 Sub

X3 X2 X1 X0
Cout C3 C2 C1 Cin
FA FA FA FA

S3 S2 S1 S0
 Arithmetic components
Cin

n
A X n
G
n n-bit G = X + Y + Cin
n parallel
B
Y
B input Y adder
S0 logic
S1

Cout

▪ In addition to addition and subtraction, many more

operations can be performed by manipulating what
is added to input A, as shown in the diagram above.
Arithmetic operations
▪ If the B input logic sends B straight through?
 Y = B → Result of addition operation is G = A+B
▪ What if B was replaced by all-ones instead?
 Y = 111…1 → Result of addition operation: G = A-1
▪ What if B was replaced by B?
 Y = B → Result of addition operation: G = A-B-1
▪ And what if B was replaced by all zeroes?
 Y = 000…0 → Result is: G = A.
 We’ll see later: this is useful for moving values between
registers, and for loading values into registers.
→ Instead of a Sub signal, the operation you want is
signaled using the select bits S0 & S1.
Operation selection G = A + Y
Select
bits Y
Result Operation
S1 S0
Input

0 0 All 0s G =A Transfer
0 1 B G = A+B Addition
1 0 B G = A+B Subtraction - 1
1 1 All 1s G = A-1 Decrement

▪ This is a good start! But something is missing…

▪ Wait, what about the carry-in bit?
Full operation selection
Select Input Operation
S1 S0 Y Cin=0 Cin=1
0 0 All 0s G = A (transfer) G = A+1 (increment)
0 1 B G = A+B (add) G = A+B+1
1 0 B G = A+B G = A+B+1 (subtract)
1 1 All 1s G = A-1 (decrement) G = A (transfer)

▪ Based on the values on the select bits and the

carry bit, we can perform any number of basic
arithmetic operations by manipulating what
value is added to A.
Full operation selection
Select Input Operation
S1 S0 Y Cin=0 Cin=1
0 0 All 0s G = A (transfer) G = A+1 (increment)
0 1 B G = A+B (add) G = A+B+1
1 0 B G = A+B G = A+B+1 (subtract)
1 1 All 1s G = A-1 (decrement) G = A (transfer)

▪ Based on the values on the select bits and the

carry bit, we can perform any number of basic
arithmetic operations by manipulating what
value is added to A.
 The “L” of ALU
▪ We also want a circuit
that can perform S0
S1
logical operations,
in addition to A
G
0 4-to-1
arithmetic ones. B mux
1
▪ How do we tell
which operation 2

to perform? 3

 Another select bit!

▪ If S2 = 1, then logic circuit block is activated.
▪ Multiplexer is used to determine which block
(logical or arithmetic) goes to the output.
Single ALU Stage
Ci+1
Ci Ci V
Ai Ai N
Z
Bi Bi Arithmetic
Gi
circuit
S0 S0
S1 S1 0
Gi
1

Ai
Bi
Logic G
i
S0 circuit
S1

S2
ALU block diagram
▪ In addition to data inputs and outputs, this circuit
also has:
 outputs indicating the different conditions,
 inputs specifying the operation to perform (similar to Sub).

A0
A1
Data input A ... … G0
An-1 G1
… ... Data output G
B0 Gn-1
B1
Data input B ... … n-bit
Bn-1 ALU Cout Carry output
Carry input Cin V Overflow indicator
S0 N Negative indicator
Operation & S1 Z Zero indicator
Mode select S2
What about multiplication?
▪ Multiplication (and division) operations are
more complicated than other arithmetic
(plus, minus) or logical (AND, OR) operations.
▪ Three major ways that multiplication can be
implemented in circuitry:
 Layered rows of adder units.
 An adder/shifter circuit with accumulator.
 Booth’s Algorithm
Multiplication
▪ Revisiting grade 3 math…

123 12 3
x 456 x 456 123
1368 x 456
1368
912
1 2 3 1 23 456
x 456 x 456
56088
1368 1368
912 912
456
Binary Multiplication
5*6 (unsigned)
▪ And now, in binary…

101 10 1 101
x 110 x 110 x 110
110 110
000
1 0 1 1 01 110
x 110 x 110 11110
110 110
000 000
110 Result: 30
Binary Multiplication
▪ Or seen another way….

101 101
x 110 x 11 0 101
000 x 110
000
101
101 101 101
x 1 1 0 x 1 10
11110
000 000
101 101
101
Binary Multiplication
Implementation
▪ Implementing this
in circuitry involves
the summation of
several AND terms.
 AND gates combine
input signals.
 Adders combine the
outputs of the AND
gates.
 Multiplication
▪ This implementation
results in an array of
adder circuits to make
the multiplier circuit.
▪ This can get a little
expensive as the size
of the operands grows.
 N-bit numbers → O(1) clock cycles, but O(N2) size.
▪ Is there an alternative to this circuit?
Accumulator circuits
▪ What if you could perform each stage of the
multiplication operation, one after the other?
 This circuit would only
Register Y
need a single row of
adders and a couple Register X cout
Shift Left 1
of shift registers.
1 x n AND
 How wide does
register R have
Shift Left 1 Adder
to be?
 Is there a simpler
Register R
way to do this?