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manojkumarsKONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY
(AUTONOMOUS)
NAMAKKAL- TRICHY MAIN ROAD, THOTTIAM
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
EC8791-EMBEDDED AND
REAL TIME SYSTEMS
Course Material
Regulation-2017
IV ECE/VII SEM
UNIT I
INTRODUCTION TO EMBEDDED SYSTEM DESIGN
Complex systems and micro processors– Embedded system design
process –Design example: Model train controller-Design
methodologies- Design flows - Requirement Analysis – Specifications-
System analysis and architecture design – Quality Assurance
techniques - Designing with computing platforms – consumer
electronics architecture – platform-level performance analysis.
Introduction-Embedded Systems
An Embedded system is an electronic system that has a software and is
embedded in computer hardware.
It is a system which has collection of components used to execute a task
according to a program or commands given to it.
Examples →Microwave ovens, Washing machine, Telephone answering
machine system, Elevator controller system, Printers, Automobiles,
Cameras, etc.
Components of Embedded system
Microprocessor
Memory Unit(RAM,ROM)
Input unit(Keyboard,mouse,scanner)
Output unit(pinters,video monitor)
Networking unit(Ethernet card)
I/O units(modem)
Real Time Operating System-RTOS
Real-Time Operating System (RTOS) is an operating system (OS)
intended to serve real-time applications that process data as it comes
in, typically without buffer delays.
It schedules their working and execution by following a plan to control
the latencies and to meet the dead lines.
Modeling and evaluation of a real-time scheduling system concern is
on the analysis of the algorithm capability to meet a process deadline.
A deadline is defined as the time required for a task to be processed.
Classification of Embedded system
1. Small scale Embedded system→(8/16bit microcontroller)
2. Medium Scale Embedded system→ →(16/32bit microcontroller,
more tools like simulator, debugger)
3. Sophisticated Embedded system →(configurable processor and PAL)
Embedded designer-skills
Designer has a knowledge in the followings field,
Microcontrollers, Data comm., motors, sensors, measurements ,C
programming, RTOS programming.
1) COMPLEX SYSTEMS AND MICROPROCESSORS
Embedded(+)computer system
Embedded system is a complex system
It is any device that includes a programmable computer but is not
itself intended to be a general-purpose computer.
History of Embedded computer system
Computers have been embedded into applications since the earliest days of
computing.
In 1940s and 1950s→Whirlwind, designed a first computer to support real-time
operation for controlling an aircraft simulator.
In 1970s→ The first microprocessor( Intel 4004) was designed for an embedded
application (Calculator), provided basic arithmetic functions.
In 1972s→ The first handheld calculator (HP-35 ) was to perform
transcendental functions , so it used several chips to implement the CPU,
rather than a single-chip microprocessor.
Designer faced critical problems to design a digital circuits to perform
operations like trigonometric functions using calculator.
But ,Automobile designers started making use of the microprocessor for to
control the engine by determining when spark plugs fire, controlling the
fuel/air mixture
Levels of Microprocessor
1. 8-bit microcontroller→ for low-cost applications and includes on-board
memory and I/O devices.
2. 16-bit microcontroller → used for more sophisticated applications that may
require either longer word lengths or off-chip I/O and memory.
3. 32-bit RISC microprocessor →offers very high performance for
computation-intensive applications.
Microprocessor Uses/Applications
Microwave oven has at least one microprocessor to control oven operation
Thermostat systems, which change the temperature level at various times during
the day
The modern camera is a prime example of the powerful features that can be
added under microprocessor control.
Digital television makes extensive use of embedded processors.
Embedded Computing Applications
Ex→BMW 850i Brake and Stability Control System
The BMW 850i was introduced with a sophisticated system for controlling the
wheels of the car.
Which uses An antilock brake system (ABS) and An automatic stability
control (ASC +T) system.
1. An antilock brake system (ABS)
Reduces skidding by pumping the brakes.
It is used to temporarily release the brake on a wheel when it rotates
too slowly—when a wheel stops turning, the car starts skidding and
becomes hard to control.
It sits between the hydraulic pump, which provides power to the
brakes.
It uses sensors on each wheel to measure the speed of the wheel.
The wheel speeds are used by the ABS system to determine how to vary
the hydraulic fluid pressure to prevent the wheels from skidding.
2. An automatic stability control (ASC +T) system
It is used to control the engine power and the brake to improve the car’s
stability during maneuvers.
It controls four different systems: throttle, ignition timing, differential
brake, and (on automatic transmission cars) gear shifting.
It can be turned off by the driver, which can be important when
operating with tire snow chains.
It has control unit has two microprocessors , one of which concentrates
on logic-relevant components and the other on performance-specific
components.
The ABS and ASC+ T must clearly communicate because the ASC+ T
interacts with the brake system.
Characteristics of Embedded Computing
Applications
1. Complex algorithms-The microprocessor that controls an automobile engine
must perform complicated filtering functions to optimize the performance of
the car while minimizing pollution and fuel utilization.
2. User interface-The moving maps in Global Positioning System (GPS)
navigation are good examples of user interfaces.
3. Real time-Embedded computing systems have to perform in real time—if the
data is not ready by a certain deadline, the system breaks. In some cases,
failure to meet a deadline or missing a deadline does not create safety
problems but does create unhappy customers
4. Multirate-Multimedia applications are examples of multirate behavior.
The audio and video portions of a multimedia stream run at very different
rates, but they must remain closely synchronized. Failure to meet a deadline
on either the audio or video portions spoils the perception of the entire
presentation.
5. Manufacturing cost- It is depends on the type of microprocessor used, the
amount of memory required, and the types of I/O devices.
6. Power and energy-Power consumption directly affects the cost of the
hardware, since a larger power supply may be necessary.
7. Energy consumption →affects battery life, which is important in many
applications, as well as heat consumption, which can be important even in
desktop applications.
Why Use Microprocessors?
Microprocessors are a very efficient way to implement digital systems.
It make it easier to design families of products with various feature at
different price points
It can be extended to provide new features to keep up with rapidly
changing markets.
It executes program very efficiently
It make their CPU run very fast
Implementing several function on a single processor
Why not use PCs for all embedded
computing?
Real time performance is very less in PC because of
different architecture.
It increases the complexity and price of components due to
broad mix of computing requirements.
Challenges in Embedded Computing System Design
1. How much hardware do we need?
To meet performance deadlines and manufacturing cost constraints, the choice of
Hardware is important.
Too much hardware and it becomes too expensive.
2. How do we meet deadlines?
To speed up the hardware so that the program runs faster. But the system more
expensive.
It is also entirely possible that increasing the CPU clock rate may not make
enough difference to execution time, since the program’s speed may be limited by
the memory system.
3. How do we minimize power consumption?
In battery-powered applications, power consumption is extremely important.
In non-battery applications, excessive power consumption can increase heat
dissipation.
Careful design is required to slow down the noncritical parts of the machine for
power consumption while still meeting necessary performance goals.
4) How do we design for upgradability?
The hardware platform may be used to add features by changing software.
4.1) Complex testing: Run a real machine in order to generate the proper data.
Testing of an embedded computer from the machine in which it is embedded.
4.2) Limited observability and controllability→No keyboard and screens, in real-
time applications we may not be able to easily stop the system to see what is
going on inside and to affect the system’s operation.
4.3) Restricted development environments:
We generally compile code on one type of machine, such as a PC, and
download it onto the embedded system.
To debug the code, we must usually rely on programs that run on the PC or
workstation and then look inside the embedded system.
Performance in Embedded Computing
Embedded system designers have to set their goal —their program must meet its
deadline.
Performance Analysis
1. CPU: The CPU clearly influences the behavior of the program, particularly when
the CPU is a pipelined processor with a cache.
2. Platform: The platform includes the bus and I/O devices. The platform
components that surround the CPU are responsible for feeding the CPU and can
dramatically affect its performance.
3. Program: Programs are very large and the CPU sees only a small window of the
program at a time. We must consider the structure of the entire program to
determine its overall behavior.
4. Task: We generally run several programs simultaneously on a CPU, creating a
multitasking system. The tasks interact with each other in ways that have profound
implications for performance.
5. Multiprocessor: Many embedded systems have more than one processor—they
may include multiple programmable CPUs as well as accelerators. Once again, the
interaction between these processors adds yet more complexity to the analysis of
overall system performance.
2)EMBEDDED SYSTEM DESIGN PROCESS
Design process has two objectives as follows.
1. It will give us an introduction to the various steps in embedded system
design.
2. Design methodology
I. Design to ensure that we have done everything we need to do, such as
optimizing performance or performing functional tests.
II. It allows us to develop computer-aided design tools.
III. A design methodology makes it much easier for members of a design
team to communicate.
Levels of abstraction in the design process.
1)Requirements
•It can be classified in to functional or nonfunctional
1.1)Functional Requirements
•Gather an informal description from the customers.
•Refine the requirements into a specification that contains
enough information to design the system architecture.
•Ex:Sample Requirements form
•Name→Giving a name to the project
Purpose→Brief one- or two-line description of what the system
is supposed to do.
•Inputs& Outputs →Analog electronic signals? Digital data?
Mechanical inputs?
•Functions→ detailed description of what the system does
Performance→ computations must be performed within a
certain time frame
•Manufacturing cost→ cost of the hardware components.
Power→ how much power the system can consume
Physical size and weight→ indication of the physical size
of the system
1.2) Non-Functional Requirements
Performance→ depends upon approximate time to perform a user-
level function and also operation must be completed within deadline.
Cost→Manufacturing cost includes the cost of components and
assembly.
• Nonrecurring engineering (NRE) costs include the personnel and other
costs of designing the
system
Physical Size and Weight→The final system can vary depending upon
the application.
Power Consumption→Power can be specified in the requirements stage
in terms of battery life.
2)SPECIFICATION
The specification must be carefully written so that it accurately reflects the
customer’s requirements.
It can be clearly followed during design.
3) Architecture Design
The architecture is a plan for the overall structure of the system.
It is in the form block diagram that shows a major operation and data flow.
4) Designing Hardware and Software Components
The architectural description tells us what components we need include both
hardware—FPGAs, boards & software modules
5)System Integration
Only after the components are built, putting them together and seeing a
working system.
Bugs are found during system integration, and good planning can help us find
the bugs quickly.
Embedded system Design Example
GPS moving map
Design Process Steps
1. Requirements analysis of a GPS moving map
The moving map is a handheld device that displays for the user a map of the
terrain around the user’s current position.
The map display changes as the user and the map device change position.
The moving map obtains its position from the GPS, a satellite-based navigation
system.
Name GPS moving map
Purpose Consumer-grade moving map for driving use
Inputs Power button, two control buttons
Outputs Back-lit LCD display 400 600
Functions Uses 5-receiver GPS system; three user-selectable
resolutions;always displays current latitude and
longitude
Performance Updates screen within 0.25 seconds upon movement
Manufacturing cost $30
Power 100mW
Physical size and No more than 2”X 6, ” 12 ounces
weight
Design Process Steps
2) Functionality→This system is designed for highway driving and similar uses.
The system should show major roads and other landmarks available in
standard topographic databases.
3)User interface→The screen should have at least 400X600 pixel resolution. The
device should be controlled by no more than 3 buttons.
→A menu system should pop up on the screen when buttons are
pressed to allow the user to make selections to control the system.
4)Performance→ The map should scroll smoothly.
→Upon power-up, a display should take no more than 1sec to appear.
→The system should be able to verify its position and display the
current map within 15 s.
5)Cost→ The selling cost of the unit should be no more than $100.
6)Physical size and weight→The device should fit comfortably in the palm of the
hand.
7) Power consumption→ The device run for at least 8 hrs on 4 AA batteries.
8) specification
1. Data received from the GPS satellite constellation.
2. Map data.
3. User interface.
4. Operations that must be performed to satisfy customer requests.
5. Background actions required to keep the system running, such as
operating the GPS receiver.
Block Diagram
Hardware architecture
•one central CPU surrounded by
memory and I/O devices.
• It used two memories: a frame buffer
for the pixels to be displayed and a
separate program/data memory for
general use by the CPU.
Software architecture
•Timer to control when we read the buttons
on the user interface and render data onto
the screen.
•Units in the software block diagram will be
executed in the hardware block diagram and
when operations will be performed in time.
3)FORMALISM FOR SYSTEM DESIGN
UML(Unified Modeling Language) is an object-oriented modeling language→
used to capture all these design tasks.
It encourages the design to be described as a number of interacting objects,
rather than blocks of code.
objects will correspond to real pieces of software or hardware in the system.
It allows a system to be described in a way that closely models real-world
objects and their interactions.
Classification of descriptor
3.1)Structural Description
3.2)Behavioral Description
3.1)Structural Description
It gives basic components of the system and designers can learn how to
describe these components in terms of object.
3.1.1) OBJECT in UML NOTATION
An object includes a set of attributes that define its internal state.
An object describing a display (CRT screen) is shown in UML notation in
Figure.
The object has a unique name, and a member of a class.
The name is underlined to show that this is a description of an object and not
of a class.
The text in the folded-corner page icon is a note.
An object in UML notation
3.1.2)CLASS IN UML NOTATION
All objects derived from the same
class have the same characteristics,
but attributes may have different
values.
It also defines the operations that
determine how the object interacts
with the rest of the world.
It defines both the interface for a
particular type of object and that
object’s implementation.
Relationships between objects and classes
1. Association →occurs between objects that communicate with each other but
have no ownership relationship between them.
2. Aggregation→ describes a complex object made of smaller objects.
3. Composition →It is a type of aggregation in which the owner does not allow
access to the component objects.
4. Generalization →allows us to define one class in terms of another.
Derived classes as a form of generalization in UML
•A derived class is defined to include all the
attributes of its base class.
• Display is the base class and BW display and
color map display are the two derived classes.
•BW display represents black and white display.
Multiple inheritance in UML
•UML allows to define multiple inheritance, in which a class is derived from more
than one base class.
•Multimedia display class by combining the Display class with a Speaker class for
sound.
•The derived class inherits all the attributes and operations of both its base classes,
Display and Speaker.
•
Links and Association
A link describes a relationship between objects and association is to
link as class is to object.
The association is drawn as a line between the two labeled with the
name of the association, namely, contains.
3.2)Behavioral Description
Behavior of an operation is specified by a state machine.
These state machines will not rely on the operation of a clock.
Changes from one state to another are triggered by the occurrence of
events.
The event may generated from the outside or inside of the system.
Signal, call, and time-out events in UML.
State
Signal →is an asynchronous occurrence.
It is defined in UML by an object that is labeled as a <<signal>>.
Signal may have parameters that are passed to the signal’s receiver.
Call event→ follows the model of a procedure call in a programming
language.
Time-out event→ causes the machine to leave a state after a certain
amount of time.
The label tm(time-value) on the edge gives the amount of time after
which the transition occurs.
State Machine specification in UML
The start and stop states are special states which organize the flow of the state
machine.
The states in the state machine represent different operations.
Conditional transitions out of states based on inputs or results of some
computation.
An unconditional transition to the next state.
Sequence diagram in UML
Sequence diagram is similar to a hardware timing diagram, although the time
flows vertically in a sequence diagram, whereas time typically flows horizontally
in a timing diagram.
It is designed to show particular choice of events—it is not convenient for
showing a number of mutually exclusive possibilities.
4) Design:Model Train Controller
In order to learn how to use UML to model systems→ specify a simple system
(Ex: model train controller)
The user sends messages to the train with a control box attached to the tracks.
The control box may have controls such as a throttle, emergency stop button,
and so on.
The train Rx its electrical power from the two rails of the track.
CONSOLE
Each packet includes an address so that the console can control several trains
on the same track.
The packet also includes an error correction code (ECC) to guard against
transmission errors.
This is a one-way communication system—the model train cannot send
commands back to the user.
Model Train Control system
REQUIREMENTS
The console shall be able to control up to eight trains on a single track.
The speed of each train controllable by a throttle to at least 63 different
levels in each direction (forward and reverse).
There shall be an inertia control→ to adjust the speed of train.
There shall be an emergency stop button.
An error detection scheme will be used to transmit messages.
Requirements:Chart Format
Name Model train controller
Purpose Control speed of up to eight model trains
Inputs Throttle, inertia setting, emergency stop, train
number
Outputs Train control signals
Functions Set engine speed based upon inertia settings;
respond
Performance Can update train speed at least 10 times per second
Manufacturing cost $50
Power 10W
Physical size and weight Console should be comfortable for two
hands,approximatesize of standard
keyboard;
weight 2 pounds
Digital Command Control (DCC)
Standard S-9.1→ how bits are encoded on the rails for transmission.
Standard S-9.2→ defines the packets that carry information.
The signal encoding system should not interfere with power transmission
Data signal should not change the DC value of the rails.
Bits are encoded in the time between transitions.
Bit 0 is at least 100 s while bit 1 is nominally 58 s.
Packet Formation in DCC
The basic packet format is given by
P → preamble, which is a sequence of at least 10 1 bits.
S → packet start bit. It is a 0 bit.
A →address is 8 bits long. The addresses 00000000, 11111110, and 11111111 are
reserved.
s→ data byte start bit, which, like the packet start bit, is a 0.
D →data byte includes 8 bits. A data byte may contain an address, instruction,
data, or error correction information.
E →packet end bit, which is a 1 bit.
Baseline packet
The minimum packet that must be accepted by all DCC implementations.
It has three data bytes.
Address data byte→ gives the intended receiver of the packet
Instruction data byte→ provides a basic instruction
Error correction data byte→ is used to detect and correct transmission errors.
Date byte
Bits 0–3→ provide a 4-bit speed value.
Bit 4 →has an additional speed bit.
Bit 5 →gives direction, with 1 for forward and 0 for reverse.
Bits 6-7 are set at 01 → provides speed and direction.
Conceptual Specification
Conceptual specification allows us to understand the system a little better.
A train control system turns commands into packets.
A command comes from the command unit while a packet is transmitted over the
rails.
Commands and packets may not be generated in a 1-to-1 ratio
UML collaboration diagram for train
controller system
The command unit and receiver are each represented by objects.
The command unit sends a sequence of packets to the train’s receiver, as
illustrated by the arrow messages as 1..n.
Those messages are of course carried over the track.
UML class diagram for the train controller
Basic characteristics of UML classes
Console class→ describes the command unit’s front panel, which contains
the analog knobs and hardware to interface to the digital parts of the system.
Formatter class→ includes behaviors that know how to read the panel knobs and creates a
bit stream for the required message.
Transmitter class →interfaces to analog electronics to send the message along the track
Knobs*→ describes the actual analog knobs, buttons, and levers on the control panel.
Sender*→ describes the analog electronics that send bits along the track.
Receiver class→ knows how to turn the analog signals on the track into digital form.
Controller class→ includes behaviors that interpret the commands and figures out how to
control the motor.
Motor interface class→ defines how to generate the analog signals required to control the
motor.
Detector* →detects analog signals on the track and converts them into digital form.
Pulser* →turns digital commands into the analog signals required to control the motor
speed.
Detailed Specification
•The Panel has three knobs
• train number (which train is currently
being controlled).
•speed (which can be positive or negative),
and inertia.
•It also has one button for emergency-
stop.
•When we change the train number
setting, to reset the other controls to the
proper values for that train.
• so that the previous train’s control
settings are not used to change the current
train’s settings.
Class diagram for panel
•The Panel class defines a behavior for each of the controls on the panel.
• The new-settings behavior uses the set-knobs behavior of the Knobs*
•Change the knobs settings whenever the train number setting is changed.
•The Motor-interface defines an attribute for speed that can be set by other
classes.
.
Class diagram for the Transmitter and Receiver
•They provide the software interface to the physical devices that send
and receive bits along the track.
•The Transmitter provides a behavior message that can be sent
• The Receiver class provides a read-cmd behavior to read a message off
the tracks.
Class diagram for Formatter
The formatter holds the current control settings for all of the trains.
The send-command serves as the interface to the transmitter.
The operate function performs the basic actions for the object.
The panel-active behavior returns true whenever the panel’s values do not
correspond to the current values
Class diagram for Controller
•The Controller’s operate behavior must execute several behaviors to
determine the nature of the message.
•Once the speed command has been parsed, it must send a sequence of
commands to the motor to smoothly change the train’s speed.
Sequences diagram for transmitting a
control input
Sequence diagram
specify the interface
between more than one
classes.
Its detailed operations
and what ways its going
to operate
5)DESIGN METHODOLOGIES
Design of Embedded system is not an easy task.
The main goal of a design process is to create a product that does something useful.
Typical specifications for a product are functionality , manufacturing cost, performance and
power consumption.
Design process has several important goals as follows
Time-to-market
Customers always want new features.
The product that comes out first can win the market, even setting customer preferences for
future generations of the product.
Design cost
Consumer products are very cost sensitive, and it is distinct from manufacturing cost.
Design costs can dominate manufacturing costs.
Design costs can also be important for high-volume consumer devices when time-to-market
pressures cause teams to swell in size.
Quality
Customers want their products fast and cheap.
Correctness, reliability, and usability must be explicitly addressed from the beginning of the
design job to obtain a high-quality product at the end
5.2)Design flows
A design flow is a sequence of steps to be followed during a design.
Some of the steps can be performed by tools and other steps can be performed by hand.
Types of Software development models
1. Waterfall model
2. Spiral model
3. Successive refinement development model
4. Hierarchical design model
5.2.1)Waterfall model
The waterfall development model consists of five major phases.
Requirements analysis→ determines the basic characteristics of the system.
Architecture design→It decomposes the functionality into major components
Coding→It implements the pieces and integrates them.
Testing→It detemines bugs.
Maintenance→ It entails deployment in the field, bug fixes,and upgrades.
The waterfall model makes work flow information from higher levels of abstraction to
more detailed design steps.
5.2.2)Spiral model
The spiral model assumes that several versions of the
system will be built.
Each level of design, the designers go through
requirements,construction,and testing phases.
At later stages when more complete versions of the
system are constructed.
Each phase requires more work, widening the design
spiral.
The first cycles at the top of the spiral are very small
and short.
The final cycles at the spiral’s bottom add detail
learned from the earlier cycles of the spiral.
The spiral model is more realistic than the waterfall
model because multiple iterations needed to
complete a design.
But too many spirals may take long time required for
design.
5.2.3)Successive refinement design model
In this approach, the system is built several times.
A first system is used as a rough prototype.
Embedded computing systems are involved the design of hardware/software project.
Front-end activities→ are specification and architecture and also includes hardware and
software aspects.
Back-end activities → includes integration and testing.
Middle activities→includes hardware and software development.
5.2.4)Hierarchical design flow
Many complex embedded systems are built of smaller designs.
The complete system may require the design of significant software
components.
It has many levels of abstraction to design flows for individual components.
The implementation phase contains a complete flow from specification
through testing.
Each flow will probably be handled by separate people or teams.
The teams must rely on each other’s results.
The component teams take their requirements from team handling the next
higher level of abstraction.
The higher-level team relies on the quality of design and testing performed by
the component team.
5.2.5) Concurrent engineering
Reduced design time is an important goal for concurrent engineering.
It eliminate “over-the-wall” design steps, one designer performs an isolated task and then
throws the result to the next designer.
Concurrent engineering efforts are comprised of several elements.
Cross-functional teams →include members from various disciplines ( manufacturing,
hardware and software design, marketing)
Concurrent product→ realize the process activities .
Designing various subsystems simultaneously, is reducing design time.
Integrated project management→ensures that someone is responsible for the entire project.
Early and continual supplier→ make the best use of suppliers’ capabilities.
Early and continual customer →ensure that the product meets customers’ needs.
Concurrent Engineering Applied to Telephone Systems
1. Benchmarking→ They compared themselves to competitors and found that it took
them 30% longer to introduce a new product than their best competitors.
2. Breakthrough improvement.
Increased partnership between design and manufacturing.
Continued existence of the basic organization of design labs and manufacturing.
Support of managers at least two levels above the working level.
3. Characterization of the current process.
Too many design and manufacturing tasks were performed sequentially.
4. Create the target process→ The core team created a model for the new development
process.
5. Verify the new process→ test the new process.
6. Implement across the product line→This activity required training of personnel,
documentation of the new standards and procedures, and improvements to information
systems.
7. Measure results and improve→Performance of the new design was measured.
5.3)REQUIREMENTS ANALYSIS
Requirements→It is a informal descriptions of what the customer wants.
A functional requirement→ states what the system must do.
A nonfunctional requirement→It can be physical size, cost, power consumption, design
time, reliability, and so on.
Requirements of tests
Correctness→Requirements should not mistakenly describe what the customer wants.
Unambiguousness→Requirements document should be clear and have only one plain
language interpretation.
Completeness→ Requirements all should be included.
Verifiability→ cost-effective way to ensure that each requirement is satisfied in the final
product.
Consistency→One requirement should not contradict another requirement.
Modifiability→The requirements document should be structured so that it can be
modified to meet changing requirements without losing consistency.
Traceability→Able to trace forward /backward from the requirements.
5.4)SPECIFICATIONS
Specifications→It is a detailed
descriptions of the system that can
be used to create the architecture.
Control-oriented specification languages
SDL specifications include states,
actions, and both conditional and
unconditional transitions between
states.
SDL is an event-oriented state
machine model.
State chart has some important
concepts.
State charts allow states to be
grouped together to show common
functionality.
Basic groupings(OR)
State machine specifies that the machine goes to state s4 from any of s1, s2, or s3 when
they receive the input i2.
The State chart denotes this commonality by drawing an OR state around s1, s2, and s3 .
Single transition out of the OR state s123 specifies that the machine goes to s4 when it
receives the i2 input while in any state included in s123.
Multiple ways to get into s123 (via s1 or s2), and transitions between states within the OR
state (from s1 to s3 or s2 to s3).
The OR state is simply a tool for specifying some of the transitions relating to these
states.
Basic groupings(AND)
In the State chart, the AND state sab is decomposed into two components, sa and sb.
When the machine enters the AND state, it simultaneously inhabits the state s1 of
component sa and the state s3 of component sb.
When it enters sab, the complete state of the machine requires examining both sa and sb.
State s1-3 in the State chart machine having its sa component in s1 and its sb component in
s3.
When exit from cluster states go to s5 only when in the traditional specification, we are in
state s2-4 and receive input r.
5.4.1)Advanced specifications
It ensure the correctness and safety of this system.
Ex→ Traffic Alert and Collision Avoidance System(TCAS)
It is a collision avoidance system for aircraft.
TCAS unit in an aircraft keeps track of the position of other nearby aircraft.
It uses pre-recorded voice (“DESCEND!) commands for mid-air collision.
TCAS makes sophisticated decisions in real time and is clearly safety critical.
It must detect as many potential collision events as possible .
It must generate a few false alarms ,at extreme maneuvers in potentially dangerous.
TCAS-II specification(RSML Language) Transition states
Collision Avoidance system
The system has Power-off and Power-on states .
In the power on state, the system may be in Standby or Fully operational mode.
In the Fully operational mode, three components are operating in parallel, as specified
by the AND state.
The own aircraft subsystem to keep track of up to 30 other aircraft.
Subsystem to keep track of up to 15 Mode S ground stations, which provide radar
information.
5.5)SYSTEM ANALYSIS AND ARCHITECTURE DESIGN
The CRC card methodology analyze and understanding the overall structure of a complex
system.
CRC cards
Classes define the logical groupings of data and functionality.
Responsibilities describe what the classes do.
Collaborators are the other classes with which a given class works.
It has space to write down the class name, its responsibilities and collaborators, and other
information.
Layout of CRC card
A class may represent a real-world object of the system.
A class has both an internal state and a functional interface.
The functional interface describes the class’s capabilities.
The responsibility set is describing that functional interface.
The collaborators of a class are simply the classes that it talks or calls upon to help it do its
work.
CRC card Analysis Process
1. Develop an initial list of classes→Write down the class name and functions of it.
2. Write an initial list of responsibilities and collaborators.
3. Create some usage scenarios→describe what the system does.
4. Walk through the scenarios→Each person on the team represents one or more classes.
5. Refine the classes, responsibilities, and collaborators→ make changes to the CRC cards.
6. Add class relationships→ subclass and super-class can be added to the cards.
Ex:Elevator system
1. One passenger requests a car on a floor, gets in the car when it arrives, requests
another floor, and gets out when the car reaches that floor.
2. One passenger requests a car on a floor, gets in the car when it arrives, and
requests the floor that the car is currently on.
3. A second passenger requests a car while another passenger is riding in the
elevator.
4. Two people push floor buttons on different floors at the same time.
5. Two people push car control buttons in different cars at the same time.
6) Quality Assurance techniques(QA)
The quality assurance (QA) process is vital for the delivery of a satisfactory system.
International Standards Organization (ISO) has created a set of quality standards known as
ISO 9000.
It was created to apply to a broad range of industries, including limited to embedded
hardware and software.
ISO 9000 quality management parameters
Process is crucial→Knowing what steps are to be followed to create a high-quality product.
Documentation is important→helps internal quality monitoring groups to ensure that the
required processes and helps outside groups understand the processes and how they are
being implemented.
Communication is important→ people should understand not only their specific tasks but
also how their jobs can affect overall system quality.
Capability Maturity Model (CMM)
It is used to measuring the quality of an organization’s software development.
1. Initial→A poorly organized process, with very few well-defined processes.
Success of a project depends on the efforts of individuals, not the organization
itself.
2. Repeatable→ provides basic tracking mechanisms to understand cost,
scheduling .
3. Defined→The management and engineering processes are documented and
standardized.
4. Managed→detailed measurements of the development process and product
quality.
5. Optimizing→feedback from detailed measurements is used to continually
improve the organization’s processes.
Verifying the specification→Discovering bugs early is crucial because it prevents bugs
from being released to customers, minimizes design costs, and reduces design time.
Validation of specifications→creating the requirements, including correctness,
completeness, consistency, and so on
Design reviews
The review leader coordinates the pre-meeting activities, the design review itself,
and the post-meeting follow-up.
The reviewer records the minutes of the meeting so that designers and others know
which problems need to be fixed.
The review audience studies the component.
7)DESIGNING WITH COMPUTING PLATFORM
7.1)System Architecture
The architecture of an embedded computing system includes both hardware
and software elements
HARDWARE
CPU →The choice of the CPU is one of the most important, but it can be
considered the software that will execute on the machine.
Bus →The choice of a bus is closely tied to that of a CPU,bus can handle the
traffic.
Memory→Selection depends total size and speed of the memory will play a
large part in determining system performance.
Input and output devices→ Dependig upon the system requirements
SOFTWARE
Run Time components
It is a critical part of the platform.
An operating system is required to control CPU and its multiple
processes .
A file system is used in many embedded systems to organize internal
data and interface with other systems
Support components
It is a complex hardware platform.
Without proper code development and operating system, the hardware
itself is useless.
ARM evaluation board
7.2)The PC as a Platform
CPU →provides basic computational facilities.
RAM→ is used for program storage.
ROM→holds the boot program.
DMA→controller provides DMA capabilities.
Timers→ used by the operating system for a variety of purposes.
High-speed bus→connected to the CPU bus through a bridge, allows
fast devices to communicate with the rest of the system.
low-speed bus→ provides an inexpensive way to connect simpler
devices.
7.3)Development Environments
Development process → used to make a complete design
of the system.
It guides the developers how to design a system .
An embedded computing system has CPU ,memory, I/O
devices.
Development of embedded system have both hardware&
software.
The software development on a PC or workstation known
as a host.
•The host and target are frequently connected by a USB link.
•The target must include a small amount of software to talk to the host
system.
Functions of Host system
Load programs into the target
Start and stop program execution on the target
Examine memory and CPU registers.
Cross-Compiler
Compiler→ kind of software that translate one form of pgm to another form of
pgm.
Cross Compiler→is a compiler that runs on one type of machine but generates
code for another
After compilation, the executable code is downloaded to the embedded system
by a serial link.
A PC or workstation offers a programming environment .
But one problem with this approach emerges when debugging code talks to I/O
devices.
Testbench program→ can be built to help debug the embedded code.
It may also take the output values and compare them against expected values.
7.4)Debugging Techniques
It is the process of checking errors and correcting those errors.
It can be done by compiling and executing the code on a PC or workstation.
It can be performed by both H/W and S/W sides.
Software debugging tools
1. Serial Port tool
It will perform the debugging process from the initial state of embedded system
design.
It can be used not only for development debugging but also for diagnosing
problems in the field.
2. Breakpoints tool
user to specify an address at which the program’s execution is to break.
When the PC reaches that address, control is returned to the monitor program.
From the monitor program, the user can examine and/or modify CPU registers,
after which execution can be continued.
▪Breakpoint is a location in memory at which a program stops executing and
returns to the debugging tool or monitor program.
To establish a breakpoint at location 0x40c in some ARM code, replaced the branch
(B) instruction with a subroutine call (BL) to the breakpoint handling routine
Hardware debugging tools
Hardware can be deployed to give a clearer view on what is happening when the
system is running.
1. Microprocessor In-Circuit Emulator (ICE)
It is a specialized hardware tool that can help debug software in a working
embedded system.
In-circuit emulator is a special version of the microprocessor that allows its
internal registers to be read out when it is stopped
2. Logic Analyer
The analyzer can sample many different signals simultaneously but can display
only 0, 1, or changing values for each.
The logic analyzer records the values on the signals into an internal memory
and then displays the results on a display once the memory is full.
Architecture of a logic analyzer
Data modes of logic analyzer
State modes
State mode represent different ways of sampling the values.
It uses the own clock to control sampling
It samples each signal only one per clock cycle.
It has less memory to store a given number of system clock.
Timing modes
Timing mode uses an internal clock that is fast enough to take several samples
per clock period in a typical system.
7.5)Debugging Challenges
Logical errors in software can be hard to track down and it will create
many problems in real time code.
Real-time programs are required to finish their work within a certain
amount of time.
Run time pgm run too long, they can create very unexpected behavior.
Missing of Deadline makes debugging process as difficult.
8)Consumer Electronic Architecture
Consumer electronic refers to any device containing an electronic circuit board
that is intended for eneryday use by individuals.
Eg→TV,cameras,digital cameras,calculators,DVDs,audio devices,smart phones
etc..,
8.1)Functional Requirements
1. Multimedia
The media may be audio, still images, or video.
These multimedia objects are generally stored in compressed form and must be
uncompressed to be played .
Eg→ multimedia compression standards (MP3,Dolby Digital(TM))
audio; JPEG for still images; MPEG-2, MPEG-4, H.264, etc. for video.
2. Data storage and management→ People want to select what multimedia objects
they save or play, data storage goes hand-in-hand with multimedia capture and
display. Many devices provide PC-compatible file systems so that data can be
shared more easily.
3. Communications→ Communications may be relatively simple, such as a USB
and another is Ethernet port or a cellular telephone link.
8.2)Non-Functional Requirements
Many devices are battery-operated, which means that they must operate under
strict energy budgets.
Battery(75mW) →support not only the processors but also the display, radio,
etc.
Consumer electronics must also be very inexpensive but provide very high
performance.
Use case for playing multimedia
use case for selecting and playing a multimedia object (audio clip, a picture,etc.).
Selecting an object makes use of both the user interface and the file system.
Playing also makes use of the file system as well as the decoding subsystem and
I/O subsystem.
Use case of synchronizing with a host
system
use case for connecting to a client.
The connection may be either over a local connection like USB or over the
Internet.
Some operations may be performed locally on the client device
most of the work is done on the host system while the connection is
established
8.3)Functional architecture of
Consumer Electronics Device(CED)
It is a two-processor architecture.
If more computation is required, more DSPs and CPUs may be added.
The RISC-CPU runs the operating system, runs the user interface, maintains
the file system, etc.
DSP→ it is a programmable one, which performs signal processing.
Operating system→ runs on the CPU must maintain processes and the file
system.
Depending on the complexity of the device, the operating system may not need
to create tasks dynamically.
If all tasks can be created using initialization code, the operating system can be
made smaller and simpler.
8.4)Flash File Systems
Many consumer electronics devices use flash memory for mass storage.
Flash memory is a type of semiconductor memory ,unlike DRAM or
SRAM, provides permanent storage.
Values are stored in the flash memory cell as electric charge using a
specialized capacitor that can store the charge for years.
The file system of a device is typically shared with a PC.
Standard file system→has two layers.bottom layer handles physical
reads and writes on the storage device and the top layer provides a
logical view of the file system.
Flash file system→imposes an intermediate layer that allows the logical-
to-physical mapping of files to be changed.
9)Platform-Level Performance Analysis
System-Level Performance involves much more than the CPU.
To move data from memory to the CPU to process it. To get the data from
memory to the CPU we must.
1. Read from the memory.
2. Transfer over the bus to the cache.
3. Transfer from the cache to the CPU.
The performance of the system based on Bandwidth of the system.
We can increase bandwidth in two ways:
1) By increasing the clock rate of the bus
2) By increasing the amount of data transferred per clock cycle.
For example, bus to carry four bytes or 32 bits per transfer, we would reduce
the transfer time to 0.058 s. If we also increase the bus clock rate to 2 MHz,
then we would reduce the transfer time to 0.029 s ,which is within our time
budget for the transfer.
t=TP
t→bus cycle counts
T→bus cycles.
p→bus clock period
9.1)Parallelism
Direct memory access is a example of parallelism.
DMA was designed to off-load memory transfers from the CPU.
The CPU can do other useful work while the DMA transfer is running.
1. Marilyn Wolf, “Computers as Components – Principles of
Embedded Computing System Design”, Third Edition “Morgan
Kaufmann Publisher (An imprint from Elsevier), 2012.
(UNIT I, II, III, V)
2.Jane W.S.Liu,‖ Real Time Systems‖, Pearson Education, Third
Indian Reprint, 2003.(UNIT IV)
UNIT II
ARM PROCESSOR AND PERIPHERALS
ARM Architecture Versions – ARM Architecture – Instruction Set –
Stacks and Subroutines – Features of the LPC 214X Family – Peripherals
– The Timer Unit – Pulse Width Modulation Unit – UART – Block
Diagram of ARM9 and ARM Cortex M3 MCU.
2.1) ARM Architecture Versions
ARM stands for ‘Advanced RISC Machine’.
It was developed in the year 1980
In year 1985 ARM1, which had less than 25,000 transistors, and operated at
6 MHz
In year 1987 ARM2 with 30,000 transistors.
In year 1990 ARM3-4-5 with 30,000 transistors.
As of 2011, ARM processors account for approximately 90 per cent of all
embedded 32-bit RISC processors.
Advanced processors of the ARM family (ARM9, ARM10, ARM11, Cortex)
have been built on the success of the ARM7 processor, which is still the
most popular and widely used member of the ARM family.
Applicaions
Consumer electronics, including PDAs, mobile phones, digital media and
music players, handheld game consoles, calculators and computer
peripherals such as hard drives and routers
2.1.1)ARM CORTEX
A profile
This profile which has the ARMv7-A architecture is meant for
high end applications.(mobile phones and video systems)
R profile
This profile which has the ARMv7-R architecture has been
designed for high-end applications which require real-time
capabilities. (automatic braking systems and other safety critical
applications)
M profile
This profile which has the ARMv7-M architecture has been
designed for industrial control applications where a large
number of peripherals may have to be handled and controlled.
2.1.2)Features of ARM
It is a 32 bit processor also supports 8 and 16 bits data types.
It can be configured either Little-endian mode ( lowest-order byte stored in the
low-order bits of the word) or Big-endian mode (lowest-order byte stored in the
highest bits of the word).
It uses a Intelligent Energy Meter(IEM) technology to optimally balancing the
workload and energy consumption.
It use Advanced High Performance Bus interface(AMBA) for on-chip
interconnect purpose.
Data bus width→The processor has a 32-bit data bus width, which means that it
can read and write 32 bits in one cycle.
Computational capability→ The instruction set of ARM has been cleverly
designed to facilitate very good computational capability.
Low power→ ARM operates at relatively low frequencies from 60 MHz to at the
most 1 GHz.
Pipelining→Any time, there are three instructions simultaneously present in the
pipeline, at different levels of processing.
Multiple register instructions→ There are instructions which access memory and
load data into multiple registers – also, contents of multiple registers can be
stored in memory, with a single instruction.
2.2)ARM-Architecture
Arrow→
represents
flow of data.
Line→
represents
the buses
Boxes→
Represent
either
storage area
or operation
unit
Data enters the processor core through data bus. It is either data
item or instruction to execute.
If it is a instruction then the instruction decoder translates
instructions before they are executed.
If it is data then the data item are placed in the register file (32bit
size).
It have register (Rn,Rm-source register and Rd-destination
register).
Source operands are read from the register file using internal
buses Aand B.
ALU takes the register values Rn and Rm from A and B buses and
write the result Rd directly to the register file using result bus.
Load and store instructions use the ALU to generate an address
and it stores in address register.
CPU modes
User mode→ The only non-privileged mode.
FIQ (fast Interrupt request)mode→A privileged mode that is entered
whenever the processor accepts a fast interrupt request.
IRQ mode→A privileged mode that is entered whenever the processor
accepts an interrupt.
Supervisor (svc) mode→ A privileged mode entered whenever the CPU
is reset or when an SVC instruction is executed.
Abort mode→A privileged mode that is entered whenever a pre-fetch
abort or data abort exception occurs.
Undefined mode→ A privileged mode that is entered whenever an
undefined instruction exception occurs.
System mode→It can only be entered by executing an instruction that
explicitly writes to the mode bits of the Current Program Status Register
(CPSR) from another privileged mode (not from user mode).
Data Operations
In ARM processor→ Arithmetic and logical operations can’t be performed
directly on memory locations.
ARM is a load-store architecture—data operands must first be loaded into
the CPU and then stored back to main memory to save the results.
Current program status register (CPSR)→ set automatically during every
arithmetic, logical, or shifting operation.
Based on the result of arithmetic/logical operation,CPSR four bits are
affected as follows
The negative (N) bit is set when the result is negative in two’s-complement
arithmetic.
The zero (Z) bit is set when every bit of the result is zero.
The carry (C) bit is set when there is a carry out of the operation.
The overflow(V) bit is set when an arithmetic operation results in an
overflow.
2.3)Instruction Set
The instruction set can be broadly classified as follows:
i) Data processing instructions
ii) Load store instructions—single register, multiple register
iii) Branch instructions-
iv) Status register access instructions
2.3.1)Data Processing Instructions
a)Move instructions
MOV and MVN Instructions→The ‘MOV’ instruction is a ‘register to
register’ data movement instruction with the format MOV destination,
source where both the source and destination have to be registers.
b)Conditional Execution
→Instructions are executed only if a specified condition is true.
In the instruction code, four bits are allotted for the condition under
which the instruction is to be executed.
c)Shift Instructions
Logical Shift Left (LSL)→ Logical Shift
Left of a 32-bit number causes it to shift
left and the vacant bits on the right are
filled with zeros.
Logical Shift Right (LSR)→ The
vacant bit positions on the left are filled
with zeros, and the last bit shifted out is
retained in the carry flag
Arithmetic Shift Right (ASR)→ The
vacant bit positions on the left are filled
with the MSB of the original number.
Rotate Right (ROR)→ The data is
moved right, and the bits shifted out
from the right are inserted back through
the left.
Rotate Right Extended (RRX)→
Rotating right through the carry bit,
that the bit that drops off from the right
side is moved to C and the carry bit
enters through the left of the data
d)Arithmetic Instructions
Addition-Subtraction-Multiplication→The destination is always a register.The
source operands may both be registers or one of them may be an immediate
data
Logical Instructions
Compare Instructions→This instruction compares two operands and the
conditional flags to be affected, but neither the destination nor the source
changes
2.3.2)Load and Store Instructions
Loading is the process of getting data from memory into a register, and
storing is just the reverse process.
Multiple Register Load and Store
Loading and storing, wherein multiple registers are involved.
2.3.3)Branch Instructions
The power to change the sequence of execution is obtained by branching,
which may be conditional or unconditional.
Branching implies transferring control to a new memory location which is
expressed as a label ’B’.
2.4)Stacks and Subroutines
A stack is an area in memory, the accessing of which is done in a special
way. Most stacks are Last-In First-Out (LIFO) type stack.
Two operations are defined for a stack, that is, the PUSH, in which data is
written into the stack, and POP in which data is read out and loaded into
registers
Types of Stacks
i. Ascending→It starts from a low memory address and, as items are
pushed onto it, progresses to higher memory addresses.
ii. Descending→It starts from a high memory address, and as items are
pushed onto it, it progresses to lower memory addresses.
iii. Empty→ stack pointer points to the next free (empty) location on the
stack
iv. Full→ stack pointer points to the topmost item in the stack
Procedures
For most processors, procedures use a stack to store the return address.
A procedure starts with a ‘CALL’ instruction. This causes the action of pushing
the current value of PC onto the stack.
The procedure ends with a ‘RETURN’ instruction. This causes the PC value to
be popped back.
2.5)Features of the LPC 214X Family
i) The core ARM 7TDMI-S in a tiny LQFP64 package
ii) 8 KB to 40 KB of on-chip static RAM
iii) 32 KB to 512 KB of on-chip flash memory
iv) 128-bit wide interface/accelerator enables high-speed 60 MHz operation
v) USB 2.0 Full-speed compliant device controller with 2 KB of endpoint
RAM.
In addition, provides 8 KB of on-chip RAM accessible to USB by DMA
i) Single 10-bit DAC provides variable analog output
ii) Two 32-bit timers/external event counters, PWM unit (six outputs) and
watchdog
iii) Low power real-time clock (RTC) with independent power and 32 kHz
clock input
iv) Multiple serial interfaces including two UARTs,two fast I2C-bus, SPI and
SSP with buffering and variable data length capabilities
2.5)Features of the LPC 214X Family(Contd..,)
v) Vectored interrupt controller (VIC) with configurable priorities and vector
addresses
vi) Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64
package
vii) Up to 21 external interrupt pins available
viii) 60 MHz maximum CPU clock available from programmable on-chip
PLL
ix) On-chip integrated oscillator operates with an external crystal from 1 to
25 MHz
x) Power saving modes include idle and power-down
xi) Processor wake-up from power-down mode via external interrupt
xii) Single power supply chip with POR and BOD circuits
Internal block diagram of LPC 2148
2.6)Peripherals
Each of the peripherals has addresses and the peripherals use the
memory mapped I/O scheme of addressing– this means that both
memory and I/O share the same address space.
Each peripheral has a number of special function registers (SFRs)
associated with it, and each SFR has a specific address.
GPIO (General Purpose I/O)
In a chip, it will be seen that most pins have more than one function.
There are three to four designations for each pin, and which of these is
valid at a time depends on how the pin has been ‘programmed’ using
the pin-select block.
There are two general purpose 32-bit ports, P0 and P1, with restrictions.
2.6a)Port 0
Port 0 is a 32-bit I/O port with individual direction controls for each bit.
28 pins of the Port 0 can be used as general purpose bi-directional digital
I/Os, while P0.31 provides digital output functions only.
The operation of Port 0 pins depends upon the pin function selected via
the pin connect block.
Pins P0.24, P0.26 and P0.27 are ‘reserved’ and not available for use.
2.6b)Port 1
Port 1 is a 32-bit bi-directional I/O port with individual direction controls for
each bit.
The operation of Port 1 pins depends upon the pin function selected via the
corresponding pin connect block.
Pins 0 through 15 are not available.
pins from 16 to 31, the pins 16 to 25 are ‘reserved’.
In effect, only very few pins of Port 1 are available and they can be used for
GPIO only, because other pin functions are used for JTAG.
2.6c)Pin Connect Block(PCB)
The purpose of PCB is to
configure the pins to the
desired functions.
Each pin of the chip has a
maximum of four functions.
To select one specific
function for a pin, a
multiplexer with two select
pins, is necessary.
The select pins function is
provided by the bits of the
PINSEL registers.
2.6d)GPIO Pins
These pins can be used for driving
an LCD display, relays, motor
controls, ON/OFF functions and so
on.
i) IODIR (IO Direction register):
register decides whether a pin is to
be an input(0) or output(1).
ii) IOSET (IO Set register): It is
used to set the output pins of the
chip.
iii) IOCLR (IO Clear register): To
make an output pin to have a ‘0’
value, i.e., to clear it.
iv) IOPIN (IO Pin register): From
this register, the value of the
corresponding pin can be read,
irrespective of whether the pin is
an input or output pin.
2.6.1)The Timer Unit
A timer and a counter are functionally
equivalent, except that a timer uses the
PCLK for its timing, while a counter uses an
external source.
Timer Operation
i) Load a number in a match register.
ii) Start the timer by enabling the ‘E’ bit in
T0TCR.
iii) The timer count register (T0TC) starts
incrementing for every tick of the peripheral
clock PCLK (no pre-scaling is done).
iv) When the content of the T0TC equals the
value in the match register, timing is said to
have occurred.
v) One of many possibilities can be made to
occur when this happens.
vi) The possibilities are to reset the timer
count register, stop the timer, or generate an
interrupt. This ‘setting’ is done in the T0MCR
Timer Count Register–T0TC
This is a 32-bit register, which gives it a range of counting from 0 to 0xFFFF
FFFF and then wraps back to the value 0x0000 0000.
This register is incremented on every tick of the clock (i.e. PCLK), if the
prescale counter is made 0
Timer Control Register–TOTCR
This is an 8-bit register in which only the lowest two bits need be used.
Bit 0–E→ When this Enable bit is ‘1’, the counter is enabled and starts.
Bit 1–R→When Reset bit ‘1’, the counter is reset on the next positiveedge of
PCLK.
Match Registers (MR0 to MR3)
There are four 32-bit match registers available: MR0 to MR3.
For the operation of one timer, one of the match registers may be sufficient and
is used by loading a number into it.
During timer operation, the timer count register starts incrementing, and at
sometime, its count ‘matches’ with the number in the match register.
Match Control Register–T0MCR
This is a 16-bit register used to specify the event to occur when the
match occurs.
The lowest three bits are for controlling the operations related to the
Match register 0.
The next three are for MR1, MR2 and MR3, in that order.
Pre-scaler
To generate a lower frequency output
prescale counter increments for every PCLK, and when it counts up to
the value in the prescale counter (T0PR), it allows the timer counter
(T0TC) to increment its value by 1.
Timer 0 in the Interupt Mode
i)Vectored Interrupt Controller (VIC)
Manages all the interrupts of the
ARM core (IRQs and FIQs.
Receive interrupt requests from
the peripherals and generate IRQ
signal to the ARM processor.
Features of VIC
32 interrupt request inputs
16 vectored IRQ interrupts
16 priority levels dynamically
assigned to interrupt requests
Software interrupt generation
ii)Interrupt Enable Register (VIC Interrupt Enable)
This is a read/write accessible register.
This register controls the decision of which of the 32 interrupt requests and
software interrupts are allowed to contribute to the generation of an interrupt.
iii)Vector Control Register (VIC Vect Cntl0-15)
Only 6 bits of this register are to be used. They are lower 6 ones
iv)Vector Address Registers (VIC Vect Add)
These are read/write accessible registers.
These registers hold the addresses of the interrupt service routines (ISRs) for
the vectored IRQ slots
v)Timer 0 in the Interrupt Mode
T0MCR is to be programmed to generate an interrupt on match
vi)Timer 0 Interrupt Register (TOIR)
This register has bits for each of the matching states of MR0 to MR3.
When a timer operates in the interrupt mode and a match occurs, an
interrupt is generated, and the corresponding flag bit in T0IR is set.
To ‘clear’ it, a ‘1’ must be written into this same register. Then only will the
interrupt fl ag be ‘reset’.
2.6.2)Pulse Width Modulation Unit
Pulse width modulation which it is possible to control the period and duty cycle of a
square wave.
Single Edge Controlled PWM
i) All single edge controlled PWM outputs go high at the beginning of a PWM cycle.
ii) Each PWM output will go low when its match value (in MR1 to MR6) is reached. If no
match occurs the PWM output remains continuously high.
iii) When a match occurs, actions can be triggered automatically. The possible actions
are to generate an interrupt, reset the PWM timer counter, or stop the timer.
The duty cycle is the ratio of ON period (P) to the total period T.
Corresponding to the six match registers, there are six PWM output pins, and they
are called the PWM channels
Control Registers of the PWM Unit
PWMTCR(PWM Timer Control Register)
It is is an 8-bit register. Only the lower 4 bits of this register need to be used.
Bit 0–CE→ COUNTER ENABLE When ‘1’, the PWM timer counter and Prescale
counter are enabled.
Bit 1–CR→ COUNTER RESET ‘When ‘1’, the above mentioned PWM timer
count register and Prescale counter are reset on the next positive going edge of
PCLK.
Bit 2→R-Reserved
Bit 3→ PE-PWM ENABLE. When ‘1’, the PWM mode is enabled. Otherwise the
PWM unit acts as just a timer.
PWMPCR(PWM Control Register)
It is a 16-bit register and is used to enable and select the type of each PWM
channel.
This register enables or disables the six PWM outputs, and also chooses
between double and single edge control.
Bits 0, 1, 7 and 8 and 15 are unused.
PWMLER ( PWM Latch Enable Register)
The PWM latch enable register is an 8-bit register used to control the
update of the PWM match registers when they are used for PWM
generation.
2.6.3)UART
This chip has two UARTs, namely, UART0
and UART1.
The Transmitter
When a data byte arrives in the Transmitter
Holding Register (THR),(from CPU) it is
‘framed’ (by adding start and stop bits) and
transferred to the Transmitter Shift
Register (TSR )and sent out through the
TxD pin one bit at a time, by clocking the
TSR at the baud decided by the transmitter
clock TCLK.
The Receiver
The data received serially through the RxD
line ,is moved bit by bit into the Receiver
Shift Register (RSR), and then transferred
to the Receiver Buff er Register (RBR). after
de-framing. From the RBR it is copied to
the CPU registers through the bus.
The BAUD Rate Generator (BRG)
It takes PCLK as input, and generates the baud rates for the transmitter and
receiver.
Registers of UART0
UART0 for transferring a character string from the LPC 2148 board to a PC,
using the ‘hyper-terminal’, at a baud of 9600.
Pinselect Register (PINSEL0)
The pin selection for the TxD and RxD pins of UART0 are referred.
PINSEL0 register selects pins P0.0 as TxD and P0.1 as RxD, by writing PINSEL0
= 0x5.
UART0 Transmit Holding Register (U0THR)
It is an 8-bit register and part of the transmit buffer.
New characters are to be loaded into this register for being transmitted.
The data to be transmitted is written into this ‘write only’ register.
UART0 Divisor Latch Registers (U0DLL and U0DLM)
The UART0 divisor Latch is part of the UART0 Fractional Baud Rate Generator
and holds the value used to divide the clock supplied by the fractional prescaler
in order to produce the baud rate clock, which must be 16x the desired baud
rate.
The U0DLL and U0DLM registers together form a 16-bit divisor where U0DLL
contains the lower 8 bits of the divisor and U0DLM contains the higher 8 bits
UART0 FIFO Control Registers (U0FCR)
Bit 0: E: This bit must be set for enabling the Tx and Rx FIFOs
Bit 1: Rx FIFO Reset: This must be set, to clear all bytes in UART0 Rx FIFO and
reset the pointer logic. This bit is self-clearing.
Bit 2: Tx FIFO Reset: This must be set to clear all bytes in UART0 Tx FIFO and
reset the pointer logic. This bit is self-clearing.
Bits 7 and 6: Rx trigger level: These two bits determine how many receiver FIFO
characters must be written before an interrupt is activated.
UART0 Line Control Register (U0LCR)
It is an 8-bit register which determines the format of the data character that is
to be transmitted or received.
Bits 1: 0 These two bits have been chosen to be ‘11’ to indicate 8-bit character
length
Bit 2: This is made ‘0’ to select one stop bit
Bit 7: This is the Divisor Latch Access Bit (DLAB) and is set, to enable the use
of the divisor latch
UART0 Line Status Register (U0LSR)
It is a read-only register that provides status information regarding the UART0
TX and RX blocks.
2.7)Block Diagram of ARM9
The ARM9 core is a more advanced member of the ARM family.
It has a 5 stage pipeline and operates at a frequency double that of ARM7.
Many ARM9 cores have DSP instructions and thus are ‘Enhanced’ ARM9E
processors.
Because the core is so powerful, it is used for more complex operations
The LPC 29xx combine an 125 MHz ARM968E-S CPU core.
Compatible with Full Speed USB2.0 host and device.
support 56 KB SRAM, up to 768 KB
Flash memory, external memory interface, three 10-bit ADCs, and multiple
serial and parallel interfaces in a single chip’.
It is obvious that this is a very powerful chip with many more peripherals than
the ARM7 MCU.
2.8)ARM Cortex M3 MCU
The LPC 17xx is an ARM Cortex-M3 based microcontroller for embedded
applications requiring a high level of integration and low-power
dissipation.
It is a next generation core that offers debug features and a higher level
of support block integration.
Feautres
High speed versions (LPC 1769 and LPC 1759) operate at up to a 120 MHz
CPU frequency.
It incorporates a 3-stage pipeline.
It uses a Harvard architecture with separate local instruction and data
buses as well as a third bus for peripherals.
It also includes an internal prefetch unit that supports speculative
branches.
The peripheral complement of the LPC 17xx includes up to 512 kB of
flash memory.
It uses up to 64 kB of data memory.
Feautres(Contd..,)
Consists of Ethernet MAC, a USB interface that can be configured as
either Host, Device.
Support 8 channel general purpose DMA controller.
Consists of 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface,
3 I2C interfaces, 2-input plus 2- output I2S interface.
It has 8 channel 12-bit ADC, 10-bit DAC, motor control PWM,
Quadrature Encoder interface.
It consists of 4 general purpose timers, 6-output general purpose
PWM.
It uses ultra-low power RTC with separate battery supply.
support up to 70 general purpose I/O pins.
1. Marilyn Wolf, “Computers as Components – Principles of
Embedded Computing System Design”, Third Edition “Morgan
Kaufmann Publisher (An imprint from Elsevier), 2012.
(UNIT I, II, III, V)
2.Jane W.S.Liu,‖ Real Time Systems‖, Pearson Education, Third
Indian Reprint, 2003.(UNIT IV)
UNIT III
EMBEDDED PROGRAMMING
Components for embedded programs- Models of programs- Assembly,
linking and loading – compilation techniques- Program level
performance analysis – Software performance optimization – Program
level energy and power analysis and optimization – Analysis and
optimization of program size- Program validation and testing.
3.1)COMPONENTS FOR EMBEDDED PROGRAMS
Embedded components are given by State machine, Circular buffer,
and the Queue.
3.1.1)STATE MACHINE
The reaction of most systems can be characterized in terms of the input
received and the current state of the system.
The finite-state machine style of describing the reactive system’s behavior..
Finite-state machines are usually first encountered in the context of hardware
design.
software state machine
seat, belt, timer
case BELTED:
#define IDLE 0 if (!seat) state = IDLE; /* person left */
#define SEATED 1
else if (!belt) state = SEATED; /*
#define BELTED 2
person still
#define BUZZER 3
switch (state) { /* check the current in seat */
state */ break;
case IDLE: case BUZZER:
if (seat) { state = SEATED;
if (belt) state = BELTED; /* belt is on—
timer_on = TRUE; }
turn off
/* default case is self-loop */
break; buzzer */
case SEATED: else if (!seat) state = IDLE; /* no one in
if (belt) state = BELTED; /* won't hear seat—turn off buzzer */
the
break;
buzzer */
else if (timer) state = BUZZER; /* }
didn't put on
belt in time */
/* default is self-loop */
break;
3.1.2)Stream-Oriented Programming and Circular Buffers
The circular buffer is a data structure that handle streaming data in an
efficient way.
Size of the window does not change.
Fixed-size buffer to hold the current data.
To avoid constantly copying data within the buffer, move the head of
the buffer in time.
The buffer points to the location at which the next sample will be
placed.
Every time add a sample, automatically overwrite the oldest sample,
which is the one that needs to be thrown out.
When the pointer gets to the end of the buffer, it wraps around to the
top.
Circular buffer for streaming data.
3.1.3)QUEUES
Queues are also used in signal processing and event
processing.
Queues are used whenever data may arrive and depart at
somewhat unpredictable times or when variable amounts
of data may arrive.
A queue is often referred to as an Elastic buffer.
3.2)MODELS OF PROGRAMS
Programs are collection of instructions to execute a specified task.
Models for programs are more general than source code.
source code can’t be used directly because of different type s such as
assembly language,C code.
Single model to describe all of them.
control/data flow graph (CDFG)it is the fundamental model for
programs
3.2.1)DATA FLOW GRAPH
A data flow graph is a model of a program with no conditionals.
In a high-level programming language, a code segment with no
conditionals have only one entry and exit point—is known as a basic
block.
A basic block in C
An extended data flow graph for our sample basic block
•The basic block in single-assignment
form
•Round nodesdenote operators
•Square nodesdenote values.
•The value nodes may be either inputs(a,b)
or variables(w,x1).
Standard data flow graph for our sample basic
block
3.2.2)Control/Data Flow Graphs(CDFG)
A CDFG uses a data flow graph as an element,adding constructs to
describe control.
CDFG having following two types of nodes.
1. Decision nodesused to describe the control in a sequential
program
Data flow nodes encapsulates a complete data flow graph to
represent a data.
C code and its CDFG
if (cond1)
basic_block_1( );
else
basic_block_2();
basic_block_3( );
switch (test1) {
case c1: basic_block_4( ); break;
case c2: basic_block_5( ); break;
case c3: basic_block_6( ): break;
}
•Rectangular nodesrepresent the basic blocks.
•Diamond-shaped nodes represent the conditionals.
•Label node’s condition
•Edges are labeled with the possible outcomes of
evaluating the condition
CDFG for a while loop
while (a < b) {
a5proc1(a,b);
b5proc2(a,b);
}
CDFG for a while loop
while (a < b) {
a5proc1(a,b);
b5proc2(a,b);
}
3.3)ASSEMBLY, LINKING AND LOADING
•Assembly and linking last steps in the compilation process
•They convert list of instructions into an image of the program’s bits in
memory.
•Loading puts the program in memory so that it can be executed.
Compilers used to create the instruction-level program in to
assembly language code.
Assembler’s used to translate symbolic assembly language
statements into bit-level representations of instructions known as
object code and also translating labels into addresses.
Linker determining the addresses of instructions.
Loader load the program into memory for execution.
Absolute addresses Assembler assumes that the starting address of
the ALP has been specified by the programmer.
Relative addresses specifying at the start of the file address is to be
computed later.
3.3.1)Assemblers
Assembler Translating assembly code into object code also assembler must
translate opcodes and format the bits in each instruction, and translate labels
into addresses.
Labels it is an abstraction provided by the assembler.
Labelsknow the locations of instructions and data.
Label processing requires making two passes
1. first pass scans the code to determine the address of each label.
2. second pass assembles the instructions using the label values computed
in the first pass.
EXAMPLE
CODE SYMBOL TABLE
3.3.2)LINKING
A linker allows a program to be stitched together out of several smaller pieces.
The linker operates on the object files and links between files.
Some labels will be both defined and used in the same file.
Other labels will be defined in a single file but used elsewhere .
The place in the file where a label is defined is known as an entry point.
The place in the file where the label is used is called an external reference.
Phases of linker
First Phaseit determines the address of the start of each object file
Second Phasethe loader merges all symbol tables from the object files into a
single,large table.
3.4)BASIC COMPILATION TECHNIQUES
•Compilation=Translation+optimization
•Compilation begins with high-level language code
(C) and produces assembly code.
•The high-level language program is parsed to break it
into statements and expressions.
•symbol table is generated, which includes all the named
objects in the program.
•Instruction-level optimizations used to generating
code. (real instructions or on a pseudo-instruction)
•This level of optimization used to create simple code .
3.4.1)Statement Translation
Translating the high-level language program with little or no optimization.
EgCompiling an arithmetic expression
a*b + 5*(c – d)
In the above example the variable is written in terms of program variables.
In ARM, first load the variables into registers.
This requires choosing which registers receive not only the named variables but also
intermediate results such as (c d).
The temporary variables for the intermediate values and final result have been named w,
x , y , and z.
To generate code, walk from the tree’s root (where z, the final result, is generated) by
traversing the nodes in post order.
During the walk, generate instructions to cover the operation at every node.
The nodes are numbered in the order in which code is generated.
Since every node in the data flow graph corresponds to an operation that is directly
supported by the instruction set.
Compiling an arithmetic expression
ARM code
3.4.2)Procedures
Another major code generation problem is the creation of procedures.
Procedure stacks are typically built to grow down from high addresses.
stack pointer (sp) defines the end of the current frame.
frame pointer (fp) defines the end of the last frame.
The procedure can refer to an element in the frame by addressing relative to sp.
When a new procedure is called, the sp and fp are modified to push another
frame onto the stack.
r1-r3 are used to pass parameters into the procedure.
r0 used to hold the return value.
r4- r7 hold register variables.
r11 is the frame pointer
r13 is the stack pointer.
r10 to check for stack overflows.
3.4.3)DATA STRUCTURE
Data structure way of organizing the data.
The compiler must also translate references to data structures into references to raw
memories
It requires address computations.
Eg one-dimensional arrays
The zeroth element is stored as the first element of the array.
The first element directly below, and so on.
Pointer for the array that points to the array’s head, namely a[0].
pointer (aptr) reading the array a[i] as*(aptr + i)
Two-dimensional arrays
Multiple possible ways to lay out a two-dimensional array in memory.
row major inner variable of the array ( j in a[i, j]), varies most quickly.
3.4.4)Compiler/Program Optimization
Compiler can optimize the program by recognizing the code and taking the
proper action.
a) Expression Simplification
It is a useful area for machine-independent transformations.
use the laws of algebra to simplify expressions.
Consider the following expression: a*b + a*c
use the distributive law to rewrite the expression as : a*(b + c)
new expression has only two operations rather than three for the original form
b) Dead Code Elimination
Code that will never be executed can be safely removed from the program.
Programmers will intentionally introduce dead code in certain situations.
Consider this C code fragment
#define DEBUG 0
...
if (DEBUG) print_debug_stuff();
print_debug_stuff( ) function is never executed, but the code allows the
programmer to override the preprocessor variable definition to enable the
debugging code.
c)Procedure Inlining
An in-lined procedure does not have a separate procedure body and procedure
linkage.
The body of the procedure is substituted in place for the procedure call.
d) Loop Transformations
Loops are important program structures.
Computation time of the processor is depends upon the loop.
loop unrollingIt helps expose parallelism that can be used by later stages of the
compiler.
Loop fusioncombines two or more loops into a single loop
Transformation to be legal, two conditions must be satisfied.
First, the loops must iterate over the same values.
Second, the loop bodies must not have dependencies that would be violated if
they are executed together
Loop distribution decomposing a single loop into multiple loops.
Loop Tiling breaks up a loop into a set of nested loops,with each inner loop
performing the operations on a subset of the data
3.5)PROGRAM-LEVEL PERFORMANCE ANALYSIS
The techniques we use to analyze program execution time are also helpful in
analyzing properties such as power consumption.
The CPU executes the entire program at the rate we desire.
The execution time of a program often varies with the input data values.
The cache has a major effect on program performance.
Cache’s behavior depends in part on the data values input to the program.
The execution time of an instruction in a pipeline depends not only on that
instruction but on the instructions around it in the pipeline.
Execution time of a program
3.5.1)Program Performance Measuring techniques
1. Simulator
It runs on a PC, takes as input an executable for the microprocessor along with
input data, and simulates the program.
Timer
It is can be used to measure performance of executing sections of code.
The length of the program that can be measured is limited by the accuracy of the
timer.
3. Logic analyzer
It is used to measure the start and stop times of a code segment.
The length of code that can be measured is limited by the size of the logic
analyzer’s buffer.
3.5.2)Types of performance Parameters
1. Average-case execution time
This is the typical execution time we would expect for typical data.
2. Worst-case execution time
The longest time that the program can spend on any input sequence is clearly
important for systems that must meet deadlines.
3. Best-case execution time
This measure can be important in multi-rate real-time systems.
3.5.3) Elements of Program Performance
•Execution time =Program path +Instruction timing
•Program path It is the sequence of instructions executed by the program.
•Instruction timingIt is determined based on the sequence of instructions
traced by the program path.
•Not all instructions take the same amount of time.
•The execution time of an instruction may depend on operand values.
3.5.4)Measurement-Driven Performance Analysis
To measure the program’s performance need CPU or its simulator .
Measuring program performance combination of determination of the
execution path and the timing of that path.
program trace record of the execution path of a program.
Cycle-Accurate Simulator
It can determine the exact number of clock cycles required for execution.
It is built with detailed knowledge of how the processor works .
It is slower than the processor itself, but a variety of techniques can be used to
make them surprisingly fast.
It has a complete model of the processor, including the cache.
It can provide information about why the program runs too slowly.
3.6)SOFTWARE PERFORMANCE OPTIMIZATION
3.6.1)Loop Optimizations-Loops are important targets for
optimization because programs with loops tend to spend a lot of time
executing those loops.
Code motion
Induction variable elimination
Strength reduction
Code motion
It can move unnecessary code out of a loop.
If a computation’s result does not depend on operations performed in the loop
body,thenwe can safely move it out of the loop.
for (i = 0; i < N*M; i++)
{
z[i] = a[i] + b[i];
}
Code motion in a loop
•The loop bound computation is performed on every iteration during the loop
test, even though the result never changes.
•We can avoid N X M- 1 unnecessary executions of this statement by moving it
before the loop.
Induction variable elimination
It is a variable whose value is derived from the loop iteration variable’s value.
The compiler often introduces induction variables to help it implement the
loop.
Properly transformed able to eliminate some variables and apply strength
reduction to others.
A nested loop is a good example of the use of induction variables.
for (i = 0; i < N; i++)
for (j = 0; j < M; j++)
z[i][j] = b[i][j];
The compiler uses induction variables to help it address the arrays. Let us
rewrite the loop in C using induction variables and pointers
for (i = 0; i < N; i++)
for (j = 0; j < M; j++) {
zbinduct = i*M + j;
*(zptr + zbinduct) = *(bptr + zbinduct);
}
Strength reduction
It reduce the cost of a loop iteration.
Consider the following assignment
y = x * 2;
In integer arithmetic, we can use a left shift rather than a multiplication by 2
If the shift is faster than the multiply, then perform the substitution.
This optimization can often be used with induction variables because loops are
often indexed with simple expressions.
3.6.2) Cache Optimizations
A loop nest is a set of loops, one inside the other.
Loop nests occur when we process arrays.
A large body of techniques has been developed for optimizing loop nests.
Rewriting a loop nest changes the order in which array elements are accessed.
This can expose new parallelism opportunities that can be exploited by later
stages of the compiler, and it can also improve cache performance.
3.7)PROGRAM-LEVEL ENERGY AND POWER
ANALYSIS AND OPTIMIZATION
Power consumption is a important design metric for battery-powered systems.
It is increasingly important in systems that run off the power grid.
Fast chips run hot, and controlling power consumption is an important
element of increasing reliability and reducing system cost.
Power consumption reduction techniques.
To replace the algorithms with others that consume less power.
By optimizing memory accesses ,able to significantly reduce power.
To turn off the subsystems of CPU, chips in the system, in order to save power.
Measuring energy consumption for a piece of code
Program’s energy consumption how
much energy the program consumes.
To measure power consumption for an
instruction or a small code fragment.
It is used to executes the code under test
over and over in a loop.
By measuring the current flowing into the
CPU,we are measuring the power
consumption of the complete loop,
including both the body and other code.
By separately measuring the power
consumption of a loop with no body.
we can calculate the power consumption
of the loop body code as the difference b/w
the full loop and the bare loop energy cost of
an instruction.
List of the factors contribution for energy consumption of the program.
Energy consumption varies somewhat from instruction to instruction.
The sequence of instructions has some influence.
The opcode and the locations of the operands also matter.
Steps to Improve Energy Consumption
Try to use registers efficiently(r4)
Analyze cache behavior to find major cache conflicts.
Make use of page mode accesses in the memory system whenever possible.
Moderate loop unrolling eliminates some loop control overhead. when the loop
is unrolled too much, power increases.
Software pipelining reducing the average energy per instruction.
Eliminating recursive procedure calls where possible saves power by getting rid
of function call overhead.
Tail recursion can often be eliminated, some compilers do this automatically.
3.8) ANALYSIS AND OPTIMIZATION OF PROGRAM SIZE
Memory size of a program is determined by the size of its data and instructions.
Both must be considered to minimize program size.
Data provide an opportunity to minimizing the size of program.
Data buffers can be reused at several different points in program, which reduces
program size.
Some times inefficient programs keep several copies of data, identifying and
eliminating duplications can lead to significant memory savings.
Minimizing the size of the instruction text and reducing the number of
instructions in a program which reduces program size
Proper instruction selection may reduce code size.
Special compilation modes produce the program in terms of the dense
instruction set.
Program size of course varies with the type of program, but programs using the
dense instruction set are often 70 to 80% of the size of the standard instruction
set equivalents.
3.9)PROGRAM VALIDATION AND TESTING
Complex systems need testing to ensure the working behavior of the
systems.
Software Testingused to generate a comprehensive set of tests to ensure
that our system works properly.
The testing problem is divided into sub-problems and analyze each sub
problem.
Types of testing strategies
1. White/Clear-box Testing generate tests ,based on the program
structure.
2. Black-box Testing generate tests ,without looking at the internal
structure of the program.
3.9.1)Clear box testing
Testingrequires the control/data flow graph of a program’s source code.
To test the program exercise both its control and data operations.
To execute and evaluate the tests control the variables in the program and
observe the results .
The following three things to be followed during a test
1. Provide the program with inputs for the test.
2. Execute the program to perform the test.
3. Examine the outputs to determine whether the test was successful.
Execution PathTo test the program by forcing the program to execute along
chosen paths. ( giving it inputs that it to take the appropriate branches)
Graph Theory
•It help us get a quantitative handle on the different paths required.
•Undirected graph-form any path through the graph from combinations of basis
paths.
•Incidence matrix contains each row and column represents a node.
•1 is entered for each node pair connected by an edge.
Cyclomatic Complexity
It is a software metric tool.
Used to measure the control complexity of a program.
M = e – n + 2p.
e number of edges in the flow graph
n number of nodes in the flow graph
p number of components in the graph
Types of Clear Box test strategy
1. Branch testing
2. Domain testing
3. Data flow testing
3.9.1.1)Branch testing
This strategy requires the true and false branches of a conditional.
Every simple condition in the conditional’s expression to be tested at
least once.
if ((x == good_pointer) && (x->field1 == 3))
{ printf("got the value\n"); }
The bad code we actually wrote
if ((x = good_pointer) && (x->field1 == 3))
{ printf("got the value\n"); }
3.9.1.2)Domain testing
It concentrates on linear-inequalities.
The program should use for the test is j <= i + 1
We test the inequality with three test points
Two on the boundary of the valid region
Third outside the region but between the i values of the other two points.
3.9.1.3)Data flow testing
It use of def-use analysis (definition-use analysis).
It selects paths that have some relationship to the program’s function.
Compilers which use def-use analysis for Optimization.
A variable’s value is defined when an assignment is made to the variable.
It is used when it appears on the right side of an assignment.
3.9.2)Block Box Testing
Black-box tests are generated without knowledge of the code being tested.
It have a low probability of finding all the bugs in a program.
We can’t test every possible input combination, but some rules help us select
reasonable sets of inputs.
1. Random Tests
Random values are generated with a given inputs.
The expected values are computed first, and then the test inputs are
applied.
2. Regression Tests
When tests are created during earlier or previous versions of the
system.
Those tests should be saved apply to the later versions of the system.
It simply exercise current version of the code and possibly exercise
different bugs.
In digital signal processing systems Signal processing algorithms are
implemented to save hardware costs.
Data sets can be generated for the numerical accuracy of the system.
These tests can often be generated from the original formulas without
reference to the source code.
1. Marilyn Wolf, “Computers as Components – Principles of
Embedded Computing System Design”, Third Edition “Morgan
Kaufmann Publisher (An imprint from Elsevier), 2012.
(UNIT I, II, III, V)
2.Jane W.S.Liu,‖ Real Time Systems‖, Pearson Education, Third
Indian Reprint, 2003.(UNIT IV)
UNIT IV REAL TIME SYSTEMS
Structure of a Real Time System – Estimating program run times –
Task Assignment and Scheduling – Fault Tolerance Techniques –
Reliability, Evaluation – Clock Synchronization.
Real Time Systems
It is a time-bound system which has well-defined, fixed time constraints.
It is required to complete the work on a time constraint.
Types:
1. Hard Real-Time Systems
Missing a deadline can cause a significant loss to the application.
Examples: Flight control, Nuclear Power plant, Manufacturing control
2. Soft Real-Time Systems
Missing a deadline causes the quality of service to degrade, but nothing terrible
happens.
Examples: Video-on-demand, web site service, satellite based applications,
teleconferencing
Characteristics of a RTS
Large and complex
Vary from a few hundred lines of assembler or C
Concurrent control of separate system components
Devices operate in parallel in the real-world
Facilities to interact with special purpose hardware
Need to be able to program devices in a reliable and
abstract way
Mixture of Hardware/Software
Some modules implemented in hardware, even whole
systems
Deterministic
Able to predict with confidence the worst case response
times for systems
Challenges in RT System
Predictability
Able to predict the future consequences of current actions
Testability
Easy to test if the system can meet all the deadlines
Cost optimality
e.g. Energy consumption, memory blocks etc
Maintainability
Modular structure to ease system modification
Fault tolerance
Hardware and software failures should not cause the system
4.1)Structure of a Real Time System
Trigger generator used to trigger the execution of individual jobs. It is
not really a separate hardware unit, typically it is part of the executive
software.
The schedule for these jobs can be obtained offline and loaded as a
lookup table to be used by the scheduler.
Jobs can also be initiated depending on the state of the controlled
process or on the operating environment.
The output of the computer is fed to the actuators and the displays.
Fault tolerant techniques ensure the erroneous outputs from the
computer.
The actuators typically have a mechanical or a hydraulic component,
and so their time constants are quite high.
A control computer exhibits a dichotomy in terms of the data rates.
The sensors and actuators run at relatively low data rates.
The computer itself must be fast enough to execute the control
algorithms, and these can require throughputs in excess of 50 million
instructions per second(MIPS).
System separates into three areas
An outer low rate area consisting of the sensors, actuators, displays and
input panels.
A middle or peripheral area consisting of the processing that is
necessary to format the data from and to this layer properly.
The central cluster of processors where the control algorithms are
executed.
4.2)Estimating program run times
Real-time systems should meet deadlines; it is important to be able to
accurately estimate program run times.
Estimating the execution time of any given program is a very difficult
task and it depends on the following factors
a)Source code
Source code that is carefully tuned and optimized takes less time to
execute.
b)Compiler
The compiler maps the source-level code into a machine-level
program.
The actual mapping will depend on the actual implementation of the
particular compiler that is being used.
c)Operating system
The operating system determines such issues as task scheduling and
memory management, and also it determines the interrupt handling
overhead
Machine architecture
Executing a program may require much interaction between the
processors and the memory and I/O devices.
The interaction can take place over an interconnection network (e.g., a
bus) that can be shared by other processors.
The number of registers per processor affects how many variables can
be held in the CPU.
The greater the number of registers and the cleverer the compiler is in
managing these registers.
This results in reducing the memory-access time, and hence the
instruction-execution time.
The size and organization of the cache (if any) will also affect the
memory-access time, as will the clock rate.
To keep the contents of these memories, we need to periodically
refresh them
This is done by periodically reading the contents of each memory
location and writing them
1. First, assume that the variables b and c are not already in
the CPU registers and have to be fetched from the cache or
the main memory.
2. Second, the execution times of individual instructions
could be loose because they are data dependent.
4.2.2)Timing Estimation system
Preprocessor
The pre-processor produces compiled assembly language code and
marks off blocks of code to be analyzed.
Parser
The parser analyzes the input source program.
Procedure timer
It maintains a table of procedures and their execution time
Loop bounds
It obtains number of iterations for the various loops in the system.
Time schema
It computes the execution times of each block using the execution time
estimates computed by the code prediction module.
Code prediction
The code prediction module does this by using the code generated by
the pre-processor and using the architecture analyzer to include the
influence of the architecture.
4.2.3) ACCOUNTING FOR PIPELINING
The first stage pipeline stage instructions
from the main memory and writes them to a
prefetch buffer.
The second stage handles the operand
read/write operations.
Both the first and second stages will thus
have occasion to access the memory.
if the second stage needs to read one or more
operands from main memory, there is a one
cycle delay in handshaking with the first
stage.
Similarly, if it needs to write some operands,
there is a one cycle handshaking delay.
if the second stage wishes to access the
memory it will wait for any ongoing opcode
fetches to finish before accessing the
memory.
4.2.3) CACHES
The time taken by access depends on whether or not the word being
accessed is in the cache.
If it is not, it is the time to access the main memory, which is much
larger.
It is difficult to predict whether a given access will result in a cache
miss, since the cache contents are not easy to predict.
To determine accurately the presence or absence of a data block thus
requires that we know the sequence of accesses.
Conditional branches-Determine the actual execution path of the
program.
Preemptions-When task A is preempted by task B, the blocks that were
brought into the cache by task A may have to be removed to make
room for B's accesses.
Then A resumes execution it will encounter a flurry of cache misses.
This can be avoided by giving each task its own portion of the cache so
that during its lifetime, each task "owns" its portion and no other task
is allowed access to it.
4.3)Task Assignment and Scheduling
Each task has resource requirements.
All tasks require some execution time on a processor.
Also, a task may require a certain amount of memory or access to a bus
Release Time
It is the time at which all the data that are required to begin executing
the task are available.
Deadline
It is the time by which the task must complete its execution.
It may be hard or soft, depending on the nature of the corresponding
task.
Classification of Task
i)Periodic
A task Ti is periodic if it is released every period Pi seconds.
It requires the task to run exactly once every period
ii)Sporadic
The task is sporadic if it is not periodic.(may be invoked at
irregular intervals)
These tasks are characterized by an upper bound on the
rate at which they may be invoked.
The successive invocations of a sporadic task T, be
separated in time by atleast t(i) seconds.
iii)Aperiodic
These tasks which are not periodic and which also have no
upper bound on their invocation rate.
Task Assignment/Schedule
It is said to be feasible if all the tasks start after their release times and complete
before their deadlines.
The schedule can be defined as follows S: Set of processors xTimeSet of Tasks
(i) Precomputed (offline scheduling)
Involves scheduling in advance of the operation, with specifications of when the
periodic tasks will be run and slots for the sporadic/aperiodic tasks in the event that
they are involved.
(ii) Dynamically (online Scheduling)
The tasks are scheduled as they arrive in the system.
The algorithms used in online scheduling must be fast and it takes to meet their
deadlines is clearly useless.
Algorithms
(1) Static priority algorithm-The task priority does not change within a mode.
Ex: Rate-Monotonic (RM) algorithm
(ii) Dynamic priority algorithm-The task priority can change with time.
Ex: Earliest Deadline First (EDF) algorithm.
4.3.1. Classical Uniprocessor Scheduling Algorithms
Uniprocessor scheduling is part of
the process of developing
multiprocessor schedule.
The goal of these algorithms is to
meet all task deadlines.
The following assumptions are made
for both the RM and EDF algorithms.
1. No task has any non-preemptive
section and the cost of preemption is
negligible.
2. Only processing requirements are
significant; memory, I/O and other
resource requirements are negligible,
3. All tasks are independent; there are
no precedence constraints.
4.3.1.a)Rate-Monotonic Scheduling
Algorithm(RMS)
It is a uniprocessor static-priority preemptive scheme.
The following assumptions are required for algorithm.
All tasks in the task set are periodic.
The relative deadline of a task is equal to its period.
The priority of a task is inversely related to its period.(If task Ti has a
smaller period than task Tj also Ti has higher priority than Tj. Higher
priority tasks can preempt lower-priority tasks)
Example
There are three tasks, with P, = 2, P₂ = 6, P, 10. The execution times are
e₁=0.5, e₂ = 2.0, e,= 1.75 and I1 = 0, I2=1, I3=3. Since P₁ <P₂ <P3, task T1
has highest priority. Every time it is released, it preempts whatever is
running on the processor. Similarly, task T3, cannot execute when
either task T₁ or T2, unfinished
Utilization Bound
If the total utilization of the tasks is no greater than n(2n-1), where n is
the number of tasks to be scheduled.
If, there may be task sets with a utilization greater than n(21/n - 1) that are
schedulable by the RM algorithm.
4.3.1.b) Preemptive Earliest Deadline First (EDF)
It is a dynamic priority scheduling algorithm.
The task priorities are not fixed but change depending on the closeness
of the absolute deadline.
EDF is also called the deadline monotonic scheduling algorithm
EDF is an optimal uniprocessor scheduling algorithm.
If EDF cannot feasibly schedule a task set on a uniprocessor, there is no
other scheduling algorithm that can.
If all the tasks are periodic and have relative deadline equal to their
periods, the test for task. Set schedulability is particularly simple.
If the total utilization of the task set is no greater than 1, the task set
can be feasibly scheduled on a single processor by the EDF algorithm.
4.3.2 Task Assignment Algorithm
Heuristics typically allocate according to some simple criterion
and checking an allocation for feasibility, we must account for
communication costs.
For example, suppose that T₁ <T₂, Task T₂ cannot start before
receiving task T1 output.
That is, if fi denotes the completion time of task Ti, and Cij is the
time to communicate from Ti to Tj
r2≥f1+c12
If tasks T₁ andT₂ are allocated to the same processor, then c12=0.
If they are allocated to separate processors, c12 is positive and
must be taken into account while checking for feasibility.
4.3.3a) Utilization-Balancing Algorithm
4.3.3b) Next-Fit Algorithm for RM Scheduling
Utilization based allocation heuristic that is meant specifically to be used
in conjunction with the rate-monotonic scheduling algorithm.
The multi processor is assumed to consist of identical processors and
tasks are assumed require no resources other than processor time.
Define M> 3 classes as follows, where M is placed by the user. Task Ti, is in
class j<M if
2 1/(j+1)+1) -1 ≤ei/Pi ≤2 ¹/j -1
Allocate tasks one by one to the appropriate processor class until all the
tasks have been scheduled, adding processors to classes if that is needed
for RM schedulability
4.3.3c) Bin-packing Assignment Algorithm for EDF
4.3.3d)Myopic Offline Scheduling (MOS) Algorithm
This algorithm suitable for non-preemptive tasks.It is an offline algorithm in
that takes in advance the entire set of tasks, their arrival times, execution times
and deadlines.
MOS proceeds by building up a schedule tree.
Each node in this tree represents an assignment and scheduling of a subset of
the tasks.
The root of the schedule tree is an empty schedule.
Each child of a node consists of a schedule of its parent node, extended by one
task.
A leaf of this tree consists of a schedule of the entire task set.
Algorithm steps
1. start at the root node, which is an empty schedule
2. Proceed to build the tree from that point by developing nodes.
A node n is developed as follows.
1. Given a node n, try to extend the schedule represented by that node by one
more task.
2.Pick up one of the as yet unscheduled tasks and try to add it to the schedule
represented by node n.
3. The augumented schedule is a child node of n.
4.3.3e) Focused Addressing and Bidding (FAB) Algorithm
It is used for task sets consisting of both critical and non-critical real
time tasks.
Critical tasks must have sufficient time reserved for them so that they
continue execute successfully.
The Non-critical tasks are either processed or not, depending on the
system's ability do so.
Each processor maintains a status table that indicates which
tasks(critical tasks and any additional noncritical tasks) it has already
committed to run.
It maintains a table of the surplus computational capacity at every
other processor in the system.
The time axis is divided into windows, which are intervals of fixed
duration and each processor regularly sends to its colleagues the
fraction of the next window that is currently free.
Since the system is distributed, this information may never be
completely up to date.
It also computes the latest time at which the focussed processor can
offload the task onto a bidder without the task deadline being missed.
Offload time is given by the expression.
toffload =Task deadline - (current time + time to move the task+ task-
execution time)
When processor P, receives an RFB, it checks to see if it can meet the
task requirements and still execute its already-scheduled tasks
successfully.
First, estimates when the new task will arrive and how long it will take
to be either guaranteed or rejected.
Arrive time is given by
tarr = Current time +time for bid to be received by Ps+ time taken by Ps
to make a decision+ time taken to transfer the task+ time taken by P, to
either guarantee or reject the task
computational time
tcomp = time allotted to critical tasks in [tarr ,D]+ time needed in [tarr,D]
to run already-accepted noncritical tasks+ fraction of recently accepted
bidsx time needed in [tarr, DJ to honor pending bids
4.4)Fault Tolerance Techniques
It is the ability of a system to maintain its functionality,even in the
presence of faults.
FaultIt is a defect or flow that occurs in some hardware or software
component.
ErrorIt is a manifestation of a fault.
FailureIt is a departure of a system from the service required.
Types of Faults
Hardware fault
It is some physical defect that can cause a component to malfunction.
A broken wire or the output of a logic gate that is perpetually stuck
some logic value (0 or 1) are hardware faults.
Software Faults
A software fault is a "bug" that can cause the program to fail for a given
set of inputs.
Faults latency
It is the duration between the onset of
a fault and its manifestation as an error.
Faults themselves are invisible to the
outside world, only showing themselves
when they cause errors such latency
can impact the reliability of the overall
system.
Error Recovery
It is the process by which the system
attempts to recover from the effects of an
error.
Forward error recovery- the error is masked
without any computations having to be
redone.
Backward error recovery- the system is
rolled back to a moment in time before the
error is believed to have occurred and the
computation is carried out again.
Failures Causes
(i) Errors in the specifications or design
(ii) Defects in the components and
(iii) Environmental effects
Fault Types
Faults are classified according to their temporal behavior and outpat
behavior.
Temporal Behaviour Classification
1.Permanent- does not die away with time but remains until it is repaired or
the affected unit is replaced
2. Intermittent- faults cycles between the fault active and fault benignstates.
3.TransientPermanent- It is hard to catch. Since quite often by the time the
system has recognized that such a failure has occurred it has disappeared,
leaving behind no permanent defect that can .be located
4.4.1)Fault detection
(i) Online detection
Goes on in parallel with normal system operation.
Fetching an opcode from a location containing data.
Writing into a portion of memory to which the process has no write access.
Fetching an illegal opcode.
Inactive for more than a prescribed period.
A monitor (watch dog processor) is associated with each processor, looking for signs
that the processor is faulty.
(ii) Offline detection
When a processor is running such a test, it obviously cannot be executing the
applications software.
Diagnostic tests can be scheduled just like ordinary tasks.
4.4.3) Fault and Error Containment
Fault containment
When a fault-free processor can put out erroneous result
of using erroneous input from a faulty unit.
i) Fault-containment zones (FCZ)
It is a subset of the system that operates correctly despite
arbitrary logical or electrical faults outside the subset.
ii) Error-containment zones (ECZ)
Used to prevent errors from propagating across zone
boundaries.
4.4.3)Redundancy
4.4.3.1)Hardware Redundancy
It is an additional hardware to compensate for failures.
It can be used in two ways.
1. First in use for fault detection, correction and masking.
2. The second is use of hardware redundancy is to replace the
malfunctioning units.
Multiple hardware units may be assigned to do the same task in parallel
and their results compared.
If only a minority of the units are faulty and a majority of the units we can
produce the same output, we can use this majority result .
If more than a minority of the units disagree, repeating the computation
on other processors, to correct for the faults.
Voting and Consensus
Multiple units execute the same task and compare their outputs.
If atleast three units are involved, this comparison can choose
the majority value a process called voting and thus mask the
effects of some failures.
If two units are used, the comparison can detect (but not correct)
an error.
The designer must decide whether exact or approximate
agreement is expected between functioning units.
Formalized majority voter- Assume that if d(x₁,x₂)≤ε then x1 and
x2 are sufficiently equal for all practical purposes
Generalized K-plurality voter- chooses any output from the
largest partition Pi,so long as Pi, contains atleast K elements
Generalized median voter-The generalized median voter works
by selecting the middle value.
Static pairing
The pair runs identical software using identical inputs and compares
the output of each task.
If the outputs are identical, the pair is functional.
If either processor the pair detects nonidentical outputs, that is an
indication that at least one of the processors in the pair is faulty.
The processor that detects this discrepancy switches off the interface
to the rest of the system, thus isolating this pair
N-Modular Redundancy(NMR)
It is a scheme for forward error recovery.
It works by using N processors instead of one and voting on their
output.
N is usually odd.
N-Voter Single Voter
Sift-out Redundancy
The comparator produces a total of(N/2)outputs, one output for each pair of
processors.
If the pair disagrees, the corresponding output line is 1, while it is 0 if the pair
produces a coincident output.
The detector is a circuit that disconnects a module that disagrees with the
majority. It recognizes this by analyzing the controller outputs.
The collector produces output by sifting out the processors that have been
disconnected by the detector.
Voting Sensor Values
A cluster of N=(2m+1) processors is
sufficient to guard against up to m
failures if the processor failures are not
malicious.
Suppose sensor 1 is maliciously faulty
and sensors 2 and 3 are good and
provide identical inputs to the three
voters.
Clusters with N voters are sometimes
called restoring organs, because they
produce N correct results as long as a
majority of the processors are
nonfaulty.
A voter should not wait until all the
inputs have been received.
If enough coincident signals are
received to make up a majority of the
number in the cluster, that is sufficient
NMR design alternatives
Memory modules are To write into a Every time there is a vote,
arranged so that a real memory module a there is the opportunity to
operation by a vote of the mask out an error.
processor. corresponding write A vote before read means
The output of these operations of the that up to one such failure
memories is voted on three processors can be masked.
and the processor carried out.
receives the result of Read can be done
the read. on just one
If a processor wishes to processor.
write, without affecting
the others
4.4.3.2)Software Redundancy
In software redundancy, there is the issue of cost.
Single version software is already more expensive than the
hardware in most large systems.
Demanding N versions of software for even small N can be
very expensive.
1. N-version programming
Involves running all N versions parallel voting on the
output.
2. Recovery block approach
This approach involves running only one version at any one
time.
N-version programming
When a system will fail whenever a majority of the
versions fails on input and so the probability of
common mode failure must be minimized.
1. Requirement specification- A mistake in the
specification causes a wrong output to be
delivered.
2. Programming language - The nature of the
language affects the programmer
3. Numerical algorithms- Algorithms implemented
to a finite precision can behave quite differently for
certain sets of inputs
4. Nature of the tools being used-If the same tools are
being used, the probability of common-mode
failure might increase.
5. Training and quality of the programmers- If
programmers have a low level of skill, this can
translate not only into an increased incidence of
errors but also into more common-mode failures
Recovery block approach
The primary software is run in the first instance.
It output is passed through an acceptance test, which is supposed to
indicate whether the output is acceptable or not.
This is the weakest point in the entire design, for the acceptance test
has no prior way of knowing what the correct output should be.
It makes sanity checks, these consists of making sure that the output is
within a certain acceptable range or that the output does not change at
more than the allowed maximum rate.
An alternative version need not always use the same inputs as the
primary, it may use other approaches to carry out the computation
4.4.3.3)Time Redundancy
The task schedule has some slack in it, so that some tasks can be rerun
if necessary and still meet critical deadlines.
Backward error recovery can take multiple forms. The simplest is retry,
where the failed instruction is repeated.
Other options include roiling the affected computation back to a
previous checkpoint and continuing from there, or restarting the
computation all the way from its beginning.
Critical to a successful implementation of backward error recovery is
the restoration of the state of the affected processor or system to what it
was before the error occurred.
Corrective action, such as assigning another processor to carry on with
the execution beyond this point or retrying on the same processor w
the corrected state information, can then be taken.
Recovery Points
One way of implementing backward
error recovery is to store the process
state at prespecified moments in
time, such snapshots are called
Checkpoint.
There are three checkpoints, taken at
recovery points, R₁,R2R3; these are
points to which we want to be able to
roll back the process.
If an error is identified, state
restoration is done by simply reading
the last checkpoint before the error is
known to have occurred.
If we don't know exactly when the
error occurred we might have to r
back all the way to the earliest
checkpoint that we have
In figure, an error in a processor occurs between checkpoints C, and
and is detected after C8.
If we know at that time that the error occurred between C3, and C4. the
proper action is to roll the processor back to the checkpoint
immediately preceding the onset of the error (i.e) to C3.
This presupposes two things.
We have enough memory available to keep checkpoints C3, to C8.
We know when the error occurred.
Due to limitations of memory, typically only the last one or two
checkpoints are kept. Also, there is no-way to know when the error
occurred unless we have some information.
When we do not know when the error occurred we can roll back to the
oldest checkpoint that is stored and hope that the error did not occur
prior to that time.
Otherwise, we have to roll all the way back to the starting point of the
computation (i.e) we will have to restart the computation.
The designer must decide when checkpoints are to be taken by
balancing the cost against the benefits.
The benefit in having many checkpoints taken at short intervals is that
the extent of the roll back is limited.
Another way is to use redundancy and voting to check that the output
is correct before the state is saved form the checkpoint.
Recovery Cache
One mechanism for
checkpointing incrementally
is the recovery cache.
Following figure illustrates
how this work.
Associated with each recovery
point is a recovery cache. The
recovery cache contains the
value, at the associated
recovery point of the variable
that are changed before the
next recovery point.
For example, consider that a
failure is detected at t2, and
the system decides to roll back
to R₁.
To restore the state to what it was at R₁, a set C to 35 and F to 40 from RC 2.
Then, we use RC 1 to set A to 100.
Suppose instead that the failure was detected at ₁, and the systemdecides to roll
back to R₁, check can be done in two ways.
1. The system can check the recovery cache to see if a value has been saved for
that variable.
2. To associate a flag with each variable, which is set whenever that variable has
been saved in the current recovery cache.
Discarding a recovery point when using recovery caches is also more
complicated than in checkpointing. Discarding a checkpoint only requires us
to throw away its contents.
Domino Effect
Thus far, we have assumed that each process
is independent, not working in operation
with any other process. If this is not the case
and the processes interact dings become
more complex.
There are two processes P1, and P₂, which
communicate as shown. An error is
discovered after t1, which forces P1, to roll
back to its previous recovery point.
However, to undo the process, the effects of
the message from P1, to P2,must also be
undone. The only way to do this is to roll
back P2, to its previous checkpoint.
If P2, is to be rolled back, everything it did
must be undone. This includes its message to
P1, at time to. But this causes everything done
by P1, after to be undone and P1, must roll
back to the checkpoint immediately
preceding to.
Both P1, to P2, are rolled back to the
Audit Trails
A second way of enabling backward error recovery is through audit
trails. These are especially popular in databases.
An audit trail consists of a record of all the actions that have been taken
by the system, together with a timestamp indicating when each action
was taken.
Backward recovery to some time t is effected by undoing actions taken
after time t and then restarting from that point.
4.4.3.4)Information Redundancy
The data are coded in such a way that a certain number of bit errors c be
detected and/or corrected.
The basic idea of information redundancy is to provide than is strictly necessary
and to use that extra information to check for errors, we use coding all the time
ourselves, while correcting for typographical errors.
All computer words are strings of 0’s and 1’s.
Coding ensures that not strings of 0’s and 1’s are legal (i.e. are valid). An illegal
combination of bits indicates an error.
Sometimes there is an unambiguous "nearest" valid word that the impermissible
combination can be read as, thus correcting the error.
Nearest is computed by defining the distance between two words as the number
of bit positions by which they differ. This is called the Hamming distance Hd
When accessing a coding scheme, we want to know how many extra bis it adds
to the words and how many bit errors it can detect or correct.
In a separable code, the coded word consists of the original word concatenated
with a number of code bits.
A non separable code does not have this property separability and is more
complex to decode.
Duplication
The simplest code of all is duplication. Each word is duplicated. An error in a bit
position is detected by the discrepancy between the bit and its duplicate.
Note that it is not possible to correct any errors. If a discrepancy is detected, we have no
way to know whether it is the bit or the duplicate that is in error.
Parity Coding
It is widely used in memory chips.
It consists of adding an extra bit (called the parity bit to each word to ensure that the
number of Is in it is always even (even parity) or add (odd parity).
Checksum
It is used when blocks of data are being transferred.
Sender computes the checksum, by adding together these words and transmits it along
with the words.
The receiver computes the check sum of the words that it with the check sum obtained
by the sender.
If two sums do not match an error is detected,
Cyclic Codes
In a cyclic code any cyclic shift of a valid code word will produce another valid code
word. Cyclic coding can be implemented with shift registers and exclusive OR gates.
Cyclic coding is carried out by multiplying the word to be coded by a polynomial, called
the generator polynomial. All additions in this process are modulo-2. Multiplication by
X essentially means shifting by n places.
4.5)Reliability, Evaluation
Computers used in life critical applications must be so reliable that they cannot
be validated by experiment alone.
To get around this difficulty, we use mathematical models of reliability.
We construct a mathematical model of the real time computer and solve it.
By doing this, we are adding one possible source of error the assumptions of the
mathematical model.
If there are not correct, neither will be the results of our model. It is with this
reservation in mind that we introduce reliability evaluation techniques. The
correctness of the predictions of the model.
4.5.1)OBTAINING PARAMETER VALUES
The first step in developing a model is to decide what the input parameters
should be.
A model should always be based on parameters that can either be accurately
measured or estimated with confidence.
4.5.1.2)Obtaining Device-Failure Rates
There are two ways to obtain device failure rates, collecting field data and life
cycle testing in the laboratory.
The former is more realistic, since it represents the failure rate when the
devices are being used in their normal operating conditions.
The latter is the only choice when the devices are new and field data do not
exist.
In the laboratory, devices can be subjected to "accelerated testing".
That is, to reduce the time it takes to gather the data, we can estimate this
acceleration factor, the failure rate under normal operating conditions can be
derived by calculations based on these accelerated data.
4.5.1.3)Measuring Error Propagation Time
To measure how quickly an error can propagate,
we use fault injection.
Special purpose hardware is used to simulate a
fault on a selected line. The status of the related
lines is monitored using logic Analyzers to
determine how far and how quickly the error
propagates.
The flow of errors can be expressed via a
directed graph.
Consider the flow graph, which shows that what
happens to an error that originates at A and
propagates to B and C.
This error spawns an error in the output of these
processors and the output of C causes an error
in the output of D.
Finally, module E receives erroneous input from
B and D, and puts out an erroneous result.
The time taken by a module to output an error
in response to an erroneous output is a function
of the module software and the task schedule.
Reliability models for hardware redundancy
In order to model the reliability of a system,
we must express the reliability of each of its
components and take into account the impact
of the failure of each component on the
functioning of the overall system.
Permanent Faults Only
1)Series-Parallel Systems
Let us begin with systems represented in
series parallel form.
A set f components is connected in series if
the failure any of them will result in syst
failure.
A parallel connection of components requires
the components to fail bef the system fails.
In figure (a), the system fails if any of the
components C₁, C₂ or C3 fails.
In figure (b), it fails only if all of the
components C₁ C₂ C3, and C4 fail.
SOFTWARE ERROR MODELS
Software error models predict the rate at which software faults will
produce errors and are meant to determine when to stop debugging, by
providing some guidance on the reliability of the software at each stage
of debugging.
Software error models express the error rate as a function of the
number of faults in the software. As the software is debugged and the
number of faults changes. So does the error rate.
More complex models take into account the fact that the error
generation rate depends not only on the number of faults but on where
those faults are placed in the program.
Some faults are in parts of the program that are frequently executed
and those will have a high error generation rate.
It is possible for software to have a substantial number of faults and to
produce no errors for long stretches of time.
4.6) Clock Synchronisation
4.6.1)SYNCHRONIZATION
4.6.2)NON FAULT TOLERANT SYNCHRONIZATION ALGORITHM
Consider the following simple procedure for synchronization.
At regular intervals of T, each clock sends out its timing signals to the other clocks.
A clock compares its own timing signals with those it receives from the others and
adjusts itself appropriately.
For the moment assume that the signal propagation times are zero consider a three-
clock system, where ti, is the Real time when clock Ci sends its signal.
The middle clock is chosen as the correct clock, and the other two t align themselves
with this clock.
It is tempting to do this by having each clock correct as soon as it can by moving
clock C1, back by t2-t₁ at real time t2 and clock C3, forward t3-t2 at Real time t3
However, this is not acceptable, since a process which was using clock C3, would see
time moving moving backwards.
For example, suppose this process time stamped event X at Real time tx
and event Y at real time ty .
Y occurs after X, but due to the
clock adjustment, its time stamp
will make it appear as if occured
before X.
This illustrates why we should
never turn a clock back in the
process of synchronization. It is also
a bad idea to introduce a jump in
the clock.
Instead of making such immediate,
and inadvisable, adjustments, we
amortize the adjustments (i.e) we
adjust the clocks so that at the next
comparison point, they try to be
aligned.
Clock C₁ will slow itself down and
clock C3, will speed itself up so that
their next clock ticks will align as
closely as possible with the next
clock tick of clock C₂.
An interval of nominal duration TC- units may actually be anything in the
range [1-ρ) T, (1 + ρ) T] r- units. Hence C1 can deliver its next clock tick in the r-
interval.
I₁=[(1- ρ) T+t₂+μ₂,1- x, (1 + ρ)T + t₂ + μ₂,1-x]
By a similar reasoning, C3, delivering its next clock tick in the r-interval
I2=[(1- ρ) T+t₂+μ₂,3- x, (1 + ρ)T + t₂ + μ₂,3-x]
Clock C₂ delivers its next clock tick in the r-interval
I2=[(1- ρ) T+t₂, (1 + ρ)T + t₂ ]
In the worst case, if μ₂,1 = μmin and clock C1 is running as fast as is legally
allowed, the next C1, tick will occur at r-time (1- ρ)T+t₂+ μmin –x and also
C3, is running as slow as is legally allowed, the next C3, tick will occur r time
(1+ρ)T+t₂+ μmin –x
The clock skew will then be
[(1+ρ)T+t₂+ μmax –x]-[(1- ρ) T+t₂+ μmin –x ]=2 Ρt+ μmax –μmin
FAULT-TOLERANT SYNCHRONIZATION IN HARDWARE
To synchronize in hardware, we can use phase-locked loops.
The objective is to align, as closely as possible, the output of the
oscillator with an oscillatory signal input.
The comparator puts out a signal that is proportional to the difference
between the phase of the input and that of the oscillator.
This is passed through a filter, and the resultant signal is used to
modify the frequency of a voltage-controlled oscillator (VCO).
Let us carry out a simple analysis of phase-locked loops.
The output voltage of the comparator at any time is proportional to the
difference between the phase of the signal input, ϕr(t), and that of the
VCO , ϕr(t)
Vc(t)= Kc{(ϕi(t)-ϕr(t)}
SYNCHRONIZATION IN SOFTWARE
When the extremely tight synchronization is provided by phase-
locking is not needed, synchronization can be carried out in software.
In software based synchronization, we have an underlying hardware
clock, and a software based correction. The clock time is the sum of the
hardware time and the correction.
A new correction is calculated at regular resynchronization intervals. It
is sometimes helpful to think of the process as starting a new clock at
every resynchronization interval, defined by the new correction value.
For example, consider the following equation
y≥α+β+ αβ
If α and β are very small quantities, then αβ is even smaller, and so
above equation can be rewritten
y≥α+β
Interactive convergence Averaging Algorithm CA1
Interactive Convergence Averaging Algorithm- CA2
Algorithm CA2 differs from CA1 in which clock signals are ignored.
In CA1, a clock ignores those time messages that differ from its own by
specified amount Δ.
In CA2, a clock ignores the first m and the last messages.
The clock is aligned with a reference equal to the averaging of the clad signals
that are not ignored.
The CA2 algorithm is as follows.
Every time its clock reads a multiple of the resynchronization interval a clock
transmits its timing message to all the clocks in the system.
Message-transmission delays range from μmin to μmax
Define the average delay μavg =(μmin + μmax )/2
N is the total number of clocks and m is the maximum number of malicious
clocks that this system is designed to tolerate.
Clock Ci, receives a time message from Cj, at real time t(i,j)
It computes the quantities a (i,j) =t (i,j)- μavg and sorts them ascending order
Convergence Nonaveraging Algorithm-CAN
The CAN algorithm ensures the synchronization of nonfaulty clocks,
regardless of the number of faulty clocks in the system.
To do this, it uses encoding to authenticate messages.
That is a clock sends out an encoded timing signal that cannot be altered by
any other clock.
CAN algorithm, does not require that there be a direct link between two
communicating clocks.
It is sufficient that there be either a one-hop path or a multi-hop path.
If we define a graph with the clocks as the nodes and the clock-to-clock
connections as directed edges, it is sufficient for the graph to be connected.
A clock labels or signs each message that it sends out, so that the recipient
knows who the sender is.
This signature is encoded so that no other clock can alter it.
A message is said to be authentic when neither the message nor the signature
has been altered; the encoding is assumed to allow clocks to detect any
alternations.
As with convergence averaging algorithms, resynchronization happens regular
intervals. Each node starts a new logical clock resynchronization.
The algorithm consists of each clock adjusting itself suitably based the
messages it receives from the other clocks.
Resynchronization happens at least once every interval of length Unless it has
been preempted each nonfaulty clock C, waits un value equals some
prespecified waiting point w.
At that time, it sends out an encoded signed message saying, "the time W", to
all its neighbouring processors.
It then defines a new resynchronization point bound by incrementing by R. W
is a local variable, held at each clock.
A message that has passed through S clocks is sufficiently close if t arrives
within SD of clock C, 's waiting point, where D is a prespecified constant.
If this message is authentic, clock C, moves itself forward to W increments W
by R, and forwards the message to all its neighbours after adding its own
signature to it.
UNIT V
PROCESSES AND OPERATING SYSTEMS
Introduction – Multiple tasks and multiple processes – Multirate systems-
Preemptive real-time operating systems- Priority based scheduling-
Interprocess communication mechanisms – Evaluating operating
system performance- power optimization strategies for processes –
Example Real time operating systems-POSIX-Windows CE-Distributed
embedded systems – MPSoCs and shared memory multiprocessors. –
Design Example - Audio player, Engine control unit – Video accelerator.
5.1)INTRODUCTION
Simple applications can be programmed on a microprocessor by writing a single
piece of code.
But for a complex application, multiple operations must be performed at widely
varying times.
Two fundamental abstractions that allow us to build complex applications on
microprocessors.
1. Process→ defines the state of an executing program
2. operating system (OS)→provides the mechanism for switching execution
between the processes.
5.2)MULTIPLE TASKS AND MULTIPLE
PROCESSES
Systems which are capable of performing multiprocessing known as multiple
processor system.
Multiprocessor system can execute multiple processes simultaneously with the
help of multiple CPU.
Multi-tasking→ The ability of an operating system to hold multiple processes
in memory and switch the processor for executing one process.
3.2.1)Tasks and Processes
Task is nothing but different parts of functionality in a single system.
Eg-Mobile Phones
When designing a telephone answering machine, we can define recording a
phone call ,answering a call and operating the user’s control panel as distinct
tasks, at different rates.
Each application in a system is called a task.
5.2.2)Process
A process is a single execution of a program.
If we run the same program two different times, we have created two
different processes.
Each process has its own state that includes not only its registers but all
of its memory.
In some OSs, the memory management unit is used to keep each
process in a separate address space.
In others, particularly lightweight RTOSs, the processes run in the
same address space.
Processes that share the same address space are often called threads.
This device is connected to serial ports on both ends.
The input to the box is an uncompressed stream of bytes.
The box emits a compressed string of bits, based on a compression table.
Ex: compress data being sent to a modem.
The program’s need to receive and send data at different rates
Eg→The program may emit 2 bits for the first byte and then 7 bits for the
second byte— will obviously find itself reflected in the structure of the code.
if we spend too much time in packaging and emitting output characters,we
may drop an input character.
5.2.3)Asynchronous input
Ex:A control panel on a machine provides a different type of rate.
The control panel of the compression box include a compression mode button
that disables or enables compression, so that the input text is passed through
unchanged when compression is disabled.
Sampling the button’s state too slowly→ machine will miss a button
depression entirely.
Sampling it too frequently→ the machine will do incorrectly compress data.
To solve this problem→ every n times the compression loop is executed.
5.3)Multi-rate Systems
In operating system implementing code for satisfies timing requirements is
more complex when multiple rates of computation must be handled.
Multirate embedded computing systems→Ex: automobile engines, printers,
and cell phones.
In all these systems, certain operations must be executed periodically with its
own rate.
Eg→Automotive engine control
The simplest automotive engine controllers, such as the ignition controller for a
basic motorcycle engine, perform only one task—timing the firing of the spark
plug, which takes the place of a mechanical distributor.
Spark Plug
The spark plug must be fired at a certain point in the combustion cycle.
Microcontroller
Using a microcontroller that senses the engine crankshaft position allows the
spark timing to vary with engine speed.
Firing the spark plug is a periodic process.
Engine controller
Automobile engine controllers use additional sensors, including the gas pedal
position and an oxygen sensor used to control emissions.
They also use a multimode control scheme. one mode may be used for engine
warm-up, another for cruise, and yet another for climbing steep hills.
The engine controller takes a variety of inputs that determine the state of the
engine.
It then controls two basic engine parameters: the spark plug firings and the
fuel/air mixture.
Task performed by engine controller unit
5.3.1)Timing Requirements on Processes
Processes can have several different types of timing requirements based on the
application.
The timing requirements on a set of processes strongly depends on the type of
scheduling.
A scheduling policy must define the timing requirements that it uses to
determine whether a schedule is valid.
1. Release time→
The time at which the process becomes ready to execute.
simpler systems→ the process may become ready at the beginning of the period.
sophisticated systems→ set the release time at the arrival time of certain data, at
a time after the start of the period.
2. Deadline
specifies when a computation must be finished.
The deadline for an a periodic process is generally measured from the release
time or initiation time.
The deadline for a periodic process may occur at the end of the period.
The period of a process is the time between successive executions.
The process’s rate is the inverse of its period.
In a Multi rate system, each process executes at its own distinct rate.
Example definitions of release times and deadlines
A sequence of processes with a high initiation rate
•In this case, the initiation interval is equal to one fourth of the period.
•It is possible for a process to have an initiation rate less than the period even in
single-CPU systems.
•If the process execution time is less than the period, it may be possible to initiate
multiple copies of a program at slightly offset times.
Data dependencies among processes
•The data dependencies define a partial ordering on process execution.
•P1 and P2 can execute in any order but must both complete before P3, and P3
must complete before P4.
•All processes must finish before the end of the period.
Directed Acyclic Graph (DAG)
•It is a directed graph that contains no cycles.
•The data dependencies must form a directed acyclic graph.
•A set of processes with data dependencies is known as a task graph.
Communication among processes at different rates
(MPEG audio/Video)
•The system decoder process demultiplexes the audio and video data and
distributes it to the appropriate processes.
•Missing Deadline
•Missing deadline in a multimedia system may cause an audio or video glitch.
•The system can be designed to take a variety of actions when a deadline is
missed.
5.3.2)CPU Metrics
CPU metrics are described by initiation time and completion time.
Initiation time→It is the time at which a process actually starts executing on
the CPU.
Completion time→It is the time at which the process finishes its work.
The CPU time of process i is called Ci .
The CPU time is not equal to the completion time minus initiation time.
The total CPU time consumed by a set of processes is
The simplest and most direct measure is utilization.
5.3.3)Process State and Scheduling
The first job of the OS is to determine that process runs next.
The work of choosing the order of running processes is known as scheduling.
There three basic scheduling ,such as waiting, ready and executing.
A process goes into the waiting state when it needs data that it has finished all its work for
the current period.
A process goes into the ready state when it receives its required data, when it enters
a new period.
Finally a process can go into the executing state only when it has all its data, is ready to
run, and the scheduler selects the process as the next process to run.
5.3.4)Scheduling Policies
A scheduling policy defines how processes are selected for promotion from the
ready state to the running state.
Scheduling→Allocate time for execution of the processes in a system .
For periodic processes, the length of time that must be considered is the hyper period,
which is the least-common multiple of the periods of all the processes.
Unrolled schedule →The complete schedule for the least-common multiple of the
periods.
Types of scheduling
1. Cyclostatic scheduling or Time Division Multiple Access scheduling
Schedule is divided into equal-sized time slots over an interval equal to the length of the
hyperperiod H. (run in the same time slot)
Two factors affect this scheduling
The number of time slots used
The fraction of each time slot that is used for useful work.
2)Round Robin-scheduling
Uses the same hyper period as does cyclostatic.
It also evaluates the processes in order.
If a process does not have any useful work to do, the scheduler moves on to the next
process in order to fill the time slot with useful work.
All three processes execute during the first hyperperiod.
During the second one, P1 has no useful work and is skipped so P3 is directly move on to
the next process.
Scheduling overhead
The execution time required to choose the next execution process, which is incurred in
addition to any context switching overhead.
To calculate the utilization of CPU
5.4)Preemptive Real-Time Operating
Systems(RTOS)
A pre emptive OS →solves the fundamental problem in multitasking system.
It executes processes based upon timing requirements provided by the system designer.
To meet timing constraints accurately is to build a preemptive OS and to use priorities to
control what process runs at any given time.
5.4.1) Preemption
Preemption is an alternative to the C function call to control execution.
To be able to take full advantage of the timer, change the process as something more than
a function call.
Break the assumptions of our high-level programming language.
Create new routines that allow us to jump from one subroutine to another at any point in
the program.
The timer, will allow us to move between functions whenever necessary based upon the
system’s timing constraints.
5.4.2) Kernel
It is the part of the OS that determines what process is running.
The kernel is activated periodically by the timer.
It determines what process will run next and causes that process to run.
5.4.3) Priorities
Based on the priorities →kernel can do the processes sequentially.
which ones actually want to execute and select the highest priority process that is ready
to run.
This mechanism is both flexible and fast.
The priority is a non-negative integer value.
•When the system begins execution,P2 is the only ready process, so it is selected for execution.
•At T=15, P1 becomes ready; it preempts P2 because p1 has a higher priority, so it execute
immediately
•P3’s data arrive at time 18, it has lowest priority.
•P2 is still ready and has higher priority than P3.
•Only after both P1 and P2 finish can P3 execute
5.4.4) Context Switching
To understand the basics of a context switch, let’s assume that the set of tasks is
in steady state.
Everything has been initialized, the OS is running, and we are ready for a timer
interrupt.
This diagram shows the application tasks, the hardware timer, and all the
functions in the kernel that are involved in the context switch.
vPreemptiveTick() → it is called when the timer ticks.
portSAVE_CONTEXT()→ swaps out the current task context.
vTaskSwitchContext ( ) →chooses a new task.
portRESTORE_CONTEXT()→ swaps in the new context
5.5) PRIORITY-BASED SCHEDULING
Operating system is to allocate resources in the computing system based on
the priority.
After assigning priorities, the OS takes care of the rest by choosing the highest-
priority ready process.
There are two major ways to assign priorities.
Static priorities→ that do not change during execution
Dynamic priorities→ that do change during execution
Types of scheduling process
1. Rate-Monotonic Scheduling
2. Earliest-Deadline-First Scheduling
5.5.1)Rate-Monotonic Scheduling(RMS)
Rate-monotonic scheduling (RMS)→ is one of the first scheduling policies
developed for real-time systems.
RMS is a static scheduling policy.
It assigns fixed priorities are sufficient to efficiently schedule the processes in
many situations.
RMS is known as rate-monotonic analysis (RMA), as summarized below.
All processes run periodically on a single CPU.
Context switching time is ignored.
There are no data dependencies between processes.
The execution time for a process is constant.
All deadlines are at the ends of their periods.
The highest-priority ready process is always selected for execution.
Priorities are assigned by rank order of period, with the process with the
shortest period being assigned the highest priority.
Example-Rate-monotonic scheduling
set of processes and their characteristics
According to RMA →Assign highest priority for least execution period.
Hence P1 the highest priority, P2 the middle priority,and P3 the lowest priority.
First execute P1 then P2 and finally P3.(T1>T2>T3)
After assigning priorities, construct a time line equal in length to hyper period, which is 12
in this case.
Every 4 time intervals P1 executes 1 units.(Execution time intervals for
P1 0-4,4-8,8-12)
Every 6 time intervals P2 executes 2 units. .(Execution time intervals
for P2 0-6,6-12)
Every 12 intervals P3 executes 3 units. .(Execution time intervals for P3
0-12)
Time interval from 10-12 no scheduling available because no process
will be available for execution. All process are executed already.
P1 is the highest-priority process, it can start to execute immediately.
After one time unit, P1 finishes and goes out of the ready state until the start of its next
period.
At time 1, P2 starts executing as the highest-priority ready process.
At time 3, P2 finishes and P3 starts executing.
P1’s next iteration starts at time 4, at which point it interrupts P3.
P3 gets one more time unit of execution between the second iterations of P1 and P2, but
P3 does not get to finish until after the third iteration of P1.
Consider the following different set of execution times.
In this case, Even though each process alone has an execution time significantly less than
its period, combinations of processes can require more than 100% of the available CPU
cycles.
During one 12 time-unit interval, we must execute P1 -3 times, requiring 6 units of CPU
time; P2 twice, costing 6 units and P3 one time, costing 3 units.
The total of 6 + 6 + 3 = 15 units of CPU time is more than the 12 time units available,
clearly exceeding the available CPU capacity(12units).
RMA priority assignment analysis
Response time→ The time at which the process finishes.
Critical instant→The instant during execution at which the task has the largest response
time.
Let the periods and computation times of two processes P1 and P2 be τ1, τ2 and T1, T2,
with τ 1 < τ 2.
let P1 have the higher priority. In the worst case we then execute P2 once during its period
and as many iterations of P1 as fit in the same interval.
Since there are τ2/ τ1 iterations of P1 during a single period of P2.
The required constraint on CPU time, ignoring context switching overhead, is
we give higher priority to P2, then execute all of P2 and all of P1 in one of P1’s periods in
the worst case.
Total CPU utilization for a set of n tasks is
5.5.2)Earliest-Deadline-First Scheduling(EDF)
Earliest deadline first (EDF)→ is a dynamic priority scheme.
It changes process priorities during execution based on initiation times.
As a result, it can achieve higher CPU utilizations than RMS.
The EDF policy is also very simple.
It assigns priorities in order of deadline.
Assign highest priority to a process who has Earliest deadline.
Assign lowest priority to a process who has farthest deadline.
After assigning scheduling procedure, the highest-priority process is chosen for
execution.
Consider the following Example
Hyper-period is 60
Dead line Table
There is one time slot left at t= 30, giving a CPU utilization of 59/60.
EDF can achieve 100% utilization
RMS vs. EDF
Ex:Priority inversion
Low-priority process blocks execution of a higher priority process by keeping hold
of its resource.
Consider a system with two processes
Higher-priority P1 and the lower-priority P2.
Each uses the microprocessor bus to communicate to peripherals.
When P2 executes, it requests the bus from the operating system and receives it.
If P1 becomes ready while P2 is using the bus, the OS will preempt P2 for P1,
leaving P2 with control of the bus.
When P1 requests the bus, it will be denied the bus, since P2 already owns it.
Unless P1 has a way to take the bus from P2, the two processes may deadlock.
Eg:Data dependencies and scheduling
Data dependencies imply that certain combinations of processes can never occur. Consider the
simple example.
We know that P1 and P2 cannot execute at the same time, since P1 must finish before P2 can
begin.
P3 has a higher priority, it will not preempt both P1 and P2 in a single iteration.
If P3 preempts P1, then P3 will complete before P2 begins.
if P3 preempts P2, then it will not interfere with P1 in that iteration.
Because we know that some combinations of processes cannot be ready at the same time,
worst-case CPU requirements are less than would be required if all processes could be ready
simultaneously.
5.5)Inter-process communication mechanisms
It is provided by the operating system as part of the process abstraction.
Blocking Communication→ The process goes into the waiting state until it receives a
response
Non-blocking Communication→It allows a process to continue execution after
sending the communication.
Types of inter-process communication
1. Shared Memory Communication
2. Message Passing
3. Signals
5.5.1) Shared Memory Communication
The communication between inter-process is used by bus-based system.
CPU and an I/O device, communicate through a shared memory location.
The software on the CPU has been designed to know the address of the shared location.
The shared location has also been loaded into the proper register of the I/O device.
If CPU wants to send data to the device, it writes to the shared location.
The I/O device then reads the data from that location.
The read and write operations are standard and can be encapsulated in a procedural
interface.
CPU and the I/O device want to communicate through a shared memory block.
There must be a flag that tells the CPU when the data from the I/O device is ready.
The flag value of 0 when the data are not ready and 1 when the data are ready.
If the flag is used only by the CPU, then the flag can be implemented using a standard
memory write operation.
If the same flag is used for bidirectional signaling between the CPU and the I/O device,
care must be taken.
Consider the following scenario to call flag
1. CPU reads the flag location and sees that it is 0.
2. I/O device reads the flag location and sees that it is 0.
3. CPU sets the flag location to 1 and writes data to the shared location.
4. I/O device erroneously sets the flag to 1 and overwrites the data left by the CPU.
Ex: Elastic buffers as shared memory
The text compressor is a good example of a shared memory.
The text compressor uses the CPU to compress incoming text, which is then sent on a
serial line by a UART.
The input data arrive at a constant rate and are easy to manage.
But the output data are consumed at a variable rate, these data require an elastic buffer.
The CPU and output UART share a memory area—the CPU writes compressed characters
into the buffer and the UART removes them as necessary to fill the serial line.
Because the number of bits in the buffer changes constantly, the compression and
transmission processes need additional size information.
CPU writes at one end of the buffer and the UART reads at the other end.
The only challenge is to make sure that the UART does not overrun the buffer.
5.5.2) Message Passing
Here each communicating entity has its own message send/receive unit.
The message is not stored on the communications link, but rather at the senders/ receivers
at the end points.
Ex:Home control system
It has one microcontroller per household device—lamp, thermostat, faucet, appliance.
The devices must communicate relatively infrequently.
Their physical separation is large enough that we would not naturally think of them as
sharing a central pool of memory.
Passing communication packets among the devices is a natural way to describe
coordination between these devices.
5.5.3) Signals
Generally signal communication used in Unix .
A signal is analogous to an interrupt, but it is entirely a software creation.
A signal is generated by a process and transmitted to another process by the OS.
A UML signal is actually a generalization of the Unix signal.
Unix signal carries no parameters other than a condition code.
UML signal is an object, carry parameters as object attributes.
The sigbehavior( ) →behavior of the class is responsible for throwing the signal,
as indicated by<<send>>.
The signal object is indicated by the <<signal>>
5.6)Evaluating operating system performance
Analysis of scheduling policies is made by the following 4 assumptions
Assumed that context switches require zero time. Although it is often
reasonable to neglect context switch time when it is much smaller than the
process execution time, context switching can add significant delay in some
cases.
We have largely ignored interrupts. The latency from when an interrupt is
requested to when the device’s service is complete is a critical parameter of real
time performance.
We have assumed that we know the execution time of the processes.
We probably determined worst-case or best-case times for the processes in
isolation.
5.6.1)Context switching time
It depends on following factors
The amount of CPU context that must be saved.
Scheduler execution time.
5.6.2)Interrupt latency
Interrupt latency →It is the duration of time from the assertion of a device interrupt to
the completion of the device’s requested operation.
Interrupt latency is critical because data may be lost when an interrupt is not serviced in
a timely fashion.
A task is interrupted by a device.
The interrupt goes to the kernel, which may need to finish a protected operation.
Once the kernel can process the interrupt, it calls the interrupt service routine (ISR),
which performs the required operations on the device.
Once the ISR is done, the task can resume execution.
Several factors in both hardware and software affect interrupt latency:
The processor interrupt latency
The execution time of the interrupt handler
Delays due to RTOS scheduling
RTOS delay the execution of an interrupt handler in two ways.
Critical sections and interrupt latency
Critical sections in the kernel will prevent the RTOS from taking interrupts.
Some operating systems have very long critical sections that disable interrupt handling for
very long periods.
If a device interrupts during a critical section, that critical section must finish before the
kernel can handle the interrupt.
The longer the critical section, the greater the potential delay.
Critical sections are one important source of scheduling jitter because a device may
interrupt at different points in the execution of processes and hit critical sections at
different points.
Interrupt priorities and interrupt latency
A higher-priority interrupt may delay a lower-priority interrupt.
A hardware interrupt handler runs as part of the kernel, not as a user thread.
The priorities for interrupts are determined by hardware.
Any interrupt handler preempts all user threads because interrupts are part of the CPU’s
fundamental operation.
We can reduce the effects of hardware preemption by dividing interrupt handling into
two different pieces of code.
Interrupt service handler (ISH)→ performs the minimal operations required to
respond to the device.
Interrupt service routine (ISR)→ Performs updating user buffers or other more
complex operation.
RTOS performance evaluation tools
Some RTOSs provide simulators or other tools that allow us to view the
operation of the processes,context switching time, interrupt response time,
and other overheads.
Windows CE provides several performance analysis tools
An instrumentation routine in the kernel that measures both interrupt service
routine and interrupt service thread latency.
OS Bench measures the timing of operating system tasks such as critical
section access, signals, and so on
Kernel Tracker provides a graphical user interface for RTOS events.
Ex: Scheduling and context switching overhead
set of processes and their characteristics
let us try to find a schedule assuming that context switching time is zero
Now let us assume that the total time to initiate a process, including context switching
and scheduling policy evaluation, is one time unit.
•It is easy to see that there is no feasible schedule for the above release time sequence, since
we require a total of 2TP1 + TP2= 2 x (1+ 3) + (1 +3) = 11 time units to execute one period of P2
and two periods of P1.
Overhead was a large fraction of the process execution time and of the periods.
In most real-time operating systems, a context switch requires only a few hundred
instructions, with only slightly more overhead for a simple real-time
scheduler like RMS.
When the overhead time is very small relative to the task periods,
then the zero-time context switch assumption is often a reasonable approximation
assuming an average number of context switches per process and computing CPU
utilization can provide at least an estimate of how close the system is to CPU
capacity
Ex:Effects of scheduling on the cache
Consider a system containing the following three processes.
Each process uses half the cache, so only two processes can be in the cache at the same
time.
Appearing below is a first schedule that uses a least-recently-used cache replacement
policy on a process-by-process basis.
In the first iteration, we must fill up the cache, but even in subsequent iterations,
competition
among all three processes ensures that a process is never in the cache when it starts to
execute. As a result, we must always use the worst-case execution time.
Another schedule in which we have reserved half the cache for P1 is shown below. This
leaves P2 and P3 to fight over the other half of the cache.
In this case, P2 and P3 still compete, but P1 is always ready. After the first iteration, we
can use the average-case execution time for P1, which gives us some spare CPU time that
could be used for additional operations.
5.7)Power optimization strategies for processes
A power management policy is a strategy for determining when to perform
certain power management operations.
The system can be designed based on the static and dynamic power
management mechanisms.
Power saving straegies
Avoiding a power-down mode can cost unnecessary power.
Powering down too soon can cause severe performance penalties.
Re-entering run mode typically costs a considerable amount of time.
A straightforward method is to power up the system when a request is received.
Predictive shutdown
The goal is to predict when the next request will be made and to start the
system just before that time, saving the requestor the start-up time.
Make guesses about activity patterns based on a probabilistic model of
expected behavior.
This can cause two types of problems
The requestor may have to wait for an activity period.
In the worst case,the requestor may not make a deadline due to the delay
incurred by system
An L-shaped usage distribution
A very simple technique is to use fixed times.
If the system does not receive inputs during an interval of length Ton, it shuts down.
Powered-down system waits for a period Toff before returning to the power-on mode.
In this distribution, the idle period after a long active period is usually very short, and the
length of the idle period after a short active period is uniformly distributed.
Based on this distribution, shutdown when the active period length was below a threshold,
putting the system in the vertical portion of the L distribution.
Advanced Configuration and Power Interface (ACPI)
It is an open industry standard for power management services.
It is designed to be compatible with a wide variety of OSs.
A decision module →determines power management actions.
ACPI supports the following five basic global power states.
1. G3, the mechanical off state, in which the system consumes no power.
2. G2, the soft off state, which requires a full OS reboot to restore the machine to
working condition. This state has four sub-states:
S1, a low wake-up latency state with no loss of system context
S2, a low wake-up latency state with a loss of CPU and system cache state
S3, a low wake-up latency state in which all system state except for main
memory is lost.
S4, the lowest-power sleeping state, in which all devices are turned off.
3. G1, the sleeping state, in which the system appears to be off.
4. G0, the working state, in which the system is fully usable.
5. The legacy state, in which the system does not comply with ACPI.
5.8)Example Real time operating systems
5.8.1)POSIX
POSIX is a Unix operating system created by a standards organization.
POSIX-compliant operating systems are source-code compatible.
Application can be compiled and run without modification on a new POSIX
platform.
It has been extended to support real time requirements.
Many RTOSs are POSIX-compliant and it serves as a good model for basic
RTOS techniques.
The Linux operating system has a platform for embedded computing.
Linux is a POSIX-compliant operating system that is available as open source.
Linux was not originally designed for real-time operation .
Some versions of Linux may exhibit long interrupt latencies,
To improve interrupt latency,A dual-kernel approach uses a specialized kernel,
the co-kernel, for real-time processes and the standard kernel for non-real-
time processes.
Process in POSIX
A new process is created by making a copy of an existing process.
The copying process creates two different processes both running the same code.
The complex task is to ensuring that one process runs the code intended for the new process
while the other process continues the work of the old process .
Scheduling in POSIX
A process makes a copy of itself by calling the fork() function.
That function causes the operating system to create a new process (the child process) which is
a nearly exact copy of the process that called fork() (the parent process).
They both share the same code and the same data values with one exception, the return value
of fork().
The parent process is returned the process ID number of the child process, while the child
process gets a return value of 0.
We can therefore test the return value of fork() to determine which process is the child
childid = fork();
if (childid == 0) { /* must be the child */
/* do child process here */
}
execv() function takes as argument the name of the file that holds the child’s
code and the array of arguments.
It overlays the process with the new code and starts executing it from the
main() function.
In the absence of an error, execv() should never return.
The code that follows the call to perror() and exit(), take care of the case where
execv() fails and returns to the parent process.
The exit() function is a C function that is used to leave a process
childid = fork();
if (childid == 0) { /* must be the child */
execv(“mychild”,childargs);
perror(“execv”);
exit(1);
}
The wait functions not only return the child process’s status, in many
implementations of POSIX they make sure that the child’s resources .
The parent stuff() function performs the work of the parent function.
childid = fork();
if (childid == 0) { /* must be the child */
execv(“mychild”,childargs);
perror(“execl”);
exit(1);
}
else { /* is the parent */
parent_stuff(); /* execute parent functionality */
wait(&cstatus);
exit(0);
}
The POSIX process model
Each POSIX process runs in its own address space and cannot directly access the
data or code.
Real-time scheduling in POSIX
POSIX supports real-time scheduling in the POSIX_PRIORITY_SCHEDULING
resource.
POSIX supports Rate-monotonic scheduling in the SCHED_FIFO scheduling
policy.
It is a strict priority-based scheduling scheme in which a process runs until it is
preempted or terminates.
The term FIFO simply refers→ processes run in first-come first-served order.
POSIX semaphores
POSIX supports semaphores and also supports a direct shared memory mechanism.
POSIX supports counting semaphores in the _POSIX_SEMAPHORES option.
A counting semaphore allows more than one process access to a resource at a time.
If the semaphore allows up to N resources, then it will not block until N processes have
simultaneously passed the semaphore;
The blocked process can resume only after one of the processes has given up its
semaphore.
When the semaphore value is 0, the process must wait until another process gives up the
semaphore and increments the count.
POSIX pipes
Parent process uses the pipe() function to create a pipe to talk to a child.
Each end of a pipe appears to the programs as a file.
The pipe() function returns an array of file descriptors, the first for the write end and the
second for the read end.
POSIX also supports message queues under the _POSIX_MESSAGE_PASSING facility..
5.8.2)Windows CE
Windows CE is designed to run on multiple hardware platforms and
instruction set architectures.
It supports devices such as smart phones, electronic instruments etc..,
Applications run under the shell and its user interface.
The Win32 APIs manage access to the operating system.
OEM Adaption Layer (OAL)→ provides an interface to the hardware and software
architecture.
OAL → provides services such as a real-time clock, power management, interrupts, and a
debugging interface.
A Board Support Package (BSP) for a particular hardware platform includes the OAL and
drivers.
Memory Space
It support for virtual memory with a flat 32-bit virtual address space.
A virtual address can be statically mapped into main memory for key kernel-mode code.
An address can also be dynamically mapped, which is used for all user-mode and some
kernel-mode code.
Flash as well as magnetic disk can be used as a backing store
The top 1 GB is reserved for system elements such as DLLs, memory mapped files, and
shared system heap.
The bottom 1 GB holds user elements such as code, data, stack, and heap.
User address space in windows CE
Threads are defined by executable files while drivers are defined by
dynamically-linked libraries (DLLs).
A process can run multiple threads.
Threads in different processes run in different execution
environments.
Threads are scheduled directly by the operating system.
Threads may be launched by a process or a device driver.
A driver may be loaded into the operating system or a process.
Drivers can create threads to handle interrupts
Each thread is assigned an integer priority.
0 is the highest priority and 255 is the lowest priority.
Priorities 248 through 255 are used for non-real-time threads .
The operating system maintains a queue of ready processes at each
priority level.
Execution of a thread can also be blocked by a higher-priority thread.
Tasks may be scheduled using either of two policies: a thread runs until the end
of its quantum; or a thread runs until a higher-priority thread is ready to run.
Within each priority level, round-robin scheduling is used.
WinCE supports priority inheritance.
When priorities become inverted, the kernel temporarily boosts the priority of
the lower-priority thread to ensure that it can complete and release its
resources.
Kernel will apply priority inheritance to only one level.
If a thread that suffers from priority inversion in turn causes priority inversion
for another thread, the kernel will not apply priority inheritance to solve the
nested priority inversion.
Sequence diagram for an interrupt
Interrupt handling is divided among three entities
The interrupt service handler (ISH)→ is a kernel service that provides the first
response to the interrupt.
The ISH selects an interrupt service routine (ISR) to handle the interrupt.
The ISR in turn calls an interrupt service thread (IST) which performs most of
the work required to handle the interrupt.
The IST runs in the OAL and so can be interrupted by a higher-priority
interrupt.
ISR→determines which IST to use to handle the interrupt and requests the
kernel to schedule that thread.
The ISH then performs its work and signals the application about the updated
device status as appropriate.
kernel-mode and user-mode drivers use the same API.
5.9) Distributed Embedded Systems (DES)
It is a collection of hardware and software and its communication.
It also has many control system performance.
Processing Element (PE)is a basic unit of DES.
It allows the network to communicate.
PE is an instruction set processor such as DSP,CPU and Microcontroller.
Network abstractions
Networks are complex systems.
It provide high-level services such as data transmission from the other
components in the system.
ISO has developed a seven-layer model for networks known as Open Systems
Interconnection (OSI) models.
5.9.1)OSI model layers
Physical layer→ defines the basic properties of the
interface between systems, including the physical
connections, electrical properties & basic procedures
for exchanging bits.
Data link layer→ used for error detection and control
across a single link.
Network layer→ defines the basic end-to-end data
transmission service.
Transport layer→ defines connection-oriented
services that ensure that data are delivered in the
proper order .
Session layer→ provides mechanisms for controlling
the interaction of end-user services across a network,
such as data grouping and checkpointing.
Presentation layer→ layer defines data exchange
formats
Application layer→ provides the application interface
between the network and end-user programs.
5.9.2)Controller Area Network(CAN)Bus
It was designed for automotive electronics
and was first used in production cars in 1991.
It uses bit-serial transmission.
CAN can run at rates of 1 Mbps over a twisted
pair connection of 40 meters.
An optical link can also be used.
5.9.2.1)Physical-electrical organization of a CAN
bus
Each node in the CAN bus has its own
electrical drivers and receivers that connect
the node to the bus in wired-AND fashion.
When all nodes are transmitting 1s, the bus is
said to be in the recessive state.
when a node transmits a 0s, the bus is in the
dominant state.
5.9.2.2)Data Frame
Arbitration field→ The first field in the packet contains the packet’s destination address 11 bits
Remote Transmission Request (RTR) bit is set to 0 if the data frame is used to request data
from the destination identifier.
When RTR = 1, the packet is used to write data to the destination identifier.
Control field→ 4-bit length for the data field with a 1 in between.
Data field→0 to 64 bytes, depending on the value given in the control field.
CRC→ It is sent after the data field for error detection.
Acknowledge field →identifier signal whether the frame was correctly received.( sender puts a
bit (1) in the ACK slot , if the receiver detected an error, it put (0) value)
Arbitration
It uses a technique known as Carrier Sense Multiple Access with Arbitration on Message
Priority (CSMA/AMP).
When a node hears a dominant bit in the identifier when it tries to send a recessive bit, it
stops transmitting.
By the end of the arbitration field, only one transmitter will be left.
The identifier field acts as a priority identifier, with the all-0 having the highest priority
Error handling
An error frame can be generated by any node that detects an error on the bus.
Upon detecting an error, a node interrupts the current transmission.
Error flag field followed by an error delimiter field of 8 recessive bits.
Error delimiter field allows the bus to return to the quiescent state so that data frame
transmission can resume.
Overload frame signals that a node is overloaded and will not be able to handle the next
message. Hence the node can delay the transmission of the next frame .
5.9.2.3)Architecture of a CAN controller
The controller implements the physical and data link layers.
CAN does not need network layer services to establish end-to-end
connections.
The protocol control block is responsible for determining when to send
messages, when a message must be resent and when a message should
be received.
5.9.3) I2C bus
I2C bus→ used to link microcontrollers
into systems.
I2C is designed to be low cost, easy to
implement, and of moderate speed (up to
100kbps for the standard bus and up to
400 kbps for the extended bus).
Serial data line (SDL) for data
transmission.
Serial clock line (SCL)→ indicates when
valid data are on the data line.
Every node in the network is connected to
both SCL and SDL.
Some nodes may act as bus masters .
Other nodes may act as slaves that only
respond to requests from masters.
5.9.3.1)Electrical interface to the I2C bus
Both bus lines are defined by an electrical signal.
Both bus signals use open collector/open drain
circuits.
The open collector/open drain circuitry allows a slave
device to stretch a clock signal during a read.
The master is responsible for generating the SCL
clock.
The slave can stretch the low period of the clock.
It is a multi master bus so different devices may act
as the master at various times.
Master drives both SCL and SDL when it is sending
data.
When the bus is idle, both SCL and SDL remain
high.
When two devices try to drive either SCL or SDL ,
the open collector/open drain circuitry prevents
errors.
Each master device make sure that it is not
interfering with another message.
5.9.3.2)Format of an I2C address transmission
Every I2C device has an separate address.
A device address is 7 bits and 1 bit for read/write data.
The address 0000000 ,which can be used to signal all devices simultaneously.
The address 11110XX is reserved for the extended 10-bit addressing scheme.
5.9.3.3)Bus transactions on the I2C bus
When a master wants to write a slave, it transmits the slave’s address followed by the data.
When a master send a read request with the slave’s address and the slave transmit the data.
Transmission address has 7-bit and 1 bit for data direction.( 0 for writing from the master to
the slave and 1 for reading from the slave to the master)
A bus transaction is initiated by a start signal and completed with an end signal.
A start is signaled by leaving the SCL high and sending a 1 to 0 transition on SDL.
A stop is signaled by setting the SCL high and sending a 0 to 1 transition on SDL.
5.9.3.4)State transition graph for an I2C bus master
Starts and stops must be paired.
A master can write and then read by sending a start after the data transmission, followed
by another address transmission and then more data.
5.9.3.5)Transmitting a byte on the I2C bus
The transmission starts when SDL is pulled low while SCL remains high.
The clock is pulled low to initiate the data transfer.
At each bit, the clock goes high while the data line assumes its proper value of 0 or 1.
An acknowledgment is sent at the end of every 8-bit transmission, whether it is an
address or data.
After acknowledgment, the SDL goes from low to high while the SCL is high, signaling
the stop condition.
5.9.3.6)I2C interface in a microcontroller
System has a 1-bit hardware interface with routines for byte-level functions.
I2C device used to generates the clock and data.
Application code calls routines to send an address, data byte, and also generates the SCL
,SDL and acknowledges.
Timers is used to control the length of bits on the bus.
When Interrupts used in master mode, polled I/O may be acceptable.
If no other pending tasks can be performed, because masters initiate their own transfers.
5.9.4)ETHERNET
It is widely used as a local area network for general-purpose computing.
It is also used as a network for embedded computing.
It is particularly useful when PCs are used as platforms, making it possible to use
standard components, and when the network does not have to meet real-time
requirements.
It is a bus with a single signal path.
It supports both twisted pair and coaxial cable.
Ethernet nodes are not synchronized, if two nodes decide to transmit at the same
time,the message will be ruined.
5.9.4.1)Ethernet CSMA/CD algorithm
A node that has a message waits for the
bus to become silent and then starts
transmitting.
It simultaneously listens, and if it hears
another transmission that interferes with
its transmission, it stops transmitting and
waits to retransmit.
The waiting time is random, but weighted
by an exponential function of the number
of times the message has been aborted
5.9.4.2)Ethernet-Packet format
Preamble→ 56-bit of alternating 1 and 0 bits, allowing devices on the network
to easily synchronize their receiver clocks.
SFD→8-bit ,indicates the beginning of the Ethernet frame
Physical or MAC addresses → destination and the source( 48-bit length)
Length data payload→The minimum payload is 42 octets
5.9.5)INTERNET PROTOCOL(IP)
It is the fundamental protocol on the Internet.
It provides connection orientded, packet-based
communication.
It transmits packet over different networks from
source to destination.
It allows data to flow seamlessly from one end user to
another.
When node A wants to send data to node B, the data
pass through several layers of the protocol stack to
get to the Internet Protocol.
IP creates packets for routing to the destination,
which are then sent to the data link and physical
layers.
A packet may go through many routers to get to its
destination.
IP works at the network layer → does not
guarantee that a packet is delivered to its
destination.
It supports best-effort routing packets→ packets
that do arrive may come out of order.
5.9.5.1)IP packet structure
Version→ it ia s 4-bit field.used to identify v4 or v6.
Header Length (HL)→It is a 4 bits, field.Indicates the length of the header.
Service Type→it is a 8 bit field ,used to specify the type of service.
Total length→Including header and data payload is 65,535 bytes.
Identification→ identifying the group of fragments of a single IP datagram.
Flags→ bit 0 Reserved.
bit 1: Don't Fragment (DF)
bit 2: More Fragments (MF)
Fragment Offset→ It is 13 bits long , specifies the offset of a particular fragment relative to
the beginning of the original unfragmented IP datagram
Time To Live (TTL)→It is a 8 bit wide, indicates th datagram's lifetime
Protocol→ protocol used in the data portion of the IP datagram
Header Checksum→(16 bit) used for error-checking of the header
Source address→ Sender packet address(32-bits size)
Destination address→ Receiver packet address(32-bits size)
5.9.5.2) Transmission Control Protocol(TCP)
It provides a connection-oriented service.
It ensures that data arrive in the appropriate order.
It uses an acknowledgment protocol to ensure that packets arrive.
TCP is used to provide File Transport Protocol (FTP) for batch file transfers.
Hypertext Transport Protocol (HTTP) for World Wide Web service.
Simple Mail Transfer Protocol (SMTP) for email.
Telnet for virtual terminals.
User Datagram Protocol (UDP), is used to provide connection-less services.
Simple Network Management Protocol (SNMP) provides the network management services.
5.10) MPSoCs and shared memory multiprocessors
Shared memory processors are well-suited to applications that require a large amount
of data to be processed(Signal processing systems )
Most MPSoCs are shared memory systems.
Shared memory allows for processors to communicate with varying patterns.
If the pattern of communication is very fixed and if the processing of different steps is
performed in different units, then a networked multiprocessor may be most appropriate.
If one processing element is used for several different steps, then shared memory also
allows the required flexibility in communication.
5.10.1)Heterogeneous shared memory multiprocessors
Many high-performance embedded platforms are heterogeneous multiprocessors.
Different processing elements (PE)perform different functions.
PEs may be programmable processors with different instruction sets or specialized
accelerators.
Processors with different instruction sets can perform different tasks faster and using less
energy.
Accelerators provide even faster and lower-power operation for a narrow range of
functions.
5.10.2)Accelerators
It is the important processing element for embedded multiprocessors.
It can provide large performance increases for applications with computational kernels .
It can also provide critical speedups for low-latency I/O functions.
CPU(host) accelerator is attached to the CPU bus.
CPU talks to the accelerator through data and control registers in the accelerator.
Control registers allow the CPU to monitor the accelerator’s operation and to give the
accelerator commands.
The CPU and accelerator may also communicate via shared memory.
The accelerator operate on a large volume of data with efficient data in memory.
Accelerator read and write memory directly .
The CPU and accelerator use synchronization mechanisms to ensure that they do not
destroy each other’s data.
An accelerator is not a co-processor.
A co-processor is connected to the internals of the CPU and processes instructions.
An accelerator interacts with the CPU through the programming model interface.
It does not execute instructions.
CPU and accelerators performs computations for specification.
CPU accelerators in a system
5.10.2)Accelerator Performance Analysis
The speed factor of accelerator will depend on the following factors.
Single threaded→CPU is in idle state while the accelerator runs.
Multithreaded→CPU do some useful work in parallel with accelerator.
Blocking→ CPU’s scheduler block other operations wait for the accelerator call to
complete.
Non-blocking→ CPU’s run some other work parallel with accelerator.
Data dependencies allow P2 and P3 to run independently on the CPU.
P2 relies on the results of the A1 process that is implemented by the accelerator.
Single-threaded→ CPU blocks to wait for the accelerator to return the results of its
computation.t, it doesn’t matter whether P2 or P3 runs next on the CPU.
Multithreaded → CPU continues to do useful work while the accelerator runs, so the CPU
can start P3 just after starting the accelerator and finish the task earlier.
5.10.3)Components of execution time for an accelerator
Execution time of a accelerator depends on the
time required to execute the accelerator’s
function.
It also depends on the time required to get the
data into the accelerator and back out of it.
Accelerator will read all its input data, perform
the required computation,and write all its results.
Total execution time given as
tacccel=tx+tin+tout
tx →execution time of the accelerator
Tin →times required for reading the required
variables
tout- →times required for writing the required
variables
5.10.4)System Architecture Framework
Architectural design depends on the application.
An accelerator can be considered from two angles.
Accelerator core functionality
Accelerator interface to the CPU bus.
The accelerator core typically operates off internal
registers.
Requirement of number of registers is an important
design decision.
Main memory accesses will probably take multiple
clock cycles.
Status registers used to test the accelerator’s state and
to perform basic operations(starting, stopping, and
resetting the accelerator)
A register file in the accelerator acts as a buffer between
main memory and the accelerator core.
Read unit can read the accelerator’s requirements and
load the registers with the next required data.
Write unit can send recently completed values to main
memory.
5.10.5)cache problem in an accelerated system
CPU cache can cause problems for
accelerators.
1. The CPU reads location S.
2. The accelerator writes S.
3. The CPU again reads S.
If the CPU has cached location S ,the
program will not see the value of S
written by the accelerator. It will instead
get the old value of S stored in the cache.
To avoid this problem, the CPU’s cache
must update the cache by setting cache
entry is invalid.
5.10.6)Scheduling and allocation
Designing a distributed embedded system, depends upon the scheduling and allocation
of resources.
We must schedule operations in time, including communication on the network and
computations on the processing elements.
The scheduling of operations on the PEs and the communications between the PEs are
linked.
If one PE finishes its computations too late, it may interfere with another communication
on the network as it tries to send its result to the PE that needs it.
This is bad for both the PE that needs the result and the other PEs whose communication
is interfered with.
We must allocate computations to the processing elements.
The allocation of computations to the PEs determines what communications are
required—if a value computed on one PE is needed on another PE, it must be
transmitted over the network.
We can specify the system as a task graph. However, different processes may end up on
different processing elements. Here is a task graph
We have labeled the data transmissions on each arc ,We want to execute the task on the
platform below.
The platform has two processing elements and a single bus connecting both PEs. Here
are the process speeds:
As an initial design, let us allocate P1 and P2 to M1 and P3 to M2This schedule shows
what happens on all the processing elements and the network.
The schedule has length 19. The d1 message is sent between the processes internal to
P1 and does not appear on the bus.
Let’s try a different allocation. P1 on M1 and P2 and P3 on M2. This makes P2 run more
slowly. Here is the new schedule:.
The length of this schedule is 18, or one time unit less than the other schedule. The
increased computation time of P2 is more than made up for by being able to transmit a
shorter message on the bus. If we had not taken communication into account when
analyzing total execution time, we could have made the wrong choice of which processes
to put on the same processing element.
5.11) Audio player/MP3 Player
5.11.1)Operation and requirements
MP3 players use either flash memory or disk drives to store music.
It performs the following functions such as audio storage, audio decompression, and
user interface.
Audio compression→ It is a lossy process. The coder eliminates certain features of the audio
stream so that the result can be encoded in fewer bits.
Audio decompression→ The incoming bit stream has been encoded using a Huffman style
code, which must be decoded.
Masking→ One tone can be masked by another if the tones are sufficiently close in frequency.
Audio compression standards
Layer 1 (MP1) →uses a lossless compression of sub bands and simple masking model.
Layer 2 (MP2) →uses a more advanced masking model.
Layer 3 (MP3)→ performs additional processing to provide lower bit rates.
5.11.2)MPEG Layer 1 encoder
Filter bank→ splits the signal into a set of 32 sub-
bands that are equally spaced in the frequency
domain and together cover the entire frequency
range of the audio.
Encoder→It reduce the bit rate for the audio
signals.
Quantizer →scales each sub-band( fits within 6
bits ), then quantizes based upon the current scale
factor for that sub-band.
Masking model → It is driven by a separate Fast
Fourier transform (FFT), the filter bank could be
used for masking, a separate FFT provides better
results.
The masking model chooses the scale factors for
the sub-bands, which can change along with the
audio stream.
Multiplexer→ output of the encoder passes along
all the required data.
MPEG Layer 1 data frame format
A frame carries the basic MPEG data, error correction codes, and additional information.
After disassembling the data frame, the data are un-scaled and inverse quantized to
produce sample streams for the sub-band.
5.11.3)MPEG Layer 1 decoder
•After disassembling the data frame, the data are un-
scaled and inverse quantized to produce sample
streams for the sub-band.
•An inverse filter bank then reassembles the sub-bands
into the uncompressed signal.
User interface→ MP3 player is simple both the
physical size and power consumption of the device.
Many players provide only a simple display and a few
buttons.
File system→ player generally must be compatible
with PCs. CD/MP3 players used compact discs that had
been created on PCs.
5.11.4)Requirements
5.11.5) Specification
The File ID class is an abstraction of a file in the flash file system.
The controller class provides the method that operates the player.
5.11.6) State diagram for file display and selection
This specification assumes that all files are in the root directory and that all files are
playable audio.
5.11.7) State diagram for Audio Playback
It refers to sending the samples to the audio system.
Playback and reading the next data frame must be overlapped to ensure continuous operation.
The details of playback depend on the hardware platform selected, but will probably involve a
DMA transfer.
5.11.8) System architecture
The audio controller includes two processors.
The 32-bit RISC processor is used to perform system control and audio decoding.
The 16-bit DSP is used to perform audio effects such as equalization.
The memory controller can be interfaced to several different types of memory.
Flash memory can be used for data or code storage.
DRAM can be used to handle temporary disruptions of the CD data stream.
The audio interface unit puts out audio in formats that can be used by A/D converters.
General- purpose I/O pins can be used to decode buttons, run displays.
5.11.9) Component design and testing
The audio output system should be tested separately from the compression system.
Testing of audio decompression requires sample audio files.
The standard file system can either implement in a DOS FAT or a new file system.
While a non-standard file system may be easier to implement on the device, it also
requires software to create the file system.
The file system and user interface can be tested independently .
5.11.20) System integration and debugging
It ensure that audio plays smoothly and without interruption.
Any file access and audio output that operate concurrently should be separately tested,
ideally using an easily recognizable test signal.
5.12)Engine Control Unit
This unit controls the operation of a
fuel-injected engine based on
several measurements taken from
the running engine.
5.12.1)Operation and
Requirements
The throttle is the command input.
The engine measures throttle,
RPM, intake air volume, and other
variables.
The engine controller computes
injector pulse width and spark.
5.12.2)Requirements
5.12.3)Specification
The engine controller must deal with processes at different rates
ΔNE and ΔT to represent the change in RPM and throttle position.
Controller computes two output signals, injector pulse width PW and spark advance
angle S.
S=k2X ΔNE-k3VS
The controller then applies corrections to these initial values
If intake air temperature (THA) increases during engine warm-up, the controller reduces
the injection duration.
If the throttle opens, the controller temporarily increases the injection frequency.
Controller adjusts duration up or down based upon readings from the exhaust oxygen
sensor (OX).
5.12.4)System architecture
The two major processes, pulse-
width and advance-angle,
compute the control parameters
for the spark plugs and injectors.
Control parameters rely on
changes in some of the input
signals.
Physical sensor classes used to
compute these values.
Each change must be updated at
the variable’s sampling rate.
5.12.5)State diagram for throttle position sensing
Throttle sensing, which saves both the
current value and change in value of
the throttle.
5.12.6)State diagram for injector pulse
width
In each case, the value is computed
in two stages, first an initial value
followed by a correction.
State diagram for spark advance angle
5.12.7)Component design and testing
Various tasks must be coded to satisfy the requirements of RTOS processes.
Variables that are maintained across task execution, such as the change-of-state
variables, must be allocated and saved in appropriate memory locations.
Some of the output variables depend on changes in state, these tasks should be tested
with multiple input variable sequences to ensure that both the basic and adjustment
calculations are performed correctly.
5.12.8)System integration and testing
Engines generate huge amounts of electrical noise that can cripple digital electronics.
They also operate over very wide temperature ranges.
1. hot during engine operation,
2. potentially very cold before the engine is started.
Any testing performed on an actual engine must be conducted using an engine
controller that has been designed to withstand the harsh environment of the engine
compartment.
5.13)Video Accelerator
It is a hardware circuits on a display adapter that speed up fill motion video.
Primary video accelerator functions are color space conversion, which converts YUV to RGB.
Hardware scaling is used to enlarge the image to full screen and double buffering which
moves the frames into the frame buffer faster.
Video compression
•MPEG-2 forms the basis for U.S. HDTV
broadcasting.
• This compression uses several
component algorithms together in a
feedback loop.
•Discrete cosine transform (DCT) used in
JPEG and MPEG-2.
•DCT used a block of pixels which is
quantized for lossy compression.
•Variable-length coder→assign number of
bits required to represent the block.
5.13.1)Block motion Estimation
MPEG uses motion to encode one frame in
terms of another.
Block motion estimation→some frames are
sent as modified forms of other frames
During encoding, the frame is divided into
macro blocks.
Encoder uses the encoding information to
recreate the lossily-encoded picture, compares
it to the original frame, and generates an error
signal.
Decoder keep recently decoded frames in
memory so that it can retrieve the pixel values
of macro-blocks.
5.13.2).Concept of Block motion estimation
To find the best match between regions in the two frames.
Divide the current frame into 16 x 16 macro blocks.
For every macro block in the frame, to find the region in the previous frame that most
closely matches the macro block.
Measure similarity using the following sum-of-differences measure
M(i,j) → intensity of the macro block at pixel i,j,
S(i,j) → intensity of the search region
N→ size of the macro block in one dimension
<ox, oy>→offset between the macro block and search region
We choose the macro block position relative to the search area that gives us the smallest
value for this metric.
The offset at this chosen position describes a vector from the search area center to the
macro block's center that is called the motion vector.
5.13.3)Algorithm and requirements
C code for a single search, which assumes that the search region does not extend past the
boundary of the frame.
The arithmetic on each pixel is simple, but we have to process a lot of pixels.
If MBSIZE is 16 and SEARCHSIZE is 8, and remembering that the search distance in each
dimension is 8 + 1 + 8, then we must perform
5.13.4)Requirements
5.13.5)Specification
Specification for the system is relatively straightforward because the algorithm is simple.
The following classes used to describe basic data types in the system motion vector,
macro block, search area.
5.13.6)Sequence Diagram
The accelerator provides a behavior
compute-mv() that performs the block
motion estimation algorithm.
After initiating the behavior, the accelerator
reads the search area and macro block from
the PC, after computing the motion vector,
it returns it to the PC.
5.13.7)Architecture
The macro block has 16 x16 = 256.
The search area has (8 + 8 + 1 + 8 + 8)2 =
1,089 pixels.
FPGA probably will not have enough
memory to hold 1,089 (8-bit )values.
The machine has two memories, one for
the macro block and another for the
search memories.
It has 16 processing elements that
perform the difference calculation on a
pair of pixels.
Comparator sums them up and selects
the best value to find the motion vector.
5.13.8)System testing
Testing video algorithms requires a large amount of data.
we are designing only a motion estimation accelerator and not a complete video
compressor, it is probably easiest to use images, not video, for test data.
use standard video tools to extract a few frames from a digitized video and store them in
JPEG format.
Open source for JPEG encoders and decoders is available.
These programs can be modified to read JPEG images and put out pixels in the format
required by your accelerator.
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