Slide 1:

Types of SRAM

Slide 2

Introduction

• SRAM is a memory device whose memory locations will hold their information as long
as power is applied and can be directly accessed by putting the appropriate address on the
address bus

• Its density gives the capacity of the SRAM

• The size and number of memory locations is given by the depth X width

• SRAM’s are more expensive than DRAM’s, but they are much faster

Slide 3

Types of SRAM
SRAMs basically come in two different flavors: synchronous and asynchronous.
Let us discuss both the types one by one

Slide 4

• The timing of an asynchronous SRAM is completely controlled by the CPU and does not
depend on the state of a clock

• The CPU sets up the address, enables the SRAM and pulses it to read data out or write
data in

• It will begin to read or write information into the memory as soon as it receives the
instruction to do so

Slide 5

• Slow Asynchronous SRAMs are typically designed to consume very low power and are
used in applications where power is a major concern

• Applications for these SRAMs include cellular phones, PDAs, radios, and pagers. In
these applications, these devices are used for temporary data storage

• Fast Asynchronous SRAMs are often used in buffer memory applications, Tag RAM for
PC caches, etc.
Slide 6 Synchronous SRAMs

• In which, all control signals, data, and address are linked with the clock signals
• The device will read and write information into the memory only on particular states of
the clock
• The particular state changes when the clock switches, i.e., when it goes from either
LOW-to-HIGH (“rising edge”), or from HIGH-to-LOW (“falling edge”)

Slide 7

• Synchronous SRAMs have internal registers, which latch the inputs on every clock edge
(either rising or falling) and, depending on the implementation, will sometimes have
registers on the data output lines

The system clock provides the timing of a synchronous SRAM. This is the same clock that
provides timing to the CPU and other peripherals in the system. The CPU still supplies the
address and enables the SRAM, but the clock controls the transfer of data. This master clock
control allows the entire system to run more efficiently and thus at higher speeds than
asynchronous systems.

Slide 8

Types of Synchronous SRAMs

Variety of synchronous SRAM are available. These devices are synchronized with an external
clock. Unlike asynchronous devices, synchronous SRAMs have internal registers, which latch
the inputs on every clock edge (either rising or falling) and, depending on the implementation,
will sometimes have registers on the data output lines. They are as follows. We will discuss
them one by one

• Single Data Rate SRAMs

• Pipelined

• Burst SRAMs

• Double Data Rate SRAMs

• ZBT SRAM

• Flow-through SRAMs
Slide 9

Pipelined SRAMs

SRAM’s may have pipelined outputs.

Pipelined SRAMs (sometimes called register to register mode SRAMs) add a register between
the memory array and the output

Pipelined SRAMs are less expensive than standard SRAMs for equivalent electrical
performance

The pipelined design does not require the aggressive manufacturing process of a standard
SRAM, which contributes to its better overall yield.

Slide 10

SRAM’s with pipelined outputs have a register on the output to hold the data read out of the
memory. Upon the conclusion of the read cycle the data is latched into the holding register
using the next clock pulse. Once the data is in the register it is available to the external system
via the data bus. . In other words, the output data will be clocked into a register before it is sent
onto the data lines. It adds one clock cycle to the process of doing a read. For pipelined
SRAMs, a write occurs in one clock cycle, while a read occurs in two.

With the pipelined SRAM, a four-word burst read takes five clock cycles.

Slide 11 Flowthrough SRAM

• If the SRAM has flow-through outputs data from the memory cells is immediately
available on the data bus at the conclusion of a read cycle

• A flowthrough SRAM does not have output registers. Data that is sent out from the
memory array is immediately placed on the external data lines. For a flowthrough
synchronous SRAM, a write again takes one cycle, while a read will also take one cycle

Slide 12

• Data that is sent out from the memory array is immediately placed on the external data
lines. For a flowthrough synchronous SRAM, a write again takes one cycle, while a read
will also take one cycle. SRAMs with flow-through outputs will output data from an
initial read request faster than a pipelined SRAM because the register loading step is not
required.
Slide 13 Burst mode

• Some SRAM’s also come with a burst mode capability for read and write

• This becomes useful when several data words are accessed in a predefined sequence.

• It is possible to retrieve up to four words of data from the memory on one command

• Burst SRAMs can be pipelined or flowthrough.

Slide 14

• These SRAM’s have an internal counter that allows them to read or write four locations
worth of data using only one address input.

• When a valid address is put on the address bus and burst mode is active, the SRAM will
write to or read from the location specified by the address. The internal counter will be
incremented to generate the next location address and the read or write will be executed
again. This process is repeated for four successive locations. Since additional addresses
do not have to be set up on the address bus this four location "burst" occurs very quickly
and is useful for reading or writing blocks of data.

Slide 15

Zero Bus Turnaround (ZBT)

The ZBT (zero bus turn-around) is designed to eliminate dead cycles when turning the bus around between read
and writes and reads.
When a ZBT SRAM is asked to perform a Read operation immediately following a Write operation the user
will see the requested Read data on the next internal clock cycle after Write data was valid on the Data Bus.

Slide 16

In traditional SRAMs when a Write operation is immediately followed by a Read operation a

delay is experienced before the Read data is available on the Data Bus. This delay is called Data
Bus Turnaround Time and it usually amounts to two internal clock cycles. This time is required
by the SRAM to fetch the data. If a particular application performs a significant number of
alternating Reads and Writes the Data Bus will not be used efficiently due to the idle states
between the reads and writes.
Zero Bus Turnaround (ZBT) SRAMs have been designed to eliminate this wasted Data Bus
usage time for these alternating Read/Write applications. When a ZBT SRAM is asked to
perform a Read operation immediately following a Write operation the user will see the
requested Read data on the next internal clock cycle after Write data was valid on the Data Bus.
Thus, as you can see in the diagram, in an alternating Read/Write situation the Data Bus will
see 100% utilization.

Slide 17

• These are synchronous SRAMs where one word of data is transferred between the
SRAMs and the controller in a given clock cycle

• SDR SRAMs differ in their implementations

Slide 18

• These SRAMs can transfer multiple data words in a given cycle

• These devices have only one port for both read and write operations, i.e., up to two words
can be written into the device or up to two words can be read from the device at the same
time

• These are generally used in very high performance (workstation and server) cache
applications

Slide 19

• Quad Data Rate SRAM are designed with an innovative architecture especially for high-
performance networking systems

• These devices have two separate ports (for read and write operations) that can run
independently at double data rate, i.e., up to two words can be written into the device and
up to two words can be read from the device at the same time

• The net result is four data items per clock cycle

Slide 20

Summary

In this module we have studied various types of sram and their features. For example
synchronous and asynchronous sram and their applications.

We have also studied their further classification on the basis of functionality