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3 MicroController

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20 views26 pages

3 MicroController

Uploaded by

pravinkumarchaudhary56
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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8051 Micro-controller

Three criteria in Choosing a


Microcontroller
 meeting the computing needs of the task efficiently
and cost effectively
◦ speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption
◦ easy to upgrade
◦ cost per unit
◦ Noise of environment
 availability of software development tools
◦ assemblers, debuggers, C compilers, emulator, simulator,
technical support
 wide availability and reliable sources of the
microcontrollers
Comparison of the 8051 Family
Members
 ROM type
◦ 8031 no ROM
◦ 80xx mask ROM
◦ 87xx EPROM
◦ 89xx Flash EEPROM
 89xx
◦ 8951
◦ 8952
◦ 8953
◦ 8955
◦ 898252
◦ 891051
◦ 892051
 Example (AT89C51,AT89LV51)
◦ AT= ATMEL(Manufacture)
◦ C = CMOS technology
◦ LV= Low Power(3.0v)
8051 Basic Component/
Feature
 4K bytes internal ROM
 128 bytes internal RAM
 Four 8-bit I/O ports (P0 - P3).
 Two 16-bit timers/counters
 One serial interface
 64k external memory for code
 64k external memory for data
 210 bit addressable
The basic 8051 Core
• 8-bitCPU optimized for control applications
• Capability for single bit Boolean operations.
• Supports up to 64K of program memory.
• Supports up to 64K of data memory.
• 4 K bytes of on-chip program memory.
• Newer devices provide more.
• 128 or 256 bytes of on-chip data RAM
• Four 8 bit ports.
• Two 16-bit timer/counters
• UART
• Interrupts
• On-chip clock oscillator
General Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for


On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
8051 Internal Block Diagram

R.K.Tiwari([email protected])
8051
Schematic
Pin out
8051 P1.0 1 40 Vcc

Foot Print
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 8051 33 P0.6(AD6)
RST 9 (8031) 32 P0.7(AD7)
(RXD)P3.0 10 (8751) 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(8951)
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
Power-On RESET Circuit
Vcc

+
10 uF
31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST
Port 0 with Pull-Up Resistors
Vcc
10 K

P0.0

Port
DS5000 P0.1
8751 P0.2
8951 P0.3
P0.4 0
P0.5
P0.6
P0.7
IMPORTANT PINS
(IO Ports)
One of the most useful features of the 8051 is that it
contains four I/O ports (P0 - P3)
Each port can be used as input or output (bi-direction)

 Port 0
pins 32-39 （P0.0～P0.7）
◦ 8-bit R/W - General
Purpose I/O
◦ Or acts as a
multiplexed low byte
address and data
bus for external
memory design
IMPORTANT PINS (IO Ports)

Port 1
（pins 1-8） （P1.0～
P1.7）
◦ Only 8-bit R/W -
General Purpose
I/O
IMPORTANT PINS (IO Ports)

 Port 2
 （pins 21-28（P2.0
～P2.7）
◦ 8-bit R/W -
General
Purpose I/O
◦ Or high byte of
the address
bus for external
memory design
IMPORTANT PINS (IO Ports)

 Port 3
 （pins 10-17 （P3.0～
P3.7）
◦ General Purpose
I/O
◦ if not using any of
the internal
peripherals (timers)
or external
interrupts.
Port 3 Alternate Functions
 ALE - Address latch enable
to select valid address
 EA/Vpp - External access enable
EA-0 execute program in external
memory
EA-1 execute program in internal
memory
Vpp it receives 21 V for on chip EPROM
PSEN Program store enable
store to read the external program memory
Registers

R0
DPTR DPH DPL
R1

R2 PC PC
R3

R4 Some 8051 16-bit Register

R5

R6

R7

Some 8-bitt Registers of the


8051
Parallel I/O Ports
• Each port can be input or output
• Direction is set in Special Function
Registers
Port0 Port1 Port2 Port3
latch latch latch latch

Port0 Port1 Port2 Port3


DPTR
 The data pointer consists of a high
byte(DPH) and a low byte (DPL). Its
function is to hold a 16 bit address. It
may be manipulated as a 16 bit data
register or two independent 8 bit
register. It serves as a base register in
indirect jumps, lookup table
instructions and external data transfer.
PROGRAM STATUS WORD
(PSW)
CY AC F0 RS1 RS0 OV P

RS0 RS BANK SELECTION


1
0 0 00H – 07H BANK0
0 1 08H – 0FH BANK 1
1 0 10H – 17H BANK2
1 1 18H – 1FH BANK 3
Memory Organization
 The 8051 memory organization is rather complex.
 The 8051 has separate address spaces for
Program Memory, Data Memory, and external
RAM.
 This is refereed to as a Harvard architecture.
 Both program memory and external data memory
are 8 bits wide and use 16 bits of address. The
internal data memory is accessed using an 8-bit
address.
 Since the same address can refer to different
locations the specific location is determined by the
type of instruction.
RAM Memory Space
Allocation
 There are 128 bytes of RAM in 8051.
 The 128 bytes of RAM inside 8051 are
assigned addresses 00h to 7FH.
 These 128 bytes are divided into three
different groups as Follows:
RAM Memory Space
Allocation
 1. A total of 32 bytes from location 00
to 1F hex are set aside for register
banks and the stack( 4 register bank
each of 8 byte)
 2. A total of 16 byte from location 20h
to 2F h are set aside for bit
addressable RAM.
 3. A total of 80bytes from 30h to 7Fh
are used for RD/WR storage which is
normally called as Scratch Pad.
RAM Memory Space
Allocation
7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH (Stack) Register Bank
08H 1
07H
Register Bank 0
00H
Stack in the 8051
7FH
 The register used to access Scratch pad RAM
the stack is called SP (stack
pointer) register. 30H

2FH
Bit-Addressable RAM
 The stack pointer in the 20H
8051 is only 8 bits wide, 1FH Register Bank 3
18H
which means that it can 17H
Register Bank 2
take value 00 to FFH. When 10H
8051 powered up, the SP 0FH 08H
(Stack) Register Bank
1
register contains value 07. 07H Register Bank 0
00H

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