AXI2WISHBONE Documentation

Le Hoang Minh - Nguyen Van Phuc Nghiep

1 Introduction 1
1.1 AXI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Wishbone protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 AXI to WISHBONE bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Functional Specification 3
2.1 Interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 AXI Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Wishbone Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.3 FIFO Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Detailed implementation specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 AXI interconnect bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 WishBone interconnect bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Verification and checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 Features to be Verified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 Test Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Environment specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1 Hardware and Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2 Simulation and Testing Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Simulation and Verification 16

3.1 Testbench Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Simulation Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

List of Figures
1 AXI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 AXI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Master and Slave Wishbone’s interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 AXI WISHBONE interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 FIFO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 AXI WishBone Bridge overview block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 AXI WishBone Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 AXI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 AXI read transaction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
10 AXI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
11 AXI write transaction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 VALID before READY handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 READY before VALID handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 READY AND VALID at the same time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
15 Wishbone Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
16 Wishbone read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
17 Wishbone write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
18 Wishbone reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
19 Wishbone handshake protocol timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
20 Wishbone Single Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
21 Wishbone Single Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1 Introduction
1.1 AXI introduction
AXI (Advanced eXtensible Interface) is an interface specification that defines the interface of IP blocks, rather than
the interconnect itself. The following diagram shows how AXI is used to interface an interconnect component:

Figure 1: AXI protocol

In AX3 and AXI4, there are only two AXI interface types, master and slave. These interface types are sym-
metrical. All AXI connections are between master interfaces and slave interfaces.

Figure 2: AXI block diagram

AXI interconnect interfaces contain the same signals, which makes integration of different IP relatively simple.
The previous diagram shows how AXI connections join master and slave interfaces.

The direct connection gives maximum bandwidth between the master and slave components with no extra logic.
And with AXI, there is only a single protocol to validate.

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1.2 Wishbone protocol
The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit
communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip.
The Wishbone Bus is used by many designs in the OpenCores project.

Wishbone is intended as a “logic bus”. It does not specify electrical information or the bus topology. Instead,
the specification is written in terms of “signals”, clock cycles, and high and low levels.

Figure 3: Master and Slave Wishbone’s interfaces.

1.3 AXI to WISHBONE bridge

The AXI to WISHBONE bridge is an AXI slave, providing an interface between the high speed AXI and the more
common bus WishBone. Read and write transfers on the AXI are converted into equivalent transfers on the APB.

An example for the use of bridge is to connect with IPs that are WISHBONE compliant. The connection
between them would be as follows:

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 Figure 4: AXI WISHBONE interconnect

2 Functional Specification
2.1 Interface specification
The AXI-to-WISHBONE bridge interface facilitates communication between AXI (Advanced eXtensible Interface)
based components and WISHBONE based components within a system-on-chip (SoC). It translates AXI protocol
transactions into WISHBONE protocol transactions and vice versa. This includes:

2.1.1 AXI Interface Specification

The AXI interface consists of five types of channels: AR (Read Address), R (Read Data), AW (Write Address), W
(Write Data), and B (Write Response). Each channel has a set of signals that are used for communication between
the master and slave components.

• AR Channel
– ARADDR (32-bit) Address for read operations from the AXI master.
– ARVALID (1-bit) Indicates that the read address is valid.
– ARREADY (1-bit) Indicates that the slave is ready to accept the read address.
• R Channel
– RDATA (32-bit) Data returned to the AXI slave from the WISHBONE master.
– RVALID (1-bit) Indicates that the read data is valid.
– RREADY (1-bit) Indicates that the slave is ready to accept the read data.
– RRESP (2-bit) Status of the write operation.
• AW Channel
– AWADDR (32-bit) Address for write operations from the AXI.
– AWVALID (1-bit) Indicates that the write address is valid.
– AWREADY (1-bit) Indicates that the slave is ready to accept the write address.
• W Channel
– WDATA (32-bit) Data to be written from the AXI master.
– WVALID (1-bit) Indicates that the write data is valid.
– WREADY (1-bit) Indicates that the slave is ready to accept the write data.
• B Channel (Write Response Channel)

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 – BRESP (2-bit) Status of the write operation.
– BVALID (1-bit) Indicates that the write response is valid.
– BREADY (1-bit) Indicates that the master is ready to accept the write response.

2.1.2 Wishbone Interface Specification

The Wishbone interface also consists of several signals which are used for communication between the master and
slave:

• Address and Control Signals

– wb adr o (32-bit) Address output from the FIFO to the WISHBONE master. This signal provides the
address of the memory location to be accessed on the Wishbone slave.
– wb we o (1-bit) Write enable signal, also serve as read enable. Write enable signal when wb we o ==
1, if not then it is Read enable.
– wb stb o (1-bit) Change to 1 when the FIFO is ready to provide data for a write operation or when it
expects to receive data for a read operation.
– wb sel o (4-bit) Wishbone select signal, controls which bytes of the data bus are active during a Wishbone
transaction.
– wb cyc o (1-bit) Cycle signal indicating a valid bus cycle.

• Data Signals

– wb dat o (32-bit) This signal carries the data from FIFO that the Wishbone master wants to write to
the Wishbone slave during a write operation.
– wb dat i (32-bit) This signal carries the data that the Wishbone slave sends back to the master during
a read operation.
– fifo data in (32-bit) Carries data that is written into the FIFO for WB to use. For a write transaction,
this data will let Wishbone master perform the write operation to the Wishbone slave. If it is a read
transaction, this carries control information so that the Wishbone master will use to initiate the read
operation.
– fifo data out (32-bit) Carries data that is written into the FIFO from WB. If it is a read transaction,
response data from WB will be sent back to FIFO.

• Wishbone Protocol Handshake Signals

– wb ack i (1-bit) This signal indicates that the Wishbone slave has successfully completed the requested
operation (Read or Write).
– fifo read en (1-bit) signal from fifo so that Wishbone master will know that there’s a read operation to
perform.
– fifo write en (1-bit) signal from fifo so that Wishbone master will know that there’s a write operation to
perform.
– fifo empty (1-bit) If 1, it means there are no transactions pending in the FIFO. If 0, then there’s a
transaction to process and the WB will initiate the appropriate read or write cycle.

2.1.3 FIFO Interface Specification

FIFO is place between AXI and Wishbone, serve as an buffering to control the data flow between AXI and Wishbone.
As while AXI can handle both read and write operation at the same time, Wishbone will only do one operation at
any given time. So the FIFO help to temporary store data until Wishbone can get to processing those data.

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 Figure 5: FIFO block diagram

• FIFO controls Signals

– fifo wr en (1-bit) Signal to indicate that a write operation is called from AxI and is transfer though
FIFO to Wishbone.
– fifo rd en (1-bit) Signal to indicate that a read operation is called from AxI and is transfer though FIFO
to Wishbone.
– fifo full (1-bit) If 1, it means there are no space left in the FIFO. If 0, then there’s a space and more
transaction can be write into FIFO.
– fifo empty (1-bit) If 1, it means there are no transactions pending in the FIFO. If 0, then there exist a
transaction to process in FIFO.

• Data Signals

– fifo data in (32-bit) Data input signal to be written into FIFO from AxI.
– fifo data out (32-bit) Data output signal to be read from FIFO into Wishbone.

2.2 Detailed implementation specification

Figure 6: AXI WishBone Bridge overview block diagram

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 Figure 7: AXI WishBone Bridge block diagram

2.2.1 AXI interconnect bus

According to previous Figure 5, AXI master-slave includes:

- Write address channels

- Read address channels
- Read data channel
- Write data channel
- Write response channel

An access or a transaction consists of four basic pieces of information:

- Address Information: Identifies the destination (location, slave) where the transaction will be processed.
- Control Information: Specifies the attributes of the transaction, such as burst type, burst length, burst
size, and other properties.
- Data Information: Contains the transaction’s data.
- Response Information: Indicates the transaction’s status, whether it has encountered an error or not.

A read transaction is managed by two channels:

- AR Channel
- R Channel

A write transaction is managed by three channels:

- AW Channel
- W Channel
- B Channel

For read transactions, both data information and response information are transmitted on the R channel.

For write transactions, data information is transmitted on the W channel, while response information is trans-
mitted on a separate B channel.

Read Transaction
A read transaction involves two processing steps:

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 - Initiation by Master: The master sends address information and control information to initiate a read
transaction on the AR channel.
- Response by Slave: The slave sends the data along with response information on the R channel. The
amount of data and the response information are determined by the control information sent from the master
on the AR channel.

Figure 8: AXI Read Transaction

Figure 9: AXI read transaction timing

Write Transaction
A write transaction involves three processing steps:

- Initiation by Master: The master sends address information and control information to initiate a write
transaction on the AW channel.
- Data Transfer by Master: The master sends the write data on the W channel. The amount of write data
is determined by the control information sent from the master on the AW channel.
- Response by Slave: The slave sends the response information on the B channel once the write burst is
completed.

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 Figure 10: AXI Write Transaction

Figure 11: AXI write transaction timing

AXI Protocol Handshake Mechanism

The AXI protocol operates based on a two-way handshake mechanism using a VALID signal and a READY
signal.

- VALID Signal: The source uses the VALID signal to indicate that an address, control information, or data
is valid on the channel. VALID acts like a request signal for the destination to receive the information.
- READY Signal: The destination uses the READY signal to notify the source that it has accepted the
information. READY acts like an acknowledgment (ACK) signal confirming the request from the source.

The source and destination can be either the master or the slave. For example, in a read transaction:

• On the AR channel, the master is the source of address and control information, and the slave is the desti-
nation. Therefore, the master controls the ARVALID signal, and the slave controls the ARREADY signal.

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 • On the R channel, the roles are reversed: the slave is the source of read data, and the master is the destination.
Thus, the slave controls the RVALID signal, and the master controls the RREADY signal.

Each channel has a pair of VALID/READY signals, known as the handshake signals, to operate according to
this mechanism:

- AR Channel: ARVALID (master) and ARREADY (slave)

- R Channel: RVALID (slave) and RREADY (master)

- AW Channel: AWVALID (master) and AWREADY (slave)
- W Channel: WVALID (master) and WREADY (slave)

- B Channel: BVALID (slave) and BREADY (master)

According to the following timing diagram, the arrows shows where the transaction occurs.

Figure 12: VALID before READY handshake

Figure 13: READY before VALID handshake

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 Figure 14: READY AND VALID at the same time

2.2.2 WishBone interconnect bus

Wishbone Finite State Machine

The Wishbone FSM works as a connection between FIFOs and Wishbone Slave, mainly in read and write requests.
Upon system reset, the FSM transitions to the Idle state. In this state, it continuously monitors the FIFO signals.
Specifically, it waits for either fifo read en or fifo write en to transit from 0 to 1, which indicates the presence of
read or write operations, respectively.

When a fifo read en signal is detected, the FSM moves into the Read Request State. Here, the FSM prepares the
necessary address and control signals for the read operation, it then sends the read request to the Wishbone slave.
After the request is made, the FSM advances to the Read Response State.

In the Read Response State, the FSM waits for a response from the Wishbone slave. Once the data is received, it
captures this data and prepares it to be sent back to the FIFO. The FSM then monitors for the wb ack i signal
from the Wishbone slave. Upon receiving the ACK signal, the FSM returns to the Idle state, indicating that the
read operation has been completed.

Similarly, when a fifo write en signal is asserted, the FSM transitions from the Idle state to the Write Request State.
During this state, it captures and prepares the address, data, and necessary control signals for the write operation.
The FSM then initiates the write request to the Wishbone slave via the Wishbone master and transitions to the
Write Response State.

In the Write Response State, the FSM waits for a response from the Wishbone slave. Once the write operation is
acknowledged by the slave through the wb ack i signal, the FSM concludes the write process and returns to the
Idle state, ready to handle the next operation.

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 Figure 15: Wishbone Finite State Machine

Wishbone Timing Diagram

- Wishbone Read transaction:

Figure 16: Wishbone read timing diagram

– Idle State: All signals are inactive, waiting for the read request from fifo read en.
– Read Request: fifo read en transitions from 0 to 1, indicating that a read operation is to be initiated.
Then, fifo empty is checked to ensure there is data in the FIFO to be processed. If fifo empty is low,
the process continues.
– Read Operation: Both wb cyc o and wb stb o are transitions from 0 to 1, indicating the start of a
valid bus cycle and that the Wishbone master is ready to initiate the read operation. Then, wb we o
remains at 0 (1 mean write operation) to indicate a read operation. After that, wb adr o is driven with
the address from which data is to be read. Then the Wishbone master waits for a response from the
Wishbone slave.
– Response and Completion: wb ack i transitions from 0 to 1 indicated by Wishbone slave, that the
data on wb dat i is valid. Then fifo data out is driven with the data read from the Wishbone slave.
Afterward, wb cyc o and wb stb o go back to 0, ending the bus cycle, and fifo read en also go back to
0, completing the read transaction.

- Wishbone Write transaction:

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 Figure 17: Wishbone write timing diagram

– Idle State: All signals are inactive, waiting for the write request from fifo write en.
– Write Request: fifo write en transitions from 0 to 1, indicating that a write operation is to be initiated.
fifo data in holds the data to be written to the Wishbone slave.
– Write Operation: Both wb cyc o and wb stb o are transitions from 0 to 1, indicating the start of a
valid bus cycle and that the Wishbone master is ready to initiate the write operation. Then wb we o is
asserted to indicate a write operation. Afterward, wb adr o is driven with the address where the data
is to be written, while wb dat o is driven with the data from fifo data in.
– Response and Completion: wb ack i transitions from 0 to 1 meaning that Wishbone slave has been
successfully write the Data. Afterward, wb cyc o and wb stb o go back to 0, signaling the end of the bus
cycle. The fifo write en also go back to 0, and the data on fifo data in is no longer needed, completing
the write transaction.

2.2.3 FIFO

AXI2WB FIFO

• Write Operation: When AXI-Lite initiates a transaction, the FIFO write pointer is used to store the request
data into the FIFO. The FIFO’s write en signal is asserted to write new data, and the pointer increments
accordingly.
• Read Operation: The Wishbone interface reads from the FIFO using the read en signal. The read pointer
is updated as data is removed from the FIFO, ensuring the next read operation accesses the next available
request.

WB2AXI FIFO

• Write Operation: The Wishbone bus writes responses or data into the FIFO when transactions are completed.
The FIFO’s write pointer is updated to reflect the new data.
• Read Operation: The AXI-Lite master reads from the FIFO when it is ready to receive responses or data.
The read pointer is updated to provide the next available data.

2.3 Verification and checklist

2.3.1 Features to be Verified

- Transaction Mapping: Ensure that AXI read and write transactions are correctly mapped to WISHBONE
read and write cycles.
- Read Transactions: Validate read operations from AXI to WISHBONE.
- Write Transactions: Verify write operations from AXI to WISHBONE.
- Reset and Initialization: Confirm correct initialization and reset behavior of the bridge.
- Signal Conversion: Ensure the accurate conversion of AXI signals to WISHBONE signals, including control,
address, and data.

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2.3.2 Test Plan

Test Case 1: Simple Read Transaction

• Purpose and Scope: Verify basic read functionality.

• Inputs:
AXI Master signals:
- ARADDR: 32’h0000 0004 (AXI read address)
- ARVALID: High (indicating a valid read request)
- RREADY: High (ready to accept read data)
• Expected Results: Data is correctly read from the Wishbone Slave to AXI-Lite Master.
• Pass/Fail Criteria:
- RDATA matches expected WISHBONE memory content.

Test Case 2: Simple Write Transaction

• Purpose and Scope: Verify basic write functionality.

• Inputs:
AXI Master signals:
- AWADDR: 32’h0000 0008 (AXI write address)
- AWVALID: High (indicating a valid write request)
- WDATA: 32’hABCD EF01 (data to be written)
- WVALID: High (valid write data)
- BREADY: High (ready to accept write response)
• Expected Results: Data is accurately written to WISHBONE.
• Pass/Fail Criteria:
- Data in WISHBONE memory matches WDATA.

Test Case 3: Address Translation Accuracy

• Purpose and Scope: Check address mapping accuracy.

• Inputs:
AXI Master signals:
- ARADDR: 32’h0000 0010 (AXI read address)
- ARVALID: High (indicating a valid read request)
• Expected Results: The Wishbone Slave receives the correct address.
• Pass/Fail Criteria:
- ADR O on WISHBONE matches the expected translated address.

Test Case 4: Reset Functionality Test

• Purpose and Scope: Check reset and initialization behavior.

• Inputs:
System reset signal:

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 - ARESETn: Low (asserted to reset)
• Expected Results: All signals are reset to initial states.
• Pass/Fail Criteria: AXI-Lite and Wishbone signals return to default states.

Test Case 5: Signal Mapping Verification

• Purpose and Scope: Ensure accurate signal conversion.

• Inputs:
AXI Master signals:
- AWADDR: 32’h0000 0020 (AXI write address)
- AWVALID: High (indicating a valid write request)
- WDATA: 32’h1234 5678 (data to be written)
- WVALID: High (valid write data)
• Expected Results: Signals are correctly converted between protocols.

• Pass/Fail Criteria:
- ADR O matches the translated AWADDR.
- DAT O matches WDATA.
- WE O, CYC O, and STB O reflect the AXI control signals correctly.

Test Case 6: Handshake Signal

• Purpose and Scope: Validate handshake signal synchronization between AXI-Lite and Wishbone.
• Inputs:
AXI Master signals:
- ARVALID: High (for read operation)
- RREADY: High (ready to accept data)
Wishbone Slave signals:
- STB O: High (indicating data transfer readiness)
• Expected Results: Handshake signals are synchronized correctly.

• Pass/Fail Criteria:
- ACK I is asserted only when STB O and ARVALID are high.

2.4 Environment specification

2.4.1 Hardware and Software Environment

• HDL Design Tools:

– VHDL/Verilog Editor: Vivaldo.
– Synthesis Tools: Vivaldo.
– Simulation Tools: Vivaldo.

• Version Control:
– Git-based repository (GitHub).

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2.4.2 Simulation and Testing Environment

• Simulators:
– Functional Simulators: Integrated simulators in Vivaldo

• Test Frameworks:
– Unit Testing: Testbenches written in VHDL/Verilog.
– Integration Testing: Testing the AXI-to-WISHBONE bridge in a full system simulation.

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3 Simulation and Verification
3.1 Testbench Structure
The testbench uses Xilinx’s AXI Verification IP (AXI VIP) to simulate the AXI-Lite master interactions with the
slave. The testbench performs:

• Write Operations: Sends data to the FIFO.

• Read Operations: Retrieves the status and data from the FIFO.

3.2 Simulation Observations

• Expected Behavior: Data written to the FIFO via AXI-Lite should be correctly stored and later read out
through the AXI-Lite interface. The status register should accurately reflect the FIFO’s full/empty state.
• Issues Encountered: Currently, there are errors in the testbench. This is likely due to VIP import packaging,
or errors in the code.

• General operation:
- Reset operation
- Transfer Cycle initiation
- Handshaking Protocol
• SINGLE READ/WRITE Cycles
• BLOCK READ/WRITE Cycles

Reset operation

Figure 18: Wishbone reset timing diagram

Transfer Cycle initiation

A transfer cycle in the WISHBONE protocol involves the following steps:

- Initiation by Master: The master initiates a transfer cycle by asserting the CYC O signal. This indicates
the beginning of a valid bus cycle.
- Validity of Master Signals: When CYC O is negated, all other master signals become invalid, indicating
the end of the transfer cycle.

- Response by Slave: Slave interfaces respond to master signals only when CYC I is asserted, ensuring that
the slave is aware of the active transfer cycle.
- Independence of SYSCON Signals: SYSCON signals and responses to SYSCON signals are not affected
by the state of the CYC O or CYC I signals.

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Handshaking Protocol
All bus cycles in the WISHBONE protocol use a handshaking mechanism between the MASTER and SLAVE
interfaces:

- Initiation by Master: The MASTER asserts the STB O (strobe) signal when it is ready to transfer data.
- Strobe Signal Duration: The STB O signal remains asserted until the SLAVE asserts one of the cycle
terminating signals: ACK I (acknowledge), ERR I (error), or RTY I (retry).
- Sampling Terminating Signals: At every rising edge of CLK I (clock), the MASTER samples the ter-
minating signal. If one of these signals is asserted, then STB O is negated, indicating the end of the data
transfer.

Figure 19: Wishbone handshake protocol timing diagram

Single READ Cycle

A WISHBONE read cycle follows these steps:

• CLOCK EDGE 0:
Address and Control Signals by Master:

- The master presents a valid address on ADR O() and any address tags on TGA O().
- The master negates WE O to indicate a read cycle.
- The master presents bank select signals on SEL O() to indicate where it expects data.
- The master asserts CYC O and TGC O() to indicate the start of the bus cycle.
- The master asserts STB O to indicate the start of the data transfer phase.

• CLOCK EDGE 1:
Response and Data Signals by Slave:
- The slave decodes the input signals and, if it can respond, asserts ACK I.
- The slave presents valid data on DAT I() and any data tags on TGD I().
- The slave asserts ACK I in response to STB O to indicate that the data is valid.
- The master monitors ACK I and prepares to latch the data on DAT I() and TGD I().
- Note: The slave may insert wait states before asserting ACK I, allowing it to control the cycle speed.
Any number of wait states may be added.

• CLOCK EDGE 2: Completion of Cycle:

- The master latches the data on DAT I() and TGD I().
- The master negates STB O and CYC O to indicate the end of the cycle.
- The slave negates ACK I in response to the negated STB O.

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 Figure 20: Wishbone Single Read timing diagram

Single WRITE Cycle

A WISHBONE write cycle follows these steps:

• CLOCK EDGE 0:
Address and Data Signals by Master:
- The master presents a valid address on ADR O() and any address tags on TGA O().
- The master presents valid data on DAT O() and any data tags on TGD O().
- The master asserts WE O to indicate a write cycle
- The master presents bank select signals on SEL O() to indicate where it sends data.
- The master asserts CYC O and TGC O() to indicate the start of the bus cycle.
- The master asserts STB O to indicate the start of the data transfer phase.

• CLOCK EDGE 1:
Response and Data Preparation by Slave:
- The slave decodes the input signals and, if it can respond, asserts ACK I.
- The slave prepares to latch the data on DAT O() and any data tags on TGD O().
- The slave asserts ACK I in response to STB O to indicate that the data is latched.
- The master monitors ACK I and prepares to terminate the cycle.
• CLOCK EDGE 2: Completion of Cycle:
- The slave latches the data on DAT O() and TGD O().

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- The master negates STB O and CYC O to indicate the end of the cycle.
- The slave negates ACK I in response to the negated STB O.

Figure 21: Wishbone Single Write timing diagram

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