Design AXI to WB bridge

Block Diagram

AXI INTERCONNECT BUS

BLOCK DIAGRAM

DESCRIPTION:
AXI master-slave includes:
- Write address channels
- Read address channels
 - Read data channel
- Write data channel
- Write response channel
An access or a transaction consists of four basic pieces of information:
- Address Information: Identifies the destination (location, slave) where the
transaction will be processed.
- Control Information: Specifies the attributes of the transaction, such as burst
type, burst length, burst size, and other properties.
- Data Information: Contains the transaction’s data.
- Response Information: Indicates the transaction’s status, whether it has
encountered an error or not.
A read transaction is managed by two channels:
- AR Channel
- R Channel
A write transaction is managed by three channels:
- AW Channel
- W Channel
- B Channel
For read transactions, both data information and response information are transmitted on
the R channel.
For write transactions, data information is transmitted on the W channel, while response
information is transmitted on a separate B channel.
Read Transaction
A read transaction involves two processing steps:
- Initiation by Master: The master sends address information and control
information to initiate a read transaction on the AR channel.
- Response by Slave: The slave sends the data along with response information on
the R channel. The amount of data and the response information are determined by
the control information sent from the master on the AR channel.
Figure 8: AXI Read Transaction

Figure 9: AXI read transaction timing

Write Transaction
A write transaction involves three processing steps:
- Initiation by Master: The master sends address information and control
information to initiate a write transaction on the AW channel.
 - Data Transfer by Master: The master sends the write data on the W channel.
The amount of write data is determined by the control information sent from the
master on the AW channel.
- Response by Slave: The slave sends the response information on the B channel
once the write burst is completed.

Figure 10: AXI Write Transaction

Figure 11: AXI write transaction timing

AXI Protocol Handshake Mechanism

The AXI protocol operates based on a two-way handshake mechanism using a VALID
signal and a READY signal.
- VALID Signal: The source uses the VALID signal to indicate that an address,
control information, or data is valid on the channel. VALID acts like a request
signal for the destination to receive the information.
- READY Signal: The destination uses the READY signal to notify the source
that it has accepted the information. READY acts like an acknowledgment (ACK)
signal confirming the request from the source.
The source and destination can be either the master or the slave. For example, in a read
transaction:
• On the AR channel, the master is the source of address and control information,
and the slave is the destination. Therefore, the master controls the ARVALID
signal, and the slave controls the ARREADY signal.
• On the R channel, the roles are reversed: the slave is the source of read data, and
the master is the destination.
Thus, the slave controls the RVALID signal, and the master controls the
RREADY signal.
Each channel has a pair of VALID/READY signals, known as the handshake signals, to
operate according to this mechanism:
- AR Channel: ARVALID (master) and ARREADY (slave)
- R Channel: RVALID (slave) and RREADY (master)
- AW Channel: AWVALID (master) and AWREADY (slave)
- W Channel: WVALID (master) and WREADY (slave)
- B Channel: BVALID (slave) and BREADY (master)
According to the following timing diagram, the arrows show where the transaction
occurs.

Figure 12: VALID before READY handshake

Figure 13: READY before VALID handshake

Figure 14: READY AND VALID at the same time

FIFO (FIRST IN FIRST OUT) BLOCK DIAGRAM

Each FIFO has these inputs and outputs according to the above FIFO diagram
Width and Depth:

● Width: 32 bits (matching the data width of the AXI-Lite and Wishbone buses)
● Depth: 16 entries

Inputs:

● clk: Clock signal

● resetn: Active-low reset signal
● write_en: Write enable signal from Wishbone side
● read_en: Read enable signal to AXI-Lite side
 ● data_in: Data to be stored in FIFO

Outputs:

● data_out: Data read from FIFO to AXI-Lite master

● empty: Indicates if the FIFO is empty
● full: Indicates if the FIFO is full
● almost_full: Indicates if the FIFO is almost full
● almost_empty: Indicates if the FIFO is almost empty

FIFO Read and Write Operations

1.1. Write Operation

1. Check Full Status: Before writing, the FIFO checks if it is full by comparing the
write pointer with the read pointer and considering the FIFO depth.
2. Write Enable Signal: If write_enable is asserted and the FIFO is not full, the data
present on data_in is written into the FIFO at the location indicated by the write
pointer.
3. Update Write Pointer: After writing, the write pointer is incremented. If it reaches
the end of the FIFO, it wraps around to the beginning.
4. Update Status: The FIFO's full and almost full status signals are updated based on
the new state of the pointers.

1.2. Read Operation

1. Check Empty Status: Before reading, the FIFO checks if it is empty by comparing
the read pointer with the write pointer.
2. Read Enable Signal: If read_enable is asserted and the FIFO is not empty, the
data at the location indicated by the read pointer is read from the FIFO and placed
on data_out.
3. Update Read Pointer: After reading, the read pointer is incremented. If it reaches
the end of the FIFO, it wraps around to the beginning.
4. Update Status: The FIFO's empty and almost empty status signals are updated
based on the new state of the pointers.

Integration of FIFOs with AXI-Lite and Wishbone

2.1. Data Flow from AXI-Lite to Wishbone

 1. AXI-Lite to FIFO:
○ AXI-Lite master generates a write request with address and data.
○ The write address and data are written into the AXI2WB FIFO.
2. FIFO to Wishbone:
○ The AXI2WB FIFO supplies the buffered address and data to the Wishbone
interface.
○ The Wishbone interface performs the write operation using the provided
address and data.
3. Status Handling:
○ The FIFO provides status signals (e.g., full, almost_full) to indicate its
current state.
○ The bridge logic ensures that the FIFO is not overloaded and that data is
correctly managed.

2.2. Data Flow from Wishbone to AXI-Lite

1. Wishbone to FIFO:
○ Wishbone master performs a read operation and the read data is stored in
the WB2AXI FIFO.
2. FIFO to AXI-Lite:
○ The WB2AXI FIFO provides the buffered read data to the AXI-Lite
interface.
○ The AXI-Lite master receives the read data and processes it accordingly.
3. Status Handling:
○ The FIFO provides status signals (e.g., empty, almost_empty) to indicate its
current state.

Wishbone interconnect bus

BLOCK DIAGRAM
FINITE STATE MACHINE

DESCRIPTION:

The FSM transitions through the following states:

1. Idle State:
○ Monitors FIFO signals (fifo_read_en and fifo_write_en).
 ○ Transitions to Read Request or Write Request states based on FIFO signals.
2. Read Request State:
○ Activates when fifo_read_en is asserted.
○ Prepares and sends a read request to the Wishbone slave.
○ Moves to Read Response State after sending the request.
3. Read Response State:
○ Waits for the Wishbone slave’s ack_i and the read data.
○ Captures the data and writes it back to the FIFO.
○ Returns to Idle State upon receiving the acknowledgment.
4. Write Request State:
○ Activates when fifo_write_en is asserted.
○ Prepares and sends a write request to the Wishbone slave.
○ Moves to Write Response State after sending the request.
5. Write Response State:
○ Waits for acknowledgment from the Wishbone slave.
○ Returns to Idle State upon receiving the acknowledgment.

Wishbone write operation timing diagram:

Wishbone read operation timing diagram: