Mac OS X Assembler Guide

2005-04-29
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 Contents

Introduction Introduction to Mac OS X Assembler Guide 9

Organization of This Document 9

Chapter 1 Using the Assembler 11

Command Syntax 11
Assembler Options 11
-o 11
-- 12
-f 12
-g 12
-v 12
-n 13
-I 13
-L 13
-V 13
-W 13
-dynamic 13
-static 13
Architecture Options 14
-arch 14
-force_cpusubtype_ALL 14
-arch_multiple 14
PowerPC-Specific Options 14
-no_ppc601 14
-static_branch_prediction_Y_bit 15
-static_branch_prediction_AT_bits 15

Chapter 2 Assembly Language Syntax 17

Elements of Assembly Language 17

Characters 17
Identifiers 17
Labels 18
Constants 18
Assembly Location Counter 20
Expression Syntax 20

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 C O N T E N T S

Operators 20
Terms 22
Expressions 22

Chapter 3 Assembly Language Statements 25

Label Field 25
Operation Code Field 26
Intel i386 Architecture–Specific Caveats 26
Operand Field 27
Intel 386 Architecture–Specific Caveats 28
Comment Field 28
Direct Assignment Statements 29

Chapter 4 Assembler Directives 31

Directives for Designating the Current Section 31

.section 31
.zerofill 32
Section Types and Attributes 32
Built-in Directives 37
Directives for Moving the Location Counter 43
.align 43
.org 44
Directives for Generating Data 44
.ascii and .asciz 45
.byte, .short, .long, and .quad 45
.comm 46
.fill 46
.lcomm 46
.single and .double 47
.space 47
Directives for Dealing With Symbols 48
.globl 48
.indirect_symbol 48
.reference 48
.weak_reference 49
.lazy_reference 49
.weak_definition 49
.private_extern 49
.stabs, .stabn, and .stabd 50
.desc 50
.set 51
.lsym 51
Directives for Dead-Code Stripping 51
.subsections_via_symbols 51

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 C O N T E N T S

.no_dead_strip 52
Miscellaneous Directives 52
.abort 52
.abs 53
.dump and .load 53
.file and .line 54
.if, .elseif, .else, and .endif 54
.include 55
.machine 55
.macro, .endmacro, .macros_on, and .macros_off 55
PowerPC-Specific Directives 56
.flag_reg 56
.greg 56
.no_ppc601 57
.noflag_reg 57
Additional Processor-Specific Directives 57

Chapter 5 PowerPC Addressing Modes and Assembler Instructions 59

PowerPC Registers and Addressing Modes 59

Registers 59
Operands and Addressing Modes 60
Extended Instruction Mnemonics & Operands 61
Branch Mnemonics 61
Branch Prediction 64
Trap Mnemonics 65
PowerPC Assembler Instructions 67
A 67
B 69
C 82
D 85
E 87
F 89
I 92
J 92
L 93
M 96
N 101
O 102
P 103
R 103
S 105
T 113
V 115
X 124

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 C O N T E N T S

Chapter 6 i386 Addressing Modes and Assembler Instructions 125

i386 Registers and Addressing Modes 125

Instruction Mnemonics 125
Registers 126
Operands and Addressing Modes 127
Register Operands 128
Immediate Operands 128
Direct Memory Operands 128
Indirect Memory Operands 129
i386 Assembler Instructions 129
A 130
B 131
C 133
D 135
E 135
F 136
H 143
I 143
J 145
L 148
M 150
N 152
O 152
P 153
R 155
S 157
T 163
V 163
W 163
X 163

Appendix A Mode-Independent Macros 167

Document Revision History 169

Index 171

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 Figures

Chapter 6 i386 Addressing Modes and Assembler Instructions 125

Figure 6-1 Register Names in the 32-bit i386 architecture 126

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 F I G U R E S

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 I N T R O D U C T I O N

Introduction to Mac OS X Assembler

Guide

The Mac OS X assembler serves a dual purpose. It assembles the output of gcc, Xcode’s default
compiler, for use by the Mac OS X linker. It also provides the means to assemble custom assembly
language code written for its supported platforms.

This document provides a reference for the use of the assembler, including basic syntax and statement
layout. It also contains a list of the specific directives recognized by the assembler and complete
instruction sets for the PowerPC and i386 processor architectures.

Important: The “i386 Addressing Modes and Assembler Instructions” (page 125) section is considered
preliminary. It has not been updated with the latest revisions to the i386 addressing modes and
instructions. While most of the information is technically accurate, the document is incomplete and
is subject to change. For more information, please see the section itself.

Organization of This Document

This document contains the following chapters:

■ “Using the Assembler” (page 11) describes how to run the assembler and its relevant input/output
files. It also discusses specific options that can be passed to the assembler on the command line.
■ “Assembly Language Syntax” (page 17) describes the basic syntax of assembly language elements
and expressions.
■ “Assembly Language Statements” (page 25) describes in greater detail the assembly language
statements that make up an assembly language program.
■ “Assembler Directives” (page 31) describes assembler directives specific to the Mac OS X assembler
and how to use them in your assembly code.
■ “PowerPC Addressing Modes and Assembler Instructions” (page 59) contains information specific
to the PowerPC processor architecture and provides a complete list of addressing modes and
instructions relevant to it.
■ “i386 Addressing Modes and Assembler Instructions” (page 125) contains information specific to
the i386 processor architecture and provides a complete list of addressing modes and instructions
relevant to it.

Organization of This Document 9

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 I N T R O D U C T I O N
Introduction to Mac OS X Assembler Guide

■ “Mode-Independent Macros” (page 167) introduces the macros included in the Mac OS X v10.4
SDK to facilitate the development of assembly code that runs in 32-bit PowerPC and 64-bit
PowerPC environments.

This document also contains a revision history, and an index.

10 Organization of This Document

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 C H A P T E R 1

Using the Assembler

This chapter describes how to run the as assembler, which produces an object file from one or more
files of assembly language source code.

Note: Although a.out is the default file name that as gives to the object file that’s created (as is
conventional with many compilers), the format of the object file is not standard 4.4BSD a.out format.
Object files produced by the assembler are in Mach-O (Mach object) file format. See Mac OS X ABI
Mach-O File Format Reference for more information.

Command Syntax

To run the assembler, type the following command in a shell:

as [ option ] ... [ file ] ...

You can specify one or more command-line options. These assembler options are described in
“Assembler Options” (page 11).

You can specify one or more files containing assembly language source code. If no files are specified,
as uses the standard input (stdin) for the assembly source input.

Note: By convention, files containing assembly language source code should have the .s extension.

Assembler Options

The following command-line options are recognized by the assembler:

-o
-o name

The name argument after -o is used as the name of the as output file, instead of a.out.

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--
--

Use the standard input (stdin) for the assembly source input.

-f
-f

Fast; no need to run app (the assembler preprocessor). This option is intended for use by compilers
that produce assembly code in a strict “clean” format that specifies exactly where whitespace can go.
The app preprocessor needs to be run on handwritten assembly files and on files that have been
preprocessed by cpp (the C preprocessor). This typically is needed when assembler files are assembled
through the use of the cc(1) command, which automatically runs the C preprocessor on assembly
source files. The assembler preprocessor strips out excess spaces, turns each character surrounded
by single quotation marks into a decimal constant, and turns occurrences of:

# number filename level

into:

.line number;.file filename

The assembler preprocessor can also be turned off by starting the assembly file with #NO_APP\n. When
the assembler preprocessor has been turned off in this way, it can be turned on and off with pairs of
#APP\n and #NO_APP\n at the beginning of lines. This is used by the compiler to wrap assembly
statements produced from asm() statements.

-g
-g

Produce debugging information for the symbolic debugger gdb(1) so the assembly source can be
debugged symbolically. For include files (included by the C preprocessor’s #include or by the
assembler directive .include) that produce instructions in the (__TEXT,__text) section, the include
file must be included while a .text directive is in effect (that is, there must be a .text directive before
the include) and end with the a .text directive in effect (at the end of the include file). Otherwise the
debugger will have trouble dealing with that assembly file.

-v
-v

Print the version of the assembler (both the Mac OS X version and the GNU version that it is based
on).

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-n
-n

Don’t assume that the assembly file starts with a .text directive.

-I
-Idir

Add dir to the list of directories to search for files included with the .include directive. The default
place to search is the current directory.

-L
-L

Save defined labels beginning with an L (the compiler generates these temporary labels). Temporary
labels are normally discarded to save space in the resulting symbol table.

-V
-V

Print the path and the command-line invocation of the assembler that the assembler driver is using.

-W
-W

Suppress warnings.

-dynamic
-dynamic

Enables dynamic linking features. This is the default.

-static
-static

Causes the assembler to treat any dynamic linking features as an error. This also causes the .text
directive to not include the pure_instructions section attribute.

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Architecture Options

The program /usr/bin/as is a driver that executes assemblers for specific target architectures. If no
target architecture is specified, it defaults to the architecture of the host it is running on.

-arch
-arch arch_type

Specifies the target architecture, arch_type, the assembler to be executed and the architecture of the
resulting object file. The target assemblers for each architecture are in
/usr/libexec/gcc/darwin/arch_type/as or /usr/local/libexec/gcc/darwin/arch_type/as. The
specified target architecture can be processor specific, in which case the resulting object file is marked
for the specific processor. See then man page arch(3) for the current list of specific processor names
for the -arch option.

-force_cpusubtype_ALL
-force_cpusubtype_ALL

Set the architecture of the resulting object file to the ALL type regardless of the instructions in the
assembly input.

-arch_multiple
-arch_multiple

This is used by the cc(1) driver program when it is run with multiple -archarch_type flags and
instructs programs like as(1) that, if it prints any messages, to precede them with one line stating
the program name—in this case as—and the architecture (from the -archarch_type flag) to distinguish
which architecture the error messages refer to. This flag is accepted only by the actual assemblers (in
/lib/arch_type/as) and not by the assembler driver, /bin/as.

PowerPC-Specific Options

The following sections describe the options specific to the PowerPC architecture.

-no_ppc601
-no_ppc601

Treat any PowerPC 601 instructions as an error.

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-static_branch_prediction_Y_bit
-static_branch_prediction_Y_bit

Treat a single trailing + or - after a conditional PowerPC branch instruction as a static branch prediction
that sets the Y bit in the opcode. Pairs of trailing ++ or -- always set the AT bits. This is the default
for Mac OS X.

-static_branch_prediction_AT_bits
-static_branch_prediction_AT_bits

Treat a single trailing + or - after a conditional Power PC branch instruction as a static branch prediction
sets the AT bits in the opcode. Pairs of trailing ++ or -- always set the AT bits, but with this option a
warning is issued if that syntax is used. With this flag the assembler behaves like the IBM tools.

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 C H A P T E R 2

Assembly Language Syntax

This chapter describes the basic lexical elements of assembly language programming, and explains
how those elements combine to form complete assembly language expressions.

This chapter goes on to explain how sequences of expressions are put together to form the statements
that make up an assembly language program.

Elements of Assembly Language

This section describes the basic building blocks of an assembly language program—these are characters,
symbols, labels, and constants.

Characters
The following characters are used in assembly language programs:

■ Alphanumeric characters—A through Z, a through z, and 0 through 9

■ Other printable ASCII characters (such as #, $, :, ., +, -, *, /, !, and |)
■ Nonprinting ASCII characters (such as space, tab, return, and newline)

Some of these characters have special meanings, which are described in “Expression Syntax” (page 20)
and in “Assembly Language Statements” (page 25).

Identifiers
An identifier (also known as a symbol) can be used for several purposes:

■ As the label for an assembler statement (see “Labels” (page 18))

■ As a location tag for data
■ As the symbolic name of a constant

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 C H A P T E R 2
Assembly Language Syntax

Each identifier consists of a sequence of alphanumeric characters (which may include other printable
ASCII characters such as ., _, and $). The first character must not be numeric. Identifiers may be of
any length, and all characters are significant. The case of letters is significant—for example, the
identifier var is different from the identifier Var.

It is also possible to define an identifier by enclosing multiple identifiers within a pair of double
quotation marks. For example:

"Object +new:":
.long "Object +new:"

Labels
A label is written as an identifier immediately followed by a colon (:). The label represents the current
value of the current location counter; it can be used in assembler instructions as an operand.

Note: You may not use a single identifier to represent two different locations.

Numeric Labels

Local numeric labels allow compilers and programmers to use names temporarily. A numeric label
consists of a digit (between 0 and 9) followed by a colon. These 10 local symbol names can be reused
any number of times throughout the program. As with alphanumeric labels, a numeric label assigns
the current value of the location counter to the symbol.

Although multiple numeric labels with the same digit may be used within the same program, only
the next definition and the most recent previous definition of a label can be referenced:

■ To refer to the most recent previous definition of a local numeric label, write digitb, (using the
same digit as when you defined the label).
■ To refer to the next definition of a numeric label, write digitf.

The Scope of a Label

The scope of a label is the distance over which it is visible to (and referenceable by) other parts of the
program. Normally, a label that tags a location or data is visible only within the current assembly
unit.

The .globl directive (described in “.globl” (page 48)) may be used to make a label external. In this
case, the symbol is visible to other assembly units at link time.

Constants
Four types of constants are available: Numeric, character, string, and floating point. All constants are
interpreted as absolute quantities when they appear in an expression.

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Assembly Language Syntax

Numeric Constants

A numeric constant is a token that starts with a digit. Numeric constants can be decimal, hexadecimal,
or octal. The following restrictions apply:

■ Decimal constants contain only digits between 0 and 9, and normally aren’t longer than 32
bits—having a value between -2,147,483,648 and 2,147,483,647 (values that don’t fit in 32
bits are bignums, which are legal but which should fit within the designated format). Decimal
constants cannot contain leading zeros or commas.
■ Hexadecimal constants start with 0x (or 0X), followed by between one and eight decimal or
hexadecimal digits (0 through 9, a through f, and A through F). Values that don’t fit in 32 bits are
bignums.
■ Octal constants start with 0, followed by from one to eleven octal digits (0 through 7). Values that
don’t fit in 32 bits are bignums.

Character Constants

A single-character constant consists of a single quotation mark (') followed by any ASCII character.
The constant’s value is the code for the given character.

String Constants

A string constant is a sequence of zero or more ASCII characters surrounded by quotation marks (for
example, "a string").

Floating-Point Constants

The general lexical form of a floating-point number is:

0flt_char[{+–}]dec...[.][dec...][exp_char[{+–}][dec...]]

where:

Item Description

flt_char A required type specification character (see the following table).

[{+-}] The optional occurrence of either + or –, but not both.

dec... A required sequence of one or more decimal digits.

[.] A single optional period.

[dec...] An optional sequence of one or more decimal digits.

[exp_char] An optional exponent delimiter character (see the following table).

The type specification character, flt_char, specifies the type and representation of the constructed
number; the set of legal type specification characters with the processor architecture, as shown here:

Elements of Assembly Language 19

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 C H A P T E R 2
Assembly Language Syntax

Architecture flt_char exp_char

ppc {dDfF} {eE}

i386 {fFdDxX} {eE}

When floating-point constants are used as arguments to the .single and .double directives, the type
specification character isn’t actually used in determining the type of the number. For convenience, r
or R can be used consistently to specify all types of floating-point numbers.

Collectively, all floating-point numbers, together with quad and octal scalars, are called bignums.
When as requires a bignum, a 32-bit scalar quantity may also be used.

Floating-point constants are internally represented as flonums in a machine-independent,

precision-independent floating-point format (for accurate cross-assembly).

Assembly Location Counter

A single period (.), usually referred to as “dot,” is used to represent the current location counter.
There is no way to explicitly reference any other location counters besides the current location counter.

Even if it occurs in the operand field of a statement, dot refers to the address of the first byte of that
statement; the value of dot isn’t updated until the next machine instruction or assembler directive.

Expression Syntax

Expressions are combinations of operand terms (which can be numeric constants or symbolic identifiers
) and operators. This section lists the available operators, and describes the rules for combining these
operators with operands in order to produce legal expressions.

Operators
Identifiers and numeric constants can be combined, through the use of operators, to form expressions.
Each operator operates on 32-bit values. If the value of a term occupies 8 or 16 bits, it is sign-extended
to a 32-bit value.

The assembler provides both unary and binary operators. A unary operator precedes its operand; a
binary operator follows its first operand, and precedes its second operand. For example:

!var | unary expression

var+5 | binary expression

The assembler recognizes the following unary operators:

Operator Description

– Unary minus: The result is the two’s complement of the operand.

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Operator Description

~ One’s complement: The result is the one’s complement of the operand.

! Logical negation: The result is zero if the operand is nonzero, and 1 if the operand is zero.

The assembler recognizes the following binary operators:

Operator Description

+ Addition: The result is the arithmetic addition of the two operands.

– Subtraction: The result is the arithmetic subtraction of the two operands.

* Multiplication: The result is the arithmetic multiplication of the two operands.

/ Division: The result is the arithmetic division of the two operands; this is integer division,
which truncates towards zero.

% Modulus: The result is the remainder that’s produced when the first operand is divided
by the second (this operator applies only to integral operands).

>> Right shift: The result is the value of the first operand shifted to the right, where the
second operand specifies the number of bit positions by which the first operand is to be
shifted (this operator applies only to integral operands). This is always an arithmetic shift
since all operators operate on signed operands.

<< Left shift: The result is the value of the first operand shifted to the left, where the second
operand specifies the number of bit positions by which the first operand is to be shifted
(this operator applies only to integral operands).

& Bitwise AND: The result is the bitwise AND function of the two operands (this operator
applies only to integral operands).

^ Bitwise exclusive OR: The result is the bitwise exclusive OR function of the two operands
(this operator applies only to integral operands).

| Bitwise inclusive OR: The result is the bitwise inclusive OR function of the two operands
(this operator applies only to integral operands).

< Less than: The result is 1 if the first operand is less than the second operand, and zero
otherwise.

> Greater than: The result is 1 if the first operand is greater than the second operand, and
zero otherwise.

<= Less than or equal: The result is 1 if the first operand is less than or equal to the second
operand, and zero otherwise.

>= Greater than or equal: The result is 1 if the first operand is greater than or equal to the
second operand, and zero otherwise.

== Equal: The result is 1 if the two operands are equal, and zero otherwise.

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Operator Description

!= Not equal (same as <>): The result is zero if the two operands are equal, and 1 otherwise.

Terms
A term is a part of an expression; it may be:

■ An identifier.
■ A numeric constant (its 32-bit value is used). The assembly location counter (.), for example, is
a valid numeric constant.
■ An expression or term enclosed in parentheses. Any quantity enclosed in parentheses is evaluated
before the rest of the expression. This can be used to alter the normal evaluation of expressions—for
example, to differentiate between x * y + z and x * (y + z) or to apply a unary operator to
an entire expression—for example, –(x * y + z).
■ A term preceded by a unary operator (for example, ~var). Multiple unary operators may be used
in a term (for example, !~var).

Expressions
Expressions are combinations of terms joined together by binary operators. An expression is always
evaluated to a 32-bit value, but in some situations a different value is used:

■ If the operand requires a 1-byte value (a .byte directive, for example), the low-order 8 bits of the
expression are used.
■ If the operand requires a 16-bit value (a .short directive or a movem instruction, for example),
the low-order 16 bits of the expression are used.

All expressions are evaluated using the same operator precedence rules that are used by the C
programming language.

When an expression is evaluated, its value is absolute, relocatable, or external, as described below.

Absolute Expressions

An expression is absolute if its value is fixed. The following are examples of absolute expressions:

■ An expression whose terms are constants

■ An identifier whose value is a constant via a direct assignment statement
■ Values to which the .set directive is applied

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Assembly Language Syntax

Relocatable Expressions

An expression (or term) is relocatable if its value is fixed relative to a base address but has an offset
value when it is linked or loaded into memory. For example, all labels of a program defined in
relocatable sections are relocatable.

Expressions that contain relocatable terms must add or subtract only constants to their value. For
example, assuming the identifiers var and dat are defined in a relocatable section of the program,
the following examples demonstrate the use of relocatable expressions:

Expression Description

var Simple relocatable term. Its value is an offset from the base address of the current
control section.

var+5 Simple relocatable expression. Since the value of var is an offset from the base address
of the current control section, adding a constant to it doesn’t change its relocatable
status.

var*2 Not relocatable. Multiplying a relocatable term by a constant invalidates the relocatable
status of the expression.

2–var Not relocatable. The expression can’t be linked by adding var’s offset to it.

var-dat+5 Relocatable expression if both var and dat are defined in the same section—that is, if
neither is undefined. This form of relocatable expression is used for
position-independent code.

External Expressions

An expression is external (or global) if it contains an external identifier not defined in the current
program. In general, the same restrictions on expressions containing relocatable identifiers apply to
expressions containing external identifiers. An exception is that the expression var–dat is incorrect
when both var and dat are external identifiers (that is, you cannot subtract two external relocatable
expressions). Also, you cannot multiply or divide any relocatable expression.

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 C H A P T E R 3

Assembly Language Statements

This chapter describes the assembly language statements that make up an assembly language program.

This is the general format of an assembly language statement:

[ label_field ] [ opcode_field [ operand_field ] ] [ comment_field ]

Each of the depicted fields is described in detail in one of the following sections.

A line may contain multiple statements separated by the @ character for the PowerPC assembler (and
a semicolon for the i386 assembler), which may then be followed by a single comment preceded by
a semicolon for the PowerPC assembler (and a # character for the i386 assembler):

[ statement [ @ statement ...] ] [ ; comment_field ]

The following rules apply to the use of whitespace within a statement:

■ Spaces or tabs are used to separate fields.

■ At least one space or tab must occur between the opcode field and the operand field.
■ Spaces may appear within the operand field.
■ Spaces and tabs are significant when they appear in a character string.

Label Field

Labels are identifiers that you use to tag the locations of program and data objects. Each label is
composed of an identifier and a terminating colon. The format of the label field is:

identifier: [ identifier: ] ...

The optional label field may occur only at the beginning of a statement. The following example shows
a label field containing two labels, followed by a (PowerPC-style) comment:

var: VAR: ; two labels defined here

As shown here, letters in identifiers are case sensitive, and both uppercase and lowercase letters may
be used.

Label Field 25
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Operation Code Field

The operation code field of an assembly language statement identifies the statement as a machine
instruction, an assembler directive, or a macro defined by the programmer:

■ A machine instruction is indicated by an instruction mnemonic. An assembly language statement

that contains an instruction mnemonic is intended to produce a single executable machine
instruction. The operation and use of each instruction is described in the manufacturer’s user
manual.
■ An assembler directive (or pseudo-op) performs some function during the assembly process. It
doesn’t produce any executable code, but it may assign space for data in the program.
■ Macros are defined with the .macro directive (see “.macro, .endmacro, .macros_on, and
.macros_off” (page 55) for more information).

One or more spaces or tabs must separate the operation code field from the following operand field
in a statement. Spaces or tabs are optional between the label and operation code fields, but they help
to improve the readability of the program.

Intel i386 Architecture–Specific Caveats

■ i386 instructions can operate on byte, word, or long word data (the last is called “double word”
by Intel). The desired size is indicated as part of the instruction mnemonic by adding a trailing
b, w, or l:

Mnemonic Description

b Byte (8-bit) data.

w Word (16-bit) data.

l Long word (32-bit) data.

For instance, a movb instruction moves a byte of data, but a movw instruction moves a 16-bit word
of data.
If no size is specified, the assembler attempts to determine the size from the operands. For example,
if the 16-bit names for registers are used as operands, a 16-bit operation is performed. When both
a size specifier and a size-specific register name are given, the size specifier is used. Thus, the
following are all correct and result in the same operation:

movw %bx,%cx
mov %bx,%cx
movw %ebx,%ecx

■ An i386 operation code can also contain optional prefixes, which are separated from the operation
code by a slash (/) character. The prefix mnemonics are:

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Prefix Description

data16 Operation uses 16-bit data.

addr16 Operation uses 16-bit addresses.

lock Exclusive memory lock.

wait Wait for pending numeric exceptions.

cs, ds, es, fs, gs, ss Segment register override.

rep, repe, repne Repeat prefixes for string instructions.

More than one prefix may be specified for some operation codes. For example:

lock/fs/xchgl %ebx,4(%ebp)

Segment register overrides and the 16-bit data specifications are usually given as part of the
operation code itself or of its operands. For example, the following two lines of assembly generate
the same instructions:

movw %bx,%fs:4(%ebp)
data16/fs/movl %bx,4(%ebp)

Not all prefixes are allowed with all instructions. The assembler does check that the repeat prefixes
for strings instructions are used correctly but doesn’t otherwise check for correct usage.

Operand Field

The operand field of an assembly language statement supplies the arguments to the machine
instruction, assembler directive, or macro.

The operand field may contain one or more operands, depending on the requirements of the preceding
machine instruction or assembler directive. Some machine instructions and assembler directives don’t
take any operand, and some take two or more. If the operand field contains more than one operand,
the operands are generally separated by commas, as shown here:

[ operand [ , operand ] ... ]

The following types of objects can be operands:

■ Register operands
■ Register pairs
■ Address operands
■ String constants
■ Floating-point constants
■ Register lists

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■ Expressions

Register operands in a machine instruction refer to the machine registers of the processor or
coprocessor. Register names may appear in mixed case.

Intel 386 Architecture–Specific Caveats

The Mac OS X assembler orders operand fields for i386 instructions in the reverse order from Intel’s
conventions. Intel’s convention is destination first, source second; Mac OS X assembler’s convention
is source first, destination second. Where Intel documentation would describe the Compare and
Exchange instruction for 32-bit operands as follows:

CMPXCHG r/m32,r32 # Intel processor manual convention

The Mac OS X assembler syntax for this same instruction is:

cmpxchg r32,r/m32 # Mac OS X assembler syntax

So, an example of actual assembly code for the Mac OS X assembler would be:

cmpxchg %ebx,(%eax) # Mac OS X assembly code

Comment Field

The assembler recognizes two types of comments in source code:

■ A line whose first nonwhitespace character is the hash character (#) is a comment. This style of
comment is useful for passing C preprocessor output through the assembler. Note that comments
of the form:

# line_number file_name level

get turned into:

.line line_number; .file file_name

This can cause problems when comments of this form that aren’t intended to specify line numbers
precede assembly errors, since the error is reported as occurring on a line relative to that specified
in the comment. Suppose a program contains these two lines of assembly source:

# 500
.var

If .var hasn’t been defined, this fragment results in the following error message:

var.s:500:Unknown pseudo-op: .var

■ A comment field, appearing on a line after one or more statements. The comment field consists
of the appropriate comment character and all the characters that follow it on the line:

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Character Description

; Comment character for PowerPC processors

# Comment character for i386 architecture processors

An assembly language source line can consist of just the comment field; in this case, it’s equivalent
to using the hash character comment style:

# This is a comment.
; This is a comment.

Note the warning given above for hash character comments beginning with a number.

Direct Assignment Statements

This section describes direct assignment statements, which don’t conform to the normal statement
syntax described earlier in this chapter. A direct assignment statement can be used to assign the value
of an expression to an identifier. The format of a direct assignment statement is:

identifier = expression

If expression in a direct assignment is absolute, identifier is also absolute, and it may be treated as a
constant in subsequent expressions. If expression is relocatable, identifier is also relocatable, and it is
considered to be declared in the same program section as the expression.

The use of an assignment statement is analogous to using the .set directive (described in
“.set” (page 51)), except that the .set directive makes the value of the expression absolute. This is
used when an assembly time constant is wanted for what would otherwise generate a relocatable
expression using the position independent expression of symbol1 - symbol2. For example, the size
of the function is needed as one of the fields of the C++ exception information and is set with:

.set L_foo_size, L_foo_end - _foo

.long L_foo_size ; size of function _foo

where a position independent pointer to the function is another field of the C++ exception information
and is set with:

.long _foo - . ; position independent pointer to _foo

where the runtime adds the address of the pointer to its contents to get a pointer to the function.

Once an identifier has been defined by a direct assignment statement, it may be redefined—its value
is then the result of the last assignment statement. There are a few restrictions, however, concerning
the redefinition of identifiers:

■ Register identifiers may not be redefined.

■ An identifier that has already been used as a label should not be redefined, since this would
amount to redefining the address of a place in the program. Moreover, an identifier that has been
defined in a direct assignment statement cannot later be used as a label. Only the second situation
produces an assembler error message.

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Assembler Directives

This chapter describes assembler directives (also known as pseudo operations, or pseudo-ops), which
allow control over the actions of the assembler.

Directives for Designating the Current Section

The assembler supports designation of arbitrary sections with the .section and .zerofill directives
(descriptions appear below). Only those sections specified by a directive in the assembly file appear
in the resulting object file (including implicit .text directives—see “Built-in Directives” (page 37).
Sections appear in the object file in the order their directives first appear in the assembly file. When
object files are linked by the link editor, the output objects have their sections in the order the sections
first appear in the object files that are linked. See the ld(1) Mac OS X man page for more details.

Associated with each section in each segment is an implicit location counter, which begins at zero
and is incremented by 1 for each byte assembled into the section. There is no way to explicitly reference
a particular location counter, but the directives described here can be used to “activate” the location
counter for a section, making it the current location counter. As a result, the assembler begins assembling
into the section associated with that location counter.

Note: If the -n command-line option isn’t used, the (__TEXT,__text) section is used by default at the
beginning of each file being assembled, just as if each file began with the .text directive.

.section
SYNOPSIS

.section segname , sectname [[[ , type ] , attribute ] , sizeof_stub ]

The .section directive causes the assembler to begin assembling into the section given by segname
and sectname. A section created with this directive contains initialized data or instructions and is
referred to as a content section. type and attribute may be specified as described under “Section Types
and Attributes” (page 32). If type is symbol_stubs, then the sizeof_stub field must be given as the size
in bytes of the symbol stubs contained in the section.

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.zerofill
SYNOPSIS

.zerofill segname , sectname [ , symbolname , size [ , align_expression ]]

The .zerofill directive causes symbolname to be created as uninitialized data in the section given
by segname and sectname, with a size in bytes given by size. A power of 2 between 0 and 15 may be
given for align_expression to indicate what alignment should be forced on symbolname, which is placed
on the next expression boundary having the given alignment. See “.align” (page 43) for details.

Section Types and Attributes

A content section has a type, which informs the link editor about special processing needed for the
items in that section. The most common form of special processing is for sections containing literals
(strings, constants, and so on) where only one copy of the literal is needed in the output file and the
same literal can be used by all references in the input files.

A section’s attributes record supplemental information about the section that the link editor may use
in processing that section. For example, the pure_instructions attribute indicates that a section
contains only valid machine instructions.

A section’s type and attribute are recorded in a Mach-O file as the flags field in the section header,
using constants defined in the header file mach-o/loader.h. The following sections describe the
various types and attributes by the names used to identify them in a .section directive. The name
of the related constant is also given in parentheses following the identifier.

Type Identifiers

The following sections describe section type identifiers.

regular (S_REGULAR)

A regular section may contain any kind of data and gets no special processing from the link editor.
This is the default section type. Examples of regular sections include program instructions or
initialized data.

cstring_literals (S_CSTRING_LITERALS)

A cstring_literals section contains null-terminated literal C language character strings. The link
editor places only one copy of each literal into the output file’s section and relocates references to
different copies of the same literal to the one copy in the output file. There can be no relocation entries
for a section of this type, and all references to literals in this section must be inside the address range
for the specific literal being referenced. The last byte in a section of this type must be a null byte, and
the strings can’t contain null bytes in their bodies. An example of a cstring_literals section is one
for the literal strings that appear in the body of an ANSI C function where the compiler chooses to
make such strings read only.

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4byte_literals (S_4BYTE_LITERALS)

A 4byte_literals section contains 4-byte literal constants. The link editor places only one copy of
each literal into the output file’s section and relocates references to different copies of the same literal
to the one copy in the output file. There can be no relocation entries for a section of this type, and all
references to literals in this section must be inside the address range for the specific literal being
referenced. An example of a 4byte_literals section is one in which single-precision floating-point
constants are stored for a RISC machine (these would normally be stored as immediates in CISC
machine code).

8byte_literals (S_8BYTE_LITERALS)

An 8byte_literals section contains 8-byte literal constants. The link editor places only one copy of
each literal into the output file’s section and relocates references to different copies of the same literal
to the one copy in the output file. There can be no relocation entries for a section of this type, and all
references to literals in this section must be inside the address range for the specific literal being
referenced. An example of a 8byte_literals section is one in which double-precision floating-point
constants are stored for a RISC machine (these would normally be stored as immediates in CISC
machine code).

literal_pointers (S_LITERAL_POINTERS)

A literal_pointers section contains 4-byte pointers to literals in a literal section. The link editor
places only one copy of a pointer into the output file’s section for each pointer to a literal with the
same contents. The link editor also relocates references to each literal pointer to the one copy in the
output file. There must be exactly one relocation entry for each literal pointer in this section, and all
references to literals in this section must be inside the address range for the specific literal being
referenced. The relocation entries can be external relocation entries referring to undefined symbols
if those symbols identify literals in another object file. An example of a literal_pointers section is
one containing selector references generated by the Objective-C compiler.

symbol_stubs (S_SYMBOL_STUBS)

A symbol_stubs section contains symbol stubs, which are sequences of machine instructions (all the
same size) used for lazily binding undefined function calls at runtime. If a call to an undefined function
is made, the compiler outputs a call to a symbol stub instead, and tags the stub with an indirect symbol
that indicates what symbol the stub is for. On transfer to a symbol stub, a program executes instructions
that eventually reach the code for the indirect symbol associated with that stub. Here’s a sample of
assembly code based on a function func() containing only a call to the undefined function foo():

.text
.align 2
.globl _func
_func:
b L_foo$stub
.symbol_stub
L_foo$stub: ;
.indirect_symbol _foo ;
lis r11,ha16(L_foo$lazy_ptr) ;
lwz r12,lo16(L_foo$lazy_ptr)(r11) ; the symbol stub
mtctr r12 ;
addi r11,r11,lo16(L_foo$lazy_ptr) ;
bctr ;
.lazy_symbol_pointer

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L_foo$lazy_ptr: ;
.indirect_symbol _foo ; the symbol pointer
.long dyld_stub_binding_helper ; to be replaced by _foo's address

In the assembly code, _func branches to L_foo$stub, which is responsible for finding the definition
of the function foo(). L_foo$stub jumps to the contents of L_foo$lazy_ptr. This value is initially
the address of the dyld_stub_binding_helper code, which after executing causes it to overwrite
the contents of L_foo$lazy_ptr with the address of the real function, _foo, and jump to _foo.

The indirect symbol entries for _foo provide information to the static and dynamic linkers for binding
the symbol stub. Each symbol stub and lazy pointer entry must have exactly one such indirect symbol,
associated with the first address in the stub or pointer entry. See “.indirect_symbol” (page 48) for
more information.

The static link editor places only one copy of each stub into the output file’s section for a particular
indirect symbol, and relocates all references to the stubs with the same indirect symbol to the stub in
the output file. Further, the static link editor eliminates a stub if a definition of the indirect symbol
for that stub is present in the output file and that output file isn't a multi-module dynamically linked
shared library file. The stub can refer only to itself, one lazy symbol pointer (referring to the same
indirect symbol as the stub), and the dyld_stub_binding_helper() function. No global symbols
can be defined in this type of section.

lazy_symbol_pointers (S_LAZY_SYMBOL_POINTERS)

A lazy_symbol_pointers section contains 4-byte symbol pointers that eventually contain the value
of the indirect symbol associated with the pointer. These pointers are used by symbol stubs to lazily
bind undefined function calls at runtime. A lazy symbol pointer initially contains an address in the
symbol stub of instructions that cause the symbol pointer to be bound to the function definition (in
the example in “symbol_stubs (S_SYMBOL_STUBS)” (page 33), the lazy pointer L_foo$lazy_ptr
initially contains the address for dyld_stub_binding_helper but gets overwritten with the address
for _foo). The dynamic link editor binds the indirect symbol associated with the lazy symbol pointer
by overwriting it with the value of the symbol.

The static link editor places a copy of a lazy pointer in the output file only if the corresponding symbol
stub is in the output file. Only the corresponding symbol stub can make a reference to a lazy symbol
pointer, and no global symbols can be defined in this type of section. There must be one indirect
symbol associated with each lazy symbol pointer. An example of a lazy_symbol_pointers section
is one in which the compiler has generated calls to undefined functions, each of which can be bound
lazily at the time of the first call to the function.

non_lazy_symbol_pointers (S_NON_LAZY_SYMBOL_POINTERS)

A non_lazy_symbol_pointers section contains 4-byte symbol pointers that contain the value of the
indirect symbol associated with a pointer that may be set at any time before any code makes a reference
to it. These pointers are used by the code to reference undefined symbols. Initially these pointers have
no interesting value but get overwritten by the dynamic link editor with the value of the symbol for
the associated indirect symbol before any code can make a reference to it.

The static link editor places only one copy of each non-lazy pointer for its indirect symbol into the
output file and relocates all references to the pointer with the same indirect symbol to the pointer in
the output file. The static link editor futher can fill in the pointer with the value of the symbol if a
definition of the indirect symbol for that pointer is present in the output file. No global symbols can
be defined in this type of section. There must be one indirect symbol assocated with each non-lazy
symbol pointer. An example of a non_lazy_symbol_pointers section is one in which the compiler

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has generated code to indirectly reference undefined symbols to be bound at runtime—this preserves
the sharing of the machine instructions by allowing the dynamic link editor to update references
without writing on the instructions.

Here's an example of assembly code referencing an element in the undefined structure. The
corresponding C code would be:

struct s {
int member1, member2;
};
extern struct s bar;
int func()
{
return(bar.member2);
}

The PowerPC assembly code might look like this:

.text
.align 2
.globl _func
_func:
lis r3,ha16(L_bar$non_lazy_ptr)
lwz r2,lo16(L_bar$non_lazy_ptr)(r3)
lwz r3,4(r2)
blr
.non_lazy_symbol_pointer
L_bar$non_lazy_ptr:
.indirect_symbol _bar
.long 0

mod_init_funcs (S_MOD_INIT_FUNC_POINTERS)

A mod_init_funcs section contains 4-byte pointers to functions that are to be called just after the
module containing the pointer is bound into the program by the dynamic link editor. The static link
editor does no special processing for this section type except for disallowing section ordering. This
is done to maintain the order the functions are called (which is the order their pointers appear in the
original module). There must be exactly one relocation entry for each pointer in this section. An
example of a mod_init_funcs section is one in which the compiler has generated code to call C++
constructors for modules that get dynamicly bound at runtime.

mod_term_funcs (S_MOD_TERM_FUNC_POINTERS)

A mod_term_funcs section contains 4-byte pointers to functions that are to be called just before the
module containing the pointer is unloaded by the dynamic link editor or the program is terminated.
The static link editor does no special processing for this section type except for disallowing section
ordering. This is done to maintain the order the functions are called (which is the order their pointers
appear in the original module). There must be exactly one relocation entry for each pointer in this
section. An example of a mod_term_funcs section is one in which the compiler has generated code
to call C++ deconstructors for modules that get dynamically bound at runtime.

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coalesced (S_COALESCED)

A coalesced section can contain any instructions or data and is used when more than one definition
of a symbol could be defined in multiple object files being linked together. The static link editor keeps
the data associated with the coalesced symbol from the first object file it links and silently discards
the data from other object files. An example of a coalesced section is one in which the compiler has
generated code for implicit instantiations of C++ templates.

Attribute Identifiers

The following sections describe attribute identifiers.

none (0)

No attributes for this section. This is the default section attribute.

S_ATTR_SOME_INSTRUCTIONS

This attribute is set by the assembler whenever it assembles a machine instruction in a section. There
is no directive associated with it, since you cannot set it yourself. It is used by the dynamic link editor
together with S_ATTR_EXT_RELOC and S_ATTR_LOC_RELOC, set by the static link editor, to know it
must flush the cache and other processor-related functions when it relocates instructions by writing
on them.

no_dead_strip (S_ATTR_NO_DEAD_STRIP)

The no_dead_strip section attribute specifies that a particular section must not be dead-stripped.
See “Directives for Dead-Code Stripping” (page 51) for more information.

no_toc (S_ATTR_NO_TOC)

The no_toc section attribute means that the global symbols in this section are not to be used in the
table of contents of a static library as produced by the program ranlib(1). This is normally used
with a coalesced section when it is expected that each object file has a definition of the symbols that
it uses.

live_support (S_ATTR_LIVE_SUPPORT)

The live_support section attribute specifies that a section’s blocks must not be dead-stripped if they
reference code that is live, but the reference is undetectable. See “Directives for Dead-Code
Stripping” (page 51) for more information.

pure_instructions (S_ATTR_PURE_INSTRUCTIONS)

The pure_instructions attribute means that this section contains nothing but machine instructions.
This attribute would be used for the (__TEXT,__text) section of Mac OS X compilers and sections
that have a section type of symbol_stubs.

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strip_static_syms (S_ATTR_STRIP_STATIC_SYMS)

The strip_static_syms section attribute means that the static symbols in this section can be stripped
from linked images that are used with the dynamic linker when debugging symbols are also stripped.
This is normally used with a coalesced section that has private extern symbols, so that after linking
and the private extern symbols have been turned into static symbols they can be stripped to save
space in the linked image.

Built-in Directives
The directives described here are simply built-in equivalents for .section directives with specific
arguments.

Designating Sections in the __TEXT Segment

The directives listed below cause the assembler to begin assembling into the indicated section of the
__TEXT segment. Note that the underscore before __TEXT, __text, and the rest of the segment names
is actually two underscore characters.

Directive Section

.text (__TEXT,__text)

.const (__TEXT,__const)

.static_const (__TEXT,__static_const)

.cstring (__TEXT,__cstring)

.literal4 (__TEXT,__literal4)

.literal8 (__TEXT,__literal8)

.constructor (__TEXT,__constructor)

.destructor (__TEXT,__destructor)

.fvmlib_init0 (__TEXT,__fvmlib_init0)

.fvmlib_init1 (__TEXT,__fvmlib_init1)

.symbol_stub (__TEXT,__symbol_stub)

.picsymbol_stub (__TEXT, __picsymbol_stub)

The following sections describe the sections in the __TEXT segment and the types of information that
should be assembled into each of them.

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.text

This is equivalent to .section __TEXT,__text,regular,pure_instructions when the default

-dynamic flag is in effect and equivalent to .section __TEXT,__text,regular when the -static
flag is specified.

The compiler places only machine instructions in the (__TEXT,__text) section (no read-only data,
jump tables or anything else). With this, the entire (__TEXT,__text) section is pure instructions and
tools that operate on object files. The runtime can take advantage of this to locate the instructions of
the program and not get confused with data that could have been mixed in. To make this work, all
runtime support code linked into the program must also obey this rule (all Mac OS X library code
follows this rule).

.const

This is equivalent to .section __TEXT,__const

The compiler places all data declared const and all jump tables it generates for switch statements in
this section.

.static_const

This is equivalent to .section __TEXT,__static_const

This is not currently used by the compiler. It was added to the assembler so that the compiler may
separate global and static const data into separate sections if it wished to.

.cstring

This is equivalent to .section __TEXT,__cstring, cstring_literals

This section is marked with the section type cstring_literals, which the link editor recognizes.
The link editor merges the like literal C strings in all the input object files to one unique C string in
the output file. Therefore this section must contain only C strings (a C string in a sequence of bytes
that ends in a null byte, \0, and does not contain any other null bytes except its terminator). The
compiler places literal C strings found in the code that are not initializers and do not contain any
embedded nulls in this section.

.literal4

This is equivalent to .section __TEXT,__literal4,4byte_literals

This section is marked with the section type 4byte_literals, which the link editor recognizes. The
link editor can then merge the like 4 byte literals in all the input object files to one unique 4 byte literal
in the output file. Therefore, this section must contain only 4 byte literals. This is typically intended
for single precision floating-point constants and the compiler uses this section for that purpose. On
some machines it is more efficient to place these constants in line as immediates as part of the
instruction.

.literal8

This is equivalent to .section __TEXT,__literal8,8byte_literals

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This section is marked with the section type 8byte_literals, which the link editor recognizes. The
link editor then can merge the like 8 byte literals in all the input object files to one unique 8 byte literal
in the output file. Therefore, this section must only contain 8 byte literals. This is typically intended
for double precision floating-point constants and the compiler uses this section for that purpose. On
some machines it is more efficient to place these constants in line as immediates as part of the
instruction.

.constructor

This is equivalent to .section __TEXT,__constructor

.destructor

This is equivalent to .section __TEXT,__destructor

The .constructor and .destructor sections are used by the C++ runtime system, and are reserved
exclusively for the C++ compiler.

.fvmlib_init0

This is equivalent to .section __TEXT,__fvmlib_init0

.fvmlib_init1

This is equivalent to .section __TEXT,__fvmlib_init1

The .fvmlib_init0 and .fvmlib_init1 sections are used by the obsolete fixed virtual memory
shared library initialization. The compiler doesn't place anything in these sections, as they are reserved
exclusively for the obsolete shared library mechanism.

.symbol_stub

This is equivalent to .section __TEXT,__symbol_stub, symbol_stubs,

pure_instructions,NBYTES

This section is of type symbol_stubs and has the attribute pure_instructions. The compiler places
symbol stubs in this section for undefined functions that are called in the module. This is the standard
symbol stub section for nonposition-independent code. The value NBYTES is dependent on the target
architecture. The standard symbol stub for the PowerPC is 20 bytes and has an alignment of 4 bytes
(.align 2) . For example, a stub for the symbol _foo would be (using a lazy symbol pointer
L_foo$lazy_ptr):

symbol_stub
L_foo$stub:
.indirect_symbol _foo
lis r11,ha16(L_foo$lazy_ptr)
lwz r12,lo16(L_foo$lazy_ptr)(r11)
mtctr r12
addi r11,r11,lo16(L_foo$lazy_ptr)
bctr

.lazy_symbol_pointer
L_foo$lazy_ptr:

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Assembler Directives

.indirect_symbol _foo
.long dyld_stub_binding_helper

The standard symbol stub for the i386 is 16 bytes and has an alignment of 1 byte (.align 0). For
example, a stub for the symbol _foo would be (using a lazy symbol pointer L_foo$lazy_ptr):

.symbol_stub
L_foo$stub:
.indirect_symbol _foo
ljmp L_foo$lazy_ptr
L_foo$stub_binder:
pushl $L_foo$lazy_ptr
jmp dyld_stub_binding_helper

.lazy_symbol_pointer
L_foo$lazy_ptr:
.indirect_symbol _foo
.long Lfoo$stub_binder

.picsymbol_stub

This is equivalent to .section __TEXT, __picsymbol_stub, symbol_stubs, pure_instructions,

NBYTES

This section is of type symbol_stubs and has the attribute pure_instructions. The compiler
places symbol stubs in this section for undefined functions that are called in the module. This is the
standard symbol stub section for position-independent code. The value of NBYTES is dependent on
the target architecture.

The standard position-independent symbol stub for the PowerPC is 36 bytes and has an alignment
of 4 bytes (.align 2). For example, a stub for thesymbol _foo would be (using a lazy symbol pointer
L_foo$lazy_ptr):

.picsymbol_stub
L_foo$stub:
.indirect_symbol _foo
mflr r0
bcl 20,31,L0$_foo
L0$_foo:
mflr r11
addis r11,r11,ha16(L_foo$lazy_ptr - L0$_foo)
mtlr r0
lwz r12,lo16(L_foo$lazy_ptr - L0$_foo)(r11)
mtctr r12
addi r11,r11,lo16(L_foo$lazy_ptr - L0$_foo)
bctr

The standard position-independent symbol stub for the i386 is 26 bytes and has an alignment of 1
byte (.align 0). For example, a stub for the symbol _foo would be (using a lazy symbol pointer
L1$lz):

.picsymbol_stub
L_foo$stub:
.indirect_symbol _foo
call LPC$1
LPC$1:
popl %eax

40 Directives for Designating the Current Section

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Assembler Directives

movl L1$lz - LPC$1(%eax),%edx

jmp %edx
L_foo$stub_binder:
lea L1$lz - LPC$1(%eax),%eax
pushl %eax
jmp dyld_stub_binding_helper
.lazy_symbol_pointer
L1$lz:
.indirect_symbol _foo
.long L_foo$stub_binder

Designating Sections in the __DATA Segment

These directives cause the assembler to begin assembling into the indicated section of the __DATA
segment:

Directive Section

.data (__DATA,__data)

.static_data (__DATA,__static_data)

.non_lazy_symbol_pointer (__DATA,__nl_symbol_pointer)

.lazy_symbol_pointer (__DATA,__la_symbol_pointer)

.dyld (__DATA,__dyld)

.mod_init_func (__DATA,__mod_init_func)

.mod_term_func (__DATA,__mod_term_func)

.const_data (__DATA,__const)

The following sections describe the sections in the __DATA segment and the types of information that
should be assembled into each of them.

.data

This is equivalent to .section __DATA, __data

The compiler places all non-const initialized data (even initialized to zero) in this section.

.static_data

This is equivalent to .section __DATA, __static_data

This is not currently used by the compiler. It was added to the assembler so that the compiler could
separate global and static data symbol into separate sections if it wished to.

.const_data

This is equivalent to .section __DATA, __const, regular.

Directives for Designating the Current Section 41

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Assembler Directives

This section is of type regular and has no attributes. This section is used when dynamic code is being
compiled for const data that must be initialized.

.lazy_symbol_ptr

This is equivalent to .section __DATA, __la_symbol_ptr,lazy_symbol_pointers

This section is of type lazy_symbol_pointers and has no attributes. The compiler places a lazy
symbol pointer in this section for each symbol stub it creates for undefined functions that are called
in the module. (See “.symbol_stub” (page 39) for examples.) This section has an alignment of 4 bytes
(.align 2).

.non_lazy_symbol_ptr

This is equivalent to .section __DATA, __nl_symbol_ptr,non_lazy_symbol_pointers

This section is of type non_lazy_symbol_pointers and has no attributes. The compiler places a
non-lazy symbol pointer in this section for each undefined symbol referenced by the module (except
for function calls). This section has an alignment of 4 bytes (.align 2).

.mod_init_func

This is equivalent to .section __DATA, __mod_init_func, mod_init_funcs

This section is of type mod_init_funcs and has no attributes. The C++ compiler places a pointer to
a function in this section for each function it creates to call the deconstructors (if the module has them).

.mod_term_func

This is equivalent to .section __DATA, __mod_term_func, mod_term_funcs

This section is of type mod_term_funcs and has no attributes. The C++ compiler places a pointer to
a function in this section for each function it creates to call the deconstructors (if the module has them).

.dyld

This is equivalent to .section __DATA, __dyld,regular

This section is of type regular and has no attributes. This section is used by the dynamic link editor.
The compiler doesn’t place anything in this section, as it is reserved exclusively for the dynamic link
editor.

Designating Sections in the __OBJC Segment

These directives cause the assembler to begin assembling into the indicated section of the __OBJC
segment (or the __TEXT segment):

Directive Section

.objc_class (__OBJC,__class)

.objc_meta_class (__OBJC,__meta_class)

42 Directives for Designating the Current Section

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Assembler Directives

Directive Section

.objc_cat_cls_meth (__OBJC,__cat_cls_meth)

.objc_cat_inst_meth (__OBJC,__cat_inst_meth)

.objc_protocol (__OBJC,__protocol)

.objc_string_object (__OBJC,__string_object)

.objc_cls_meth (__OBJC,__cls_meth)

.objc_inst_meth (__OBJC,__inst_meth)

.objc_cls_refs (__OBJC,__cls_refs)

.objc_message_refs (__OBJC,__message_refs)

.objc_symbols (__OBJC,__symbols)

.objc_category (__OBJC,__category)

.objc_class_vars (__OBJC,__class_vars)

.objc_instance_vars (__OBJC,__instance_vars)

.objc_module_info (__OBJC,__module_info)

.objc_class_names (__TEXT,__cstring)

.objc_meth_var_types (__TEXT,__cstring)

.objc_meth_var_names (__TEXT,__cstring)

.objc_selector_strs (__OBJC,__selector_strs)

All sections in the __OBJC segment, including old sections that are no longer used and future sections
that may be added, are exclusively reserved for the Objective-C compiler’s use.

Directives for Moving the Location Counter

This section describes directives that advance the location counter to a location higher in memory.
They have the additional effect of setting the intervening memory to some value.

.align
SYNOPSIS

.align align_expression [ , 1byte_fill_expression [,max_bytes_to_fill]]

.p2align align_expression [ , 1byte_fill_expression [,max_bytes_to_fill]]
.p2alignw align_expression [ , 2byte_fill_expression [,max_bytes_to_fill]]

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Assembler Directives

.p2alignl align_expression [ , 4byte_fill_expression [,max_bytes_to_fill]]

.align32 align_expression [ , 4byte_fill_expression [,max_bytes_to_fill]]

The align directives advance the location counter to the next align_expression boundary, if it isn't
currently on such a boundary. align_expression is a power of 2 between 0 and 15 (for example, the
argument of .align 3 means 2 ^ 3 (8)–byte alignment). The fill expression, if specified, must be
absolute. The space between the current value of the location counter and the desired value is filled
with the fill expression (or with zeros, if fill_expression isn't specified). The space between the current
value of the location counter to the alignment of the fill expression width is filled with zeros first.
Then the fill expression is used until the desired alignment is reached. max_bytes_to_fill is the maximum
number of bytes that are allowed to be filled for the align directive. If the align directive can't be done
in max_bytes_to_fill or less, it has no effect. If there is no fill_expression and the section has the
pure_instructions attribute, or contains some instructions, the nop opcode is used as the fill
expression.

Note: The assembler enforces no alignment for any bytes created in the object file (data or machine
instructions). You must supply the desired alignment before any directive or instruction.

EXAMPLE

.align 3
one: .double 0r1.0

.org
SYNOPSIS

.org expression [ , fill_expression ]

The .org directive sets the location counter to expression, which must be a currently known absolute
expression. This directive can only move the location counter up in address. The fill expression, if
specified, must be absolute. The space between the current value of the location counter and the
desired value is filled with the low-order byte of the fill expression (or with zeros, if fill_expression
isn’t specified).

Note: If the output file is later link-edited, the .org directive isn’t preserved.

EXAMPLE

.org 0x100,0xff

Directives for Generating Data

The directives described in this section generate data. (Unless specified otherwise, the data goes into
the current section.) In some respects, they are similar to the directives explained in “Directives for
Moving the Location Counter” (page 43)—they do have the effect of moving the location counter—but
this isn’t their primary purpose.

44 Directives for Generating Data

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Assembler Directives

.ascii and .asciz

SYNOPSIS

.ascii [ “string” ] [ , “string” ] ...

.asciz [ “string” ] [ , “string” ] ...

These directives translate character strings into their ASCII equivalents for use in the source program.
Each directive takes zero or more comma-separated strings surrounded by quotation marks. Each
string can contain any character or escape sequence that can appear in a character string; the newline
character cannot appear, but it can be represented by the escape sequence \012 or \n:

■ The .ascii directive generates a sequence of ASCII characters.

■ The .asciz directive is similar to the .ascii directive, except that it automatically terminates
the sequence of ASCII characters with the null character (\0), necessary when generating strings
usable by C programs.

If no strings are specified, the directive is ignored.

EXAMPLE

.ascii "Can't open the DSP.\0"

.asciz "%s has changes.\tSave them?"

.byte, .short, .long, and .quad

SYNOPSIS

.byte [ expression ] [ , expression ] ...

.short [ expression ] [ , expression ] ...
.long [ expression ] [ , expression ] ...
.quad [ expression ] [ , expression ] ...

These directives reserve storage locations in the current section and initialize them with specified
values. Each directive takes zero or more comma-separated absolute expressions and generates a
sequence of bytes for each expression. The expressions are truncated to the size generated by the
directive:

■ .byte generates 1 byte per expression.

■ .short generates 2 bytes per expression.

■ .long generates 4 bytes per expression.

■ .quad generates 8 bytes per expression.

EXAMPLE

.byte 74,0112,0x4A,0x4a,'J | the same byte

.short 64206,0175316,0xface | the same short
.long -1234,037777775456,0xfffffb2e | the same long
.quad -1234,01777777777777777775456,0xfffffffffffffb2e | the same quad

Directives for Generating Data 45

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Assembler Directives

Note: The .quad directive doesn’t handle a relocatable expression of the form .quad foo - bar
when the values of foo or bar are more than 32 bits.

.comm
SYNOPSIS

.comm name, size

The .comm directive creates a common symbol named name of size bytes. If the symbol isn’t defined
elsewhere, its type is “common.”

The link editor allocates storage for common symbols that aren’t otherwise defined. Enough space is
left after the symbol to hold the maximum size (in bytes) seen for each symbol in the
(__DATA,__common) section.

The link editor aligns each such symbol (based on its size aligned to the next greater power of two)
to the maximum alignment of the (__DATA,__common) section. For information about how to change
the maximum alignment, see the description of -sectalign in the ld(1) Mac OS X man page.

EXAMPLE

.comm _global_uninitialized,4

.fill
SYNOPSIS

.fill repeat_expression , fill_size , fill_expression

The .fill directive advances the location counter by repeat_expression times fill_size bytes:

■ fill_size is in bytes, and must have the value 1, 2, or 4

■ repeat_expression must be an absolute expression greater than zero
■ fill_expression may be any absolute expression (it gets truncated to the fill size)

EXAMPLE

.fill 69,4,0xfeadface | put out 69 0xfeadface’s

.lcomm
SYNOPSIS

.lcomm name, size [ , align ]

The .lcomm directive creates a symbol named name of size bytes in the (__DATA,__bss) section. It
contains zeros at execution. The name isn’t declared as global, and hence is unknown outside the
object module.

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Assembler Directives

The optional align expression, if specified, causes the location counter to be rounded up to an align
power-of-two boundary before assigning the location counter to the value of name.

EXAMPLE

.lcomm abyte,1 | or: .lcomm abyte,1,0

.lcomm padding,7
.lcomm adouble,8 | or: .lcomm adouble,8,3

These are the same as:

.zerofill __DATA,__bss,abyte,1
.lcomm __DATA,__bss,padding,7
.lcomm __DATA,__bss,adouble,8

.single and .double

SYNOPSIS

.single [ number ] [ , number ] ...

.double [ number ] [ , number ] ...

These directives reserve storage locations in the current section and initialize them with specified
values. Each directive takes zero or more comma-separated decimal floating-point numbers:

■ .single takes IEEE single-precision floating point numbers. It reserves 4 bytes for each number
and initializes them to the value of the corresponding number.
■ .double takes IEEE double-precision floating point numbers. It reserves 8 bytes for each number
and initializes them to the value of the corresponding number.

EXAMPLE

.single 3.33333333333333310000e-01
.double 0.00000000000000000000e+00
.single +Infinity
.double -Infinity
.single NaN

.space
SYNOPSIS

.space num_bytes [ , fill_expression ]

The .space directive advances the location counter by num_bytes, where num_bytes is an absolute
expression greater than zero. The fill expression, if specified, must be absolute. The space between
the current value of the location counter and the desired value is filled with the low-order byte of the
fill expression (or with zeros, if fill_expression isn’t specified).

EXAMPLE

ten_ones:
.space 10,1

Directives for Generating Data 47

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Assembler Directives

Directives for Dealing With Symbols

This section describes directives that have an effect on symbols and the symbol table.

.globl
SYNOPSIS

.globl symbol_name

The .globl directive makes symbol_name external. If symbol_name is otherwise defined (by .set or
by appearance as a label), it acts within the assembly exactly as if the .globl statement was not given;
however, the link editor may be used to combine this object module with other modules referring to
this symbol.

EXAMPLE

.globl abs
.set abs,1

.globl var
var: .long 2

.indirect_symbol
SYNOPSIS:

.indirect_symbol symbol_name

The .indirect_symbol directive creates an indirect symbol withsymbol_name and associates the
current location with the indirect symbol. An indirect symbol must be defined immediately before
each item in a symbol_stub, lazy_symbol_pointers, and non_lazy_symbol_pointers section.
The static and dynamic linkers usesymbol_name to identify the symbol associated with the item
following the directive.

.reference
SYNOPSIS

.reference symbol_name

The .reference directive causes symbol_name to be an undefined symbol present in the output file’s
symbol table. This is useful in referencing a symbol without generating any bytes to do it (used, for
example, by the Objective-C runtime system to reference superclass objects).

EXAMPLE

.reference .objc_class_name_Object

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Assembler Directives

.weak_reference
SYNOPSIS

.weak_reference symbol_name

The .weak_reference directive causes symbol_name to be a weak undefined symbol present in the
output file’s symbol table. This is used by the compiler when referencing a symbol with the
weak_import attribute.

EXAMPLE

.weak_reference .objc_class_name_Object

.lazy_reference
SYNOPSIS

.lazy_reference symbol_name

The .lazy_reference directive causes symbol_name to be a lazy undefined symbol present in the
output file’s symbol table. This is useful when referencing a symbol without generating any bytes to
do it (used, for example, by the Objective-C runtime system with the dynamic linker to reference
superclass objects but allow the runtime to bind them on first use).

EXAMPLE

.lazy_reference .objc_class_name_Object

.weak_definition
SYNOPSIS

.weak_definition symbol_name

The .weak_definition directive causes symbol_name to be a weak definition. symbol_name can be

defined only in a coalesced section. This is used by the C++ compiler to support template instantiation.
The compiler uses a coalesced section with the .weak_definition directive for implicitly instantiated
templates. And it uses a regular section (.text, .data, a so on) for an explicit template instantiation.

.private_extern
SYNOPSIS:

.private_extern symbol_name

Directives for Dealing With Symbols 49

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Assembler Directives

The .private_extern directive makes symbol_name a private external symbol. When the link editor
combines this module with other modules (and the -keep_private_externs command-line option
is not specified) the symbol turns it from global to static. If both .private_extern and .globl
assembler directives are used on the same symbol, the effect is as if only the .private_extern directive
was used.

.stabs, .stabn, and .stabd

SYNOPSIS

.stabs n_name , n_type , n_other , n_desc , n_value

.stabn n_type , n_other , n_desc , n_value
.stabd n_type , n_other , n_desc

These directives are used to place symbols in the symbol table for the symbolic debugger (a “stab”
is a symbol table entry).

■ .stabs specifies all the fields in a symbol table entry. n_name is the name of a symbol; if the
symbol name is null, the .stabn directive may be used instead.
■ .stabn is similar to .stabs, except that it uses a NULL ("") name.

■ .stabd is similar to .stabn, except that it uses the value of the location counter (.) as the n_value
field.

Note: The n_other field of a .stabs directive is ignored, and the value of the n_sect field (what was
the n_other field) is set based on the symbol used for the n_value parameter.

In each case, the n_type field is assumed to contain a 4.3BSD-like value for the N_TYPE bits (defined
in mach-o/stab.h). For .stabs and .stabn, the n_sect field of the Mach-O file’s nlist is set to the
section number of the symbol for the specified n_value parameter. For .stabd, the n_sect field is set
to the current section number for the location counter. The nlist structure is defined in
mach-o/nlist.h.

EXAMPLE

.stabs "hello.c",100,0,0,Ltext
.stabn 192,0,0,LBB2
.stabd 68,0,15

.desc
SYNOPSIS

.desc symbol_name , absolute_expression

The .desc directive sets the n_desc field of the specified symbol to absolute_expression.

EXAMPLE

.desc _environ, 0x10 ; set the REFERENCED_DYNAMICALLY bit

50 Directives for Dealing With Symbols

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Assembler Directives

.set
SYNOPSIS

.set symbol_name , absolute_expression

The .set directive creates the symbol symbol_name and sets its value to absolute_expression. This is the
same as using symbol_name=absolute_expression.

EXAMPLE

.set one,1
two = 2

.lsym
SYNOPSIS

.lsym symbol_name , expression

A unique and otherwise unreferenceable symbol of the symbol_name, expression pair is created in the
symbol table. The symbol created is a static symbol with a type of absolute (N_ABS). Some Fortran 77
compilers use this mechanism to communicate with the debugger.

Directives for Dead-Code Stripping

Dead-code stripping is the process by which the static link editor removes unused code and data
blocks from executable files. This process helps reduce the overall size of executables, which in turn
improves performance by reducing the memory footprint of the executable. It also allows programs
to link successfully in the situation where unused code refers to an undefined symbol, something
that would normally result in a link error. For more information on dead-code stripping, see "Linking"
in Xcode 2.2 User Guide.

The following sections describe the dead-code stripping directives.

.subsections_via_symbols
SYNOPSIS

.subsections_via_symbols

The .subsections_via_symbols directive tells the static link editor that the sections of the object
file can be divided into individual blocks. These blocks are then stripped if they are not used by other
code. This directive applies to all section declarations in the assembly file and should be placed outside
any section declarations, as shown here:

.subsections_via_symbols

; Section declarations...

Directives for Dead-Code Stripping 51

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Assembler Directives

When using this directive, ensure that each symbol in the section is at the beginning of a block of
code. Implicit dependencies between blocks of code may result in the removal of needed code from
the executable. For example, the following section contains three symbols, but execution of the code
at _plus_three ends at the blr statement at the bottom of the code block:

.text
.globl _plus_three
_plus_three:
addi r3, r3, 1
.globl _plus_two
_plus_two:
addi r3, r3, 1
.globl _plus_one
_plus_one:
addi r3, r3, 1
blr

If you use the .subsections_via_symbols directive on this code and _plus_two and _plus_three
are not called by any other code, the static link editor would not add _plus_two and _plus_one to
the executable. In that case, _plus_three would not return the correct value because part of its
implementation would be missing. In addition, if _plus_one is dead-stripped, the program may crash
when _plus_three is executed, as it would continue executing into the following block.

.no_dead_strip
SYNOPSIS

.no_dead_strip symbol_name

The .no_dead_strip directive tells the assembler that the symbol specified by symbol_name must
not be dead-stripped. For example, the following code prevents _my_version_string from being
dead-stripped:

.no_dead_strip _my_version_string
.cstring
_my_version_string:
.ascii "Version 1.1"

Miscellaneous Directives

This section describes additional directives that don’t fit into any of the previous sections.

.abort
SYNOPSIS

.abort [ "abort_string" ]

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Assembler Directives

The .abort directive causes the assembler to ignore further input and quit processing. No files are
created. The directive could be used, for example, in a pipe-interconnected version of a compiler—the
first major syntax error would cause the compiler to issue this directive, saving unnecessary work in
assembling code that would have to be discarded anyway.

The optional abort_string is printed as part of the error message when the .abort directive is
encountered.

EXAMPLE

#ifndef VAR
.abort "You must define VAR to assemble this file."
#endif

.abs
SYNOPSIS

.abs symbol_name , expression

This directive sets the value of symbol_name to 1 if expression is an absolute expression; otherwise, it
sets the value to zero.

EXAMPLE

.macro var
.abs is_abs,$0
.if is_abs==1
.abort "must be absolute"
.endif
.endmacro

.dump and .load

SYNOPSIS

.dump filename
.load filename

These directives let you dump and load the absolute symbols and macro definitions for faster loading
and faster assembly.

These work like this:

.include "big_file_1"
.include "big_file_2"
.include "big_file_3"
...
.include "big_file_N"
.dump "symbols.dump"

The .dump directive writes out all the N_ABS symbols and macros. You can later use the .load
directive to load all the N_ABS symbols and macros faster than you could with .include:

Miscellaneous Directives 53
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Assembler Directives

.load "symbols.dump"

One useful side effect of loading symbols this way is that they aren’t written out to the object file.

.file and .line

SYNOPSIS

.file file_name
.line line_number

The .file directive causes the assembler to report error messages as if it were processing the file
file_name.

The .line directive causes the assembler to report error messages as if it were processing the line
line_number. The next line after the .line directive is assumed to be line_number.

The assembler turns C preprocessor comments of the form:

# line_number file_name level

into:

.line line_number; .file file_name

EXAMPLE

.line 6
nop | this is line 6

.if, .elseif, .else, and .endif

SYNOPSIS

.if expression
.elseif expression
.else
.endif

These directives are used to delimit blocks of code that are to be assembled conditionally, depending
on the value of an expression. A block of conditional code may be nested within another block of
conditional code. expression must be an absolute expression.

For each .if directive:

■ there must be a matching .endif

■ there may be as many intervening .elseif’s as desired
■ there may be no more than one intervening .else before the tailing .endif

Labels or multiple statements must not be placed on the same line as any of these directives; otherwise,
statements including these directives are not recognized and produce errors or incorrect conditional
assembly.

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Assembler Directives

EXAMPLE

.if a==1
.long 1
.elseif a==2
.long 2
.else
.long 3
.endif

.include
SYNOPSIS

.include "filename"

The .include directive causes the named file to be included at the current point in the assembly. The
-Idir option to the assembler specifies alternative paths to be used in searching for the file if it isn’t
found in the current directory.

EXAMPLE

.include "macros.h"

.machine
SYNOPSIS

.machine arch_type

The .machine directive specifies the target architecture of the assembly file. arch_type can be any
architecture type you can specify in the -arch option of the assembler driver. See “Assembler
Options” (page 11) for more information.

.macro, .endmacro, .macros_on, and .macros_off

SYNOPSIS

.macro
.endmacro
.macros_on
.macros_off

These directives allow you to define simple macros (once a macro is defined, however, you can’t
redefine it). For example:

.macro var
instruction_1 $0,$1
instruction_2 $2
. . .
instruction_N
.long $n

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Assembler Directives

.endmacro

$d (where d is a single decimal digit, 0 through 9) represents each argument—there can be at most
10 arguments. $n is replaced by the actual number of arguments the macro is invoked with.

When you use a macro, arguments are separated by a comma (except inside matching parentheses—for
example, xxx(1,3,4),yyy contains only two arguments). You could use the macro defined above as
follows:

var #0,@sp,4

This would be expanded to:

instruction_1 #0,@sp
instruction_2 4
. . .
instruction_N
.long 3

The directives .macros_on and .macros_off allow macros to be written that override an instruction
or directive while still using the instruction or directive. For example:

.macro .long
.macros_off
.long $0,$0
.macros_on
.endmacro

If you don’t specify an argument, the macro substitutes nothing (see “.abs” (page 53)).

PowerPC-Specific Directives

The following directives are specific to the PowerPC architecture.

.flag_reg
SYNOPSIS

.flag_reg reg_number

This causes the uses of the reg_number general register to get flagged as warnings. This is intended
for use in macros.

.greg
SYNOPSIS

.greg symbol_name, expression...

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Assembler Directives

This directive sets symbol_name to 1 when expression is a general register or zero otherwise. It is
intended for use in macros.

.no_ppc601
SYNOPSIS

This causes PowerPC 601 instructions to be flagged as errors. This is the same as if the -no_ppc601
option is specified.

.noflag_reg
SYNOPSIS

.noflag_reg reg_number

This turns off the flagging of the uses of the reg_number general register so they don’t get flagged as
warnings. This is intended for use in macros.

Additional Processor-Specific Directives

The following processor-specific directives are synonyms for other standard directives described
earlier in this chapter; although they are listed here for completeness, their use isn’t recommended.
Wherever possible, you should use the standard directive instead.

The following are i386-specific directives:

i386 Directive Standard Directive

.ffloat .single

.dfloat .double

.tfloat [expression] ¨ 80-bit IEEE extended precision floating-point

.word .short

.value .short

.ident (ignored)

.def (ignored)

.optim (ignored)

.version (ignored)

.ln (ignored)

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58 Additional Processor-Specific Directives

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PowerPC Addressing Modes and

Assembler Instructions

This chapter contains information specific to the PowerPC processor architecture.

PowerPC Registers and Addressing Modes

This section describes the conventions used to specify addressing modes and instruction mnemonics
for the PowerPC series processor architecture. The instructions themselves are detailed in the next
section, “PowerPC Assembler Instructions” (page 67).

Registers
Many instructions accept register names as operands. The available register names are listed in this
section. These are the user registers:

Register Description

r0-r31 General Purpose Registers

f0-f31 Floating-Point Registers

xer Fixed-Point Exception Register

fpscr Floating-Point Status and Control Register

cr Condition Register

lr Link Register

ctr Count Register

v0–v31 Vector Registers (AltiVec specific)

For instructions that take either 0 or a general purpose register as an operand, r0 may not be used as
either a zero or a register operand; the literal value 0 must be used instead.

These are the special registers

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Registers Description

sr0-sr15 Segment Registers

Operands and Addressing Modes

The PowerPC processor architecture has only one addressing mode for load and store instructions:
register plus displacement. The general form for address operands is:

displacement(register)

If there is no displacement, the parentheses around the register name must still be used. For example,
the first two of the following statements are legal, but the last isn't:

lwz r12,4(r1)
lwz r12,(r1) ; same as displacement of 0
lwz r12,r1 ; INCORRECT

To specify an arbitrary 32-bit address, two instructions must be used, since all instructions are 32 bits
long and can't contain both an opcode and a full address. A pair of instructions used to load or store
data at an address falls into one of a small set of idioms, using the assembler operators lo16(), hi16(),
and ha16() to isolate the required portion of the 32-bit address expression. The idioms themselves
are discussed below

■ lo16(expression) evaluates to the low (least significant) 16 bits of expression, with a relocation type
of PPC_RELOC_LO16, PPC_RELOC_LO14, PPC_RELOC_LO16_SECTDIFF, or
PPC_RELOC_LO14_SECTDIFF depending on the instruction and the expression it is used with.
■ hi16(expression) evaluates to the high (most significant) 16 bits of expression shifted right 16 bits,
with a relocation type of PPC_RELOC_HI16 or PPC_RELOC_HI16_SECTDIFF depending on the
expression it is used with.
■ ha16(expression) evaluates to the high (most significant) 16 bits of expression shifted right 16 bits,
increased by one if bit 15 of expression is set (that is, if the value given by lo16(expression) is
negative). This allows the address to be properly reconstituted when the low 16 bit quantity of
expression is sign-extended by some operators. It has a relocation type of PPC_RELOC_HA16 or
PPC_RELOC_HA16_SECTDIFF depending on the expression it is used with.

In specifying a 32-bit address, the desired result is that the 32-bit quantity be in a register. To do this,
the high and low 16 bits of the address are entered separately with instructions suited to this task.
Generally, the high 16 bits can be entered into a register with the addis (Add Immediate Shifted)
instruction and the hi16() operator. For example, this instruction:

addis r2,0,hi16(expr)

adds the high 16 bits of expr to 0, and enters the result into the high 16 bits of register 2. The instruction
that immediately follows can then combine the low 16 bits with the high 16 bits in the register and
perform whatever other operation it does (if any).

For example, to load the address of the global variable spot into general register 2, the instructions
below would be used. The ori instruction doesn't sign-extend the displacement, so the high 16 bits
of the address needn't be adjusted, and the hi16() assembler operator is used.

60 PowerPC Registers and Addressing Modes

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addis r2,0,hi16(spot) ; ori doesn't sign-extend

ori r2,r2,lo16(spot)

In loading the data stored at spot the lwz operator is used, which does sign-extend the displacement,
the adjusted high 16 bits must be given, with the ha16() assembler operator:

addis r2,0,ha16(spot) ; lwz sign-extends

lwz r3,lo16(spot)(r2)

lwz treats the sign-extended low 16 bits as a displacement, adding it to the contents of register 2 to
get a 32-bit address, and then loads the word at that address into register 3.

Extended Instruction Mnemonics & Operands

Branch Mnemonics
The PowerPC processor family supports a rich variety of extended mnemonics for its three conditional
branch operators: bc, bclr, and bcctr. Normally, the condition and the nature of the branch are
specified by numeric operands, but with the extended mnemonics, these numeric operands are
determined by the assembler from the mnemonic used.

Conditional branches can alter the contents of the Count Register (ctr), and can take effect based on
the resulting value in the Count Register, and on whether a specified condition is true or false. The
first table below summarizes the extended mnemonics for branches that affect the Count Register,
while the second summarizes additional mnemonics for branches on true and false conditions that
don't affect the Count Register. The effect of the branch is given on the left. The first four columns of
each table are for branches where the Link Register bit in the instruction is clear (not set); the remaining
columns are for branches where the Link Register bit in the instruction is set. Each set of four columns
gives mnemonics for relative and absolute branches, and for branches to the Link Register or the
Count Register.

LR not
Branch Type LR set
set

bc bca bclr bcctr bcl bcla bclrl bcctrl

to to
Rel. Abs. to LR Rel. Abs. to LR
CTR CTR

unconditional b ba blr bctr bl bla blrl bctrl

if condition true bt bta btlr btctr btl btla btlrl btctrl

if condition false bf bfa bflr bfctr bfl bfla bflrl bfctrl

decrement CTR, branch if bdnz bdnza bdnzlr – bdnzl bdnzla bdnzlrl –

CTR non-zero

Decrement CTR, branch if bdnzt bdnzta bdnztlr – bdnztl bdnztla bdnztlrl –

CTR non-zero and
condition true

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LR not
Branch Type LR set
set

bc bca bclr bcctr bcl bcla bclrl bcctrl

to to
Rel. Abs. to LR Rel. Abs. to LR
CTR CTR

Decrement CTR, branch if bdnzf bdnzfa bdnzflr – bdnzfl bdnzfla bdnzflrl –

CTR non-zero and
condition false

Decrement CTR, branch if bdz bdza bdzlr – bdzl bdzla bdzlrl –

CTR zero

Decrement CTR, branch if bdzt bdzta bdztlr – bdztl bdztla bdztlrl –

CTR zero and condition
true

Decrement CTR, branch if bdzf bdzfa bdzflr – bdzfl bdzfla bdzflrl –

CTR zero and condition
false

The mnemonics in the table above encode specific values for the BO field of the non-extended operators.
The BO field controls the effect on the Count Register and on what type of condition the branch is to
be taken. The BI field, which controls the specific condition to consider, must still be given, as the
first operand. The value of this operand indicates which field of the Condition Register to use, and
which bit within that field to consider.

The Condition Register has 8 fields, numbered 0 to 7, each of which contains a bit for conditions less
than, greater than, equal, and summary overflow or unordered. The numeric value for field n of the Condition
Register is 4*n, and the numeric values for the conditions are 0, 1, 2, and 3, respectively. The following
symbols may be used instead of numbers:

Symbol Value Meaning

lt 0 Less than

gt 1 Greater than

eq 2 Equal

so 3 Summary overflow

un 3 Unordered (after floating-point comparison)

cr0 0 Condition Register field 0

cr1 4 Condition Register field 1

cr2 8 Condition Register field 2

cr3 12 Condition Register field 3

cr4 16 Condition Register field 4

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PowerPC Addressing Modes and Assembler Instructions

Symbol Value Meaning

cr5 20 Condition Register field 5

cr6 24 Condition Register field 6

cr7 28 Condition Register field 7

For example, a branch if condition true for the condition greater than in Condition Register field 3 could
be written in any of these ways:

bt cr3+gt,target
bt 12+1,target
bt 13,target

Omitting the symbol for either the Condition Register field or the condition is permitted, as long as
the result of the expression is a number from 0-31:

bt gt,target ; uses field 0

bt cr3,target ; branches on less than in field 3
bt 13,target ; branches on less than in field 3

Another way to specify these conditions is to use the extended mnemonics in the second table, below.
These mnemonics encode the actual condition on which to take a branch. The second and third letters
of the mnemonic indicate that condition:

Code Meaning

lt Less than

le Less than or equal

eq Equal

ge Greater than or equal

gt Greater than

nl Not less than

ne Not equal

ng Not greater than

so Summary overflow

ns Not summary overflow

uo Unordered (after floating-point comparison)

nu Not unordered (after floating-point comparison)

Some condition codes, such as le, are actually more compact codes for a false result on the opposite
condition in the set of conditions given previously (for example, le is equivalent to if condition false
on condition greater than).

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PowerPC Addressing Modes and Assembler Instructions

By default, the extended mnemonics in the table below used Condition Register field 0. An optional
first operand can be given to specify another field, in either numeric form or as a symbol of the form
crn. For example:

bgt target ; branch if cr0 shows "greater than"

bgt cr3,target ; branch if cr3 shows "greater than"

Branch Type LR not set LR set

bc bca bclr bcctr bcl bcla bclrl bcctrl

Rel. Abs. to LR to CTR Rel. Abs. to LR to CTR

less than blt blta bltlr bltctr bltl bltla bltlrl bltctrl

less than or equal ble blea blelr blectr blel blela blelrl blectrl

equal beq beqa beqlr beqctr beql beqla beqlrl beqctrl

greater than or equal bge bgea bgelr bgectr bgel bgela bgerl bgectrl

greater than bgt bgta bgtlr bgtctr bgttl bgla bgtlrl bgtctrl

not less than bnl bnla bnllr bnlctr bnll bnlla bnllrl bnlctrl

not equal bne bnea bnelr bnectr bnel bnela bnelrl bnectrl

not greater than bng bnga bnglr bngctr bngl bngla bnglrl bngctrl

summary overflow bso bsoa bsolr bsoctr bsol bsola bsolrl bsoctrl

not summary overflow bns bnsa bnslr bnsctr bnsl bnsla bnslrl bnsctrl

unordered bun buna bunlr bunctr bunl bunla bunlrl bunctrl

not unordered bnu bnua bnulr bnuctr bnul bnula bnulrl bnuctrl

Branch Prediction

PowerPC processors attempt to determine whether a conditional branch is likely to be taken or not.
By default, they assume the following about conditional branches:

■ A conditional branch with a negative displacement (that is, a branch to a lower address) is predicted
to be taken. This type of branch may, for example, lead to the beginning of a loop that's repeated
many times.
■ A conditional branch with a non-negative displacement is predicted not to be taken (that is, it
falls through).
■ A conditional branch to an address in the Link or Count Registers is predicted not to be taken
(that is, it falls through).

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PowerPC Addressing Modes and Assembler Instructions

If the assembly language programmer knows the likely outcome of a conditional branch, a suffix can
be added to the mnemonic that indicates which way the branch should be predicted to go: a ‘+’
instructs the processor to predict that the branch will be taken, while a ‘-’ instructs it to predict that
the branch will not be taken. The branch prediction in for the 64-bit PowerPC AS architecture uses a
different encoding for static branch prediction than the classic PowerPC architecture. This is encoded
in the AT bits instead of the Y-bit of the conditional branch. The assembler takes ‘++’ and ‘--’
suffixes to encode branch prediction using the AT bits. The ‘+’ and ‘-’ suffixes encode the branch
prediction using the Y-bit by default. The flag -static_branch_prediction_AT_bits changes this
so that the ‘+’ and ‘-’ suffixes encode the AT bits. Where an operator allows a prediction suffix, a
‘±’ symbol appears after it in the table in “PowerPC Assembler Instructions” (page 67).

Use the jbsr pseudo instruction when you may not be able to reach the target of a branch and link
instruction with a bl instruction. The jbsr instruction uses a sequence of code called a long branch
stub which will always be able to reach the target.

jbsr _foo,L1
...
L1: lis r12,hi16(_foo) ; long branch stub
ori r12,r12,lo16(_foo)
mtctr r12
bctr

The jbsr pseudo instruction assembles to a bl instruction targeted at L1. It also generates a
PPC_RELOC_JBSR relocation entry for the symbol _foo. Then when the linker creates a non-relocatable
output file it will change the target of the bl instruction to _foo if the bl instruction's displacement
will reach. Else it will leave the bl instruction targeted at L1.

Trap Mnemonics

Like the branch-on-condition mnemonics above, the trap operator also has extended mnemonics
which encode the numeric TO field as follows:

Code Meaning TO encoding

lt Less than 16

le Less than or equal 20

eq Equal 4

ge Greater than or equal 12

gt Greater than 8

nl Not less than 12

ne Not equal 24

ng Not greater than 20

llt Logically less than 2

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PowerPC Addressing Modes and Assembler Instructions

Code Meaning TO encoding

lle Logically less than or equal 6

lge Logically greater than or equal 5

lgt Logically greater than 1

lnl Logically not less than 5

lng Logically not greater than 6

(none) Unconditional 31

The condition is indicated from the third letter of the extended mnemonics in the table below:

Trap Type 64-bit comparison 32-bit-comparison

tdi td twi tw

Immediate Register Immediate Register

unconditional – – – trap

if less than tdlti tdlt twlti twlt

if less than or equal tdlei tdle twlei twle

if equal tdeqi tdeq tweqi tweq

if greater than or equal tdgei tdge twgei twge

if greater than tdgti tdgt twgti twgt

if not less than tdnli tdnl twnli twnl

if not equal tdnei tdne twnei twne

if not greater than tdngi tdng twngi twng

if logically less than tdllti tdllt twllti twllt

if logically less than or equal tdllei tdlle twllei twlle

if logically greater than or equal tdlgei tdlge twlgei twlge

if logically greater than tdlgti tdlgt twlgti twlgt

if logically not less than tdlnli tdlnl twlnli twlnl

if logically not greater than tdlngi tdlng twlngi twlng

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PowerPC Addressing Modes and Assembler Instructions

PowerPC Assembler Instructions

Note the following points about the information contained in this section:

■ Operation Name is the name that appears in the PowerPC manuals, or the effect of the operator
for an extended mnemonic.
■ The form of operands is that used in PowerPC Microprocessor Family: The Programming Environments.
■ The order of operands is destination <- source.

A
Operator Operands Operation Name

abs RT,RA Absolute (601 specific)

abs. RT,RA

abso RT,RA

abso. RT,RA

add RT,RA,RB Add

add. RT,RA,RB

addo RT,RA,RB

addo. RT,RA,RB

addc RT,RA,RB Add Carrying

addc. RT,RA,RB

addco RT,RA,RB

addco. RT,RA,RB

adde RT,RA,RB Add Extended

adde. RT,RA,RB

addeo RT,RA,RB

addeo. RT,RA,RB

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addi RT,RA,SI Add Immediate

addic RT,RA,SI Add Immediate Carrying

addic. RT,RA,SI Add Immediate Carrying and Record

addis RT,RA,UI Add Immediate Shifted

addme RT,RA Add To Minus One Extended

addme. RT,RA

addmeo RT,RA

addmeo. RT,RA

addze RT,RA Add To Zero Extended

addze. RT,RA

addzeo RT,RA

addzeo. RT,RA

and RA,RT,RB AND

and. RA,RT,RB

andc RA,RT,RB AND with Complement

andc. RA,RT,RB

andi. RA,RT,UI AND Immediate

andis. RA,RT,UI AND Immediate Shifted

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attn UI Support Processor Attention

B
Operator Operands Operation Name

b target_addr Branch

ba target_addr

bl target_addr

bla target_addr

bc± BO,BD,target_addr Branch Conditional

bca± BO,BD,target_addr

bcl± BO,BD,target_addr

bcla± BO,BD,target_addr

bclr± BO,BD Branch Conditional to Link Register

bclr BO,BD, BH

bclr± BO,BD, BH

bclrl± BO,BD

bclrl± BO,BD,BH

bcctr± BO,BD Branch Conditional to Count Register

bcctr± BO,BD, BH

bcctrl± BO,BD

bcctrl± BO,BD,BH

bctr Branch unconditionally to CTR

bctrl

bctrl BH

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bctr± BO,BD Equiv. to bcctr± BO,BD

bctrl± BO,BD Equiv. to bcctrl± BO,BD

bdnz± target_addr Decrement CTR, branch if CTR non-zero

bdnza± target_addr

bdnzl± target_addr

bdnzla± target_addr

bdnzlr± ...to LR

bdnzlr± BH

bdnzlrl±

bdnzlrl± BH

bdnzf± CRF+COND,target_addr Decrement CTR, branch if CTR non-zero and condition false

bdnzfa± CRF+COND,target_addr

bdnzfl± CRF+COND,target_addr

bdnzfla± CRF+COND,target_addr

bdnzflr± CRF+COND ...to LR

bdnzflr± CRF+COND, BH .

bdnzflrl± CRF+COND

bdnzflrl± CRF+COND, BH

bdnzt± CRF+COND,target_addr Decrement CTR, branch if CTR non-zero and condition true

bdnzta± CRF+COND,target_addr

bdnztl± CRF+COND,target_addr

bdnztla± CRF+COND,target_addr

bdnztlr± CRF+COND ...to LR

bdnztlr± CRF+COND,BH

bdnztlrl± CRF+COND

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bdnztlrl± CRF+COND,BH

bdz± target_addr Decrement CTR, branch if CTR zero

bdza± target_addr

bdzl± target_addr

bdzla± target_addr

bdzf± CRF+COND,target_addr Decrement CTR, branch if CTR zero and condition false

bdzfa± CRF+COND,target_addr

bdzfl± CRF+COND,target_addr

bdzfla± CRF+COND,target_addr

bdzflr± CRF+COND ...to LR

bdzflr± CRF+COND,BH .

bdzflrl± CRF+COND

bdzflrl± CRF+COND,BH

bdzlr±

bdzlr± BH

bdzlrl±

bdzlrl± BH

bdzt± CRF+COND,target_addr Decrement CTR, branch if CTR zero and condition false

bdzta± CRF+COND,target_addr

bdztl± CRF+COND,target_addr

bdztla± CRF+COND,target_addr

bdztlr± CRF+COND ...to LR

bdztlr± CRF+COND,BH

bdztlrl± CRF+COND

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bdztlrl± CRF+COND,BH

beq± CRF,target_addr Branch if equal

beq± target_addr

beqa± CRF,target_addr

beqa± target_addr

beql± CRF,target_addr

beql± target_addr

beqla± CRF,target_addr

beqla± target_addr

beqctr± CRF ...to CTR

beqctr± CRF,BH

beqctr±

beqctrl± CRF

beqctrl± CRF,BH

beqctrl±

beqlr± CRF ...to LR

beqlr± CRF,BH

beqlr±

beqlrl± CRF

beqlrl± CRF,BH

beqlrl±

bf± CRF+COND,target_addr Branch if condition false

bfa± CRF+COND,target_addr

bfl± CRF+COND,target_addr

bfla± CRF+COND,target_addr

bfctr± CRF+COND ...to CTR

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bfctr± CRF+COND,BH

bfctrl± CRF+COND

bfctrl± CRF+COND,BH

bflr± CRF+COND ...to LR

bflr± CRF+COND,BH

bflrl± CRF+COND

bflrl± CRF+COND,BH

bge± CRF,target_addr Branch if greater than or equal

bge± target_addr

bgea± CRF,target_addr

bgea± target_addr

bgel± CRF,target_addr

bgel± target_addr

bgela± CRF,target_addr

bgela± target_addr

bgectr± CRF ...to CTR

bgectr± CRF,BH

bgectr±

bgectrl± CRF

bgectrl± CRF,BH

bgectrl±

bgelr± CRF ...to LR

bgelr± CRF,BH

bgelr±

bgelrl± CRF

bgelrl± CRF,BH

bgelrl±

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bgt± CRF,target_addr Branch if greater than

bgt± target_addr

bgta± CRF,target_addr

bgta± target_addr

bgtl± CRF,target_addr

bgtl± target_addr

bgtla± CRF,target_addr

bgtla± target_addr

bgtctr± CRF ...to CTR

bgtctr± CRF,BH

bgtctr±

bgtctrl± CRF

bgtctrl± CRF,BH

bgtctrl±

bgtlr± CRF ...to LR

bgtlr± CRF,BH

bgtlr±

bgtlrl± CRF

bgtlrl± CRF,BH

bgtlrl±

ble± CRF,target_addr Branch if less than or equal

ble± target_addr

blea± CRF,target_addr

blea± target_addr

blel± CRF,target_addr

blel± target_addr

blela+± CRF,target_addr

74 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

blela± target_addr

blectr± CRF ...to CTR

blectr± CRF,BH

blectr±

blectrl± CRF

blectrl± CRF,BH

blectrl±

blelr± CRF ...to LR

blelr± CRF,BH

blelr±

blelrl± CRF

blelrl± CRF,BH

blelrl±

blr Branch unconditionally to LR

blr BH

blrl

blrl BH

blt± CRF,target_addr Branch if less than

blt± target_addr

blta± CRF,target_addr

blta± target_addr

bltl± CRF,target_addr

bltl± target_addr

bltla± CRF,target_addr

bltla± target_addr

bltctr± CRF ...to CTR

PowerPC Assembler Instructions 75

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

bltctr± CRF,BH

bltctr±

bltctrl± CRF

bltctrl± CRF,BH

bltctrl±

bltlr± CRF ...to LR

bltlr± CRF,BH

bltlr±

bltlrl± CRF

bltlrl± CRF,BH

bltlrl±

bne± CRF,target_addr Branch if not equal

bne± target_addr

bnea± CRF,target_addr

bnea± target_addr

bnel± CRF,target_addr

bnel± target_addr

bnela± CRF,target_addr

bnela± target_addr

bnectr± CRF ...to CTR

bnectr± CRF,BH

bnectr±

bnectrl± CRF

bnectrl± CRF,BH

bnectrl±

bnelr± CRF ...to LR

bnelr± CRF,BH

76 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

bnelr±

bnelrl± CRF

bnelrl± CRF,BH

bnelrl±

bng± CRF,target_addr Branch if not greater than

bng± target_addr

bnga± CRF,target_addr

bnga± target_addr

bngl± CRF,target_addr

bngl± target_addr

bngla± CRF,target_addr

bngla± target_addr

bngctr± CRF ...to CTR

bngctr± CRF,BH

bngctr±

bngctrl± CRF

bngctrl± CRF,BH

bngctrl±

bnglr± CRF ...to LR

bnglr± CRF,BH

bnglr±

bnglrl± CRF

bnglrl± CRF,BH

bnglrl±

bnl± CRF,target_addr Branch if not less than

bnl± target_addr

PowerPC Assembler Instructions 77

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

bnla± CRF,target_addr

bnla± target_addr

bnll± CRF,target_addr

bnll± target_addr

bnlla± CRF,target_addr

bnlla± target_addr

bnlctr± CRF ...to CTR

bnlctr± CRF,BH

bnlctr±

bnlctrl± CRF

bnlctrl± CRF,BH

bnlctrl±

bnllr± CRF ...to LR

bnllr± CRF,BH

bnllr±

bnllrl± CRF

bnllrl± CRF,BH

bnllrl±

bns± CRF,target_addr Branch if not summary overflow

bns± target_addr

bnsa± CRF,target_addr

bnsa± target_addr

bnsl± CRF,target_addr

bnsl± target_addr

bnsla± CRF,target_addr

bnsla± target_addr

bnsctr± CRF ...to CTR

78 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

bnsctr± CRF,BH

bnsctr±

bnsctrl± CRF

bnsctrl± CRF,BH

bnsctrl±

bnslr± CRF ...to LR

bnslr± CRF,BH

bnslr±

bnslrl± CRF

bnslrl± CRF,BH

bnslrl±

bnu± CRF,target_addr Branch if not unordered

bnu± target_addr

bnua± CRF,target_addr

bnua± target_addr

bnul± CRF,target_addr

bnul± target_addr

bnula± CRF,target_addr

bnula± target_addr

bnuctr± CRF ...to CTR

bnuctr± CRF,BH

bnuctr±

bnuctrl± CRF

bnuctrl± CRF,BH

bnuctrl±

bnulr± CRF ...to LR

bnulr± CRF,BH

PowerPC Assembler Instructions 79

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

bnulr±

bnulrl± CRF

bnulrl± CRF,BH

bnulrl±

bso± CRF,target_addr Branch if summary overflow

bso± target_addr

bsoa± CRF,target_addr

bsoa± target_addr

bsol± CRF,target_addr

bsol± target_addr

bsola± CRF,target_addr

bsola± target_addr

bsoctr± CRF ...to CTR

bsoctr± CRF,BH

bsoctr±

bsoctrl± CRF

bsoctrl± CRF,BH

bsoctrl±

bsolr± CRF ...to LR

bsolr± CRF,BH

bsolr±

bsolrl± CRF

bsolrl± CRF,BH

bsolrl±

bt± CRF+COND,target_addr Branch if condition true

bta± CRF+COND,target_addr

80 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

btl± CRF+COND,target_addr

btla± CRF+COND,target_addr

btctr± CRF+COND ...to CTR

btctr± CRF+COND,BH

btctrl± CRF+COND

btlr± CRF+COND ...to LR

btlr± CRF+COND,BH

btlrl± CRF+COND

btlrl± CRF+COND,BH

bun± CRF,target_addr Branch if unordered

bun± target_addr

buna± CRF,target_addr

buna± target_addr

bunl± CRF,target_addr

bunl± target_addr

bunla± CRF,target_addr

bunla± target_addr

bunctr± CRF ...to CTR

bunctr± CRF,BH

bunctr±

bunctrl± CRF

bunctrl± CRF,BH

bunctrl±

bunlr± CRF ...to LR

bunlr± CRF,BH

bunlr±

bunlrl± CRF

PowerPC Assembler Instructions 81

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

bunlrl± CRF,BH

bunlrl±

C
Operator Operands Operation Name

clcs RD,RA Cache Line Compute Size (601 specific)

clrldi ra,rs,n Macro: rldicl ra,rs,0,n

clrldi. ra,rs,n Macro: rldicl. ra,rs,0,n

clrlsldi ra,rs,b,n Macro: rldic ra,rs,n,b-n

clrlsldi. ra,rs,b,n Macro: rldic. ra,rs,n,b-n

clrlslwi ra,rs,b,n Macro: rlwinm ra,rs,n,b-n,31-n

clrlslwi. ra,rs,b,n Macro: rlwinm. ra,rs,n,b-n,31-n

clrlwi ra,rs,n Macro: rlwinm ra,rs,0,n,31

clrlwi. ra,rs,n Macro: rlwinm. ra,rs,0,n,31

clrrdi ra,rs,n Macro: rldicr ra,rs,0,63-n

clrrdi. ra,rs,n Macro: rldicr. ra,rs,0,63-n

clrrwi ra,rs,n Macro: rlwinm ra,rs,0,0,31-n

clrrwi. ra,rs,n Macro: rlwinm. ra,rs,0,0,31-n

cmp BF,L,RA,RB Compare

cmp CRF,L,RA,RB

cmp BF,RA,RB Equiv to cmp BF,0,RA,RB

cmp CRF,L,RA,RB Equiv. to cmp CRF,0,RA,RB

cmpd RA,RB Equiv. to cmp 0,1,RA,RB

cmpd BF,RA,RB Equiv. to cmp BF,1,RA,RB

cmpd CRF,RA,RB Equiv. to cmp BF,1,RA,RB

82 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

cmpw RA,RB Equiv. to cmp 0,0,RA,RB

cmpw BF,RA,RB Equiv. to cmp BF,0,RA,RB

cmpw CRF,RA,RB Equiv. to cmp CRF,0,RA,RB

cmpi BF,L,RA,SI Compare Immediate

cmpi CRF,L,RA,SI

cmpi BF,RA,SI Equiv. to cmpi BF,0,RA,SI

cmpi CRF,RA,SI Equiv. to cmpi CRF,0,RA,SI

cmpdi RA,SI Equiv. to cmpi 0,1,RA,SI

cmpdi BF,RA,SI Equiv. to cmp BF,1,RA,SI

cmpdi CRF,RA,SI Equiv. to cmpi CRF,1,RA,SI

cmpwi RA,SI Equiv. to cmpi 0,0,RA,SI

cmpwi BF,RA,SI Equiv. to cmpi BF,0,RA,SI

cmpwi CRF,RA,SI Equiv. to cmpi CRF,0,RA,SI

cmpl BF,L,RA,RB Compare Logical

cmpl CRF,L,RA,RB

cmpl BF,RA,RB Equiv. to cmpl BF,0,RA,RB

cmpl CRF,RA,RB Equiv. to cmpl CRF,0,RA,RB

cmpld RA,RB Equiv. to cmpl 0,1,RA,RB

cmpld BF,RA,RB Equiv. to cmpl BF,1,RA,RB

cmpld CRF,RA,RB Equiv. to cmpl CRF,1,RA,RB

cmplw RA,RB Equiv. to cmpl 0,0,RA,RB

cmplw BF,RA,RB Equiv. to cmpl BF,0,RA,RB

cmplw CRF,RA,RB Equiv. to cmpl CRF,0,RA,RB

PowerPC Assembler Instructions 83

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

cmpli BF,L,RA,UI Compare Logical Immediate

cmpli CRF,L,RA,UI

cmpli BF,RA,UI Equiv. to cmpli BF,0,RA,UI

cmpli CRF,RA,UI Equiv. to cmpli CRF,0,RA,UI

cmpldi RA,UI Equiv. to cmpi 0,1,RA,UI

cmpldi BF,RA,UI Equiv. to cmpi BF,1,RA,UI

cmpldi CRF,RA,UI Equiv. to cmpi CRF,1,RA,UI

cmplwi BF,RA,UI Equiv. to cmpi BF,0,RA,UI

cmplwi CRF,RA,UI Equiv. to cmpi CRF,0,RA,UI

cmplwi RA,UI Equiv. to cmpi CRF,0,RA,UI

cntlzd RA,RT Count Leading Zeros Doubleword

cntlzd. RA,RT

cntlzw RA,RT Count Leading Zeros Word

cntlzw. RA,RT

crand BT,BA,BB Condition Register AND

crandc BT,BA,BB Condition Register AND with Complement

creqv BT,BA,BB Condition Register Equivalent

crmove BT,BA Condition Register Move (Equiv. to cror BT,BA,BA)

crnand BT,BA,BB Condition Register NAND

84 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

crnor BT,BA,BB Condition Register NOR

crnot BT,BA Condition Register NOT (Equiv. to crnor BT,BA,BA)

cror BT,BA,BB Condition Register OR

crorc BT,BA,BB Condition Register OR with Complement

crxor BT,BA,BB Condition Register XOR

D
Operator Operands Operation Name

dcba RA,RB Data Cache Block Allocate

dcbf RA,RB Data Cache Block Flush

dcbi RA,RB Data Cache Block Invalidate

dcbst RA,RB Data Cache Block Store

dcbt RA,RB Data Cache Block Touch

dcbt RA,RB,TH Data Cache Block Touch X-form

dcbt128 RA,RB,TH (same as above)

dcbtl RA,RB Data Cache Block Touch Line

dcbtl RA,RB,TH Data Cache Block Touch Line X-form

dcbtl128 RA,RB,TH (same as above)

PowerPC Assembler Instructions 85

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

dcbtst RA,RB Data Cache Block Touch for Store

dcbz RA,RB Data Cache Block Set to Zero

dcbzl RA,RB Data Cache Block Set to Zero Line

dcbzl128 RA,RB (same as above)

div RT,RA,RB Divide (601 specific)

div. RT,RA,RB

divo RT,RA,RB

divo. RT,RA,RB

divd RT,RA,RB Divide Doubleword

divd. RT,RA,RB

divdo RT,RA,RB

divdo. RT,RA,RB

divdu RT,RA,RB Divide Doubleword Unsigned

divdu. RT,RA,RB

divduo RT,RA,RB

divduo. RT,RA,RB

divs RT,RA,RB Divide Short (601 specific)

divs. RT,RA,RB

divso RT,RA,RB

divso. RT,RA,RB

divw RT,RA,RB Divide Word

86 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

divw. RT,RA,RB

divwo RT,RA,RB

divwo. RT,RA,RB

divwu RT,RA,RB Divide Word Unsigned

divwu. RT,RA,RB

divwuo RT,RA,RB

divwuo. RT,RA,RB

doz RT,RA,RB Difference or Zero (601 specific)

doz. RT,RA,RB

dozo RT,RA,RB

dozo. RT,RA,RB

dozi RT,RA,SI Difference or Zero Immediate (601 specific)

dss tag Data Stream Stop (AltiVec specific)

dssall Data Stream Stop All (AltiVec specific)

dst RA,RB,tag Data Stream Touch (AltiVec specific)

dstst RA,RB,tag Data Stream Touch for Store (AltiVec specific)

dststt RA,RB,tag Data Stream Touch for Store Transient (AltiVec specific)

dstt RA,RB,tag Data Stream Touch Transient (AltiVec specific)

E
Operator Operands Operation Name

eciwx RT,RA,RB External Control In Word Indexed

PowerPC Assembler Instructions 87

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

ecowx RT,RA,RB External Control Out Word Indexed

eieio Enforce In-order Execution of I/O

eqv RA,RT,RB Equivalent

eqv. RA,RT,RB

extldi ra,rs,n,b Macro: rldicr ra,rs,b,n-1

extldi. ra,rs,n,b Macro: rldicr. ra,rs,b,n-1

extlwi ra,rs,n,b Macro: rlwinm ra,rs,b,0,n-1

extlwi. ra,rs,n,b Macro: rlwinm. ra,rs,b,0,n-1

extrdi ra,rs,n,b Macro: rldicl ra,rs,b+n,64-n

extrdi. ra,rs,n,b Macro: rldicl. ra,rs,b+n,64-n

extrwi ra,rs,n,b Macro: rlwinm ra,rs,b+n,32-n,31

extrwi. ra,rs,n,b Macro: rlwinm. ra,rs,b+n,32-n,31

extsb RA,RT Extend Sign Byte

extsb. RA,RT

extsh RA,RT Extend Sign Halfword

extsh. RA,RT

extsw RA,RT Extend Sign Word

extsw. RA,RT

88 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

F
Operator Operands Operation Name

fabs FRT, FRB Floating Absolute Value

fabs. FRT, FRB

fadd FRT,FRA,FRB Floating Add

fadd. FRT,FRA,FRB

fadds FRT,FRA,FRB

fadds. FRT,FRA,FRB

fcfid FRT,FRB Floating Convert From Integer Doubleword

fcfid. FRT,FRB

fcmpo BF,FRA,FRB Floating Compare Ordered

fcmpo CBF,FRA,FRB

fcmpu BF,FRA,FRB Floating Compare Unordered

fcmpu CBF,FRA,FRB

fctid FRT,FRB Floating Convert to Integer Doubleword

fctid. FRT,FRB

fctidz FRT,FRB Floating Convert to Integer Doubleword with Round toward Zero

fctidz. FRT,FRB

fctiw FRT,FRB Floating Convert to Integer Word

fctiw. FRT,FRB

PowerPC Assembler Instructions 89

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

fctiwz FRT,FRB Floating Convert to Integer Word with Round toward Zero

fctiwz. FRT,FRB

fdiv FRT,FRA,FRB Floating Divide

fdiv. FRT,FRA,FRB

fdivs FRT,FRA,FRB

fdivs. FRT,FRA,FRB

fmadd FRT,FRA,FRC,FRB Floating Multiply-Add [Single]

fmadd. FRT,FRA,FRC,FRB

fmadds FRT,FRA,FRC,FRB

fmadds. FRT,FRA,FRC,FRB

fmr FRT,FRB Floating Move Register

fmr. FRT,FRB

fmsub FRT,FRA,FRC,FRB Floating Multiply-Subtract

fmsub. FRT,FRA,FRC,FRB [Single]

fmsubs FRT,FRA,FRC,FRB

fmsubs. FRT,FRA,FRC,FRB

fmul FRT,FRA,FRC Floating Multiply

fmul. FRT,FRA,FRC

fmuls FRT,FRA,FRC

fmuls. FRT,FRA,FRC

fnabs FRT,FRB Floating Negative Absolute Value

fnabs. FRT,FRB

90 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

fneg FRT,FRB Floating Negate

fneg. FRT,FRB

fnmadd FRT,FRA,FRC,FRB Floating Negative Multiply-Add [Single]

fnmadd. FRT,FRA,FRC,FRB

fnmadds FRT,FRA,FRC,FRB

fnmadds. FRT,FRA,FRC,FRB

fnmsub FRT,FRA,FRC,FRB Floating Negative Multiply-Subtract [Single]

fnmsub. FRT,FRA,FRC,FRB

fnmsubs FRT,FRA,FRC,FRB

fnmsubs. FRT,FRA,FRC,FRB

fres FRT,FRB Floating Reciprocal Estimate Single

fres. FRT,FRB

frsp FRT,FRB Floating Round to Single-Precision

frsp. FRT,FRB

frsqrte FRT,FRB Floating Reciprocal Square Root Estimate

frsqrte. FRT,FRB

fsel FRT,FRA,FRC,FRB Floating Select

fsel. FRT,FRA,FRC,FRB

fsqrt FRT,FRB Floating Square Root (Double-Precision)

fsqrt. FRT,FRB

PowerPC Assembler Instructions 91

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

fsqrts FRT,FRB Floating Square Root Single

fsqrts. FRT,FRB

fsub FRT,FRA,FRB Floating Subtract

fsub. FRT,FRA,FRB

fsubs FRT,FRA,FRB

fsubs. FRT,FRA,FRB

I
Operator Operands Operation Name

icbi RA,RB Instruction Cache Block Invalidate

inslwi ra,rs,n,b Macro: rlwimi ra,rs,32-b,b,(b+n)-1

inslwi. ra,rs,n,b Macro: rlwimi. ra,rs,32-b,b,(b+n)-1

insrdi ra,rs,n,b Macro: rldimi ra,rs,64-(b+n),b

insrdi. ra,rs,n,b Macro: rldimi. ra,rs,64-(b+n),b

insrwi ra,rs,n,b Macro: rlwimi ra,rs,32-(b+n),b,(b+n)-1

insrwi. ra,rs,n,b Macro: rlwimi. ra,rs,32-(b+n),b,(b+n)-1

isync Instruction Synchronize

J
Operator Operands Operation Name

jbsr Lstub, Lbranch_island Branch and Link (pseudo-instruction, see “Branch

Prediction” (page 64) for more)

jmp Lstub, Lbranch_island Branch (pseudo-instruction, see “Branch Prediction” (page 64)
for more)

92 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

L
Operator Operands Operation Name

la RT,D(RA) Load Address (Equiv to addi RT,RA,D)

lbz RT,D(RA) Load Byte and Zero

lbzu RT,D(RA) Load Byte and Zero with Update

lbzux RT,RA,RB Load Byte and Zero with Update Indexed

lbzx RT,RA,RB Load Byte and Zero Indexed

ld RT,DS(RA) Load Doubleword

ldarx RT,RA,RB Load Doubleword and Reserve Indexed

ldu RT,DS(RA) Load Doubleword with Update

ldux RT,RA,RB Load Doubleword with Update Indexed

ldx RT,RA,RB Load Doubleword Indexed

lfd FRT,D(RA) Load Floating-Point Double

lfdu FRT,D(RA) Load Floating-Point Double with Update

PowerPC Assembler Instructions 93

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

lfdux FRT,RA,RB Load Floating-Point Double with Update Indexed

lfdx FRT,RA,RB Load Floating-Point Double Indexed

lfs FRT,D(RA) Load Floating-Point Single

lfsu FRT,D(RA) Load Floating-Point Single with Update

lfsux FRT,RA,RB Load Floating-Point Single with Update Indexed

lfsx FRT,RA,RB Load Floating-Point Single Indexed

lha RT,D(RA) Load Halfword Algebraic

lhau RT,D(RA) Load Halfword Algebraic with Update

lhaux RT,RA,RB Load Halfword Algebraic with Update Indexed

lhax RT,RA,RB Load Halfword Algebraic Indexed

lhbrx RT,RA,RB Load Halfword Byte-Reverse Indexed

lhz RT,D(RA) Load Halfword and Zero

lhzu RT,D(RA) Load Halfword and Zero with Update

lhzux RT,RA,RB Load Halfword and Zero with Update Indexed

94 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

lhzx RT,RA,RB Load Halfword and Zero Indexed

li Rx,value Load Immediate

lis Rx,value

lmw RT,D(RA) Load Multiple Word

lscbx RT,RA,RB Load String and Compare Byte Indexed (601 specific)

lscbx. RT,RA,RB

lswi RT,RA,NB Load String Word Immediate

lswx RT,RA,RB Load String Word Indexed

lvebx VT,RA,RB Load Vector Element Byte Indexed (AltiVec specific)

lvehx VT,RA,RB Load Vector Element Halfword Indexed (AltiVec specific)

lvewx VT,RA,RB Load Vector Element Word Indexed (AltiVec specific)

lvsl VT,RA,RB Load Vector for Shift Left (AltiVec specific)

lvsr VT,RA,RB Load Vector for Shift Right (AltiVec specific)

lvx VT,RA,RB Load Vector Indexed (AltiVec specific)

lvxl VT,RA,RB Load Vector Indexed LRU (AltiVec specific)

lwa RT,DS(RA) Load Word Algebraic

lwarx RT,RA,RB Load Word and Reserve Indexed

PowerPC Assembler Instructions 95

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

lwaux RT,RA,RB Load Word Algebraic with Update Indexed

lwax RT,RA,RB Load Word Algebraic Indexed

lwbrx RT,RA,RB Load Word Byte-Reverse Indexed

lwsync Light-Weight Sync Operation

lwz RT,D(RA) Load Word and Zero

lwzu RT,D(RA) Load Word and Zero with Update

lwzux RT,RA,RB Load Word and Zero with Update Indexed

lwzx RT,RA,RB Load Word and Zero Indexed

M
Operator Operands Operation Name

maskg RA,RS,RB Mask Generate (601 specific)

maskg. RA,RS,RB

maskir RA,RS,RB Mask Insert From Register (601 specific)

maskir. RA,RS,RB

mcrf CRF,CRF Move Condition Register Field

mcrf BF,BFA

96 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

mcrfs BF,BFA Move to Condition Register from FPSCR

mcrfs CRF,BFA

mcrxr BF Move to Condition Register from XER

mcrxr CRF

mfcr RT Move From Condition Register

mfcr RT,FXM

mfctr RT Move From Count Register

mffs FRT Move From FPSCR

mffs. FRT

mfmsr RT Move From Machine State Register

mfspr RT,SPR Move From Special Purpose Register

mfxer Rx Fixed-Point Exception Register (equiv. to mfspr 1,Rx)

mflr Rx Link Register (equiv. to mfspr 8,Rx)

mfctr Rx Count Register (equiv. to mfspr 8,Rx)

mfdsisr Rx Data Storage Interrupt Status Register (macro)

mfdar Rx Data Address Register (macro)

mfdec Rx Decrementer (macro)

mfear Rx Move from External Address (Equiv. to mfspr 282, Rx)

mfsdr1 Rx Storage Description Register 1 (macro)

mfsrr0 Rx Save/Restore Register 0 (macro)

mfsrr1 Rx Save/Restore Register 1 (macro)

mfsprg n,Rx Special Purpose Register n (macro)

PowerPC Assembler Instructions 97

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PowerPC Addressing Modes and Assembler Instructions

mfasr Rx Address Space Register (macro)

mfmq Rx Move from MQ Register (601 Only) (Equiv to mfspr 0,Rx)

mfrtcd Rx Real Time Clock Divisor (macro)

mfrtcl Rx Move from Real Time Clock Lower (601 Only) (Equiv. to mfspr 5, Rx)

mfrtcu Rx Move from Real Time Clock Upper (601 Only) (Equiv. to mfspr 4, Rx)

mfrtci Rx Real Time Clock Increment (macro)

mfpvr Rx Processor Version Register (macro)

mfibatu n,Rx IBAT Register n, Upper (macro)

mfibatl n,Rx IBAT Register n, Lower (macro)

mfdbatu n,Rx DBAT Register n, Upper (macro)

mfdbatl n,Rx DBAT Register n, Lower (macro)

mfsr RT,SR Move From Segment Register

mfsrin RT,RB Move From Segment Register Indirect

mftb RT Move from Time Base

mftb RT,TBR

mftbu RT Move from Time Base Upper

mfvscr VT Move From Vector Status and Control Register (AltiVec specific)

mr Rx,Ry Move Register

mr. Rx,Ry

mtcrf FXM,RT Move to Condition Register Fields

98 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

mtfsb0 BT Move to FPSCR Bit 0

mtfsb0. BT

mtfsb1 BT Move to FPSCR Bit 1

mtfsb1. BT

mtfsf FLM,FRB Move to FPSCR Fields

mtfsf. FLM,FRB

mtfsfi BF,U Move to FPSCR Field Immediate

mtfsfi. BF,U

mtfs Rx Equiv. to mtfsf 0xFF,Rx

mtfs. Rx Equiv. to mtfsf. OxFF, Rx

mtmsr RT Move to Machine State Register

mtmsrd RA

mtmsrd RA,L

mtspr SPR,RT Move To Special Purpose Register

mtxer Rx Fixed-Point Exception Register (equiv. to mtspr 1,Rx)

mtlr Rx Link Register (equiv. to mtspr 8,Rx)

mtctr Rx Count Register (equiv. to mtspr 8,Rx)

mtdsisr Rx Data Storage Interrupt Status Register (macro)

mtdar Rx Data Address Register (macro)

mtdec Rx Decrementer (macro)

mtear Rx Move to External Address Register (Equiv. to mtspr 282,Rx)

mtsdr1 Rx Storage Description Register 1 (macro)

mtsrr0 Rx Save/Restore Register 0 (macro)

PowerPC Assembler Instructions 99

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

mtsrr1 Rx Save/Restore Register 1 (macro)

mtsprg n,Rx Special Purpose Register n (macro)

mtasr Rx Address Space Register (macro)

mtmq Rx Move to MQ Register (601 Only) (Equiv. to mtspr 0,Rx)

mtrtcd Rx Real Time Clock Divisor (macro)

mtrtcl Rx Move to Real Time Clock Lower (601 Only) (Equiv. to mtspr 21,Rx)

mtrtcu Rx Move to Real Time Clock Upper (601 Only) (Equiv. to mtspr 20,Rx)

mtrtci Rx Real Time Clock Increment (macro)

mtibatu n,Rx IBAT Register n, Upper (macro)

mtibatl n,Rx IBAT Register n, Lower (macro)

mtdbatu n,Rx DBAT Register n, Upper (macro)

mtdbatl n,Rx DBAT Register n, Lower (macro)

mtsr SR,RT Move to Segment Register

mtsrin RT,RB Move to Segment Register Indirect

mttbu RB Move to Time Base Upper (Equiv. to mtspr 285,RB)

mttrbl RB Move to Time Base Lower (Equiv. to mtspr 284,RB)

mtvscr VB Move To Vector Status and Control Register (AltiVec specific)

mul RT,RA,RB Multiply (601 specific)

mul. RT,RA,RB

mulo RT,RA,RB

mulo. RT,RA,RB

mulhd RT,RA,RB Multiply High Doubleword

mulhd. RT,RA,RB

100 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

mulhdu RT,RA,RB Multiply High Doubleword Unsigned

mulhdu. RT,RA,RB

mulhw RT,RA,RB Multiply High Word

mulhw. RT,RA,RB

mulhwu RT,RA,RB Multiply High Word Unsigned

mulhwu. RT,RA,RB

mulld RT,RA,RB Multiply Low Doubleword

mulld. RT,RA,RB

mulldo RT,RA,RB

mulldo. RT,RA,RB

mullw RT,RA,RB Multiply Low

mullw. RT,RA,RB

mullwo RT,RA,RB

mullwo. RT,RA,RB

mulli RT,RA,SI Multiply Low Immediate

N
Operator Operands Operation Name

nabs RT,RA Negative Absolute (601 specific)

nabs. RT,RA

nabso RT,RA

nabso. RT,RA

PowerPC Assembler Instructions 101

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

nand RA,RT,RB NAND

nand. RA,RT,RB

neg RT,RA Negate

neg. RT,RA

nego RT,RA

nego. RT,RA

nop No-op

nor RA,RT,RB Nor

nor. RA,RT,RB

not RA,RT Not

not. RA,RT

O
Operator Operands Operation Name

or RA,RT,RB OR

or. RA,RT,RB

orc RA,RT,RB OR with Complement

orc. RA,RT,RB

ori RA,RT,UI OR Immediate

oris RA,RT,UI OR Immediate Shifted

102 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

P
Operator Operands Operation Name

ptesync Page Table Entry Synchronize

R
Operator Operands Operation Name

rfi Return From Interrupt

rfid Return From Interrupt Doubleword

rldcl RA,RS,RB,mb Rotate Left Doubleword then Clear Left

rldcl. RA,RS,RB,mb

rldcr RA,RS,RB,mb Rotate Left Doubleword then Clear Right

rldcr. RA,RS,RB,mb

rldic RA,RS,sh,mb Rotate Left Doubleword Immediate then Clear

rldic. RA,RS,sh,mb

rldicl RA,RS,sh,mb Rotate Left Doubleword Immediate then Clear Left

rldicl. RA,RS,sh,mb

rldicr RA,RS,sh,mb Rotate Left Doubleword Immediate then Clear

rldicr. RA,RS,sh,mb Right

rldimi RA,RS,sh,mb Rotate Left Doubleword then Mask Insert

rldimi. RA,RS,sh,mb

PowerPC Assembler Instructions 103

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

rlmi RA,RS,RB,MB,ME Rotate Left then Mask Insert (601 specific)

rlmi. RA,RS,RB,MB,ME

rlmi RA,RS,RB,BM Rotate Left then Mask Insert (601 specific)

rlmi. RA,RS,RB,BM

rlwimi RA,RS,SH,MB,ME Rotate Left Word Immediate then Mask Insert

rlwimi. RA,RS,SH,MB,ME

rlwimi RA,RS,SH,BM Rotate Left Word Immediate then Mask Insert

rlwimi. RA,RS,SH,BM

rlwinm RA,RS,SH,MB,ME Rotate Left Word Immediate then AND with Mask

rlwinm. RA,RS,SH,MB,ME

rlwinm RA,RS,SH,BM Rotate Left Word Immediate then AND with Mask

rlwinm. RA,RS,SH,BM

rlwnm RA,RS,RB,MB,ME Rotate Left Word then AND with Mask

rlwnm. RA,RS,RB,MB,ME

rlwnm RA,RS,SH,BM Rotate Left Word then AND with Mask

rlwnm. RA,RS,SH,BM

rotld ra,rs,rb Macro: rldicl ra,rs,rb,0

rotld. ra,rs,rb Macro: rldicl. ra,rs,rb,0

rotldi ra,rs,n Macro: rldicl ra,rs,n,0

104 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

rotldi. ra,rs,n Macro: rldicl. ra,rs,n,0

rotlw ra,rs,rb Macro: rlwnm ra,rs,rb,0,31

rotlw. ra,rs,rb Macro: rlwnm. ra,rs,rb,0,31

rotlwi ra,rs,n Macro: rlwinm ra,rs,n,0,31

rotlwi. ra,rs,n Macro: rlwinm. ra,rs,n,0,31

rotrdi ra,rs,n Macro: rldicl ra,rs,64-n,0

rotrdi. ra,rs,n Macro: rldicl. ra,rs,64-n,0

rotrwi ra,rs,n Macro: rlwinm ra,rs,32-n,0,31

rotrwi. ra,rs,n Macro: rlwinm. ra,rs,32-n,0,31

rrib RA,RS,RB Rotate Right and Insert Bit (601 specific)

rrib. RA,RS,RB

S
Operator Operands Operation Name

sc System Call

slbia Segment Lookaside Buffer Invalidate All

slbie RB Segment Lookaside Buffer Invalidate Entry

slbmfee RS,RB SLB Move From Entry ESID

slbmfev RS,RB SLB Move From Entry VSID

slbmte RS,RB SLB Move To Entry

sld RA,RS,RB Shift Left Doubleword

PowerPC Assembler Instructions 105

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

sld. RA,RS,RB

sldi ra,rs,n Macro: rldicr ra,rs,n,63-n

sldi. ra,rs,n Macro: rldicr. ra,rs,n,63-n

slwi ra,rs,n Macro: rlwinm ra,rs,n,0,31-n

slwi. ra,rs,n Macro: rlwinm. ra,rs,n,0,31-n

sle RA,RS,RB Shift Left Extended (601 specific)

sle. RA,RS,RB

sleq RA,RS,RB Shift Left Extended with MQ (601 specific)

sleq. RA,RS,RB

sliq RA,RS,SH Shift Left Immediate with MQ (601 specific)

sliq. RA,RS,SH

slliq RA,RS,SH Shift Left Long Immediate with MQ (601 specific)

slliq. RA,RS,SH

sllq RA,RS,RB Shift Left Long with MQ (601 specific)

sllq. RA,RS,RB

slq RA,RS,RB Shift Left with MQ (601 specific)

slq. RA,RS,RB

slw RA,RS,RB Shift Left Word

slw. RA,RS,RB

106 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

srad RA,RS,RB Shift Right Algebraic Doubleword

srad. RA,RS,RB

sradi RA,RS,sh Shift Right Algebraic Doubleword Immediate

sradi. RA,RS,sh

sraiq RA,RS,SH Shift Right Algebraic Immediate with MQ (601 specific)

sraiq. RA,RS,SH

sraq RA,RS,RB Shift Right Algebraic with MQ (601 specific)

sraq. RA,RS,RB

sraw RA,RS,RB Shift Right Algebraic Word

sraw. RA,RS,RB

srawi RA,RS,SH Shift Right Algebraic Word Immediate

srawi. RA,RS,SH

srd RA,RS,RB Shift Right Doubleword

srd. RA,RS,RB

srdi ra,rs,n Macro: rldicl ra,rs,64-n,n

srdi. ra,rs,n Macro: rldicl. ra,rs,64-n,n

srwi ra,rs,n Macro: rlwinm ra,rs,32-n,n,31

srwi. ra,rs,n Macro: rlwinm. ra,rs,32-n,n,31

sre RA,RS,RB Shift Right Extended (601 specific)

sre. RA,RS,RB

PowerPC Assembler Instructions 107

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

srea RA,RS,RB Shift Right Extended Algebraic (601 specific)

srea. RA,RS,RB

sreq RA,RS,RB Shift Right Extended with MQ (601 specific)

sreq. RA,RS,RB

sriq RA,RS,SH Shift Right Immediate with MQ (601 specific)

sriq. RA,RS,SH

srliq RA,RS,SH Shift Right Long Immediate with MQ (601 specific)

srliq. RA,RS,SH

srlq RA,RS,RB Shift Right Long with MQ (601 specific)

srlq. RA,RS,RB

srq RA,RS,RB Shift Right with MQ (601 specific)

srq. RA,RS,RB

srw RA,RS,RB Shift Right Word

srw. RA,RS,RB

stb RT,D(RA) Store Byte

stbu RT,D(RA) Store Byte with Update

stbux RT,RA,RB Store Byte with Update Indexed

108 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

stbx RT,RA,RB Store Byte Indexed

std RT,DS(RA) Store Doubleword

stdcx. RT,RA,RB Store Doubleword Conditional Indexed

stdu RT,DS(RA) Store Doubleword with Update

stdux RT,RA,RB Store Doubleword with Update Indexed

stdx RT,RA,RB Store Doubleword Indexed

stfd FRT,D(RA) Store Floating-Point Double

stfdu FRT,D(RA) Store Floating-Point Double with Update

stfdux FRT,RA,RB Store Floating-Point Double with Update Indexed

stfdx FRT,RA,RB Store Floating-Point Double Indexed

stfiwx FRT,RA,RB Store Floating-Point as Integer Word Indexed

stfs FRT,D(RA) Store Floating-Point Single

stfsu FRT,D(RA) Store Floating-Point Single with Update

stfsux FRT,RA,RB Store Floating-Point Single with Update Indexed

PowerPC Assembler Instructions 109

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

stfsx FRT,RA,RB Store Floating-Point Single Indexed

sth RT,D(RA) Store Halfword

sthbrx RT,RA,RB Store Halfword Byte-Reverse Indexed

sthu RT,D(RA) Store Halfword with Update

sthux RT,RA,RB Store Halfword with Update Indexed

sthx RT,RA,RB Store Halfword Indexed

stvebx VS,RA,RB Store Vector Element Byte Indexed (AltiVec specific)

stvehx VS,RA,RB Store Vector Element Halfword Indexed (AltiVec specific)

stvewx VS,RA,RB Store Vector Element Word Indexed (AltiVec specific)

stvx VS,RA,RB Store Vector Indexed (AltiVec specific)

stvxl VS,RA,RB Store Vector Indexed LRU (AltiVec specific)

stmw RT,D(RA) Store Multiple Word

stswi RT,RA,NB Store String Word Immediate

stswx RT,RA,RB Store String Word Indexed

stw RT,D(RA) Store Word

110 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

stwbrx RT,RA,RB Store Word Byte-Reverse Indexed

stwcx. RT,RA,RB Store Word Conditional Indexed

stwu RT,D(RA) Store Word with Update

stwux RT,RA,RB Store Word with Update Indexed

stwx RT,RA,RB Store Word Indexed

sub RT,RB,RA Equiv. to subf RT,RA,RB

sub. RT,RB,RA Equiv. to subf. RT,RA,RB

subo RT,RB,RA Equiv. to subfo RT,RA,RB

subo. RT,RB,RA Equiv. to subfo. RT,RA,RB

subc RT,RB,RA Equiv. to subfc RT,RA,RB

subc. RT,RB,RA Equiv. to subfc. RT,RA,RB

subco RT,RB,RA Equiv. to subfco RT,RA,RB

subco. RT,RB,RA Equiv. to subfco. RT,RA,RB

subf RT,RA,RB Subtract From

subf. RT,RA,RB

subfo RT,RA,RB

subfo. RT,RA,RB

subfc RT,RA,RB Subtract From Carrying

subfc. RT,RA,RB

PowerPC Assembler Instructions 111

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

subfco RT,RA,RB

subfco. RT,RA,RB

subfe RT,RA,RB Subtract From Extended

subfe. RT,RA,RB

subfeo RT,RA,RB

subfeo. RT,RA,RB

subfic RT,RA,SI Subtract From Immediate Carrying

subfme RT,RA Subtract From Minus One Extended

subfme. RT,RA

subfmeo RT,RA

subfmeo. RT,RA

subfze RT,RA Subtract From Zero Extended

subfze. RT,RA

subfzeo RT,RA

subfzeo. RT,RA

subi Rx,Ry,value Equiv. to addi Rx,Ry,-value

subic Rx,Ry,value Equiv. to addic Rx,Ry,-value

subic. Rx,Ry,value Equiv. to addic. Rx,Ry,-value

subis Rx,Ry,value Equiv. to addis Rx,Ry,-value

sync Synchronize

sync L

112 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

T
Operator Operands Operation Name

td TO,RA,RB Trap Doubleword

tdeq RA,RB if equal

tdne RA,RB if not equal

tdgt RA,RB if greater than

tdge RA,RB if greater than or equal

tdng RA,RB if not greater than

tdlt RA,RB if less than

tdle RA,RB if less than or equal

tdnl RA,RB if not less than

tdlgt RA,RB if logically greater than

tdlge RA,RB if logically greater than or equal

tdlng RA,RB if logically not greater than

tdllt RA,RB if logically less than

tdlle RA,RB if logically less than or equal

tdlnl RA,RB if logically not less than

tdi TO,RA,SI Trap Doubleword Immediate

tdeqi RA,SI if equal

tdnei RA,SI if not equal

tdgti RA,SI if greater than

tdgei RA,SI if greater than or equal

tdngi RA,SI if not greater than

tdlti RA,SI if less than

tdlei RA,SI if less than or equal

tdnli RA,SI if not less than

tdlgti RA,SI if logically greater than

PowerPC Assembler Instructions 113

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

tdlgei RA,SI if logically greater than or equal

tdlngi RA,SI if logically not greater than

tdllti RA,SI if logically less than

tdllei RA,SI if logically less than or equal

tdlnli RA,SI if logically not less than

tlbia Translation Lookaside Buffer Invalidate All

tlbie RB Translation Lookaside Buffer Invalidate Entry

tlbie RB,L

tlbiel RB Translation Lookaside Buffer Invalidate Entry Local

tlbld RB Load Data TLB Entry (603 specific)

tlbli RB Load Instruction TLB Entry (603 specific)

tlbsync TLB Synchronize

trap Trap Unconditionally

tw TO,RA,RB Trap Word

tweq RA,RB if equal

twne RA,RB if not equal

twgt RA,RB if greater than

twge RA,RB if greater than or equal

twng RA,RB if not greater than

twlt RA,RB if less than

twle RA,RB if less than or equal

twnl RA,RB if not less than

114 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

twlgt RA,RB if logically greater than

twlge RA,RB if logically greater than or equal

twlng RA,RB if logically not greater than

twllt RA,RB if logically less than

twlle RA,RB if logically less than or equal

twlnl RA,RB if logically not less than

twi TO,RA,SI Trap Word Immediate

tweqi RA,RB if equal

twnei RA,RB if not equal

twgti RA,RB if greater than

twgei RA,RB if greater than or equal

twngi RA,RB if not greater than

twlti RA,RB if less than

twlei RA,RB if less than or equal

twnli RA,RB if not less than

twlgti RA,RB if logically greater than

twlgei RA,RB if logically greater than or equal

twlngi RA,RB if logically not greater than

twllti RA,RB if logically less than

twllei RA,RB if logically less than or equal

twlnli RA,RB if logically not less than

V
Operator Operands Operation Name

vaddcuw VT,VA,VB Vector Add Carry-out Unsigned Word (AltiVec specific)

vaddfp VT,VA,VB Vector Add Float (AltiVec specific)

PowerPC Assembler Instructions 115

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

Operator Operands Operation Name

vaddsbs VT,VA,VB Vector Add Signed Byte Saturate (AltiVec specific)

vaddshs VT,VA,VB Vector Add Signed Halfword Saturate (AltiVec specific)

vaddsws VT,VA,VB Vector Add Signed Word Saturate (AltiVec specific)

vaddubm VT,VA,VB Vector Add Unsigned Byte Modulo (AltiVec specific)

vaddubs VT,VA,VB Vector Add Unsigned Byte Saturate (AltiVec specific)

vadduhm VT,VA,VB Vector Add Unsigned Halfword Modulo (AltiVec specific)

vadduhs VT,VA,VB Vector Add Unsigned Halfword Saturate (AltiVec specific)

vadduwm VT,VA,VB Vector Add Unsigned Word Modulo (AltiVec specific)

vadduws VT,VA,VB Vector Add Unsigned Word Saturate (AltiVec specific)

vand VT,VA,VB Vector Logical AND (AltiVec specific)

vandc VT,VA,VB Vector Logical AND with Complement (AltiVec specific)

vmaddfp VT,VA,VC,VB Vector Multiply-Add Float (AltiVec specific)

vavgsb VT,VA,VB Vector Average Signed Byte (AltiVec specific)

vavgsh VT,VA,VB Vector Average Signed Halfword (AltiVec specific)

vavgsw VT,VA,VB Vector Average Signed Word (AltiVec specific)

vavgub VT,VA,VB Vector Average Unsigned Byte (AltiVec specific)

vavguh VT,VA,VB Vector Average Unsigned Halfword (AltiVec specific)

vavguw VT,VA,VB Vector Average Unsigned Word (AltiVec specific)

vcfsx VT,VB,UIM Vector Convert From Signed fiXed-point word (AltiVec specific)

116 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

Operator Operands Operation Name

vcfux VT,VB,UIM Vector Convert From Unsigned fiXed-point word (AltiVec specific)

vcmpbfp VT,VA,VB Vector Compare Bounds Float [Record] (AltiVec specific)

vcmpbfp. VT,VA,VB

vcmpeqfp VT,VA,VB Vector Compare Equal-To Float [Record] (AltiVec specific)

vcmpeqfp. VT,VA,VB

vcmpequb VT,VA,VB Vector Compare Equal-To Unsigned Byte [Record] (AltiVec specific)

vcmpequb. VT,VA,VB

vcmpequh VT,VA,VB Vector Compare Equal-To Unsigned Halfword [Record] (AltiVec

specific)

vcmpequh. VT,VA,VB

vcmpequw VT,VA,VB Vector Compare Equal-To Unsigned Word [Record] (AltiVec specific)

vcmpequw. VT,VA,VB

vcmpgefp VT,VA,VB Vector Compare Greater-Than-or-Equal-To Float [Record] (AltiVec

specific)

vcmpgefp. VT,VA,VB

vcmpgtfp VT,VA,VB Vector Compare Greater-Than Float [Record] (AltiVec specific)

vcmpgtfp. VT,VA,VB

vcmpgtsb VT,VA,VB Vector Compare Greater-Than Signed Byte [Record] (AltiVec specific)

vcmpgtsb. VT,VA,VB

vcmpgtsh VT,VA,VB Vector Compare Greater-Than Signed Halfword [Record] (AltiVec

specific)

vcmpgtsh. VT,VA,VB

vcmpgtsw VT,VA,VB Vector Compare Greater-Than Signed Word [Record] (AltiVec

specific)

vcmpgtsw. VT,VA,VB

PowerPC Assembler Instructions 117

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 C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

Operator Operands Operation Name

vcmpgtub VT,VA,VB Vector Compare Greater-Than Unsigned Byte [Record] (AltiVec

specific)

vcmpgtub. VT,VA,VB

vcmpgtuh VT,VA,VB Vector Compare Greater-Than Unsigned Halfword [Record] (AltiVec

specific)

vcmpgtuh. VT,VA,VB

vcmpgtuw VT,VA,VB Vector Compare Greater-Than Unsigned Word [Record] (AltiVec

specific)

vcmpgtuw. VT,VA,VB

vctsxs VT,VB,UIM Vector Convert To Signed fiXed-point word Saturate (AltiVec

specific)

vctuxs VT,VB,UIM Vector Convert To Unsigned fiXed-point word Saturate (AltiVec

specific)

vexptefp VT,VB Vector 2 Raised to the Exponent Estimate Float (AltiVec specific)

vlogefp VT,VB Vector Log 2 Estimate Float (AltiVec specific)

vmaxfp VT,VA,VB Vector Maximum Float (AltiVec specific)

vmaxsb VT,VA,VB Vector Maximum Signed Byte (AltiVec specific)

vmaxsh VT,VA,VB Vector Maximum Signed Halfword (AltiVec specific)

vmaxsw VT,VA,VB Vector Maximum Signed Word (AltiVec specific)

vmaxub VT,VA,VB Vector Maximum Unsigned Byte (AltiVec specific)

vmaxuh VT,VA,VB Vector Maximum Unsigned Halfword (AltiVec specific)

vmaxuw VT,VA,VB Vector Maximum Unsigned Word (AltiVec specific)

vmhaddshs VT,VA,VB,VC Vector Multiply-High and Add Signed Halfword Saturate (AltiVec
specific)

118 PowerPC Assembler Instructions

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C H A P T E R 5
PowerPC Addressing Modes and Assembler Instructions

Operator Operands Operation Name

vmhraddshs VT,VA,VB,VC Vector Multiply-High Round and Add Signed Halfword Saturate
(AltiVec specific)

vminfp VT,VA,VB Vector Minimum Float (AltiVec specific)

vminsb VT,VA,VB Vector Minimum Signed Byte (AltiVec specific)

vminsh VT,VA,VB Vector Minimum Signed Halfword (AltiVec specific)

vminsw VT,VA,VB Vector Minimum Signed Word (AltiVec specific)

vminub VT,VA,VB Vector Minimum Unsigned Byte (AltiVec specific)

vminuh VT,VA,VB Vector Minimum Unsigned Halfword (AltiVec specific)

vminuw VT,VA,VB Vector Minimum Unsigned Word (AltiVec specific)

vmladduhm VT,VA,VB,VC Vector Multiply-Low and Add Unsigned Halfword Modulo (AltiVec
specific)

vmr VT,VS Vector Move Register (AltiVec specific)

vmrghb VT,VA,VB Vector Merge High Byte (AltiVec specific)

vmrghh VT,VA,VB Vector Merge High Halfword (AltiVec specific)

vmrghw VT,VA,VB Vector Merge High Word (AltiVec specific)

vmrglb VT,VA,VB Vector Merge Low Byte (AltiVec specific)

vmrglh VT,VA,VB Vector Merge Low Halfword (AltiVec specific)

vmrglw VT,VA,VB Vector Merge Low Word (AltiVec specific)

vrsqrtefp VT,VB Vector Reciprocal Square Root Estimate Float (AltiVec specific)

vmsummbm VT,VA,VB,VC Vector Multiply-Sum Mixed-sign Byte Modulo (AltiVec specific)

PowerPC Assembler Instructions 119

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Operator Operands Operation Name

vmsumshm VT,VA,VB,VC Vector Multiply-Sum Signed Halfword Modulo (AltiVec specific)

vmsumshs VT,VA,VB,VC Vector Multiply-Sum Signed Halfword Saturate (AltiVec specific)

vmsumubm VT,VA,VB,VC Vector Multiply-Sum Unsigned Byte Modulo (AltiVec specific)

vmsumuhm VT,VA,VB,VC Vector Multiply-Sum Unsigned Halfword Modulo (AltiVec specific)

vmsumuhs VT,VA,VB,VC Vector Multiply-Sum Unsigned Halfword Saturate (AltiVec specific)

vmulesb VT,VA,VB Vector Multiply Even Signed Byte (AltiVec specific)

vmuleub VT,VA,VB Vector Multiply Even Unsigned Byte (AltiVec specific)

vmulesh VT,VA,VB Vector Multiply Even Signed Halfword (AltiVec specific)

vmuleuh VT,VA,VB Vector Multiply Even Unsigned Halfword (AltiVec specific)

vmulosb VT,VA,VB Vector Multiply Odd Signed Byte (AltiVec specific)

vmuloub VT,VA,VB Vector Multiply Odd Unsigned Byte (AltiVec specific)

vmulosh VT,VA,VB Vector Multiply Odd Signed Halfword (AltiVec specific)

vmulouh VT,VA,VB Vector Multiply Odd Unsigned Halfword (AltiVec specific)

vnmsubfp VT,VA,VC,VB Vector Negative Multiply-Subtract Float (AltiVec specific)

vnor VT,VA,VB Vector Logical NOR (AltiVec specific)

vnot VT,VS Vector Logical Complement (AltiVec specific)

vor VT,VA,VB Vector Logical OR (AltiVec specific)

vperm VT,VA,VB,VC Vector Permute (AltiVec specific)

vpkpx VT,VA,VB Vector Pack Pixel32 (AltiVec specific)

120 PowerPC Assembler Instructions

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PowerPC Addressing Modes and Assembler Instructions

Operator Operands Operation Name

vpkshss VT,VA,VB Vector Pack Signed Halfword Signed Saturate (AltiVec specific)

vpkshus VT,VA,VB Vector Pack Signed Halfword Unsigned Saturate (AltiVec specific)

vpkswss VT,VA,VB Vector Pack Signed Word Signed Saturate (AltiVec specific)

vpkswus VT,VA,VB Vector Pack Signed Word Unsigned Saturate (AltiVec specific)

vpkuhum VT,VA,VB Vector Pack Unsigned Halfword Unsigned Modulo (AltiVec specific)

vpkuhus VT,VA,VB Vector Pack Unsigned Halfword Unsigned Saturate (AltiVec specific)

vpkuwum VT,VA,VB Vector Pack Unsigned Word Unsigned Modulo (AltiVec specific)

vpkuwus VT,VA,VB Vector Pack Unsigned Word Unsigned Saturate (AltiVec specific)

vrefp VT,VB Vector Reciprocal Estimate Float (AltiVec specific)

vrfim VT,VB Vector Round to Floating-Point Integer toward Minus infinity

(AltiVec specific)

vrfin VT,VB Vector Round to Floating-Point Integer Nearest (AltiVec specific)

vrfip VT,VB Vector Round to Floating-Point Integer toward Positive infinity

(AltiVec specific)

vrfiz VT,VB Vector Round to Floating-Point Integer toward Zero (AltiVec specific)

vrlb VT,VA,VB Vector Rotate Left Integer Byte (AltiVec specific)

vrlh VT,VA,VB Vector Rotate Left Integer Halfword (AltiVec specific)

vrlw VT,VA,VB Vector Rotate Left Integer Word (AltiVec specific)

vsel VT,VA,VB,VC Vector Conditional Select (AltiVec specific)

vsl VT,VA,VB Vector Shift Left (AltiVec specific)

PowerPC Assembler Instructions 121

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Operator Operands Operation Name

vslb VT,VA,VB Vector Shift Left Integer Byte (AltiVec specific)

vsldoi VT,VA,VB,SH Vector Shift Left Double by Octet Immediate (AltiVec specific)

vslh VT,VA,VB Vector Shift Left Integer Halfword (AltiVec specific)

vslo VT,VA,VB Vector Shift Left by Octet (AltiVec specific)

vslw VT,VA,VB Vector Shift Left Integer Word (AltiVec specific)

vspltb VT,VB,UIM Vector Splat Byte (AltiVec specific)

vsplth VT,VB,UIM Vector Splat Halfword (AltiVec specific)

vspltisb VT,SIM Vector Splat Immediate Signed Byte (AltiVec specific)

vspltish VT,SIM Vector Splat Immediate Signed Halfword (AltiVec specific)

vspltisw VT,SIM Vector Splat Immediate Signed Word (AltiVec specific)

vspltw VT,VB,UIM Vector Splat Word (AltiVec specific)

vsr VT,VA,VB Vector Shift Right (AltiVec specific)

vsrab VT,VA,VB Vector Shift Right Algebraic Byte (AltiVec specific)

vsrah VT,VA,VB Vector Shift Right Algebraic Halfword (AltiVec specific)

vsraw VT,VA,VB Vector Shift Right Algebraic Word (AltiVec specific)

vsrb VT,VA,VB Vector Shift Right Byte (AltiVec specific)

vsrh VT,VA,VB Vector Shift Right Halfword (AltiVec specific)

vsro VT,VA,VB Vector Shift Right by Octet (AltiVec specific)

vsrw VT,VA,VB Vector Shift Right Word (AltiVec specific)

122 PowerPC Assembler Instructions

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Operator Operands Operation Name

vsubcuw VT,VA,VB Vector Subtract & write Carry-out Unsigned Word (AltiVec specific)

vsubfp VT,VA,VB Vector Subtract Float (AltiVec specific)

vsubsbs VT,VA,VB Vector Subtract Signed Byte Saturate (AltiVec specific)

vsubshs VT,VA,VB Vector Subtract Signed Halfword Saturate (AltiVec specific)

vsubsws VT,VA,VB Vector Subtract Signed Word Saturate (AltiVec specific)

vsububm VT,VA,VB Vector Subtract Unsigned Byte Modulo (AltiVec specific)

vsububs VT,VA,VB Vector Subtract Unsigned Byte Saturate (AltiVec specific)

vsubuhm VT,VA,VB Vector Subtract Unsigned Halfword Modulo (AltiVec specific)

vsubuhs VT,VA,VB Vector Subtract Unsigned Halfword Saturate (AltiVec specific)

vsubuwm VT,VA,VB Vector Subtract Unsigned Word Modulo (AltiVec specific)

vsubuws VT,VA,VB Vector Subtract Unsigned Word Saturate (AltiVec specific)

vsumsws VT,VA,VB Vector Sum Across Signed Word Saturate (AltiVec specific)

vsum2sws VT,VA,VB Vector Sum Across Partial (1/2) Signed Word Saturate (AltiVec
specific)

vsum4sbs VT,VA,VB Vector Sum Across Partial (1/4) Signed Byte Saturate (AltiVec
specific)

vsum4shs VT,VA,VB Vector Sum Across Partial (1/4) Signed Halfword Saturate (AltiVec
specific)

vsum4ubs VT,VA,VB Vector Sum Across Partial (1/4) Unsigned Byte Saturate (AltiVec
specific)

vupkhpx VT,VB Vector Unpack High Pixel16 (AltiVec specific)

vupkhsb VT,VB Vector Unpack High Signed Byte (AltiVec specific)

PowerPC Assembler Instructions 123

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Operator Operands Operation Name

vupkhsh VT,VB Vector Unpack High Signed Halfword (AltiVec specific)

vupklsb VT,VB Vector Unpack Low Signed Byte (AltiVec specific)

vupklpx VT,VB Vector Unpack Low Pixel16 (AltiVec specific)

vupklsh VT,VB Vector Unpack Low Signed Halfword (AltiVec specific)

vxor VT,VA,VB Vector Logical XOR (AltiVec specific)

X
Operator Operands Operation Name

xor RA,RT,RB XOR

xor. RA,RT,RB

xori RA,RT,UI XOR Immediate

xoris RA,RT,UI XOR Immediate Shifted

124 PowerPC Assembler Instructions

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i386 Addressing Modes and Assembler

Instructions

Important: This is a preliminary section. It has not been updated with the latest revisions to the i386
addressing modes and instructions. While most of the information is technically accurate, the document
is incomplete and is subject to change.You can check http://developer.apple.com/ for information
about updates to this and other developer documents. To receive notification of documentation
updates, you can sign up for a free Apple Developer Connection Online membership and receive the
biweekly ADC News e-mail newsletter. (See http://developer.apple.com/membership/ for more
details about ADC membership.)

This chapter contains information specific to the Intel i386 processor architecture, which includes the
i386, i486, and Pentium processors. The first section, “i386 Registers and Addressing Modes” (page 125),
lists the registers available and describes the addressing modes used by assembler instructions. The
second section, “i386 Assembler Instructions” (page 129), lists each assembler instruction with Mac
OS X assembler syntax.

Note: Don’t confuse the i386 architecture with the i386 processor. Darwin makes use of instructions
specific to the i486 and Pentium processors, and will not run on an i386 processor.

i386 Registers and Addressing Modes

This section describes the conventions used to specify addressing modes and instruction mnemonics
for the Intel i386 processor architecture. The instructions themselves are detailed in the next section,
“i386 Assembler Instructions” (page 129).

Instruction Mnemonics
The instruction mnemonics that the assembler uses are based on the mnemonics described in the
relevant Intel processor manuals.

i386 Registers and Addressing Modes 125

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i386 Addressing Modes and Assembler Instructions

Note: The Mac OS X assembler for Intel i386 processors always produces branch instructions that are
long (32 bits) for non-local labels. This allows the link editor to do procedure ordering (seethe
description of the -sectorder option in the ld(1) man page).

Registers
Many instructions accept registers as operands. The available registers are listed in this section. The
Mac OS X assembler for Intel i386 processors always uses names beginning with a percent sign (‘%’)
for registers, so naming conflicts with identifiers aren’t possible; further, all register names are in
lowercase letters.

General Registers

Each of the 32-bit general registers of the i386 architecture are accessible by different names, which
specify parts of that register to be used. For example, the AX register can be accessed as a single byte
(%ah or %al), a 16-bit value (%ax), or a 32-bit value (%eax). The figure below shows the names of
these registers and their relation to the full 32-bit storage for each register:

Figure 6-1 Register Names in the 32-bit i386 architecture

high-byte low-byte 16-bit 32-bit default use

%ah %al %ax %eax accumulator

%dh %dl %dx %edx data
%ch %cl %cx %ecx count
%bh %bl %bx %ebx base

%bp %ebp frame base pointer

%si %esi source index
%di %edi destination index
%sp %esp stack pointer

31 16|15 8|7 0

Floating-Point Registers

Register

%st

%st(0)–%st(7)

126 i386 Registers and Addressing Modes

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i386 Addressing Modes and Assembler Instructions

Segment Registers

Register Description

%cs code segment register

%ss stack segment register

%ds data segment register

%es data segment register (string operation destination segment)

%fs data segment register

%gs data segment register

Other Registers

Register Description

%cr0–%cr3 control registers

%db0–%db7 debug registers

%tr3–%tr7 test registers

%mm0–%mm7 MMX registers

%xmm0–%xmm7 XMM registers

Operands and Addressing Modes

The i386 architecture uses four kinds of instruction operands:

■ Register
■ Immediate
■ Direct Memory
■ Indirect Memory

Each type of operand corresponds to an addressing mode. Register operands specify that the value
stored in the named register is to be used by the operator. Immediate operands are constant values
specified in assembler code. Direct memory operands are the memory location of labels, or the value
of a named register treated as an address. Indirect memory operands are calculated at run time from
the contents of registers and optional constant values.

Operands and Addressing Modes 127

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i386 Addressing Modes and Assembler Instructions

Register Operands
A register operand is given simply as the name of a register. It can be any of the identifiers beginning
with ‘%’ listed above; for example, %eax. When an operator calls for a register operand of a particular
size, the operand is listed as r8, r16, or r32.

Immediate Operands
Immediate operands are specified as numeric values preceded by a dollar sign (‘$’). They are decimal
by default, but can be marked as hexadecimal by beginning the number itself with ‘0x’. Simple
calculations are allowed if grouped in parentheses. Finally, an immediate operand can be given as a
label, in which case its value is the address of that label. Here are some examples:

$100
$0x5fec4
$(10*6) # calculated by the assembler
$begloop

A reference to an undefined label is allowed, but that reference must be resolved at link time.

Direct Memory Operands

Direct memory operands are references to labels in assembler source. They act as static references to
a single location in memory relative to a specific section, and are resolved at link time. Here’s an
example:

.data
var: .byte 0 # declare a byte-size variable labelled "var"
.text
.
.
.
movb %al,var # move the low byte of the AX register into the
# memory location specified by "var"

By default, direct memory operands use the %ds segment register. This can be overridden by prefixing
the operands with the segment register desired and a colon:

movb %es:%al,var # move the low byte of the AX register into the
# memory location in the segment given by %es
# and "var"

Note that the segment override applies only to the memory operands in an instruction; “var” is
affected, but not %al. The string instructions, which take two memory operands, use the segment
override for both. A less common way of indicating a segment is to prefix the operator itself:

es/movb %al,%var # same as above

128 Operands and Addressing Modes

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i386 Addressing Modes and Assembler Instructions

Indirect Memory Operands

Indirect memory operands are calculated from the contents of registers at run time. An indirect
memory operand can contain a base register, and index register, a scale, and a displacement. The
most general form is:

displacement(base_register,index_register,scale)

displacement is an immediate value. The base and index registers may be any 32-bit general register
names, except that %esp can’t be used as an index register. scale must be 1, 2, 4, or 8; no other values
are allowed. The displacement and scale can be omitted, but at least one register must be specified.
Also, if items from the end are omitted, the preceding commas can also be omitted, but the comma
following an omitted item must remain:

10(%eax,%edx)
(%eax)
12(,%ecx,2)
12(,%ecx)

The value of an indirect memory operand is the memory location given by the contents of the register,
relative to a segment’s base address. The segment register used is %ss when the base register is %ebp
or %esp, and %ds for all other base registers. For example:

movl (%eax),%edx # default segment register here is %ds

The above assembler instruction moves 32 bits from the address given by %eax into the %edx register.
The address %eax is relative to the %ds segment register. A different segment register from the default
can be specified by prefixing the operand with the segment register name and a colon (‘:’):

movl %es:(%eax),%edx

A segment override can also be specified as an operator prefix:

es/movl (%eax),%edx

i386 Assembler Instructions

Note the following points about the information contained in this section:

■ Name is the name that appears in the upper left corner of a page in the Intel manuals.

■ Operation Name is the name that appears after the operator name in the Intel manuals.
Processor-specific instructions are marked as they occur.
■ The form of operands is that used in Intel’s i486 Microprocessor Programmer’s Reference Manual.
■ The order of operands is source -> destination, the opposite of the order in Intel’s manuals.

i386 Assembler Instructions 129

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i386 Addressing Modes and Assembler Instructions

A
Name Operator Operand Operation Name

aaa aaa ASCII Adjust after Addition

aad aad ASCII Adjust AX before Division

aam aam ASCII Adjust AX after Division

aas aas ASCII Adjust AL after Subtraction

adc adc $imm8,r/m8 Add with Carry

adc $imm16,r/m16

adc $imm32,r/m32

adc $imm8,r/m16

adc $imm8,r/m32

adc r8,r/m8

adc r16,r/m16

adc r32,r/m32

adc r/m8,r8

adc r/m16,r16

adc r/m32,r32

add add $imm8,r/m8 Add

add $imm16,r/m16

add $imm32,r/m32

add $imm8,r/m16

add $imm8,r/m32

130 i386 Assembler Instructions

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add r8,r/m8

add r16,r/m16

add r32,r/m32

add r/m8,r8

add r/m16,r16

add r/m32,r32

and and $imm8,r/m8 Logical AND

and $imm16,r/m16

and $imm32,r/m32

and $imm8,r/m16

and $imm8,r/m32

and r8,r/m8

and r16,r/m16

and r32,r/m32

and r/m8,r8

and r/m16,r16

and r/m32,r32

arpl arpl r16,r/m16 Adjust RPL Field of Selector

B
Name Operator Operand Operation Name

bound bound m16&16,r16 Check Array Index Against Bounds

bound m32&32,r32

bsf bsf r/m16,r16 Bit Scan Forward

bsf r/m32,r16

i386 Assembler Instructions 131

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bsr bsr r/m16,r16 Bit Scan Reverse

bsr r/m32,r16

bswap bswap r32 Byte Swap (i486-specific)

bt bt r16,r/m16 Bit Test

bt r32,r/m32

bt $imm8,r/m16

bt $imm8,r/m32

btc btc r16,r/m16 Bit Test and Complement

btc r32,r/m32

btc $imm8,r/m16

btc $imm8,r/m32

btr btr r16,r/m16 Bit Test and Reset

btr r32,r/m32

btr $imm8,r/m16

btr $imm8,r/m32

bts bts r16,r/m16 Bit Test and Set

bts r32,r/m32

bts $imm8,r/m16

bts $imm8,r/m32

132 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

C
Name Operator Operand Operation Name

call call rel16 Call Procedure

call r/m16

call ptr16:16

call m16:16

call rel32

call r/m32

lcall $imm16,$imm32

lcall m16

lcall m32

cbw cwde cbw Convert Byte to Word

cwde Convert Word to Doubleword

clc clc Clear Carry Flag

cld cld Clear Direction Flag

cli cli Clear Interrupt Flag

clts clts Clear Task-Switched Flag inCR0

cmc cmc Complement Carry Flag

cmp cmp $imm8,r/m8 Compare Two Operands

cmp $imm16,r/m16

i386 Assembler Instructions 133

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i386 Addressing Modes and Assembler Instructions

cmp $imm32,r/m32

cmp $imm8,r/m16

cmp $imm8,r/m32

cmp r8,r/m8

cmp r16,r/m16

cmp r32,r/m32

cmp r/m8,r8

cmp r/m16,r16

cmp r/m32,r32

cmps cmpsb cmpsw cmpsd Compare String Operands

cmps m8,m8

cmps m16,m16

cmps m32,m32

cmpsb

cmpsw

cmpsd

(optional forms with segment override)

cmpsb %seg:0(%esi),%es:0(%edi)

cmpsw %seg:0(%esi),%es:0(%edi)

cmpsd %seg:0(%esi),%es:0(%edi)

cmpxchg cmpxchg r8,r/m8 Compare and Exchange (i486-specific)

cmpxchg r16,r/m16

cmpxchg r32,r/m32

cmpxchg8b cmpxchg8b m32 Compare and Exchange 8 Bytes (Pentium-specific)

134 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

cpuid cpuid CPU Identification (Pentium-specific)

cwd cdq cwd Convert Word to Doubleword/

cdq Convert Doubleword to Quadword

D
Name Operator Operand Operation Name

daa daa Decimal Adjust AL after Addition

das das Decimal Adjust AL after Subtraction

dec dec r/m8 Decrement by 1

dec r/m16

dec r/m32

dec r16

dec r32

div div r/m8,%al Unsigned Divide

div r/m16,%ax

div r/m32,%eax

E
Name Operator Operand Operation Name

enter enter $imm16,$imm8 Make Stack Frame for Procedure Parameters

i386 Assembler Instructions 135

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i386 Addressing Modes and Assembler Instructions

F
Name Operator Operand Operation Name

f2xm1 f2xm1 Computer 2x–1

fabs fabs Absolute Value

fadd faddp fiadd Add

fadd m32real

fadd m64real

fadd ST(i),ST

fadd ST,ST(i)

faddp ST,ST(i)

fadd

fiadd m32int

fiadd m16int

fbld fbld m80dec Load Binary Coded Decimal

fbstp fbstp m80dec Store Binary Coded Decimal and Pop

fchs fchs Change Sign

fclex fnclex fclex Clear Exceptions

fnclex

fcom fcomp fcompp Compare Real

fcom m32real

136 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

fcom m64real

fcom ST(i)

fcom

fcomp m32real

fcomp m64real

fcomp ST(i)

fcomp

fcompp

fcos fcos Cosine

fdecstp fdecstp Decrement Stack-Top Pointer

fdiv fdivp fidiv Divide

fdiv m32real

fdiv m64real

fdiv ST(i),ST

fdiv ST,ST(i)

fdivp ST,ST(i)

fdiv

fidiv m32int

fidiv m16int

fdivr fdivpr fidivr Reverse Divide

fdivr m32real

fdivr m64real

fdivr ST(i),ST

fdivr ST,ST(i)

i386 Assembler Instructions 137

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i386 Addressing Modes and Assembler Instructions

fdivrp ST,ST(i)

fdivr

fidivr m32int

fidivr m16int

ffree ffree ST(i) Free Floating-Point Register

ficom ficomp Compare Integer

ficom m16real

ficom m32real

ficomp m16int

ficomp m32int

fild filds m16int Load Integer

fildl m32int

fildq m64int

fincstp fincstp Increment Stack-Top Pointer

finit fninit finit Initialize Floating-Point Unit

fninit

fist fistp fists m16int Store Integer

fistl m32int

fistps m16int

fistpl m32int

fistpq m64int

138 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

fld flds m32real Load Real

fldl m64real

fldt m80real

fld ST(i)

fld1 fldl2t fldl2e fldpi fldlg2 gldln2 fldz Load Constant

fld1

fld2t

fld2e

fldpi

fldlg2

fldln2

fldz

fldcw fldcw m2byte Load Control Word

fldenv fldenv m14/28byte Load FPU Environment

fmul fmulp fimul Multiply

fmul m32real

fmul m64real

fmul ST(i),ST

fmul ST(i),ST

fmulp ST,ST(i)

fmul

fimul m32int

fimul m16int

i386 Assembler Instructions 139

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i386 Addressing Modes and Assembler Instructions

fnop fnop No Operation

fpatan fpatan Partial Arctangent

fprem fprem Partial Remainder

fprem1 fprem1 Partial Remainder

fptan fptan Partial Tangent

frndint frndint Round to Integer

frstor frstor m94/108byte Restore FPU State

fsave fnsave Store FPU State

fsave m94/108byte

fnsave m94/108byte

fscale fscale Scale

fsin fsin Sine

fsincos fsincos Sine and Cosine

fsqrt fsqrt Square Root

fst fstp fst m32real Store Real

140 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

fst m64real

fst ST(i)

fstp m32real

fstp m64real

fstp m80real

fstp ST(i)

fstcw fnstcw Store Control Word

fstcw m2byte

fnstcw m2byte

fstenv fnstenv Store FPU Environment

fstenv m14/28byte

fnstenv m14/28byte

fstsw fnstsw Store Status Word

fstsw m2byte

fstsw %ax

fnstsw m2byte

fnstsw %ax

fsub fsubp fisub Subtract

fsub m32real

fsub m64real

fsub ST(i),ST

fsub ST,ST(i)

fsubp ST,ST(i)

fsub

i386 Assembler Instructions 141

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i386 Addressing Modes and Assembler Instructions

fisub m32int

fisub m16int

fsubr fsubpr fisubr Reverse Subtract

fsubr m32real

fsubr m64real

fsubr ST(i),ST

fsubr ST,ST(i)

fsubpr ST,ST(i)

fsubr

fisubr m32int

fisubr m16int

ftst ftst Test

fucom fucomp fucompp Unordered Compare Real

fucom ST(i)

fucom

fucomp ST(i)

fucomp

fucompp

fwait fwait Wait

fxam fxam Examine

fxch fxch ST(i) Exchange Register Contents

fxch

142 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

fxtract fxtract Extract Exponent and Significand

fyl2x fyl2x Compute y ¥ log2x

fyl2xp1 fyl2xp1 Compute y ¥ log2(x+1)

H
Name Operator Operand Operation Name

hlt hlt Halt

I
Name Operator Operand Operation Name

idiv idiv r/m8 Signed Divide

idiv r/m16,%ax

idiv r/m32,%eax

imul imul r/m8 Signed Multiply

imul r/m16

imul r/m32

imul r/m16,r16

imul r/m32,r32

imul $imm8,r/m16,r16

imul $imm8,r/m32,r32

imul $imm8,r16

imul $imm8,r32

imul $imm16,r/m16,r16

imul $imm32,r/m32,r32

i386 Assembler Instructions 143

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i386 Addressing Modes and Assembler Instructions

imul $imm16,r16

imul $imm32,r32

in in $imm8,%al Input from Port

in $imm8,%ax

in $imm8,%eax

in %dx,%al

in %dx,%ax

in %dx,%eax

inc inc r/m8 Increment by 1

inc r/m16

inc r/m32

inc r16

inc r32

ins insb insw insd Input from Port to String

ins

insb

insw

insd

int into int 3 Call to Interrupt Procedure

int $imm8

into

invd invd Invalidate Cache (i486-specific)

144 i386 Assembler Instructions

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C H A P T E R 6
i386 Addressing Modes and Assembler Instructions

invlpg invlpg m Invalidate TLB Entry (i486-specific)

iret iretd iret Interrupt Return

iretd

J
Name Operator Operand Operation Name

jcc Jump if Condition is Met

ja rel8 short if above

jae rel8 short if above or equal

jb rel8 short if below

jbe rel8 short if below or equal

jc rel8 short if carry

jcxz rel8 short if %cx register is 0

jecxz rel8 short if %ecx register is 0

je rel8 short if equal

jz rel8 short if 0

jg rel8 short if greater

jge rel8 short if greater or equal

jl rel8 short if less

jle rel8 short if less or equal

jna rel8 short if not above

jnae rel8 short if not above or equal

jnb rel8 short if not below

jnbe rel8 short if not below or equal

jnc rel8 short if not carry

jne rel8 short if not equal

jng rel8 short if not greater

i386 Assembler Instructions 145

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i386 Addressing Modes and Assembler Instructions

Name Operator Operand Operation Name

jnge rel8 short if not greater or equal

jnl rel8 short if not less

jnle rel8 short if not less or equal

jno rel8 short if not overflow

jnp rel8 short if not parity

jns rel8 short if not sign

jnz rel8 short if not 0

jo rel8 short if overflow

jp rel8 short if parity

jpe rel8 short if parity even

jpo rel8 short if parity odd

js rel8 short if sign

jz rel8 short if zero

ja rel16/32 near if above

jae rel16/32 near if above or equal

jb rel16/32 near if below

jbe rel16/32 near if below or equal

jc rel16/32 near if carry

je rel16/32 near if equal

jz rel16/32 near if 0

jg rel16/32 near if greater

jge rel16/32 near if greater or equal

jl rel16/32 near if less

jle rel16/32 near if less or equal

jna rel16/32 near if not above

jnae rel16/32 near if not above or equal

jnb rel16/32 near if not below

146 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

Name Operator Operand Operation Name

jnbe rel16/32 near if not below or equal

jnc rel16/32 near if not carry

jne rel16/32 near if not equal

jng rel16/32 near if not greater

jnge rel16/32 near if not greater or less

jnl rel16/32 near if not less

jnle rel16/32 near if not less or equal

jno rel16/32 near if not overflow

jnp rel16/32 near if not parity

jns rel16/32 near if not sign

jnz rel16/32 near if not 0

jo rel16/32 near if overflow

jp rel16/32 near if parity

jpe rel16/32 near if parity even

jpo rel16/32 near if parity odd

js rel16/32 near if sign

jz rel16/32 near if 0

jmp jmp rel8 Jump

jmp rel16

jmp r/m16

jmp rel32

jmp r/m32

ljmp $imm16,$imm32

ljmp m16

ljmp m32

i386 Assembler Instructions 147

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i386 Addressing Modes and Assembler Instructions

L
Name Operator Operand Operation Name

lahf lahf Load Flags into AH Register

lar lar r/m16,r16 Load Access Rights Byte

lar r/m32,r32

lea lea m,r16 Load Effective Address

lea m,r32

leave leave High Level Procedure Exit

lgdt lidt lgdt m16&32 Load Global/Interrupt

lidt m16&32 Descriptor Table Register

lgs lss lds les lfs Load Full Pointer

lgs m16:16,r16

lgs m16:32,r32

lss m16:16,r16

lss m16:32,r32

lds m16:16,r16

lds m16:32,r32

les m16:16,r16

les m16:32,r32

lfs m16:16,r16

lfs m16:32,r32

148 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

lldt lldt r/m16 Load Local Descriptor Table Register

lmsw lmsw r/m16 Load Machine Status Word

lock lock Assert LOCK# Signal Prefix

lods lodsb lodsw lodsd Load String Operand

lods m8

lods m16

lods m32

lodsb

lodsw

lodsd

(optional forms with segment override)

lodsb %seg:0(%esi),%al

lodsw %seg:0(%esi),%al

lodsd %seg:0(%esi),%al

loop loopcond Loop Control with CX Counter

loop rel8

loope rel8

loopz rel8

loopne rel8

loopnz rel8

lsl lsl r/m16,r16 Load Segment Limit

lsl r/m32,r32

i386 Assembler Instructions 149

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i386 Addressing Modes and Assembler Instructions

ltr ltr r/m16 Load Task Register

M
Name Operator Operand Operation Name

mov mov r8,r/m8 Move Data

mov r16,r/m16

mov r32,r/m32

mov r/m8,r8

mov r/m16,r16

mov r/m16,r16

mov Sreg,r/m16

mov r/m16,Sreg

mov moffs8,%al

mov moffs8,%ax

mov moffs8,%eax

mov %al,moffs8

mov %ax,moffs16

mov %eax,moffs32

mov $imm8,reg8

mov $imm16,reg16

mov $imm32,reg32

mov $imm8,r/m8

mov $imm16,r/m16

mov $imm32,r/m32

mov mov r32,%cr0 Move to/from Special Registers

mov %cr0/%cr2/%cr3,r32

mov %cr2/%cr3,r32

150 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

mov %dr0–3,r32

mov %dr6/%dr7,r32

mov r32,%dr0–3

mov r32,%dr6/%dr7

mov %tr4/%tr5/%tr6/%tr7,r32

mov r32,%tr4/%tr5/%tr6/%tr7

mov %tr3,r32

mov r32,%tr3

movs movsb movsw movsd Move Data from String to String

movs m8,m8

movs m16,m16

movs m32,m32

movsb

movsw

movsd

(optional forms with segment override)

movsb %seg:0(%esi),%es:0(%edi)

movsw %seg:0(%esi),%es:0(%edi)

movsd %seg:0(%esi),%es:0(%edi)

movsx movsx r/m8,r16 Move with Sign-Extend

movsx r/m8,r32

movsx r/m16,r32

movzx movzx r/m8,r16 Move with Zero-Extend

movzx r/m8,r32

i386 Assembler Instructions 151

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i386 Addressing Modes and Assembler Instructions

movzx r/m16,r32

mul mul r/m8,%al Unsigned Multiplication of AL or AX

mul r/m16,%ax

mul r/m32,%eax

N
Name Operator Operand Operation Name

neg neg r/m8 Two’s Complement Negation

neg r/m16

neg r/m32

nop nop No Operation

not not r/m8 One’s Complement Negation

not r/m16

not r/m32

O
Name Operator Operand Operation Name

or or $imm8,r/m8 Logical Inclusive OR

or $imm16,r/m16

or $imm32,r/m32

or $imm8,r/m16

or $imm8,r/m32

or r8,r/m8

or r16,r/m16

152 i386 Assembler Instructions

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C H A P T E R 6
i386 Addressing Modes and Assembler Instructions

Name Operator Operand Operation Name

or r32,r/m32

or r/m8,r8

or r/m16,r16

or r/m32,r32

out out %al,$imm8 Output to Port

out %ax,$imm8

out %eax,$imm8

out %al,%dx

out %ax,%dx

out %eax,%dx

outs outsb outsw outsd Output String to Port

outs r/m8,%dx

outs r/m16,%dx

outs r/m32,%dx

outsb

outsw

outsd

P
Name Operator Operand Operation Name

pop pop m16 Pop a Word from the Stack

pop m32

pop r16

pop r32

pop %ds

i386 Assembler Instructions 153

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i386 Addressing Modes and Assembler Instructions

Name Operator Operand Operation Name

pop %es

pop %ss

pop %fs

pop %gs

popa popad Pop all General Registers

popa

popad

popf popfd popf Pop Stack into FLAGS or

popfd EFLAGS Register

push push m16 Push Operand onto the Stack

push m32

push r16

push r32

push $imm8

push $imm16

push $imm32

push Sreg

pusha pushad Push all General Registers

pusha

pushad

pushf pushfd Push Flags Register onto the Stack

pushf

154 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

pushfd

R
Name Operator Operand Operation Name

rcl rcr rol ror Rotate

rcl 1,r/m8

rcl %cl,r/m8

rcl $imm8,r/m8

rcl 1,r/m16

rcl %cl,r/m16

rcl $imm8,r/m16

rcl 1,r/m32

rcl %cl,r/m32

rcl $imm8,r/m32

rcr 1,r/m8

rcr %cl,r/m8

rcr $imm8,r/m8

rcr 1,r/m16

rcr %cl,r/m16

rcr $imm8,r/m16

rcr 1,r/m32

rcr %cl,r/m32

rcr $imm8,r/m32

rol 1,r/m8

rol %cl,r/m8

rol $imm8,r/m8

rol 1,r/m16

rol %cl,r/m16

i386 Assembler Instructions 155

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i386 Addressing Modes and Assembler Instructions

Name Operator Operand Operation Name

rol $imm8,r/m16

rol 1,r/m32

rol %cl,r/m32

rol $imm8,r/m32

ror 1,r/m8

ror %cl,r/m8

ror $imm8,r/m8

ror 1,r/m16

ror %cl,r/m16

ror $imm8,r/m16

ror 1,r/m32

ror %cl,r/m32

ror $imm8,r/m32

rdmsr rdmsr Read from Model-Specific Register (Pentium-specific)

rdstc rdstc Read from Time Stamp Counter (Pentium-specific)

rep repe repz repne repnz Repeat Following String

rep ins %dx,rm8 Operation

rep ins %dx,rm16

rep ins %dx,rm32

rep movs m8,m8

rep movs m16,m16

rep movs m32,m32

rep outs rm8,%dx

rep outs rm16,%dx

156 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

rep outs rm32,%dx

rep lods m8

rep lods m16

rep lods m32

rep stos m8

rep stos m16

rep stos m32

repe cmps m8,m8

repe cmps m16,m16

repe cmps m32,m32

repe scas m8

repe scas m16

repe scas m32

repne cmps m8,m8

repne cmps m16,m16

repne cmps m32,m32

repne scas m8

repne scas m16

repne scas m32

ret ret Return from Procedure

ret $imm16

rsm rsm Resume from System-Management Mode (Pentium-specific)

S
Name Operator Operand Operation Name

sahf sahf Store AH into Flags

i386 Assembler Instructions 157

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 C H A P T E R 6
i386 Addressing Modes and Assembler Instructions

sal sar shl shr Shift

Instructions

sal 1,r/m8

sal %cl,r/m8

sal $imm8,r/m8

sal 1,r/m16

sal %cl,r/m16

sal $imm8,r/m16

sal 1,r/m32

sal %cl,r/m32

sal $imm8,r/m32

sar 1,r/m8

sar %cl,r/m8

sar $imm8,r/m8

sar 1,r/m16

sar %cl,r/m16

sar $imm8,r/m16

sar 1,r/m32

sar %cl,r/m32

sar $imm8,r/m32

shl 1,r/m8

shl %cl,r/m8

shl $imm8,r/m8

shl 1,r/m16

shl %cl,r/m16

shl $imm8,r/m16

shl 1,r/m32

shl %cl,r/m32

shl $imm8,r/m32

158 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

shr 1,r/m8

shr %cl,r/m8

shr $imm8,r/m8

shr 1,r/m16

shr %cl,r/m16

shr $imm8,r/m16

shr 1,r/m32

shr %cl,r/m32

shr $imm8,r/m32

sbb sbb $imm8,r/m8 Integer Subtraction with Borrow

sbb $imm16,r/m16

sbb $imm32,r/m32

sbb $imm8,r/m16

sbb $imm8,r/m32

sbb r8,r/m8

sbb r16,r/m16

sbb r32,r/m32

sbb r/m8,r8

sbb r/m16,r16

sbb r/m32,r32

scas scasb scasw scasd Compare String Data

scas m8

scas m16

scas m32

scasb

scasw

i386 Assembler Instructions 159

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i386 Addressing Modes and Assembler Instructions

scasd

(optional forms with segment override)

scasb %al,%seg:0(%edi)

scasw %ax,%seg:0(%edi)

scasd %eax,%seg:0(%edi)

setcc Byte Set on Condition

seta r/m8 above

setae r/m8 above or equal

setb r/m8 below

setbe r/m8 below or equal

setc r/m8 carry

sete r/m8 equal

setg r/m8 greater

setge r/m8 greater or equal

setl r/m8 less

setle r/m8 less or equal

setna r/m8 not above

setnae r/m8 not abover or equal

setnb r/m8 not below

setnbe r/m8 not below or equal

setnc r/m8 not carry

setne r/m8 not equal

setng r/m8 not greater

setnge r/m8 not greater or equal

setnl r/m8 not less

setnle r/m8 not less or equal

setno r/m8 not overflow

160 i386 Assembler Instructions

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C H A P T E R 6
i386 Addressing Modes and Assembler Instructions

setnp r/m8 not parity

setns r/m8 not sign

setnz r/m8 not zero

seto r/m8 overflow

setp r/m8 parity

setpe r/m8 parity even

setpo r/m8 parity odd

sets r/m8 sign

setz r/m8 zero

sgdt sidt sgdt m Store Global/Interrupt

sidt m Descriptor Table Register

shld shld $imm8,r16,r/m16 Double Precision Shift Left

shld $imm8,r32,r/m32

shld %cl,r16,r/m16

shld %cl,r32,r/m32

shrd shrd $imm8,r16,r/m16 Double Precision Shift Right

shrd $imm8,r32,r/m32

shrd %cl,r16,r/m16

shrd %cl,r32,r/m32

sldt sldt r/m16 Store Local Descriptor Table Register

smsw smsw r/m16 Store Machine Status Word

stc stc Set Carry Flag

i386 Assembler Instructions 161

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i386 Addressing Modes and Assembler Instructions

std std Set Direction Flag

sti sti Set Interrupt Flag

stos stosb stosw stosd Store String Data

stos m8

stos m16

stos m32

stosb

stosw

stosd

(optional forms with segment override)

stosb %al,%seg:0(%edi)

stosw %ax,%seg:0(%edi)

stosd %eax,%seg:0(%edi)

str str r/m16 Store Task Register

sub sub $imm8,r/m8 Integer Subtraction

sub $imm16,r/m16

sub $imm32,r/m32

sub $imm8,r/m16

sub $imm8,r/m32

sub r8,r/m8

sub r16,r/m16

sub r32,r/m32

sub r/m8,r8

sub r/m16,r16

162 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

sub r/m32,r32

T
Name Operator Operand Operation Name

test test $imm8,r/m8 Logical Compare

test $imm16,r/m16

test $imm32,r/m32

test r8,r/m8

test r16,r/m16

test r32,r/m32

V
Name Operator Operand Operation Name

verr verw verr r/m16 Verify a Segment for Reading or Writing

verw r/m16

W
Name Operator Operand Operation Name

wait wait Wait

wbinvd wbinvd Write-Back and Invalidate Cache (i486-specific)

wrmsr wrmsr Write to Model-Specific Register (Pentium-specific)

X
Name Operator Operand Operation Name

xadd xadd r8,r/m8 Exchange and Add (i486-specific)

i386 Assembler Instructions 163

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 C H A P T E R 6
i386 Addressing Modes and Assembler Instructions

Name Operator Operand Operation Name

xadd r16,r/m16

xadd r32,r/m32

xchg xchg r16,%ax Exchange Register/Memory

xchg %ax,r16 with Register

xchg %eax,r32

xchg r32,%eax

xchg r8,r/m8

xchg r/m8,r8

xchg r16,r/m16

xchg r/m16,r16

xchg r32,r/m32

xchg r/m32,r32

xlat xlatb xlat m8 Table Look-up Translation

xlatb

xor xor $imm8,r/m8 Logical Exclusive OR

xor $imm16,r/m16

xor $imm32,r/m32

xor $imm8,r/m16

xor $imm8,r/m32

xor r8,r/m8

xor r16,r/m16

xor r32,r/m32

xor r/m8,r8

xor r/m16,r16

164 i386 Assembler Instructions

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i386 Addressing Modes and Assembler Instructions

xor r/m32,r32

i386 Assembler Instructions 165

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i386 Addressing Modes and Assembler Instructions

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A P P E N D I X A

Mode-Independent Macros

If you want to write assembly code that runs both in 32-bit PowerPC and 64-bit PowerPC environments,
you must make sure that 32-bit–specific code runs in 32-bit environments and 64-bit–specific code
runs in 64-bit environments. This appendix introduces the macros included in the Mac OS X v10.4
SDK to facilitate the development of assembly code that runs in both environments.

The mode_independent_asm.h file in /usr/include/architecture/ppc defines a set of macros that

make it easy to write code that runs in 32-bit PowerPC and 64-bit PowerPC environments. These
macros include both manifest constants and pseudo mnemonics. For instance, the GPR_BYTES constant
is either 4 or 8 (the size of the general-purpose registers). And lg pseudo mnemonic expands to lwz
in a 32-bit environment or ld in a 64-bit environment. The header file documents all the macros in
detail.

For example, the 32-bit code to get a pointer at offset 16 from GPR15 into GPR14 is:

lwz r14,16(r15)

The 64-bit code is:

ld r14,16(r15)

One way to support both environments is by using conditional inclusion statements. For example,
the following code uses __ppc64__ to determine whether the program is running in 64-bit mode and
executes the appropriate statement:

#ifdef __ppc64__
ld r14,16(r15)
#else
lwz r14,16(r15)
#endif

However, a simpler way is to use the lg pseudo mnemonic, as shown here:

#include <architecture/ppc/mode_independent_asm.h>
...
lg r14,16(r15)

If you write code that invokes functions that may be relocated, you may need to create a lazy symbol
pointer in 32-bit code similar to this:

.lazy_symbol_pointer
L_foo$lazy_ptr:
.indirect_symbol _foo

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 A P P E N D I X A
Mode-Independent Macros

.long dyld_stub_binding_helper

The assembly sequence for is as for 64-bit code is similar to the 32-bit code, but you need to ensure
you allocate an 8-byte space for the symbol, using .quad instead of .long, as shown here:

.lazy_symbol_pointer
L_foo$lazy_ptr:
.indirect_symbol _foo
.quad dyld_stub_binding_helper

Using the g_long mode-independent macro instead of .long or .quad, you can write a streamlined
dual-environment sequence without adding an #ifdef statement. The mode-independent sequence
would look like this:

#include <architecture/ppc/mode_independent_asm.h>
...
.lazy_symbol_pointer
L_foo$lazy_ptr:
.indirect_symbol _foo
.g_long dyld_stub_binding_helper

168
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R E V I S I O N H I S T O R Y

Document Revision History

This table describes the changes to Mac OS X Assembler Guide.

Date Notes

2005-04-29 Updated content to reflect additions made to the assembler and the Mac
OS X SDK.

Added dcbtl and dcbtl128 operators to “PowerPC Assembler

Instructions” (page 67).

Added four-argument form of rlmi, rlwimi, rlwinm , and rlwnm operators.

Added “Mode-Independent Macros” (page 167) to introduce the

mode-independent macros in the Mac OS X v10.4 SDK.

2004-07-27 Added information on dead-code stripping and the .machine and .quad
assembler directives.

Added “Directives for Dead-Code Stripping” (page 51), which documents

.subsections_via_symbols and .no_dead_strip.

Added information on no_dead_strip and live_support section attributes

to “Attribute Identifiers” (page 36).

Added “.machine” (page 55), which provides details on the .machine

directive.

Added information on .quad directive to “.byte, .short, .long, and

.quad” (page 45) in “Directives for Generating Data” (page 44).

Removed all 68000-related content.

Performed minor formatting and layout changes.

2004-03-09 Clarified applicability of .private_extern directive.

2003-11-02 Added jbsr and jmp instructions to the PPC Assembler Instructions
section.

2003-09-11 Added introduction and fixed minor organization bugs.

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 R E V I S I O N H I S T O R Y
Document Revision History

Date Notes

2003-06-16 Updated with relevant information for hardware updates at WWDC.

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 Index

advancing 43
Symbols
__DATA segment 41
__OBJC segment 42 M
__TEXT segment 37
.mod_init_func assembler directive 41

A P
assembler directives 31
.picsymbol_stub assembler directive 37
pseudo-ops <Italic> See assembler directives

C
.const assembler directive 37 S
.constructor assembler directive 37
.static_data assembler directive 41
.cstring assembler directive 37
symbols 48
.symbol_stub assembler directive 37

D
.data assembler directive 41 T
data
.text assembler directive 37
generating 44
.destructor assembler directive 37

F
.fvmlib_init0 assembler directive 37
.fvmlib_init1 assembler directive 37

L
.literal4 assembler directive 37
.literal8 assembler directive 37
location counter 31

171
2005-04-29 | © 2003, 2005 Apple Computer, Inc. All Rights Reserved.