Name : Mohanapriya K

RegNo:3122223002076

Exp No. : 0
Date : 29.07.2024
STUDY OF XILINX FPGA TRAINER KIT
Aim:

To study the Xilinx FPGA Trainer Kit Specifications

1. FPGA Specifications:

1.1 Hardware: Family:

Spartan 3E Device: XC3S250E

Package: PQ208
Speed Grade: -4

1.2 Software:
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)

2. Other hardware:

2.1 Clock Generation:

The trainer kit has two clock sources:
● Fixed clock of 4MHz connected to PIN No: 181
● Manual clock by push-to-on switch connected to PIN No: 178.
When the key is pressed once, one positive going pulse will be applied to the clock pin of FPGA.

2.2 Input Signal Generation:

The input signal level is generated using DIP switches. The DIP-switch has 8 separate switches.
The switch diagram is shown below:
 Name : Mohanapriya K
RegNo:3122223002076

When the switch is ON position the output will be ‘0’ level, which is fed to FPGA as input. When the
switch is OFF position the output of this will be ‘1’ level. The ‘RC’ is used to limit the current, while
connecting to ground point.

2.3 Output’s:
The FPGA device outputs are connected to bar-graph LEDs which shows the output level. The output is
‘1’ level the LED will be glowing and when the output is at ‘0’ level the LED will be in off.

2.4 Bi-directional Lines:

The PIN Nos. 106, 107, 108, 109, 112, 113, 115 & 116 of FPGA can be used as bi-directional, in which
the output can be viewed at DS7 and the input can be set by switch S1. The circuit diagram of single line
is given below:

2.5 Edge Triggered Signals:

PIN Nos. 126, 127 and 128 are connected to push-to-on switches, which generate a positive going pulse.

2.6 Keyboard:
The trainer kit has a 4*4 key matrix connected to the FPGA I/O lines. The connection details are given
below:

2.7 Seven Segment Display:

The trainer kit has 4 digit seven segment displays, which are multiplexed. The connection detail is given
below.
 Name : Mohanapriya K
RegNo:3122223002076

2.8 LCD:
The trainer kit has one 16*2 LCD displays. The connection details are given below:

RS - LCD Register Select Signal

R/W - LCD Read / Write Signal
EN - LCD Enable Signal
D7-D0 - LCD Data Lines

2.9 26-pin FRC Lines:

FPGA Kit Interfacing Diagram

 Name : Mohanapriya K
RegNo:3122223002076

XILINX SPARTAN 3E TRAINER KIT SPECIFICATIONS

Model No: VSK-SPARTAN 3E

Key components and features:

Family: Xilinx Spartan 3E FPGA Device: XC3S500E
Package: FT256
Speed Grade: -4
16 Nos. of digital input using slide switches
16 Nos. of digital output using discrete LEDs
FPGA configuration through
● JTAG port
● Slave serial
● Onboard Flash PROM XCFO4S
Onboard programmable oscillator from 3 MHz to 200 MHz

16 Nos. of digital input using slide switches:

 Name : Mohanapriya K
RegNo:3122223002076

16 Nos. of digital output using discrete LEDs:

Result:
Thus the Xilinx FPGA Trainer Kit and their specifications have been studied.
 Name :Subiksha A R A
Reg No : 3122223002115

Exp No. : 1
Date : 05.08.2024

DESIGN AND IMPLEMENTATION OF 4-BIT FULL ADDER

Aim :

● To design and implement the adders using structural/behavioral model and verify their
functionality using Nexys A7 Artix-7 Trainer Board.
● To compile, simulate and plot the results using Xilinx Vivado.
● To implement the proposed systems using Xilinx Tools and generate the synthesis report.
● To demonstrate the working of the proposed systems using Nexys A7 Artix-7 Trainer
Board.

Equipment/Software required :

● Hardware : Nexys A7 Artix-7 FPGA Trainer Board

● Software : Xilinx Vivado

Theory:

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are A and B
and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output
is designated as S which is SUM. The C-OUT is also known as the majority 1’s detector, whose output goes
high when more than one input is high. A 1-bit full adder adds three operands and generates 2-bit results.

FUNCTIONAL DESCRIPTION:

TRUTH TABLE:

A B Carry-in Sum Carry-out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1
 Name :Subiksha A R A
Reg No : 3122223002115

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Boolean Equation:
Inputs: A, B & Cin
Outputs: Sum: A ^ B ^ Cin
Carry: (A & B) || (B & Cin) || (Cin & A)

Block Diagram:

Schematic Diagram:
 Name :Subiksha A R A
Reg No : 3122223002115

Verilog HDL Program:

module fulladd(sum,cout,a,b,c);

output sum,cout;
input a,b,c;
wire s1, c1, c2, c3;
xor(s1, a,b);
xor(sum, s1,c);
and (c1, a,b);
and (c2, b,c);
and (c3, a,c);
or (cout, c1, c2, c3);
endmodule

Stimulus File:

module fulladdstim;
reg a,b,c;
wire sum,cout;
fulladder fa(sum,cout,a,b,c);
initial
begin
$monitor ($time, "a=%b, b=%b, c=%b,sum=%b, cout=%b",a, b, c, sum, cout);
end
initial
begin
a=1'b0; b=1'b0;c=1'b0;
#5 a=1'b0;b=1'b0;c=1'b1;
#5 a=1'b0; b=1'b1;c=1'b0;
#5 a=1'b0;b=1'b1;c=1'b1;
#5 a=1'b1; b=1'b0;c=1'b0;
#5 a=1'b1;b=1'b0;c=1'b1;
#5 a=1'b1; b=1'b1;c=1'b0;
#5 a=1'b1; b=1'b1;c=1'b1;
end
endmodule
 Name :Subiksha A R A
Reg No : 3122223002115

Simulation Results:

OUTPUT WAVEFORMS

UTILIZATION REPORT:

Result :

The design and implementation of 4 bit full adder using structural/behavioral/dataflow modeling has been
successfully executed and their functionality is verified using FPGA Trainer kit.
 Name :Subiksha A R A
Reg No : 3122223002115

Exp No : 2
Date : 12.08.2024

DESIGN AND IMPLEMENTATION OF 4-BIT CARRY LOOK AHEAD ADDER

Aim :
● To design and model a 4-bit carry look ahead adder using structural/behavioral/dataflow
modeling
● To compile, simulate and plot the results using Xilinx Vivado.
● To implement the proposed systems and operate the synthesis report.
● To demonstrate the working of the proposed system using Nexys A7 Artix-7 Trainer Board.

Equipment/Software required :
● Hardware : Nexys A7 Artix-7 FPGA Trainer Board
● Software : Xilinx Vivado

Theory:
A digital computer needs circuits for arithmetic operations like addition, subtraction, multiplication, and
division. The Carry Look-ahead Adder is a faster circuit that reduces propagation delay during addition
by using more complex hardware. It allows the carry input at any stage to be independent of the bits
generated at independent stages, allowing the circuit to evaluate the carry bit at any instant without
waiting for the previous stage's generation.

FULL FUNCTIONAL DESCRIPTION:

Truth Table:

A B Ci Ci+1 Condition

0 0 0 0 No
Carry
0 0 1 0 Generate
0 1 0 0

0 1 1 1 No
Carry
1 0 0 0 Propagate

1 0 1 1

1 1 0 1 Carry
Generate
1 1 1 1
 Name :Subiksha A R A
Reg No : 3122223002115

Boolean Equation:
Input: Ai , Bi
Carry generate : Gi
Carry propagator: Pi
Sum : Si
Carry: Ci+1

Gi = Ai. Bi
Pi = Ai ⊕ Bi
Si = Pi ⊕ Gi
Ci+1 = Ci.Pi + Gi

by which,

C1 = C0P0 + G0
C2 = C1P1 + G1 = C0P0P1 + G0P1 + G1
C3 = C2P2 + G2 = C0P0P1P2 + G0P1P2 + G1P2 + G2
C4 = C3P3 + G3 = C0P0P1P2P3 + G0P1P2P3 + G1P2P3 + G2P3 + G4

Logic Diagram:
 Name :Subiksha A R A
Reg No : 3122223002115

Schematic Diagram :

Verilog HDL Program :

//dataflow modeling

module CarryLookAheadAdder(
input [3:0]A, B,
input Cin,
output [3:0] S,
output Cout
);
wire [3:0] Ci;
// Carry intermediate for intermediate computation

assign Ci[0] = Cin;

assign Ci[1] = (A[0] & B[0]) | ((A[0]^B[0]) & Ci[0]);
//assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & Ci[1]); expands to
assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])));
//assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & Ci[2]); expands to
 Name :Subiksha A R A
Reg No : 3122223002115

assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) |
((A[0]^B[0]) & Ci[0])))));
//assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & Ci[3]); expands to
assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & ((A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) |
((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])))))));

assign S = A^B^Ci;
endmodule

Stimulus File :
module TB;
reg [3:0]A, B;
reg Cin;
wire [3:0] S;
wire Cout;
wire[4:0] add;

CarryLookAheadAdder cla(A, B, Cin, S, Cout);

assign add = {Cout, S};

initial begin
$monitor("A = %b: B = %b, Cin = %b --> S = %b, Cout = %b, Addition = %0d", A, B, Cin, S, Cout,
add);
A = 1; B = 0; Cin = 0; #3;
A = 2; B = 4; Cin = 1; #3;
A = 4'hb; B = 4'h6; Cin = 0; #3;
A = 5; B = 3; Cin = 1;
end
endmodule
 Name :Subiksha A R A
Reg No : 3122223002115

Simulation Results:

OUTPUT WAVEFORMS:

UTILIZATION REPORT:

Result:

The design and implementation of 4-bit carry look ahead adder using structural/behavioral/dataflow
modeling has been successfully executed and their functionality is verified using FPGA Trainer
 Name :Subiksha A R A
Reg No : 3122223002115

Exp No : 3
Date : 19.08.2024

DESIGN AND IMPLEMENTATION OF 4-BIT BOOTH MULTIPLIER

Aim :
● To design and model a 4-bit booth multiplier using structural/behavioral/dataflow modeling
● To compile, simulate and plot the results using Xilinx Vivado.
● To implement the proposed systems and operate the synthesis report.
● To demonstrate the working of the proposed system using Nexys A7 Artix-7 Trainer Board.

Equipment/Software required :
● Hardware : Nexys A7 Artix-7 FPGA Trainer Board
● Software : Xilinx Vivado

Theory :
The Booth multiplier is an algorithm for multiplying signed binary numbers in 2's complement form. It
optimizes multiplication by reducing the number of addition operations through efficient handling of
sequences of 0s and 1s in the multiplier. The algorithm uses a combination of addition, subtraction, and
arithmetic shifts to compute the product, making it particularly useful for multiplying signed numbers
quickly and efficiently in digital systems.

FULL FUNCTIONAL DESCRIPTION:

Flow Chart :
 Name :Subiksha A R A
Reg No : 3122223002115

Logic Diagram :

Verilog HDL Program :

module BoothMulti(X, Y, Z);

input signed [3:0] X, Y;
output signed [7:0] Z;
reg signed [7:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [3:0] Y1;
always @ (X, Y)
begin
Z = 8'd0;
E1 = 1'd0;
for (i = 0; i < 4; i = i + 1)
begin
temp = {X[i], E1};
Y1 = - Y;
 Name :Subiksha A R A
Reg No : 3122223002115

case (temp)
2'd2 : Z [7 : 4] = Z [7 : 4] + Y1;
2'd1 : Z [7 : 4] = Z [7 : 4] + Y;
default : begin end
endcase
Z = Z >> 1;
Z[7] = Z[6];
E1 = X[i];
end
end
endmodule

Stimulus file:

module BoothTB;
reg [3:0] X;
reg [3:0] Y;
wire [7:0] Z;

BoothMulti uut (
.X(X),
.Y(Y),
.Z(Z)
);

initial begin
X = 0;
Y = 0;
#100;
X=4;
Y=-6;
end
endmodule
 Name :Subiksha A R A
Reg No : 3122223002115

Simulation Results:
OUTPUT WAVEFORMS

UTILIZATION REPORT

Result :

The design and implementation of 4 bit booth multiplier using structural/behavioral/dataflow modeling
has been successfully executed and their functionality is verified using FPGA Trainer kit.