UNIT–I 2.

Control Unit
Basic Microprocessor architecture: This unit is responsible for looking after all the processing. It organizes and manages the
execution of tasks of the CPU.
Microprocessor Definition: 3. Registers
A microprocessor is basically the brain of the computer. We can also call it simply a processor These are memory areas which the CPU directly uses for processing. So, it’s function is to
or CPU. Furthermore, a microprocessor is basically a computer processor that is mounted on store data from input or store data between calculations. Besides, it also stores the output
a single IC (Integrated Circuit). It means that all the functions of the processor are included on results. Moreover, accessing registers is much faster than accessing the RAM.
a single chip. In 1971, Intel introduced the first commercial microprocessor which was Intel 4. Decoder
4004.
It decodes the instructions from high-level language to machine language and passes them to
Furthermore, the basic task of a microprocessor is to input the instructions from the memory, the CPU.
decode, and process them and produce the output. It performs three basic tasks while 5. Instruction Register (IR)
processing the information. They are as follows:
It stores the instruction which will execute currently.
1. Performing some basic calculations using ALU for example, addition, division, Bus
multiplication, subtraction, etc.
2. Moving data from one location to another. The functional components usually use a bus architecture for communication. A bus is a
3. It has a Program Counter (PC), which is a pointer that stores the address of the next collection of wires used for the communication of different parts of a computer. Further, it
instruction. It keeps track of the PC and performs instructions accordingly. uses electric signals to pass the data and information.
Parts of a Microprocessor
The basic parts of a microprocessor are as follows:
 CPU Bus Architecture
 Bus Different Types of Buses used are:
 Memory 1. Address Bus
CPU (Central Processing Unit) The address bus is used to communicate the address of the given data and instructions.
This is a really important part of a computer as it performs all the processing parts of the 2.Data Bus
computer. It processes the data and instructions which the user gives. Moreover, it carries out The data bus is used to communicate the data from one part to another.
the calculations and other such tasks. Other names of CPU are Central Processor or Main
Processor. It has the following parts:
1. Arithmetic and Logical Unit 3. Control Bus
As the name suggests, this unit is responsible for performing arithmetic tasks like addition, The control bus is used to control the signals between different devices. Therefore, in
subtraction, multiplication, division moreover, it also makes logical decisions like greater than conclusion, we can say that these functional components communicate through this bus
less than, etc. And hence the name, the ‘brain’ of the computer. architecture. The input device takes the input, then the data is processed and the output
devices display the results. Besides, the system bus performs all the communication that the Most microcontrollers have power-
cycle involves. saving modes like idle mode and
Most microprocessors do not have
power-saving mode. This helps to
Memory power-saving features.
reduce power consumption even
The parts of memory are: further.
Since memory and I/O components are
Primary Memory Since components are internal, most
all external, each instruction will
of the operations are internal
This is the internal memory that stores the data and instructions of the CPU. It is volatile in need an external operation, hence it
instruction, hence speed is fast.
is relatively slower.
nature (data is lost when the power is disconnected).
Microcontrollers have more registers, Microprocessors have less number of
The primary memory has two types: hence the programs are easier to registers, hence more operations
1. RAM (Random Access Memory) write. are memory based
Microcontrollers are based on Microprocessors are based on the von
As per the name, data can be accessed randomly and quickly. Harvard architecture where Neumann model/architecture
1. ROM (Read Only Memory) program memory and Data where programs and data are stored
memory are separate in the same memory module
As per the name, we can only read data and cannot write (store) to it. Used mainly in washing machines,
Mainly used in personal computers
Secondary Memory MP3 players
As we know that the primary memory is volatile therefore, we need some devices to store the
data permanently so we use some external storage devices for this purpose which we name as 8086 microprocessor: 8086 Microprocessor is an enhanced version of
the secondary memory. Some examples: CD, DVD, etc. 8085Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor
having 20 address lines and16 data lines that provides up to 1MB storage. It consists of
Microprocessor Unit versus Microcontroller Unit: powerful instruction set, which provides operations like multiplication and division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum
Microcontroller Microprocessor
mode is suitable for system having multiple processors and Minimum mode is suitable for
system having a single processor.
Features of 8086
The most prominent features of a 8086 microprocessor are as follows −
 It has an instruction queue, which is capable of storing six instruction bytes from the
memory resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus,
The microcontroller is the heart of an The microprocessor is the heart of a and 16-bit external data bus resulting in faster processing.
embedded system. Computer system.  It is available in 3 versions based on the frequency of operation −
The microcontroller has an external It is just a processor. Memory and I/O o 8086 → 5MHz
processor along with internal components have to be connected o 8086-2 → 8MHz
memory and i/O components externally o (c)8086-1 → 10 MHz
Since memory and I/0 are present
Since memory and I/O have to be  It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
connected externally, the circuit performance.
internally, the circuit is small.
becomes large.  Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
Can be used in compact systems and Cannot be used in compact systems  Execute stage executes these instructions.
hence it is an efficient technique and hence inefficient  It has 256 vectored interrupts.
The cost of the entire system is low Cost of the entire system increases  It consists of 29,000 transistors.
Since external components are low, Due to external components, the entire
total power consumption is less power consumption is high. Hence it 8086 Microprocessor family:
and can be used with devices is not suitable to use with devices Transistor was invented in 1948 (23 December 1947 in Bell lab). IC was invented in 1958
running on stored power like running on stored power like (Fair Child Semiconductors) By Texas Instruments J Kilby. The first microprocessor was
batteries. batteries.
invented by INTEL(INTegrated ELectronics).
Size of the microprocessor – 4 bit Clock Number of
Name Year of Invention Clock speedNumber of transistorsInst. per sec Name Year of Invention speed transistors Inst. per sec
INTEL 4004/4040 1971 by Ted Hoff and Stanley Mazor 740 kHz 2300 60,000 bit address bus 32 bit) MHz
16 MHz
Size of the microprocessor – 8 bit
INTEL 1986 (other versions 80486DX, – 100 1.2 Million
80486 80486SX, 80486DX2, 80486DX4) MHz transistors 8 KB of cache memory
Name Year of Invention Clock speedNumber of transistors Inst. per sec
Cache memory 8 bit for
8008 1972 500 kHz 3500 50,000 instructions 8 bit for
PENTIUM 1993 66 MHz data
8080 1974 2 MHz 6000 10 times faster than 8008
Size of the microprocessor – 64 bit
8085 1976 (16-bit address bus) 3 MHz 6500 769230
Number of
Name Year of Invention Clock speed transistors Inst. per sec
INTEL 2006 (other versions core2 duo, 291 Million 64 KB of L1 cache per
core 2 core2 quad, core2 extreme) 1.2 GHz to 3 GHz transistors core 4 MB of L2 cache
2.2GHz – 3.3GHz, 2.4GHz –
Size of the microprocessor – 16 bit i3, i5, i7 2007, 2009, 2010 3.6GHz, 2.93GHz – 3.33GHz
Number of Inst. per
Name Year of Invention Clock speed transistors sec
Internal architecture of 8086:
4.77 MHz,
1978 (multiply and divide instruction, 16-bit 8 MHz, 10 2.5
8086 data bus and 20-bit address bus) MHz 29000 Million
1979 (cheaper version of 8086 and 8-bit 2.5
8088 external bus) Million
1982 (80188 cheaper version of 80186, and
additional components like interrupt
controller, clock generator, local bus
80186/80188 controller, counters) 6 MHz
4
80286 1982 (data bus 16bit and address bus 24 bit) 8 MHz 134000 Million
Size of the microprocessor – 32 bit
Clock Number of
Name Year of Invention speed transistors Inst. per sec
INTEL 1986 (other versions 80386DX, 16 MHz
80386 80386SX, 80386SL , and data bus 32- – 33 275000
 purpose registers of 16-bit length each. Each of them is further divided into two subparts of
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit 8-bit length each: one high, which stores the higher-order bits and another low which
(BIU), and The Execution Unit (EU). These are explained as following below. stores the lower order bits
1. The Bus Interface Unit (BIU): AX = [AH:AL]
BX = [BH:BL]
It provides the interface of 8086 to external memory and I/O devices via the System Bus. CX = [CH:CL]
It performs various machine cycles such as memory read, I/O read, etc. to transfer data DX = [DH:DL]
between memory and I/O devices.
Segment Registers: There are 4 segment registers in 8086 Microprocessor and each of
BIU performs the following functions are as follows: them is of 16 bit. The code and instructions are stored inside these different segments.
 It generates the 20-bit physical address for memory access. Code Segment (CS) Register: The user cannot modify the content of these registers. Only the
 It fetches instructions from the memory. microprocessor's compiler can do this.
 It transfers data to and from the memory and I/O. Data Segment (DS) Register: The user can modify the content of the data segment.
 Maintains the 6-byte pre-fetch instruction queue(supports pipelining). Stack Segment (SS) Registers: The SS is used to store the information about the memory
segment. The operations of the SS are mainly Push and Pop.
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch Extra Segment (ES) Register: By default, the control of the compiler remains in the DS where
queue, and an Address Generation Circuit. the user can add and modify the instructions. If there is less space in that segment, then ES is
used. ES is also used for copying purpose.
 It is a 6-byte queue (FIFO). Pointers and Index Registers:
 Fetching the next instruction (by BIU from CS) while executing the current instruction
is called pipelining. The pointers will always store some address or memory location. In 8086 Microprocessor,
they usually store the offset through which the actual address is calculated.
The Execution Unit (EU): Instruction Pointer (IP):
The main components of the EU are General purpose registers, the ALU, Special purpose The instruction pointer usually stores the address of the next instruction that is to be
registers, the Instruction Register and Instruction Decoder, and the Flag/Status Register.
executed. Apart from this, it also acts as an offset for CS register.
1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic
Base Pointer (BP):
operations using the ALU.
2. Sends control signals for internal data transfer operations within the The Base pointer stores the base address of the memory. Also, it acts as an offset for Stack
microprocessor.(Control Unit) Segment (SS).
3. Sends request signals to the BIU to access the external module. Stack Pointer (SP):
4. It operates with respect to T-states (clock cycles) and not machine cycles. The Stack Pointer Points at the current top value of the Stack. Like the BP, it also acts as an
8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store
offset to the Stack Segment (SS).
intermediate values during execution. Each of these has two 8-bit parts (higher and
lower). The indexes are used with the extra segment and they usually are used for copying the
contents of a particular block of memory to a new location.
Source Index (SI):
It stores the offset address of the source.
Register organization of 8086: In the 8086 Microprocessor, the registers are categorized
into mainly four types: Destination Index (DI):
 General Purpose Registers It stores the offset address of the Destination.
 Segment Registers
 Pointers and Index Registers
 Flag or Status Register Flag or Status Register: Intel 8086 has 16 flag registers among which 9 are active. The
purposes of the FLAG registers are to indicate the various statuses of the processor. It is
General Purpose Registers: The use of general-purpose registers is to store temporary done by setting the individual bits called flags.
data. While the instructions are executed in the control unit, they may work on some
numeric value or some operands. These need to be stored somewhere so that the processor There are two kinds of FLAGS; Status FLAG and Control FLAG.
can operate on them easily. So, these registers are used in these cases. There are 4 general-
Status FLAG reflect the result of an operation executed by the processor. The control FLAG SF: If the result after performing any arithmetic or logic operation in the given instruction
enables or disables certain operations of the processor. is negative, then the sign flag is set to 1. Else, for a positive result, the sign flag remains
reset.
There are 6 status flag registers and 4 control flag registers. Following are the 9 active flag Control flags:
registers of 8086 with their purposes. There are three types of control flags, and by default all are zero.
TF: This stands for trap flag. Generally processors give output after the complete program,
but when TF = 1, output is given after every instruction.
This is useful to check logical errors, when the program is too long.
IF: This is interrupt flag. IF = 1, then enable interrupts IF = 0, then interrupts are disabled.
By default interrupts are disabled.
DF: This stands for direction flag. In the case string operation, by default address keeps
incrementing for instruction execution. It means after execution of an instruction, whether
the processor should execute next instruction or previous instruction.
If DF = 1 ; address is auto decrementing ( processor executes previous instruction ). DF =0 ;
address is auto incrementing ( processor executes next instruction ).
Status flags:
CF: It stands for carry flag. If CF = 1 ; it means carry is generated from the MSB. If CF = 0 ;
no carry is generated out of MSB.
Pin diagram of 8086 microprocessor: The Intel 8086 is 40 pin DIP Microprocessor. Here
we will see the actual pin level diagram of 8086 MPU.
8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package)
chip. Let us now discuss in detail the pin configuration of a 8086 Microprocessor.
PF:It stands for parity flag. If PF = 1 ; it means it is even parity in the result ( there are even
numbers of 1’s )
AF: AF stands for auxiliary flag. As 8-bits form a byte, similarly 4 bits form a nibble. So in 16
bit operations there are 4 nibbles.
If AF = 1 ; there is a carry out from lower nibble.
If AF = 0 ;no carry out of lower nibble.
ZF: This is zero flag. Whenever the output is 0 this flag is 1. If ZF = 1 ; output is zero.
If ZF = 0 ; output is non zero.
OF: This flag will be set (1) if the result of a signed operation is too large to fit in the
number of bits available to represent it, otherwise reset (0). This is the actual pin diagram of 8086 Microprocessor.
Now let us see the Pin functions of the 8086 microprocessor.
 Pins Function
Pins Function DT/R It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is
AD15 – AD0 These are 16 address/data bus. AD0-AD7 carries low order byte data and
transmitted out and vice-a-versa.
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-
bit address and after that it carries 16-bit data. M/IO This signal is used to distinguish between memory and I/O operations. When it is
high, it indicates I/O operation and when it is low indicating the memory
A16 – A19 These are the 4 address/status buses. During the first clock cycle, it carries 4-bit operation. It is available at pin 28.
address and later it carries status signals.
WR It stands for write signal and is available at pin 29. It is used to write the data into
Vcc It uses 5V DC supply at VCC pin 40 the memory or the output device depending on the status of M/IO signal.
GND These are ground at VSS pin 1 and 20.
HLDA It stands for Hold Acknowledgement signal and is available at pin 30. This signal
Clock Clock signal is provided through Pin-19. It provides timing to the processor for acknowledges the HOLD signal.
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and HOLD This signal indicates to the processor that external devices are requesting to
10MHz. access the address/data buses. It is available at pin 31.
S7/BHE BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the QS1 and QS0 These are queue status signals and are available at pin 24 and 25. These signals
transfer of data using data bus D8-D15. This signal is low during the first clock
provide the status of instruction queue.
cycle, thereafter it is active.
Read(RD) It is available at pin 32 and is used to read signal for Read operation.
S0, S1, S2 These are the status signals that provide the status of operation, which is used by
Ready It is available at pin 22. It is an acknowledgement signal from I/O devices that the Bus Controller 8288 to generate memory & I/O control signals. These are
data is transferred. It is an active high signal. When it is high, it indicates that the available at pin 26, 27, and 28.
device is ready to transfer data. When it is low, it indicates wait state.
LOCK When this signal is active, it indicates to the other processors not to ask the CPU
RESET It is available at pin 21 and is used to restart the execution. It causes the processor to leave the system bus. It is activated using the LOCK prefix on any instruction
to immediately terminate its present activity. This signal is active high for the first and is available at pin 29.
4 clock cycles to RESET the microprocessor.
RQ/GT1 and These are the Request/Grant signals used by the other processors requesting the
INTR It is available at pin 18. It is an interrupt request signal, which is sampled during RQ/GT0 CPU to release the system bus. When the signal is received by CPU, then it sends
the last clock cycle of each instruction to determine if the processor considered acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
this as an interrupt or not.
NMI It stands for non-maskable interrupt and is available at pin 17. It is an edge
triggered input, which causes an interrupt request to the microprocessor.
There are some conditions for QS0 and QS1. These conditions are as follows.
TEST This signal is like wait state and is available at pin 23. When this signal is high,
then the processor has to wait for IDLE state, else the execution continues.
QS0 QS1 Status
MN/MX It stands for Minimum/Maximum and is available at pin 33. It indicates what
0 0 No operation
mode the processor is to operate in; when it is high, it works in the minimum
mode and vice-versa. 0 1 First byte of opcode from the queue
INTA It is an interrupt acknowledgement signal and id available at pin 24. When the 1 0 Empty the queue
microprocessor receives this signal, it acknowledges the interrupt.
1 1 Subsequent byte from the queue
ALE It stands for address enable latch and is available at pin 25. A positive pulse is
generated each time the processor begins any operation. This signal indicates the
availability of a valid address on the address/data lines. The S2, S1 and S0 are the status signals. Here is a list of status and their bit patterns.
DEN It stands for Data Enable and is available at pin 26. It is used to enable S2 S1 S0 Status
Transreceiver 8286. The transreceiver is a device used to separate data from the
address/data bus. 0 0 0 Interrupt acknowledgement
 S2 S1 S0 Status
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
The remaining components in the system are latches, Tran receivers, clock generator,
memory and I/O devices. Some type of chip selection logic may be required for selecting
System Bus timings: Minimum mode 8086: memory or I/O devices, depending upon the address map of the system.
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are
by strapping its MN//MX pin to logic 1. used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
In this mode, all the control signals are given out by the microprocessor chip itself. There is
a single microprocessor in the minimum mode system. Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals. They are controlled by two signals namely, DEN and DT/R.
The DEN signal indicates the direction of data, i.e. from or to the processor. The system
contains memory for the monitor and users program storage.
Timing diagram :
The working of min mode can be easily understood by timing diagrams.
 All processors bus cycle is of at least 4 T-states(T1,T 2,T 3,T 4) .The address is given by
processor in the T1 state. It is available on the bus for one T-state.
 In T 2, the bus is tristated for changing the direction of the bus( in the case of a data
read cycle.)
 The data transfer takes place between T 3 and T4.
 If the addressed device is slower, then the wait state is inserted between T 3 and T 4.
  The data is buffered on the bus until the middle of T 4 state.
 The WR’=0 becomes at the beginning of T 2.
 The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O word.
 During T 2 DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which indicates that the
data is transferred by the processor to the addressed device.
All kinds of memory and i/o operations are performed using the decoding of M/IO’and
RD’ WR’ as shown in the table above.
System Bus timings: Maximum mode 8086:
 In this we can connect more processors to 8086 (8087/8089).
 8086 max mode is basically for implementation of allocation of global resources and
passing bus control to other coprocessor(i.e. second processor in the system), because
two processors can not access system bus at same instant.
 All processors execute their own program.
 The resources which are common to all processors are known as global resources.
 The resources which are allocated to a particular processor are known as local or
private resources.
Opcode fetch or read timing diagram
 At T 1 state ALE =1 ,this indicates that a valid address is latched on the address bus and
also M / IO’= 1, which indicates the memory operation is in progress.
 In T2, the address is removed from the local bus and is sent to the addressed device.
Then the bus is tristated.
 When RD’ = 0 , the valid data is present on the data bus.
 During T 2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates that the
data is received.
 During T 3, data is put on the data bus and the processor reads it.
 The output device makes the READY line high. This means the output device has
performed the data transfer process. When the processor makes the read signal to 1,
then the output device will again tristate its bus drivers.
 When MN/ MX’ = 0 , 8086 works in max mode.
 Clock is provided by 8284 clock generator.
 8288 bus controller- Address form the address bus is latched into 8282 8-bit latch.
Three such latches are required because address bus is 20 bit. The ALE(Address latch
enable) is connected to STB(Strobe) of the latch. The ALE for latch is given by 8288
bus controller.
 The data bus is operated through 8286 8-bit transceiver. Two such transceivers are
 At T 1 state ALE =1 ,this indicates that a valid address is latched on the address bus and required, because data bus is 16-bit. The transceivers are enabled the DEN signal,
also M / IO’= 1, which indicates the memory operation is in progress. while the direction of data is controlled by the DT/R signal. DEN is connected
 In T 2, the processor sends the data to be written to the addressed location.
 to OE’ and DT/ R’ is connected to T. Both DEN and DT/ R’ are given by 8288 bus
controller.
 Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ 0/GT0 has more Interrupts and Interrupt response in 8086:
priority than RQ1/GT1.
 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086. Interrupt
 In max mode, the advanced write signals get enabled one T-state in advance as interrupts in 8086 is a special condition that arises while the microprocessor is executing
compared to normal write signals. This gives slower devices more time to get ready to the main program. Then the microprocessor stops where it is executing in the program and
accept the data, therefore it reduces the number of cycles. goes to the Interrupt service routine ( ISR is the another code ) , the microprocessor
executes the ISR and completes it and then continues the main program. This is similar to
call branching. The called function is known as Subroutine in the case of call branching,
Here it is Interrupt service routine( ISR ). In the call branching, to return to the main
program RET command is given at the end of the subroutine, here IRET is the command to
return to the main program.
Eg: Playing a game in mobile phone ( Processor is running main program i.e. game )
A call comes, then the processor pop ups the call ( here call is an interrupt ), then
processor goes to ISR ( here ISR is call )
While the CPU is executing a program, an interrupt breaks the normal execution of Types of Interrupts:
instructions, diverts its execution to some other program called Interrupt Service Routine In general there are two types of Interrupts:
(ISR) Whenever an interrupt occurs the processor completes the execution of the current Internal (or) Software Interrupts are generated by a software instruction and operate
instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt similarly to a jump or branch instruction.
Handler. ISR is a program that tells the processor what to do when the interrupt occurs. At External (or) Hardware Interrupts are caused by an external hardware module.
the end of the ISR the last instruction should be IRET. After the execution of ISR, control
returns back to the main routine where it was interrupted.
Whenever a number of devices interrupt a CPU at a time, and if the processor is able to
handle them properly, it is said to have multiple interrupt processing capability. HARDWARE INTERRUPTS:
There are two interrupt pins in 8086. NMI and INTR Hardware interrupts are generated by hardware devices when something unusual
Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices that happens; this could be a key-press or a mouse move or any other action.
provide or require data at relatively low data transfer rate. It can be divided into two
NMI: 1.Maskable 2. Non maskable
It is a single non-maskable interrupt pin (NMI) having higher prority. When this interrupt Maskable Interrupts: There are some interrupts which can be masked (disabled)or enabled
is activated, these actions take place by the processor.
 Completes the current instruction that is in progress. Non-Maskable Interrupts: There are some interrupts which cannot be masked out or
 Pushes the Flag register values on to the stack. ignored by the processor. These are associated with high priority tasks which cannot be
ignored (like memory parity or bus faults).
 Pushes the CS (code segment) value and IP (instruction pointer) value of the return
SOFTWARE INTERRUPTS : Interrupts are generated by a software instruction and operate
address on to the stack.
similarly to a jump or branch instruction.
 IP is loaded from the contents of the word location 00008H.(Type 2*4=00008 H)
256 interrupts are there
 CS is loaded from the contents of the next word location 0000AH.
 INT n is invoked as software interrupts- n is the type no in the range 0 to 255(00 to FF)
 Interrupt flag and trap flag are reset to 0.
Interrupts are divided into three groups
INTR:
Type 0 to Type4 (Dedicated Interrupts) - TYPE 0 interrupt represents division by zero
The INTR is a maskable interrupt pin. It can be accepted (enable) or rejected (masked).
situation.
The microprocessor enabled the interrupt using set interrupt flag instruction. It should
- TYPE 1 interrupt represents single-step execution during the debugging of a program.
disable using clear interrupt Flag instruction.
- TYPE 2 interrupt represents non-maskable NMI interrupt.
These actions are taken by the microprocessor −
- TYPE 3 interrupt represents break-point interrupt.
 First completes the current instruction.
- TYPE 4 interrupt represents overflow interrupt.
 Activates INTA output and receives the interrupt type, say X.
-Type 5 to 31(Not used by 8086, reserved for higher processor like 80286,80386….
 Flag register value, CS value of the return address and IP value of the return address are -Type 32-255(Available for user)
pushed on to the stack.
-User defined interrupts
 IP value is loaded from the contents of word location X × 4 Interrupt Service Routine:
 CS is loaded from the contents of the next word location. For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler.
 Interrupt flag and trap flag is reset to 0 When an interrupt is invoked, the microprocessor runs the interrupt service routine. For
every interrupt, there is a fixed location in memory that holds the address of its ISR. The
group of memory locations set aside to hold the addresses of ISRs is called the interrupt
vector table.
When an interrupt is occurred, the microprocessor stops execution of current instruction.
UNIT–II: 8086 Programming: Program development steps, instructions, addressing modes, assembler
It transfers the content of program counter (CS and IP) into stack. directives, writing simple programs with an assembler, assembly language program development tools.
After this, it jumps to the memory location specified by Interrupt Vector Table (IVT). After
that the code written on that memory area will execute.
UNIT – II: 8086 PROGRAMMING
Program Development Steps:
Major steps in developing an assembly language program
• Defining the Problem
• Representing program operations
• Finding the right instructions
• Writing a program
Defining the problems
• Find out the problem.
For example: Sensing temperature, detecting fire, detecting smock, decoder-
encoder,Intelligent machine controller etc.
Representing program operations
The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing the • Formula or sequence of operations used to solve a programming problem is called as the
starting addresses of Interrupt Service Procedures(ISP).Since 4-bytes are required for algorithm.
storing starting addresses of ISPs, the table can hold 256 Interrupt procedures. The starting
• There are two ways of representing algorithms:
address of an ISP is often called the Interrupt Vector or Interrupt Pointer .Therefore the
table is referred as Interrupt Vector Table. - Flowchart
- Structured programming and pseudo code
Finding the right instructions
• Instructions in 8086 are mainly divided into following categories
• Data Transfer Instructions
• Arithmetic Instruction
• Bit manipulation Instruction
• String Instruction
• Program execution transfer Instruction
• Processor control Instruction
Writing a program
• We need to do the following steps to write the program effectively:
- INITIALIZATION INSTRUCTIONS: used to initialize various parts of the program
likesegment registers, flags and programmable port devices.
- STANDARD PROGRAM FORMAT: it’s a tabular format containing ADDRESS, DATAOR
CODE, LABELS, MNEM, OPERAND(S) and COMMENTS as the columns.
 - DOCUMENTATION: you should document the program. E.g. each page of the document f) Flag Manipulation Instructions:
contains page number and name of the program, heading block containing the abstract All instructions which directly affect the flag register belong to this category. The instructions
aboutthe program, comments should be added wherever necessary. CLD, STD, CLI, STI etc. belong to this category.
g) Shift and Rotate Instructions:
Instruction Set of 8086: These instructions involve the bitwise shifting or rotation in either direction with or without a
The 8086 instructions are categorized into the following main types. count in CX.
h) String Instructions:
a. Data Copy / Transfer Instructions
b. Arithmetic and Logical Instructions These instructions involve string manipulation operations like load, scan, compare, store etc. These
instructions are only to be operated upon the string.
c. Branch Instructions
d. Loop Instructions a) Data Copy / Transfer Instructions: -
e. Machine Control Instructions MOV:
f. Flag Manipulation Instructions This instruction copies a word or a byte of data from some source to a destination.
g. Shift and Rotate Instructions The destination can be a register or a memory location. The source can be a register, a memory location,
h. String Instructions or an immediate number.
MOV AX, BX
a) Data Transfer Instruction: MOV AX, 5000H
These types of instructions are used to transfer data from source operand to destination operand. MOV AX, [SI]
All the store, load, move, exchange, input and output operations belong to this category. MOV AX, [2000H]
b) Arithmetic and Logical Instructions: MOV AX, 50H [BX]
MOV [734AH], BX
All the instructions performing arithmetic, logical, increment, decrement, compare and scan
MOV DS, CX
instructions belong to this category.
MOV CL, [357AH]
c) Branch Instructions:
Direct loading of the segment registers with immediate data is not permitted.
These instructions transfer control of execution to the specified address. All the call, jump,
PUSH: Push to Stack
interrupt and return instructions belong to this category.
This instruction pushes the contents of the specified register/memory location on to the stack. The stack
d) Loop Instructions:
pointer is decremented by 2, after each execution of the instruction.
The LOOP, LOOPNZ and LOOPZ instructions belong to this category. These are useful to
implement different loop structures. Ex: - PUSH AX
e) Machine control Instructions: PUSH DS
These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions belongs to PUSH [5000H]
this category.
 XLAT: Translate byte using look-up table
Ex: - MOV BX, OFFSET TABLE
MOV AL, 00H
XLAT
3
5
(AL) ← 5 (BX)
AL [BX+AL]
Base of table
Simple input and output port transfer Instructions:
IN:
Copy a byte or word from specified port to accumulator.
Ex: - IN AL,03H
Fig: Push data to Stack memory
IN AX, DX
POP: Pop from Sack OUT:
This instruction when executed, loads the specified register/memory location with the contents of the Copy a byte or word from accumulator specified port.
memory location of which the address is formed using the current stack segment and stack pointer. Ex: - OUT 03H, AL
The stack pointer is incremented by 2 OUT DX, AX
Ex: - POP AX LEA:
POP DS Load effective address of operand in specified register.
POP [5000H] [reg] offset portion of address in DS
Ex: - LEA reg, offset
LDS:
Load DS register and other specified register from memory.
[reg] [mem]
[DS] [mem + 2]
Ex: - LDS reg, mem
LES:
Load ES register and other specified register from memory.
Fig: Poping Register content from stack memory [reg] [mem]
[ES] [mem + 2]
XCHG: Exchange byte or word
Ex: - LES reg, mem
This instruction exchanges the contents of the specified source and destination operands
Ex: - XCHG [5000H], AX
XCHG BX, AX
Flag transfer instructions: ADC: Add with Carry
This instruction performs the same operation as ADD instruction, but adds the carry flag to the result.
LAHF:
Ex: - ADC 0100H
Load (copy to) AH with the low byte the flag register.
ADC AX, BX
[AH] [Flags low byte]
ADC AX, [SI]
Ex: - LAHF
ADC AX, [5000]
SAHF: ADC [5000], 0100H
Store (copy) AH register to low byte of flag register.
SUB: Subtract
[Flags low byte] ← [AH]
The subtract instruction subtracts the source operand from the destination operand and the result is left in
Ex: - SAHF
the destination operand.
PUSHF:
Ex: - SUB AX, 0100H
Copy flag register to top of stack.
SUB AX, BX
[SP] ← [SP] – 2
SUB AX, [5000H]
[[SP]] ← [Flags]
SUB [5000H], 0100H
Ex: - PUSHF
SBB: Subtract with Borrow
POPF:
The subtract with borrow instruction subtracts the source operand and the borrow flag (CF) which may
Copy word at top of stack to flag register.
reflect the result of the previous calculations, from the destination operand
[Flags] ← [[SP]]
Ex: - SBB AX, 0100H
[SP] ← [SP] + 2
SBB AX, BX
Ex: - POPF SBB AX, [5000H]
SBB [5000H], 0100H
b) Arithmetic Instructions:
INC: Increment
The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication and
This instruction increases the contents of the specified Register or memory location by 1. Immediate data
comparing two values.
cannot be operand of this instruction.
ADD:
Ex: - INC AX
The add instruction adds the contents of the source operand to the destination operand.
INC [BX]
Ex: - ADD AX, 0100H
INC [5000H]
ADD AX, BX
ADD AX, [SI] DEC: Decrement
ADD AX, [5000H] The decrement instruction subtracts 1 from the contents of the specified register or memory location.
ADD [5000H], 0100H Ex: - DEC AX
ADD 0100H DEC [5000H]
NEG: Negate Ex: - CWD
The negate instruction forms 2’s complement of the specified destination in the instruction. The Convert signed word in AX to signed double word in DX: AX
destination can be a register or a memory location. This instruction can be implemented by inverting each DX= 1111 1111 1111 1111
bit and adding 1 to it. Result in AX = 1111 0000 1100 0001
Ex: - NEG AL DIV: Unsigned division
AL = 0011 0101 35H Replace number in AL with its 2’s complement This instruction is used to divide an unsigned word by a byte or to divide an unsigned double word by a
AL = 1100 1011 = CBH word.
CMP: Compare Ex: - DIV CL ; Word in AX / byte in CL
This instruction compares the source operand, which may be a register or an immediate data or a memory ; Quotient in AL, remainder in AH
location, with a destination operand that may be a register or a memory location DIV CX ; Double word in DX and AX / word in CX, and Quotient in AX, remainder in DX
Ex: - CMP BX, 0100H AAA: ASCII Adjust After Addition
CMP AX, 0100H The AAA instruction is executed after an ADD instruction that adds two ASCII coded operand to give a
CMP [5000H], 0100H byte of result in AL. The AAA instruction converts the resulting contents of AL to a unpacked decimal
CMP BX, [SI] digits.
CMP BX, CX AAA operation:
MUL: Unsigned Multiplication Byte or Word 1) In AL If rightmost nibble is >9 (ie) A to F or Auxiliary Flag=1
This instruction multiplies an unsigned byte or word by the contents of AL. ADD 6 to rightmost nibble
Ex: - MUL BH; (AX) ← (AL) x (BH) 2) Clear left nibble form AL.
MUL CX; (DX) (AX) ← (AX) x (CX) 3) In AH ADD 1
MUL WORD PTR [SI]; (DX) (AX) ← (AX) x ([SI]) 4) Set Carry and Auxiliary Carry
IMUL: Signed Multiplication Ex: - ADD CL, DL ; [CL] = 34H = ASCII for 4
This instruction multiplies a signed byte in source operand by a signed byte in AL or a signed word in ; [DL] = 38H = ASCII for 8
source operand by a signed word in AX. ; Result [CL] = 6CH
Ex: - IMUL BH AAA ; [AL] =02, unpacked BCD for 2
IMUL CX ; [AH] =01, unpacked BCD for 1
IMUL [SI] AAS: ASCII Adjust AL after Subtraction
CBW: Convert Signed Byte to Word This instruction corrects the result in AL register after subtracting two unpacked ASCII operands. The
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be sign extension result is in unpacked decimal format. The procedure is similar to AAA instruction except for the
of AL. subtraction of 06 from AL.
Ex: - CBW AAS operation:
AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX. 1) AAS checks the rightmost nibble in AL If rightmost nibble is >9 (ie) A to F Or
Result in AX = 1111 1111 1001 1000 Auxiliary Flag=1, Then Subtract 6 from rightmost nibble
CWD: Convert Signed Word to Double Word 2) Clear left nibble in AL.
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be sign extension
3) Subtracts 1 from AH
of AL.
 4) Set Carry and Auxiliary Carry DAS: Decimal Adjust after Subtraction
Ex: - MOV AL, 34H This instruction converts the result of the subtraction of two packed BCD numbers to a valid BCD
SUB AL, 38H ; AX=00FC number. The subtraction has to be in AL only.
AAS ; AX= FF06 ten’s complement i.e -4 (Borrow one from AH) Ex: - AL = 75H, BH = 46H
OR AL, 30H ; AL=34 SUB AL, BH ; AL ← 2 FH = (AL) - (BH)
AAM: ASCII Adjust after Multiplication ; AF = 1
This instruction, after execution, converts the product available In AL into unpacked BCD format. DAS ; AL ← 29 (as F>9, F - 6 = 9)
AAM performs the following operations
1) Divides AL value by 10 (0AH)
2) Stores Quotient in AH Logical Instructions:
3) Store Remainder in AL AND: Logical AND
Ex: - MOV AL, 04 ; AL = 04 This instruction bit by bit ANDs the source operand that may be an immediate register or a memory
MOV BL, 09 ; BL = 09 location to the destination operand that may a register or a memory location. The result is stored in the
MUL BL ; AX = AL*BL ; AX=0024H destination operand.
AAM ; AH = 03H, AL=06H Ex: - AND AX, 0008H
AAD: ASCII Adjust before Division AND AX, BX
This instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. OR: Logical OR
This adjustment must be made before dividing the two unpacked BCD digits in AX by an unpacked BCD This instruction bit by bit ORs the source operand that may be an immediate, register or a memory
byte. In the instruction sequence, this instruction appears Before DIV instruction. location to the destination operand that may a register or a memory location. The result is stored in the
Operations done by AAD instruction destination operand.
1) AAD multiplies the AH by 10(0Ah). Ex: - OR AX, 0008H
2) Then adds the product to AL and clears the AH OR AX, BX
Ex: - AX 05 08 NOT: Logical Invert
AAD result in AL 00 3A 58D = 3A H in AL This instruction complements the contents of an operand register or a memory location, bit by bit.
The result of AAD execution will give the hexadecimal number 3A in AL and 00 in AH. Where 3A is the Ex: - NOT AX
hexadecimal equivalent of 58 (decimal). NOT [5000H]
DAA: Decimal Adjust Accumulator XOR: Logical Exclusive OR
This instruction is used to convert the result of the addition of two packed BCD numbers to a valid BCD This instruction bit by bit XORs the source operand that may be an immediate, register or a memory
number. The result has to be only in AL. location to the destination operand that may a register or a memory location. The result is stored in the
Ex: - AL = 53H, CL = 29H destination operand.
ADD AL, CL ; AL ← (AL) + (CL) Ex: - XOR AX, 0098H
; AL ← 53 + 29 XOR AX, BX
; AL ← 7C TEST: Logical Compare Instruction
DAA ; AL ← 7C + 06 (as C > 9) The TEST instruction performs a bit by bit logical AND operation on the two operands. The result of this
; AL 82 AND ing operation is not available for further use, but flags are affected.
Ex: - TEST AX, BX JMP: Unconditional Jump
TEST [0500], 06H This instruction unconditionally transfers the control of execution to the specified address using an 8-bit or
16-bit displacement. No Flags are affected by this instruction.
c) Branch Instructions:
IRET: Return from ISR
Branch Instructions transfers the flow of execution of the program to a new address specified in the
When it is executed, the values of IP, CS and Flags are retrieved from the stack to continue the execution
instruction directly or indirectly. When this type of instruction is executed, the CS and IP registers get
of the main program.
loaded with new values of CS and IP corresponding to the location to be transferred.
The Branch Instructions are classified into two types
d) LOOP Instructions:
i. Unconditional Branch Instructions.
LOOP Unconditionally
ii. Conditional Branch Instructions.
This instruction executes the part of the program from the Label or address specified in the instruction up
Unconditional Branch Instructions:
to the LOOP instruction CX number of times. At each iteration, CX is decremented automatically and
In Unconditional control transfer instructions, the execution control is transferred to the specified
JUMP IF NOT ZERO structure.
location independent of any status or condition. The CS and IP are unconditionally modified to the new
Ex: - MOV CX, 0004H
CS and IP.
MOV BX, 7526H
CALL: Unconditional Call
Label 1: MOV AX, CODE
This instruction is used to call a Subroutine (Procedure) from a main program. Address of procedure may
OR BX, AX
be specified directly or indirectly.
LOOP Label 1
There are two types of procedure depending upon whether it is available in the same segment or in another
Conditional Branch Instructions:
segment.
When this instruction is executed, execution control is transferred to the address specified
i. Near CALL i.e., ±32K displacement.
relatively in the instruction, provided the condition implicit in the opcode is satisfied. Otherwise execution
ii. Far CALL i.e., anywhere outside the segment.
continues sequentially.
On execution this instruction stores the incremented IP & CS onto the stack and loads the CS & IP
JZ/JE Label
registers with segment and offset addresses of the procedure to be called.
Transfer execution control to address ‘Label’, if ZF=1.
RET: Return from the Procedure.
JNZ/JNE Label
At the end of the procedure, the RET instruction must be executed. When it is executed, the previously
Transfer execution control to address ‘Label’, if ZF=0
stored content of IP and CS along with Flags are retrieved into the CS, IP and Flag registers from the stack
JS Label
and execution of the main program continues further.
Transfer execution control to address ‘Label’, if SF=1.
INT N: Interrupt Type N.
JNS Label
In the interrupt structure of 8086, 256 interrupts are defined corresponding to the types from 00H to FFH.
Transfer execution control to address ‘Label’, if SF=0.
When INT N instruction is executed, the type byte N is multiplied by 4 and the contents of IP and CS of
JO Label
the interrupt service routine will be taken from memory block in 0000 segment.
Transfer execution control to address ‘Label’, if OF=1.
INTO: Interrupt on Overflow
JNO Label
This instruction is executed, when the overflow flag OF is set. This is equivalent to a Type 4 Interrupt
Transfer execution control to address ‘Label’, if OF=0.
instruction.
JNP Label
Transfer execution control to address ‘Label’, if PF=0.
JP Label iii. NOP – No operation.
Transfer execution control to address ‘Label’, if PF=1. iv. ESC – Escape to external device like NDP
JB Label v. LOCK – Bus lock instruction prefix.
Transfer execution control to address ‘Label’, if CF=1. f) Shift & Rotate Instructions:
JNB Label SAL/SHL: SAL / SHL destination, count
Transfer execution control to address ‘Label’, if CF=0. SAL and SHL are two mnemonics for the same instruction. This instruction shifts each bit in the specified
JCXZ Label destination to the left and 0 is stored at LSB position. The MSB is shifted into the carry flag. The
Transfer execution control to address ‘Label’, if CX=0 destination can be a byte or a word.
It can be in a register or in a memory location. The number of shifts is indicated by count.
Conditional LOOP
LOOPZ / LOOPE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0.
LOOPNZ / LOOPENE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0. Ex: - SAL CX, 1
SAL AX, CL
e) Flag Manipulation and Processor Control Instructions: SHR: SHR destination, count
These instructions control the functioning of the available hardware inside the processor chip. These This instruction shifts each bit in the specified destination to the right and 0 is stored at MSB position. The
instructions are categorized into two types: LSB is shifted into the carry flag. The destination can be a byte or a word.
1. Flag Manipulation instructions. It can be a register or in a memory location. The number of shifts is indicated by count.
2. Machine Control instructions.
Flag Manipulation instructions:
The Flag manipulation instructions directly modify some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag. Ex: - SHR CX, 1
iii. STC – Set Carry Flag. MOV CL, 05H
iv. CLD – Clear Direction Flag. SHR AX, CL
v. STD – Set Direction Flag. SAR: SAR destination, count
vi. CLI – Clear Interrupt Flag. This instruction shifts each bit in the specified destination some number of bit positions to the right. As a
vii. STI – Set Interrupt Flag. bit is shifted out of the MSB position, a copy of the old MSB is put in the MSB position. The LSB will be
shifted into CF.
Machine Control instructions
The Machine control instructions control the bus usage and execution
i. WAIT – Wait for Test input pin to go low.
ii. HLT – Halt the process.
Ex: - SAR BL, 1 RCR Instruction: RCR destination, count
MOV CL, 04H This instruction rotates all bits in a specified byte or word some number of bit positions to the right along
SAR DX, CL with the carry flag. LSB is placed as a new carry and previous carry is place as new MSB.
ROL Instruction: ROL destination, count
This instruction rotates all bits in a specified byte or word to the left some number of bit positions. MSB is
placed as a new LSB and a new CF.
Ex: - RCR CX, 1
MOV CL, 04H
RCR AL, CL
Ex: - ROL CX, 1
MOV CL, 03H g) String Manipulation Instructions:
ROL BL, CL A series of data byte or word available in memory at consecutive locations, to be referred as Byte
ROR Instruction: ROR destination, count String or Word String. A String of characters may be located in consecutive memory locations, where
This instruction rotates all bits in a specified byte or word to the right some number of bit positions. LSB each character may be represented by its ASCII equivalent.
is placed as a new MSB and a new CF. The 8086 supports a set of more powerful instructions for string manipulations for referring to a string,
two parameters are required.
I. Starting and End Address of the String.
II. Length of the String.
Ex: - ROR CX, 1 The length of the string is usually stored as count in the CX register. The incrementing or decrementing of
MOV CL, 03H the pointer, in string instructions, depends upon the Direction Flag (DF) Status. If it is a Byte string
ROR BL, CL operation, the index registers are updated by one. On the other hand, if it is a word string operation, the
index registers are updated by two.
RCL Instruction: RCL destination, count
This instruction rotates all bits in a specified byte or word some number of bit positions to the left along
REP: Repeat Instruction Prefix
with the carry flag. MSB is placed as a new carry and previous carry is place as new LSB.
This instruction is used as a prefix to other instructions, the instruction to which the REP prefix is
provided, is executed repeatedly until the CX register becomes zero (at each iteration CX is automatically
decremented by one).
i. REPE / REPZ - repeat operation while equal / zero.
ii. REPNE / REPNZ - repeat operation while not equal / not zero.
These are used for CMPS, SCAS instructions only, as instruction prefixes.
Ex: - RCL CX, 1
MOV CL, 04H
RCL AL, CL
 SCANSB/SW: Scan String Byte or String Word
This instruction scans a string of bytes or words for an operand byte or word specified in the
register AL or AX. The String is pointed to by ES: DI register pair. The length of the string s stored in CX.
The DF controls the mode for scanning of the string. Whenever a match to the specified operand is
found in the string, execution stops and the zero Flag is set. If no match is found, the zero flag is reset.
LODSB/SW: Load String Byte or String Word
The LODS instruction loads the AL / AX register by the content of a string pointed to by DS: SI
register pair. The SI is modified automatically depending upon DF, If it is a byte transfer (LODSB), the SI
is modified by one and if it is a word transfer (LODSW), the SI is modified by two. No other Flags are
affected by this instruction.
STOSB/SW: Store String Byte or String Word
- The STOS instruction Stores the AL / AX register contents to a location in the string pointer by ES: DI
MOVSB / MOVSW: Move String Byte or String Word register pair. The DI is modified accordingly; No Flags are affected by this instruction.
Suppose a string of bytes stored in a set of consecutive memory locations is to be moved to another - The direction Flag controls the String instruction execution, the source index SI and Destination Index
set of destination locations. The starting byte of source string is located in the memory location whose DI are modified after each iteration automatically.
address may be computed using SI (Source Index) and DS (Data Segment) contents. - If DF=1, then the execution follows auto-decrement mode, SI and DI are decremented automatically
The starting address of the destination locations where this string has to be relocated is given by DI after each iteration.
(Destination Index) and ES (Extra Segment) contents. - If DF=0, then the execution follows auto-increment mode. In this mode, SI and DI are incremented
Ex: - Block move program using the move string instruction automatically after each iteration.
MOV AX, DATA SEG ADDR Ex:- Clearing a block of memory with a STOSB operation.
MOV DS, AX MOV AX, 0
MOV ES, AX MOV DS, AX
MOV SI, BLK 1 ADDR MOV ES, AX
MOV DI, BLK 2 ADDR MOV DI, A000
MOV CK, N MOV CX, OF
CLD ; DF=0 CLD
NEXT: MOV SB AGAIN: STOSB
LOOP NEXT LOOPNE AGAIN
HLT NEXT: Clear A000 to A00F to 00H
CMPSB/SW: Compare String Byte or String Word
- The CMPS instruction can be used to compare two strings of byte or words. The length of the string
must be stored in the register CX. If both the byte or word strings are equal, zero Flag is set.
- The REP instruction Prefix is used to repeat the operation till CX (counter) becomes zero or the
condition specified by the REP Prefix is False.
Addressing Modes of 8086: 6. Register Relative: In this addressing mode the data is available at an effective address formed by
The default segment for the addressing modes using BP and SP is SS. For all other addressing adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in
modes, the default segments are DS or ES. the default either DS or ES segment.
Addressing mode indicates a way of locating data or operands. Ex: - MOV AX, 50H BX 
Different addressing modes of 8086: The effective address of the data is 10H  DS  50H BX 
1. Immediate:
7. Based Indexed:
In this addressing mode, immediate data is a part of instruction, and appears in the form of
In this addressing mode the effective address of the data is formed by adding the content of a base
successive byte or bytes.
register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default
Ex: - MOV AX, 0050H
segment register may be ES or DS.
Here 0050H is the immediate data and it is moved to register AX. The immediate data may be 8-bit or 16-
Ex: - MOV AX, BX  SI 
bit in size.
2. Direct: The effective address is 10H  DS BX    SI 
In the direct addressing mode, a 16-bit address (offset) is directly specified in the instruction as a 8. Relative Based Indexed:
part of it. The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of contents
Ex: - MOV AX, [1000H] of any one of the base register (BX or BP) and any one of the index registers in a default segment.
Here data resides in a memory location in the data segment, whose effective address is Ex: - MOV AX, 50H BX SI 
10H  DS 1000H Here 50H is an immediate displacement. The effective address is10H DS BX SI 50H .
3. Register: 9.String mode – This addressing mode is related to string instructions. In this the value of SI and DI are
In register addressing mode, the data is stored in a register and it is referred using the particular auto incremented and decremented depending upon the value of directional flag.
Example :MOVS B
register. All the registers except IP may be used in this mode.
MOVS W
Ex: - MOV AX, BX 10. Input/Output mode – This addressing mode is related with input output operations.
Example: IN A, 45
OUT A, 50
4. Register Indirect:
1. Intrasegment Direct Mode:
In this addressing mode, the address of the memory location which contains data or operand is
In this mode, the address to which the control is to be transferred lies in the segment in which the
determined in an indirect way using offset registers. The offset address of data is in either BX or SI or DI
control transfer instruction lies and appears directly in the instruction as an immediate displacement value.
register. The default segment register is either DS or ES.
The displacement is computed relative to the content of the instruction pointer IP.
Ex: - MOV AX, BX 
2. Intrasegment Indirect Mode:
The data is present in a memory location in DS whose offset is in BX. The effective address is
This mode is similar to intrasegment direct mode except the displacement to which control is to be
10H  DS BX  transferred is passed to the instruction indirectly. Here the branch address is found as the content of a
5. Indexed: register or a memory location.
In this addressing mode offset of the operand is stored in one of the index register. DS and ES are 3. Intersegment Direct Mode:
the default segments for index registers SI and DI respectively In this mode, the address to which the control is to be transferred is in a different segment. This
Ex: - MOV AX, SI  addressing mode provides a means of branching from one code segment to another code segment. Here,
The effective address of the data is 10H  DS SI 
the CS and IP of the destination address are specified directly in the instruction.
 4. Intersegment Indirect Mode: DW: Define Word.
This mode is similar to intersegment direct mode except the address to which the control is to be The DW directive serves the same purposes as the DB directive, but it now makes the assembler
transferred is passed to the instruction indirectly. This information is kept in a memory block of 4 bytes: reserve the number of memory words (16-bit) instead of bytes.
IP (LSB), IP(MSB), LS(LSR) and CS(MSB) sequentially. The starting address of the memory block may Example:
be referred using any of the addressing modes, except immediate mode. WORDS DW 1234H, 4567H, 78ABH, 045CH
This makes the assembler reserve four words in memory (8 bytes), and initialize the words with the
specified values in the statements.
Assembler Directives and Operators:
An assembler is a program used to convert an assembly language program into the equivalent Another option of the DW directive is explained with the DUP operator.
machine code modules which may further be converted to executable codes. The assembler decides the WDATA DW 5 DUP (6666H)
address of each label and substitutes the values for each of the constants and variables. It then forms the This statement reserves five words, i.e. 10-bytes of memory for a word label WDATA and initializes all
machine code for the mnemonics and data in the assembly language program. While doing these things, the word locations with 6666H.
the assembler may find out syntax errors. The logical errors or other programming errors are not found out
by the assembler. For completing all these tasks, an assembler needs some hints from the programmer, i.e. DQ: Define Quad word
the required storage for a particular constant or variable, logical names of the segments, types of the This directive is used to direct the assembler to reserve 4 words (8 bytes) of memory for the
different routines and modules, end of file, etc. These, types of hints are given to the assembler using specified variable and may initialize it with the specified values.
some predefined alphabetical strings called assembler directives. Assembler directives help the assembler
to correctly understand the assembly language programs to prepare the codes. DT: Define Ten Bytes.
Another type of hint which helps the assembler to assign a particular constant with a label or The DT directive directs the assembler to define the specified variable requiring 10-bytes for its
initialize particular memory locations or labels with constants is called an operator. Rather, the operators storage and initialize the 10 bytes with the specified values. The directive may be used in case of variables
perform the arithmetic and logical tasks unlike directives that just direct the assembler to correctly facing heavy numerical calculations, generally processed by numerical processors.
interpret the program to code it appropriately. The following directives are commonly used in the ASSUME: Assume Logical Segment Name
assembly language programming practice using Microsoft Macro Assembler (MASM) or Turbo The ASSUME directive is used to inform the assembler, the names of the logical segments to be assumed
Assembler (TASM). for different segments used in the program.
ASSUME CS: CODE, DS: DATA, SS: STACK
DIRECTIVES:
END: END of Program
DB: Define Byte
The END directive marks the end of an assembly language program.
The DB directive is used to reserve byte or bytes of memory locations in the available memory.
Example: LIST DB 0lH, 02H, 03H, 04H
ENDS: END of Segment
This statement directs the assembler to reserve four memory locations for a list named LIST and initialize
This directive marks the end of a logical segment. The logical segments are assigned with the names using
them with the above specified four values. MESSAGE DB 'GOOD MORNING'
the ASSUME directive.
This makes the assembler reserve the number of bytes of memory equal to the number of characters in the DATA SEGMENT
string named MESSAGE and initialize those locations by the ASCII equivalent of these characters. .
VALUE DB 50H .
This statement directs the assembler to reserve 50H memory bytes and leave them uninitialized for the DATA ENDS
variable named VALUE. ASSUME CS: CODE, DS: DATA
 CODE SEGMENT. PUBLIC directive.
. If one wants to call a procedure FACTORIAL appearing in MODULE 1 from MODULE 2; in
. MODULE1, it must be declared PUBLIC using the statement PUBLIC FACTORIAL and in module 2, it
CODE ENDS must be declared external using the declaration EXTRN FACTORIAL. The statement of declaration
END EXTRN must be accompanied by the SEGMENT and ENDS directives of the MODULE 1, before it is
called in MOBULE 2. Thus, the MODULE 1 and MODULE 2 must have the following declarations.
ENDP: END of Procedure.
In assembly language programming, the subroutines are called procedures. The ENDP directive is
Ex: - MODULEl SEGMENT
used to indicate the end of a procedure.
Ex: - PROCEDURE STAR
PUBLIC FACTORIAL FAR
.
.
MODULEl ENDS
.
MODULE2 SEGMENT
STAR ENDP
EVEN: Align on Even Memory Address
EXTRN FACTORIAL FAR
The EVEN directive updates the location counter to the next even address if the current location
counter contents are not even, and assigns the following routine or variable or constant to that address.
MODULE2 ENDS
Ex: - EVEN
PROCEDURE ROOT
.
.
.
ROOT ENDP
EQU: Equate
The directive EQU is used to assign a label with a value or a symbol. The use of this directive is
just to reduce the recurrence of the numerical values or constants in a program code.
Ex: -
LABEL EQU 0500H
ADDITION EQU ADD
EXTRN: External and PUBLIC: Public
The directive EXTRN informs the assembler that the names, procedures and labels declared after
this directive have already been defined in some other assembly language modules. While in the other
module, where the names, procedures and labels actually appear, they must be declared public, using the
GROUP: Group the Related segment OPERATORS:
The directive is used to form logical groups of segments with similar purpose or type. This OFFSET: Offset of a Label
directive is used to inform the assembler to form a logical group of the following segment names. When the assembler comes across the OFFSET operator along with a label, it first computes the
Ex: - PROGRAM GROUP CODE, DATA, STACK 16-bit displacement (also called as offset interchangeably) of the particular label, and replaces the string
'OFFSET LABEL' by the computed displacement. This operator is used with arrays, strings, lables and
ASSUME CS: PROGRAM, DS: PROGRAM, SS: PROGRAM.
procedures to decide their offsets in their default segments.
LABEL: Label
Ex: - DATA SEGMENT
The Label directive is used to assign a name to the current content of the location counter.
LIST DB 10H
A LABEL directive may be used to make a FAR jump as shown below.
DATA ENDS
A FAR jump cannot be made at a normal label with a colon.
CODE SEGMENT
MOV SI, OFFSET LIST
LENGTH: Byte Length of a Label
CODE ENDS
This directive is not available in TASM. This is used to refer to the length of a data array or a string.
PTR: Pointer
Ex: - MOV CX, LENGTH ARRAY
The pointer operator is used to declare the type of a label, variable or memory operand. The
This statement, when assembled, will substitute the length of the array ARRAY in bytes, in the
operator PTR is prefixed by either BYTE or WORD.
instruction.
 If the prefix is BYTE, then the particular label, variable or memory operand is treated as an 8-bit
quantity, while if WORD is the prefix, then it is treated as a 16- bit quantity.
ORG: Origin
Ex: - MOV AL, BYTE PTR [SI] ; Moves content of memory location addressed by SI (8-bit) to AL
The ORG directive directs the assembler to start the memory allotment for the particular segment,
INC BYTE PTR [BX] ; Increments byte contents of memory location addressed by BX
block or code from the declared address in the ORG statement while starting the assembly process for a
MOV BX, WORD PTR [2000H] ; Moves 16-bit content of memory location 2000H to BX, i.e.
module, the assembler initializes a location counter to keep track of the allotted addresses for the module.
[2000H] to BL [2001 H] to BH
If the ORG statement is not written in the program, the location counter is initialized to 0000.
INC WORD PTR [3000H] ; Increments word contents of memory location 3000H
considering contents of 3000H (lower byte) and 3001 H
PROC: Procedure
(higher byte) as a 16-bit number
The PROC directive marks the start of a named procedure in the statement. Also, the types NEAR
SEG: Segment of a Label
or FAR specify the type of the procedure, i.e whether it is to be called by the main program located within
The SEG operator is used to decide the segment address of the label, variable, or procedure and
64K of physical memory or not.
substitutes the segment base address in place of ‘SEG label’.
Ex: - RESULT PROC NEAR
Ex: - MOV AX, SEG ARRAY ; This statement moves the segment address
ROUTINE PROC FAR MOV DS, AX ; of ARRAY in which it is appearing, to register AX and then to DS.
SEGMENT: Logical Segment
The SEGMENT directive marks the starting of a logical segment. The started segment is also SHORT
assigned a name, i.e. label, by this statement. The SHORT operator indicates to the assembler that only one byte is required to code the
displacement for a jump (i.e. displacement is within -128 to +127 bytes from the address of the byte next
to the jump opcode).
Ex: - JMP SHORT LABEL
Assembly Language Program Development Tools: program and troubleshoot or debug it.
1. Editor - The debugger allows you to look at the contents of registers and memory locations after your program runs.
- An editor is a program which allows you to create a file containing the assembly language statements for your - It allows you to change the contents of registers and memory locations and re-run the program.
program.
Example: PC-Write, Wordstar. - Some debuggers allow you to stop execution after each instruction so that you can check or alter after each
register contents.
- As you type in your program, the editor stores the ASCII codes for the letters and numbers in successive RAM
locations. - A debugger also allows you to set a breakpoint at any point in your program. If you insert a breakpoint at any
point in your program, the debugger will run the program up to the instruction where you put the breakpoint and
- When you have typed in all your program, you then save the file on the hard disk. This file is called source then stop the execution.
file and the extension is .asm.
6. Emulator
2. Assembler
- An emulator is a mixture of hardware and software.
- An assembler program is used to translate the assembly language mnemonics for instructions to corresponding
binary codes. When you run the assembler, it reads the source file of your program from the disk where you have - It is used to test and debug the hardware and software of an external system, such as the prototype of a
saved it after editing. microprocessor based instrument. Part of the hardware of an emulator is a multiwire cable which connects the
host system to the system being developed.
- On the first pass through the source program, the assembler determines the displacement of named data items,
the offset of labels, etc. and puts this information in a symbol table.
- On the second pass through the source program, the assembler produces the binary code for each instruction
and inserts the offsets, etc. that it calculated during the first pass.
- The assembler generates 2 files on the floppy disk or hard disk. The first file is called object file (.obj).
- The second file generated by assembler is called the assembler list file and is given extension (.lst).
3. Linker
- A linker is a program used to join several object files into one large object file.
- The linker produces a link file which contains the binary codes for all the combined modules. The linker also
produces a link map file which contains the address information about the linked files (.obj).
4. Locator
- A locator is a program used to assign the specific address of where the segments of object code are to be loaded
into memory.
- A locator program called EXE2BIN comes with the IBM PC Disk Operating System (DOS). EXE2BIN
converts a .exe file to a .bin file which has physical addresses.
5. Debugger
- A debugger is a program which allows you to load your object code program into system memory, execute the
www.Jntufastupdates.com 38
UNIT-III 8086 Interfacing: Semiconductor memories interfacing (RAM, ROM), Intel 8255
programmable peripheral interface, Interfacing switches and LEDS, Interfacing seven segment
displays, software and hardware interrupt applications, Intel 8251 USART architecture and
interfacing, Intel 8237a DMA controller, stepper motor, A/D and D/A converters, Need for
8259 programmable interrupt controllers.
SEMICONDUCTORMEMORYINTERFACING
Semiconductor memories are of two types, viz. RAM (Random Access Memory) and
ROM (Read Only Memory).
The semiconductor RAMs are of broadly two types-static RAM and dynamic RAM. The
semiconductor memories are organized as two dimensional arrays of memory
locations. For example, 4Kx8 or 4K byte memory contains 4096 locations, where each
location contains 8-bit data and only one of the 4096locations can be selected at a
time.
The general procedure of static memory interfacingwith8086 is briefly described as
follows:
1. Arrange the available memory chips so as to obtain 16-bit data bus width. The
upper 8-bit bank is called "odd address memory bank" and the lower 8-bit bank is
called" even address memory bank".
2. Connect available memory address lines of memory chips with those of the
microprocessor and also connect the memory RD’ and WR’ inputs to the
corresponding processor control signals. Connect 16-bit data bus of the memory bank
with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE’ and A0 are used for
decoding the required chip select signals for the odd and even memory banks. The CS’
of memory is derived from the O/P of the decoding circuit.
Relation between number of address pins and memory capacity
Problem1
Interface two 4Kx8EPROM and two 4Kx8RAM chips with 8086.Select suitable maps.
Solution:
We know that, after reset, the IP and CS are initialized to form address FFFF0H.
Hence, this address must lie in the EPROM. The address of RAM may be selected
anywhere in the 1MB address space of 8086, but we will select the RAM address such
that the address map of the system is continuous.
Memory Map Table
Address A19 A18 A1 A16 A15 A14 A13 A12 A11 A10 A0 A0 A0 A0 A0 A0 A0 A0 A01 A00
7 9 8 7 6 5 4 3 2
FFFFFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM 8KX8
FE000 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
H
FDFFF 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
H
RAM 8KX8
FC000 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
H
Total 8Kbytesof EPROM need 13 address lines A0-A12 (sinceA13=8K). Address line
A13-A19 are used for decoding to generate the chip select.
The BHE’ signal goes low when a transfer is at odd address or higher byte of data is to be
accessed.
Let us assume that the latched address, BHE’ and de multiplexed data lines are readily
available for interfacing.
The memory system in this problem contains into two four4Kx8memory chips.
The two 4K x 8 chips of RAM and ROM are arranged in parallel to obtain 16-bit data
bus width. If A0 is 0,i.e., the address is even and is in RAM, then the lower RAM chip is
selected indicating 8-bit transfer at an even address. If A0 is i.e., the address is odd Memory Chip Selection Table:
and is in RAM, the BHE’ goes low, the upper RAM chip is selected, further indicating DecoderI/P--> A2A13 A1A0 A0 Selection/Com
that the 8-bit transfer is at an odd address. If the selected addresses are inROM, the Address/𝐵𝐵𝐵--> BHE’ ment
respective ROM chips are selected. If at a time A0 and BHE’ both are 0, both the RAM Word transfer on D0-D15 0 0 0 Even and odd address in RAM
or ROM chips are selected, i.e., the data transfer is of 16 bits. The selection of chips Byte transfer on D7-D0 0 0 1 Only even address in RAM
Byte transfer on D8-D15 0 1 0 Only odd address in RAM
here takes place as shown in table below.
Word transfer on D0-D15 1 0 0 Even and odd address in RAM
Byte transfer on D7-D0 1 0 1 Only even address in RAM
Byte transfer on D8-D15 1 1 0 Only odd address in ROM
 Problem3: It is required to interface two chips of 32K×8ROM and four chips of 32K×8RAM
Problem2: Design an interface between 8086CPU and two chips of 16K×8EPROM and two with 8086, according to following map.
ROM1 and ROM2 F0000H-FFFFFH, RAM1 andRAM2 D0000H-DFFFFH, RAM3 and
chips of 32K×8RAM. Select the starting address of EPROM suitably.
RAM4 E0000H-EFFFFH. Show the implementation of this memory system.
The RAM address must start at 00000H. Solution:
Solution: The last address in the map of 8086 is FFFFFH. after resetting, the processor
starts from FFFF0H. hence this address must lie in the address range of EPROM.
It is better not to use a decoder to implement the above map because it is not
continuous, i.e. there is some unused address pace between the last RAM address
(0FFFFH) and the first EPROM address (F8000H).Hence the logic is implemented using
logic gates.
INTERFACING I/O PORTS: Programmable Input-Output 8255:
 I/O ports or Input/output ports are the devices through which the PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with
microprocessor communicates with other devices or external data its outside world such as ADC, DAC, keyboard etc. We can program it according to the given
source/destinations. condition. It can be used with almost any microprocessor.
 Input activity, as one may expect, is the activity that enables the microprocessor It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can
to read data from external devices, and for example keyboards. These devices are assign different ports as input or output functions.
known as input devices as they feed data into microprocessor system.
 Output activity transfers data from the microprocessor to the external devices, for
example CRT display. These devices which accept the data from a microprocessor
system are called output devices.
 Thus for a microprocessor the input activity is similar to read operation, while the
output activity is similar to write operation.
Steps in Interfacing an I/O Device
 Connect the data bus of the microprocessor system with the data bus of the I/Oport.
 Derive a device address pulse by decoding the required address of the device and
use it as the chip select of the device.
 Use a suitable control signal i.e RD’ and WR’ to carry out device operations.
Methods of Interfacing I/O Devices
Memory Mapping IO mapping
1. 20-bit addresses are provided for IO 1. 8-bit or16-bit address are provided for IO
devices. devices
2. The IO ports or peripherals can be 2. Only IN and OUT instructions can be used
treated like memory locations and so for data transfer between IO device and
all instructions related to memory can the processor.
be used for data transfer.
 The parallel input-output port chip 8255 is also known as programmable peripheral
3.In memory mapped ports, the data can be 3.In IO mapped ports, the data transfer can
Moved from any register to port and vice take Only between the accumulator and the input-output port.
versa  It has 24 input/output lines which may be individually programmed in two groups of
ports
4. When memory mapping is used for IO 4.When IO mapping is used for IO devices, twelve lines each, or three groups of eight lines.
devices,the full memory address space then the full address space can be used for  The two groups of I/O pins are named as Group A and Group B.
cannot be used for addressing memory. addressing memory.  Each of these two groups contains a sub group of eight I/O lines called as 8- bit port
and another subgroup of four I/O lines or a 4-bitport.
 Thus GroupA contains an8-bit portA along with a 4-bit port, C upper. The portA lines
are identified by symbols PA0 –PA7 while the portC lines are identified as PC4-PC7.
 Similarly, GroupB contains an8-bitport and a 4-bitportC with lower bits.
 The portC upper and portC lower can be used in combination as an 8-bit portC.
 All of these ports function independently either as input or as output ports.
 This can be achieved by programming the bits of internal register of 8255 called as
Control Word Register.
  The 8-bit data bus buffer is controlled by read/write control logic. The read/write CS’: A low signal at CS’ pin simply allows the communication between the 8255 & the
control logic manages all of the internal and external transfer of both data and processor which means at this pin, the operation of data transfer gets allowed by an active low
control words. signal.
Pin configuration: RD’: The pin5 like RD’ is a read input pin that puts the chip within the reading mode. A low
signal at this RD’s pin provides data to the CPU by a data buffer.
WR’: a low signal at WR’ pin simply allows the CPU to execute the write operation above the
ports otherwise microprocessor’s control register through the data bus buffer.
RESET: It is an active high signal where the high signal at the RESET pin clears the control
registers &the ports are placed within the input mode.
GND: The pin7 is a GND pin of IC.
VCC: The pin26 like VCC is the 5V input pin of IC.
Modes of Operation of 8255
 There are two basic modes of operation of 8255-
I/O mode and
Bit Set-Reset mode (BSR).
 In the I/O mode, the 8255 ports work as programmable I/Oports, while in BSR mode
only portC (PC0-PC7) can be used to set or reset its individual port bits.
 Under the I/O mode of operation, further there are three modes of operation of 8255
so as to support different types of applications -mode0, mode1 and mode2.
Bit Set-Reset Mode
 In this mode, any of the 8bits of portC can be set or reset depending on B0 of the control
This microprocessor includes 40-pins like PA7-PA0, PC7-PC0, PC3-PC0, PB0-PB7, RD, WR, CS, word.
A1 & A0,D0-D7 and RESET. These pins are discussed below.  The individual bits of portC can be set or reset by sending out a single OUT
instruction to the control register.
PA7 to PA0 (PortA Pins):  When portC is used for control/status operation, this feature can be used to set or
These eight port A pins work as either buffered input lines or latched output based on the reset individual bits.
loaded control word into the control word register.  The bit to be set or reset is selected by bit select flags B3,B2 and B1 of theCWR.
PB0 to PB7 (Port B Pins):
The PB0 to PB7 from 18 to 25 are the data line pins that carry the port B data. BSR Mode Control Word Register Format
PC0 to PC7 (Port C Pins):
PC0 to PC7 pins are port C pins which include pin10 to pin17 which carry the port A data bits.
From there, pins 10 – pin13 are known as Port C upper pins & pin14 to pin17 are known as
lower pins. The pins from these two sections can be used individually to transmit 4 data bits
using two separate port C parts.
D0 to D7 (Data bus pins):
These pins are used to carry the 8-bit binary code and it is utilized to train the entire IC work.
These pins are jointly known as the control register/control word which carries the data of the
control word.
A0 & A1:
A0 and A1 pins at pin8 & pin9 simply make a decision about which port will be preferred for
transmitting the data.
If A0 = 0 & A1=0 then Port-A is selected.
If A0 = 0 & A1=1 then Port-B is selected.
If A0 = 1 & A1=0 then Port-C is selected.
If A0 = 1 & A1=1 then the control register is selected.
I/O Modes: MODE2: This mode is also known as strobed Bidirectional input/output mode. The salient
This is further divided into three modes: features of this mode are
MODE 0 (basic input/output mode) 1. The single 8-bit port in groupA is available.
MODE 1 (strobed input/output mode) 2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.
MODE 2 (strobed Bidirectional input/output mode.) 3. Three I/O lines are available at portC
4. Input and output ports are both latched
MODE0: This mode is also known as basic input/output mode. This mode provides 5. The 5-bit control portC is used for generating/accepting hand shake signals
simple input and output capability using each of the three ports. for 8-bit data transfer on portA.
In this mode all the three ports (port A, B, C) can work as simple input function
or simple output function. In this mode there is no interrupt handling capacity. All these modes can be selected by programming are internal to 8255 known as Control Word
Register(CWR) which has two formats.
MODE1: This mode is also known as strobed input/output mode. In this mode the
Hand shaking signals control the input or output action of the specified port.
The salient features of this mode are
1. Two groups- groupA and groupB are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one4-bit control/data port.
3. The 8-bit port can be either used as input or an output port.
4. Out of 8-bit portC, PC0-PC2 are used to generate control signals for port B and
PC3-PC5 are used to generate control signals for portA. The lines PC6, PC7 may be
used as independent data lines.
Mode 1 is unidirectional handshaking, which means either handshaking can be done for
input devices or output devices only. In traditional CPUs, there were separate ports only
for keyboard, mouse….. Which means the keyboard port could be only used for keyboard
only.
1. Input device gives STB signal ( active low ) to 8255 before sending data. If 8255 already
has some data, then it doesn’t allow the Input device to send data.
2. 8255 accepts data and stores it in the input buffer register. As soon as it receives the
data, it gives an IBF signal ( input buffer is full ) . If IBF = 1, it does not allow any other
data to enter 8255 PPI.
3. Now 8255 has data that should be sent to 8086. It makes INTR high, which means it is
interrupting the processor.
4. Whenever the processor is free, it services this INTR. Then the Processor sends an RD (
active low ) signal and makes data transfer via data bus.
5. As soon as the RD signal is given , INTR gets low.
Interfacing 8255 to 8086:
Interfacing switches and LEDS:
INTERFACING LIGHT EMITTING DIODE (LED) WITH 8086:
Anode is connected through a resistor to GND & the Cathode is connected to the
Microprocessor pin as shown in Fig. When the Port Pin is HIGH, the LED is OFF & when the
Port Pin is LOW the LED is turned ON.
We now want to flash a LED. It works by turning ON a LED & then turning it OFF & then Figure LEDs connected to port pins of 8255
looping back to START. A delay is generated between the flashing of LEDs.
Interfacing seven segment displays:
The seven segment LED display is a multiport display It can display all decimal digits and some
characters It is very popular among multiple displays as it has the smallest number of
separately controlled light emitting diodes (LED) Multiple displays of 9-segment LED,
14-segment LED and dot matrix type are available In seven-segment displays there are seven
light emitting diodes (LED) as shown in figure 1 Each LED can be controlled separately To
display a digit or letter the desired segments are made ON as shown in figure.
We can produce a truth table for each decimal digit
It is widely used in digital clocks, basic calculators, electronic meters, and other electronic
devices that display numerical information. It consists of seven segments of light-emitting
diodes (LEDs) which are assembled like numerical 8.
Types of Seven Segment Displays:
According to the type of application, there are two types of configurations of seven-segment
displays:
common anode display
common cathode display.
1. In common cathode seven segment displays, all the cathode connections of LED segments
are connected together to logic 0 or ground. We use logic 1 through a current limiting
resistor to forward bias the individual anode terminals a to g.
2. Whereas all the anode connections of the LED segments are connected together to logic 1 Applications of Seven Segment Displays:
in a common anode seven segment display. We use logic 0 through a current limiting
resistor to the cathode of a particular segment a to g. Common applications of seven-segment displays are:
Common anode seven segment displays are more popular than cathode seven segment Digital clocks
displays because logic circuits can sink more current than they can source and it is the same Clock radios
as connecting LEDs in reverse. Calculators
Wristwatches
Speedometers
Motor-vehicle odometers
Radiofrequency indicators
 Intel 8251 USART architecture and interfacing: 1. Data bus buffer –
 8251 USART is a universal synchronous and asynchronous controller designed by This block helps in interfacing the internal data bus of 8251 to the system data bus. The
Intel basically to facilitate communication. data transmission is possible between 8251 and CPU by the data bus buffer block.
 USART standsfor Universal Synchronousand Asynchronous Receiver Transmitter 2. Read/Write control logic –
and functions as an intermediary that allows serial and parallel communication It is a control block for overall device. It controls the overall working by selecting the
between the microprocessor and the peripheral devices. operation to be done. The operation selection depends upon input signals as:
 We know that microprocessors allow parallel communication. And in parallel
Communication, the number of cables required for data transmission is equal to the
number of bits to be transmitted per cycle.
Thus the approach of transmitting data parallelly to long distance is cost-ineffective.
 So, to reduce the overall cost of the system despite parallel data communication
between the processor and peripheral devices, the serial transfer of data is
permitted.
Hence for this purpose, USART acts as a mediator between the processor and peripheral
devices so, that the parallel data from the processor can be converted into serial data and
efficiently transferred to the peripheral devices.
In a similar way, the serial data from the peripheral devices is converted by the USART into
the parallel form so that it can be accepted by the processor.
Also, it allows both synchronous and asynchronous transmission and reception thus is called
so.
3. Modem control (modulator/demodulator) –
Architecture and Working of 8251 USART:
A device converts analog signals to digital signals and vice-versa and helps the
computers to communicate over telephone lines or cable wires. The following are
active-low pins of Modem.
1. DSR: Data Set Ready signal is an input signal.
2. DTR: Data terminal Ready is an output signal.
3. CTS: It is an input signal which controls the data transmit circuit.
RTS: It is an output signal which is used to set the status RTS.
4. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for
conversion into serial signal and further transmission onto the common channel.
1. TXD: It is an output signal, if its value is one, means transmitter will transmit
the data.
5. Transmit control –
This block is used to control the data transmission with the help of following pins:
1. TXRDY: It means transmitter is ready to transmit data character.
2. TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
3. TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
6. Receive buffer –
This block acts as a buffer for the received data.
1. RXD: An input signal which receives the data.
7. Receive control –
This block controls the receiving data.
1. RXRDY: An input signal indicates that it is ready to receive the data.
2. RXC: An active-low input signal which controls the data transmission rate of
received data.
 3. SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.
Pin Diagram of 8251:
The device, which requires serial communication with processor, can be connected to this
9-pin D-type connector using 9-core cable.
INTERFACING 8251A TO 8086 PROCESSOR: Intel 8237a DMA controller:
The chip select for I/O mapped devices are generated by using a 3-to-8 decoder.  Direct Memory Access (DMA) is a method of allowing data to be moved from one
location to another in a computer without intervention from the central processor
• The address lines A5, A6 and A7 are decoded to generate eight chip select signals (IOCS-0 (CPU).
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 825lA.  It is also a fast way of transferring data within (and sometimes between) computer.
 The DMA I/O technique provides direct access to the memory while the microprocessor
• The address line A0 and the control signal M/IO(low) are used as enable for decoder. is temporarily disabled.
 The DMA controller temporarily borrows the address bus, data bus and control bus
• The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal addresses. from the microprocessor and transfers the data directly from the external devices to a
series of memory locations (and vice versa).
• The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data transfer. Basic DMA Operation:
 Two control signals are used to request and acknowledge a direct memory access (DMA)
• The RESET and clock signals are supplied by 8284 clock generator. Here the processor
transfer in the microprocessor-based system.
clock is directly connected to 8251A. This clock controls the parallel data transf er between
1. The HOLD signal as an input(to the processor) is used to request a DMA action.
the processor and 825lA.
2. The HLDA signal as an output that acknowledges the DMA action.
 When the processor recognizes the hold, it stops its execution and enters hold cycles.
• 8251A in I/O mapped in the system is shown in the figure.
 HOLD input has higher priority than INTR or NMI.
 The only microprocessor pin that has a higher priority than a HOLD is the RESET pin.
 HLDA becomes active to indicate that the processor has placed its buses at high-impedance
state.
Basic DMA Definitions: o After every byte is transferred, the address register is incremented (or
decremented) and the count register is decremented.
 Direct memory accesses normally occur between an I/O device and memory without o This continues till the count reaches zero (Terminal count). Now the DMA
the use of the microprocessor. transfer is completed.
1. A DMA read transfers data from the memory o At the end of the transfer, the system bus is released by the DMAC by making
to the I/O device. HOLD = 0. Thus microprocessor takes control of the system bus and continues
2. A DMA write transfers data from an I/O device its operation.
to memory. When DMA operates:
 The system contains separate memory and I/O control signals.
 Hence the Memory & the I/O are controlled simultaneously
 The DMA controller provides memory with its address, and the controller signal selects
the I/O device during the transfer.
 Data transfer speed is determined by speed of the memory device or a DMA controller.
 In many cases, the DMA controller slows the speed of the system when transfers occur.
 The serial PCI (Peripheral Component Interface) Express bus transfers data at rates
exceeding DMA transfers.
 This in modern systems has made DMA is less important.
8237:
 The 8237 supplies memory & I/O with control signals and memory address information
during the DMA transfer.
 It is actually a special-purpose microprocessor whose job is high-speed data transfer
between memory and I/O
 8237 is not a discrete component in modern microprocessor-based systems.
 It appears within many system controller chip sets
 8237 is a four-channel device compatible with 8086/8088, adequate for small systems.
 Expandable to any number of DMA channel inputs
1. The sequence of DMA transfer is as follows:  8237 is capable of DMA transfers at rates up to 1.6MB per second.
o Microprocessor initializes the DMAC (DMA controller) by giving the starting  Each channel is capable of addressing a full64K-byte section of memory.
address and the number of bytes to be transferred.
o An I/O device requests the DMAC to perform DMA transfer through the DREQ
line.
o The DMAC in turn sends a request signal to the microprocessor through the
HOLD line.
o The microprocessor finishes the current machine cycle and releases the system
bus (gets disconnected from it). It also acknowledges receiving the HOLD signal
through the HLDA line.
o The DMAC acquires control of the system bus. The DMAC sends the DACK signal
to the I/O peripheral and the DMA transfer begins.
Block Diagram of 8237: BA and BWC:
The base address (BA) and base word count (BWC) registers are used when auto-
initialization is selected for a channel.
In auto-initialization mode, these registers are used to reload the CAR and CWCR after the
DMA action is completed.
MR:
The mode register programs the mode of operation for a channel.
Each channel has its own mode register as selected by bit positions 1 and 0.
Remaining bits of the mode register select operation, auto-initialization,
increment/decrement, and mode for the channel
8237 Internal Registers:
CAR:
The current address register holds a 16-bit memory address used for the DMA transfer.
 each channel has its own current addressregister for this purpose.
BR:
 When a byte of data is transferred during a DMA operation, CAR is either incremented
The bus request register is used to request
or decremented. depending on how it is programmed
a DMA transfer via software.
CWCR:
very useful in memory-to-memory transfers, where an external signal is not available to
The current word count register programs a channel for the number of bytes to transferred
begin the DMA transfer
during a DMA action.
CR:
The command register programs the operation of the 8237 DMA controller.
The register uses bit position 0 to select the memory-to-memory DMA transfer mode.
Memory-to-memory DMA transfers use DMA channel
DMA channel 0 to hold the source address
DMA channel 1 holds the destination address
Pin Diagram and Pin description of 8237: Interfacing Analog to Digital Data Converters:
 In most of the cases, the PIO 8255 is used for interfacing the analog to digital
converters with microprocessor.
 The analog to digital converters is treated as an input device by the
microprocessor that sends an initializing signal to the ADC to start the analogy to
digital data conversation process. The start of conversation signal is a pulse of a
specific duration.
 The process of analog to digital conversion is a slow
 Process and the microprocessor have to wait for the digital data till the
conversion is over. After the conversion is over, the ADC sends end of conversion
EOC signal to inform the microprocessor that the conversion is over and the
result is ready at the output buffer of the ADC. These tasks of issuing an SOC pulse
to ADC, reading EOC signalfrom the ADC and reading the digital output of the ADC
are carried out by the CPU using 8255 I/O ports.
 The time taken by the ADC from the active edge of SOC pulse till the active edge of
VCC :POWER: a5V supply. EOCsignal is called as the conversion delay of the ADC.
VSS: GROUND: Ground.
 It may range anywhere from a few microseconds in case of fast ADC to even a few
CLK Input: Clock Input controls the internal operations of the 8237A and its rate of data
hundred milliseconds in case of slow ADCs.
transfers. The input may be driven at up to 5 MHz for the 8237A-5.
CS Input :CHIP SELECT:Chip Select is an active low input used to select the 8237A as an I/O  The available ADC in the market use different conversion techniques for
device during the Idle cycle. This allows CPU communication on the data bus. conversion of analog signal to digitals. Successive approximation techniques and
RESET Input: Reset is an active high input which clears the Command, Status, Request and dual slope integration techniques are the most popular techniques used in the
Temporary registers. It also clears the first/ last flip/flop and sets the Mask register. Following a integrated ADC chip.
Reset the device is in the Idle cycle.  General algorithm for ADC interfacing contains the following steps:
READY: Ready is an input used to extend the memory read and write pulses from the 8237A to  Ensure the stability of analog input, applied to the ADC.
accommodate slow memories or I/O peripheral devices. Ready must not make transitions
 Issue start of conversion pulse to ADC
during its specified setup/hold time.
HLDA Input:HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates  Read end of conversion signal to mark the end of conversion processes.
that it has relinquished control of the system busses.  Read digital data output of the ADC as equivalent digital output.
DREQ0 ±DREQ3 Input  Analog input voltage must be constant at the input of the ADC right from the start
DMA REQUEST: The DMA Request lines are individual asynchronous channel request inputs of conversion till the end of the conversion to get correct results. This may be
used by peripheral circuits to obtain DMA service. In fixed Priority, DREQ0 has the highest ensured by a sample and hold circuit which samples the analog signal and holds it
priority and DREQ3 has the lowest priority. constant for specific time duration. The microprocessor may issue a hold signal to
DB0 ±DB7
the sample and hold circuit.
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system
data bus.  If the applied input changes before the complete conversion process is over, the
In memory-to-memory operations, data from the memory comes into the 8237A on the data bus digital equivalent of the analog input calculated by the ADC may not be correct.
during the read-from-memory transfer. In the write-to-memory transfer, the data bus outputs ADC 0808/0809:
place the data into the new memory location.  The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive
IOR Input/Output:I/O READ: I/O Read is a bidirectional active low three-state line.8237A to approximation converters. This technique is one of the fast techniques for analog to
access data from a peripheral
digital conversion. The conversion delay is 100µs at a clock frequency of 640 KHz,
IOW Input/Output
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle which is quite low as compared to other converters. These converters do not need any
external zero or full scale adjustments as they are already taken care of by internal
circuits.
  These converters internally have a 3:8 analog multiplexer so that at a time
eight different analog conversion by using address lines - ADD A, ADD B,
ADD C, as shown. Using these address inputs, multichannel data acquisition
system can be designed using a single ADC. The CPU may drive these lines
using output port lines in case of multichannel applications. In case ofsingle
input applications, these may be hardwired to select the proper input.
 There are uni polar analog to digital converters, i.e. they are able to convert
only positive analog input voltage to their digital equivalent. These chips do
not contain any internal sample and hold circuit.
 If one needs a sample and hold circuit for the conversion of fast signal into
equivalent digital quantities, it has to be externally connected at each of the
analog inputs.
Fig (1) and Fig (2) show the block diagrams and pin diagrams for ADC 0808/0809.
Address lines
Analog I/P selected
C B A
I/P 0 0 0 0
I/P 1 0 0 1
I/P 2 0 1 0
I/P 3 0 1 1
I/P 4 1 0 0
I/P 5 1 0 1
I/P 6 1 1 0
I/P 7 1 1 1
Interfacing ADC 0808 to 8086:
Interfacing Digital To Analog Converters:
The digital to analog converters convert binary numbers into their analog
equivalent voltages. The DAC find applications in areas like digitally controlled gains,
motor speed controls, programmable gain amplifiers, etc.
DAC08008-bit Digital to Analog Converter
The DAC 0800 is a monolithic 8-bit DAC manufactured by National Semiconductor.
It has settling time around 100ms and can operate on a range of power supply voltages i.e. from
4.5V to +18V.
Usually the supply V+ is 5V or +12V.
The V-pin can be kept at a minimum of -12V. Pin Diagram of AD7523:
The supply range extends from +5V to +15V , while Vref may be anywhere between -10V to
+10V. The maximum analog output voltage will be +10V, when all the digital inputs are at logic
high state. Usually a Zener is connected between OUT1 and OUT2 to save the DAC from
negative transients.
An operational amplifier is used as a current to voltage converter at the output of AD 7523 to
convert the current output of AD7523 to a proportional output voltage.
It also offers additional drive capability to the DAC output. An external feedback resistor acts to
Pin Diagram of DAC 0800 control the gain. One may not connect any external feedback resistor, if no gain control is
required.
Interfacing DAC 0800 with 8086:
Ad75238-BitMultiplying DAC:
Intersil‟s AD 7523 is a 16 pin DIP, multiplying digital to analog converter, containing R-2R
ladder(R=10KΩ) for digital to analog conversion along with single pole double through NMOS
switches to connect the digital inputs tothe ladder.
Stepper Motor Interfacing:
Fig.3 Stepper motor rotor
The circuit for interfacing a winding Wn with an I/O port is given in fig.4. Each ofthe windings
of a stepper motor needs this circuit for its interfacing with the output port. A typical stepper
motor may have parameters like torque 3 Kg-cm, operating voltage 12V, current rating 0.2 A
and a step angle 1.80 i.e. 200 steps/revolution (number of rotor teeth).
Fig.1 Internal schematic of a four winding stepper motor
 A stepper motor is a device used to obtain an accurate position control of rotating shafts.
It employs rotation of its shaft in terms of steps, rather than continuous rotation as in
case of AC or DC motors. To rotate the shaft of the stepper motor, a sequence of pulses is
needed to be applied to the windings of the stepper motor, in a proper sequence.
 The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to its number of internal teeth on its rotor. The stator teeth and the rotor
teeth lock with each other to fix a position of the shaft.
 With a pulse applied to the winding input, the rotor rotates by one teeth position or an
angle x. The angle x may be calculated as:
X=3600/no. of rotor teeth
 After the rotation of the shaft through angel x, the rotor locks itself with the next tooth in
the sequence on the internal surface of stator.
 The internal schematic of a typical stepper motor with four windings is shown in fig.1.
 The stepper motors have been designed to work with digital circuits. Binary level pulses Fig.4 interfacing stepper motor winding
of 0-5V are required at its winding inputs to obtain the rotation of shafts. The sequence
of the pulses can be decided, depending upon the required motionof the shaft. A simple schematic for rotating the shaft of a stepper motor is called a wave scheme. In this
scheme, the windings Wa, Wb, Wc and Wd are applied with the required voltages pulses, in a
 Fig.2 shows a typical winding arrangement of the stepper motor.
cyclic fashion. By reversing the sequence of excitation, the direction of rotation of the stepper
 Fig.3 shows conceptual positioning of the rotor teeth on the surface of rotor, fora six motor shaft may be reversed.
teeth rotor.
Table.1 shows the excitation sequences for clockwise and anticlockwise rotations. Another
popular scheme for rotation of a stepper motor shaft applies pulses to two successive
windings at a time but these are shifted only by one position at a time. This scheme for
rotation of stepper motor shaft is shown in table2.
Fig.2 Winding arrangement of a stepper motor.
 Table.1 Excitation sequence of a stepper motor using wave switching scheme. Need of Programmable Interrupt Controller:
 We know whenever an interrupt occurs then the microprocessor suspends the current
Motion step A B C D program and switches to the Interrupt Service Routine (ISR).
1 1 0 0 0  there are many devices connected to a processor. So, for such a case the processor must
Clock wise
2 0 1 0 0 have more number of lines to handle several interrupts.
3 0 0 1 0
 But it is not practically possible to increase the number of lines each time with the
4 0 0 0 1 increase in the number of interrupts.
5 1 0 0 0  So, to overcome this problem 8259 PIC chip is used. 8259 allows the combining of
1 1 0 0 0 multiple interrupts and providing them to the processor based on priority through a
2 0 0 0 1 common line.
Anticlock
3 0 0 1 0 Features of 8259:
wise
4 0 1 0 0
5 1 0 0 0 1. The 8259 programmable interrupt controller has 8 interrupt pins thus can handle 8
interrupt inputs.
Table.2 An alternative scheme for rotating stepper motor shaft
2. The priority of interrupts in 8259 can be programmed. The priority of interrupts is
Motion step A B C D decided by the different operating modes.
1 0 0 1 1 3. We know that a single 8259 can handle 8 interrupt inputs but by cascading multiple
Clock wise 2 0 1 1 0 8259, it can handle maximal 64 interrupt inputs.
3 1 1 0 0 4. 8259 allows individual masking of each generated interrupt using interrupt mask
4 1 0 0 1 register.
5 0 0 1 1
5. 8259 is programmed in a way that it can handle either edge-triggered or level-triggered
1 0 0 1 1 interrupt request at a time.
Anticlock 2 1 0 0 1 6. If multiple interrupts are generated, then 8259 holds the status of interrupts that are
wise 3 1 1 0 0 masked, in-service and pending.
4 0 1 1 0 7. It reduces the software and real-time overhead generated due to handling multilevel
5 0 0 0 0 priority interrupts.
Architecture of 8259
The figure below shows the architectural representation of 8259 programmable interrupt
controller:
8259 Programmable Interrupt Controller:
 Programmable interrupt controllers are used to enhance the number of interrupts of
a microprocessor.
 8259 is a programmable interrupt controller which shows compatibility with 8085 and
8086 microprocessor.
 It is also known as a priority interrupt controller and was designed by Intel to
increase the interrupt handling ability of the microprocessor.
 An 8259 PIC never services an interrupt; it simply forwards the interrupt to the
processor for the execution of interrupt service routine.
 By connecting Intel 8259 with these microprocessors, we can increase their interrupt
handling capability. Intel 8259 combines the multi-interrupt input sources into a
single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from
IR0-IR7.
Thus, the above architecture has different units that combinely functions to increase the 8. Cascade buffer/comparator: As we have already discussed that by cascading multiple
interrupts handled by the processor. 8259, the number of interrupts handled by 8259 can be expanded up to 64. The unit allows the
comparison of IDs of different 8259s cascaded together.
1. Data Bus Buffer: 8259 has tri-stated bidirectional 8-bit data bus buffer (i.e., D0 to D7) that It permits the operation of the system in two modes: master mode and slave mode.
interfaces with the internal bus of the processor. The 8085 microprocessor sends/ receives In the master mode of operation, it acts as a cascaded buffer. Whereas in slave mode, this unit
control or status words to / from the 8259 using data bus buffer. acts as a comparator.
2. Read/ Write Logic: This unit is responsible for controlling the internal read-write
operations of the system. It holds initialization command word register and operation Among the various cascaded 8259, one 8259 directly handles the interrupts by forming a
command word register inside which various control formats exist that are needed for the connection with the processor and it is known to be master 8259. While the other 8259s that
device operation. interrupts the master 8259 are known as slave 8259.
RD, WR, A0 and CS are the pins that are associated with this unit. Basically, these pins are used
by the processor for read and write operations. Each of the 8259s can be separately programmed as all of them holds a specific address. The
A low signal at CS i.e., chip select shows that now the communication has been set up between cascading pins of the master 8259, CAS0, CAS1 and CAS2 forms connection with the
the processor and 8259. corresponding pins of slave 8259s.
3. Control Logic: This unit is the heart of the architecture of 8259. It controls the overall For the slave devices, these pins act as input pins while for a master device these acts as output
operation of the system by sending the INTR signal to the processor whenever an interrupt pins. An active-low signal at SP/EN for a device shows that it is operating in slave mode.
request is generated.
Also, it receives INTA signal by the processor when microprocessor demands for the address In this way, a programmable interrupt controller operates.
of the interrupt service routine. The control logic is responsible for sending the address of the
desired interrupt service routine through the data bus. The pin level diagram and interfacing diagram is like below –
4. Interrupt request register (IRR): This unit stores the interrupt requests generated by the
peripheral devices. We know that 8259 has 8 interrupt request pins (i.e., IR0 to IR7). So, the
unit can store 8 interrupt requests that are requesting the service from the processor.
5. Priority Resolver: This logic unit decides that among all the interrupt request present in the
IRR which holds the highest priority and needs to be executed first.
Suppose at the time of servicing an interrupt, another incoming interrupt request gets
generated then that request will be ignored as the one in-service is holding the highest
priority.
But in case the incoming request has greater priority than the one which is being in current
execution then that respective bit will be set in ISR and INTR signal is sent to the
microprocessor.
This simply means that only the interrupt holding the highest priority will be forwarded by the
8259 to the processor.
6. In-service register: Here the name of the unit is itself indicating the operation performed by
it. This register unit stores the interrupts which are currently being executed by the processor.
The priority resolver sets each bit of ISR and after getting interrupt word command by the
processor, the bits get reset. As the processor holds the ability to directly read the status of in-
service register.
7. Interrupt mask register: This register unit holds the masking bit of those interrupts which
are to be masked. Through operation command word (OCW) the processor sends the required
information and programs the interrupt mask register.
 UNIT V: INTEL 8051 MICRCONTROLLER Microcontroller:
A microcontroller is a highly integrated single chip, which consists of on chip CPU (Central Processing
Unit), RAM (Random Access Memory), EPROM/PROM/ROM (Erasable Programmable Read Only
Introduction:
A decade back the process and control operations were totally implemented by the Memory), I/O (input/output) – serial and parallel, timers, interrupt controller. For example, Intel 8051 is
Microprocessors only. But now a day the situation is totally changed and it is occupied by the new 8-bit microcontroller and Intel 8096 is 16-bit microcontroller. The block diagram of Microcontroller is
devices called Microcontroller. The development is so drastic that we can’t find any electronic gadget shown in Fig.2.
without the use of a microcontroller. This microcontroller changed the embedded system design so simple
and advanced that the embedded market has become one of the most sought after for not only
entrepreneurs but for design engineers also.
What is a Microcontroller?
A single chip computer or A CPU with all the peripherals like RAM, ROM, I/O Ports, Timers,
ADCs etc... on the same chip. For ex: Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X etc…
MICROPROCESSORS & MICROCONTROLLERS:
Microprocessor:
A CPU built into a single VLSI chip is called a microprocessor. It is a general-purpose device and
additional external circuitry are added to make it a microcomputer. The microprocessor contains
arithmetic and logic unit (ALU), Instruction decoder and control unit, Instruction register, Program
counter (PC), clock circuit (internal or external), reset circuit (internal or external) and registers. But the
microprocessor has no on chip I/O Ports, Timers , Memory etc.
For example, Intel 8085 is an 8-bit microprocessor and Intel 8086/8088 a 16-bit microprocessor. The Fig.2.Block Diagram of a Microcontroller
block diagram of the Microprocessor is shown in Fig.1
Fig.1 Block diagram of a Microprocessor.
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Distinguish between Microprocessor and Microcontroller
EVOLUTION OF MICROCONTROLLERS:
S. No Microprocessor Microcontroller
The first microcontroller TMS1000 was introduced by Texas Instruments in the year 1974. In the
A microprocessor is a general year 1976, Motorola designed a Microprocessor chip called 6801 which replaced its earlier chip 6800
A microcontroller is a dedicated chip which
1 purpose device which is called a with certain add-on chips to make a computer. This paved the way for the new revolution in the history of
is also called single chip computer.
CPU chip design and gave birth to a new entity called “Microcontroller”. Later the Intel company produced
its first Microcontroller 8048 with a CPU and 1K bytes of EPROM, 64 Bytes of RAM an 8-Bit Timer
A microprocessor do not contain A microcontroller includes RAM, ROM,
serial and parallel interface, timers, and 27 I/O pins in 1976. Then followed the most popular controller 8051 in the year 1980 with 4K bytes
2 onchip I/OPorts, Timers, Memories
interrupt circuitry (in addition to CPU) in a of ROM,128 Bytes of RAM , a serial port, two 16-bit Timers , and 32 I/O pins. The 8051 family has
etc.. single chip. many additions and improvements over the years and remains a most acclaimed tool for today’s circuit
Microprocessors are most designers. INTEL introduced a 16 bit microcontroller 8096 in the year 1982 . Later INTEL introduced
Microcontrollers are used in small,
3 commonly used as the CPU in minimum component designs performing 80c196 series of 16-bit Microcontrollers for mainly industrial applications. Microchip, another company
microcomputer systems control-oriented applications. has introduced an 8-bit Microcontroller PIC 16C64 in the year 1985.The 32-bit microcontrollers have
been developed by IBM and Motorola. MPC 505 is a 32-bit RISC controller of Motorola. The 403 GA is
Microprocessor instructions are Microcontroller instructions are both bit
4 a 32 -bit RISC embedded controller of IBM.
mainly nibble or byte addressable addressable as well as byte addressable.
In recent times ARM Company (Advanced RISC machines) has developed and introduced 32 bit
Microprocessor instruction sets are Microcontrollers have instruction sets
controllers for high-end application devices like mobiles, IPods etc...
5 mainly intended for catering to catering to the control of inputs and
large volumes of data. outputs. TYPES OF MICROCONTROLLERS:
Microcontrollers can be classified on the basis of internal bus width, architecture, memory and
Microprocessor based system Microcontroller based system design is
6 instruction set as 4-bit, 8-bit, 16-bit and 32-bit microcontrollers.
design is complex and expensive rather simple and cost effective
4-bit Microcontrollers : These 4-bit microcontrollers are small size, minimum pin count and low cost
The instruction set of a Microcontroller is controllers which are widely used for low end applications like LED & LCD display drivers ,portable
The Instruction set of
very simple with less number of battery chargers etc.. Their power consumption is also low. The popular 4-bit controllers are Renasa
7 microprocessor is complex with
instructions. For, ex: PIC microcontrollers M34501 which is a 20 pin DIP chip with 4kB of ROM, 256 Bytes of RAM,2-Counters and 14 I/O Pins.
large number of instructions.
have only 35 instructions. Similarly ATAM862 series from ATMEL.
A microprocessor has zero status 8-bit Microcontrollers : These are the most popular and widely used microcontrollers .About 55% of all
8 A microcontroller has no zero flag.
flag CPUs sold in the world are 8-bit microcontrollers only.The 8-bit microcontroller has 8-bitinternal bus and
the ALU performs all the arithmetic and logical operations on a byte instruction. The well known 8-bit
microcontroller is 8051 which was designed by Intel in the year 1980 for the use in embedded systems.
Other 8-bit microcontrollers are Intel 8031/8052 and Motorola MC68HC11 and AVR Microcontrollers,
Microchip’s PIC Microcontrollers 12C5XX ,16C5X and 16C505 etc...
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16-bit Microcontrollers: When the microcontroller performs 16-bit arithmetic and logical operations at To develop an assembly language program we need certain program development tools. An
an instruction, the microcontroller is said to be a 16-bit microcontroller. The internal bus width of 16-bit assembly language program consists of Mnemonics which are nothing but short abbreviated English
microcontroller is of 16-bit. These microcontrollers are having increased memory size and speed of instructions given to the controller. The various development tools required for Microcontroller
operation when compared to 8-bit microcontrollers. These are most suitable for programming in High- programming are explained below.
level languages like C or C ++. They find applications in disk drivers, modems, printers, scanners and
1. Editor: An Editor is a program which allows us to create a file containing the assembly language
servomotor control. Examples of 16-bit microcontrollers are Intel 8096 family and Motorola MC68HC12
statements for the program. Examples of some editors are PC writes WordStar. As we type the program
and MC68332 families, the performance and computing capability of 16 bit microcontrollers are
the editor stores the ACSII codes for the letters and numbers in successive RAM locations. If any typing
enhanced with greater precision as compared to the 8-bit microcontrollers.
mistake is done editor will alert us to correct it. If we leave out a program statement an editor will let
32-Bit Microcontrollers: These microcontrollers used in high-end applications like Automotive control, you move everything down and insert a line. After typing all the program we have to save the program .
Communication networks, Robotics, Cell phones ,GPRS & PDAs etc.. This we call it as source file. The next step is to process the source file with an assembler.
For EX: PIC32, ARM 7, ARM9, SHARP LH79520, ATMEL 32 (AVR) , Ex: Sample. asm
Texas Instrument’s –.TMS320F2802x/2803x etc... are some of the popular 32-bit microcontrollers. 2. Assemble r: An Assembler is used to translate the assembly language mnemonics into machine
language ( i.e binary codes). When you run the assembler it reads the source file of your program from
COMMERCIAL MICROCONTROLLERS where you have saved it. The assembler generates a file with the extension .hex. This file consists of
There are various manufacturers who are supplying various types of microcontrollers suitable for hexadecimal values encoding a sequence of data and their starting offset or absolute address.
different applications depending on the power consumption and the available features..They are given
3. Compiler: A compiler is a program which converts the high level language program like “C” into
below in tables. First the various members of INTEL 51 family are given in below table. binary or machine code. Using high level languages it is easy to manage complex data structures which
INTEL MCS 51 Family are often required for data manipulation. Because of its ease, flexibility and debug options now a days the
compilers have become very popular in the market. Compilers like Keil, Ride and IAR workbench are
On chi p RAM On chi p program
Microcontroller Ti mers/Counters Interrupts Serial ports very popular.
(Bytes) memory
3. Debugger/Simulator: A debugger is a program which allows executes the program, and
8031 128 None 2 5 1
troubleshoots or debugs it. The debugger allows looking into the contents of registers and memory
8032 256 None 3 6 1 locations after the program runs. We can also change the contents of registers and memory locations and
rerun the program. Some debuggers allow stopping the program after each instruction so that you can
8051 128 4K ROM 2 5 1
check or alter memory and register contents. This is called single step debug. A debugger also allows
8052 256 8K ROM 3 6 1 setting a breakpoint at any point in the program. If we insert a break point, the debugger will run the
program up to the instruction where the breakpoint is put and then stop the execution.
8751 128 4K EPROM 2 5 1
A simulator is a software program which virtually executes the instructions similar to a
8752 256 8K EPROM 3 6 1
microcontroller and shows the results. This will help in evaluating the results without committing any
MICROCONTROLLER DEVELOPMENT TOOLS: errors. By doing so we can detect the possible logic errors
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INTEL 8051 MICRCONTROLLER :
The 8051 microcontroller is a very popular 8-bit microcontroller introduced by Intel in the year
1981 and it has become almost the academic standard now a days. The 8051 is based on an 8-bit CISC
core with Harvard architecture. Its 8-bit architecture is optimized for control applications with extensive
Boolean processing. It is available as a 40-pin DIP chip and works at +5 Volts DC. The salient features of
8051 controller are given below.
SALIENT FEATURES: The salient features of 8051 Microcontroller are
1. 4 KB on chip program memory (ROM or EPROM)).
2. 128 bytes on chip data memory (RAM).
3. 8-bit data bus
4. 16-bit address bus
5. 32 general purpose registers each of 8 bits
6. Two -16 bit timers T0 and T1
7. Five Interrupts (3 internal and 2 external).
8. Four Parallel ports each of 8-bits (PORT0, PORT1, PORT2, PORT3) with a total of 32 I/O lines.
9. One 16-bit program counter and One 16-bit DPTR ( data pointer)
10. One 8-bit stack pointer
XTAL1, XTAL2: These two pins are connected to Quartz crystal oscillator which runs the on-chip
11. One Microsecond instruction cycle with 12 MHz Crystal.
oscillator. The quartz crystal oscillator is connected to the two pins along with a capacitor of 30pF as
12. One full duplex Serial Communication port.
shown in the circuit. If we use a source other than the crystal oscillator, it will be connected to XTAL1
PIN Diagram of 8051 Microcontroller: and XTAL2 is left unconnected.
The 8051 microcontroller is available as a 40 pin DIP chip and it works at +5 volts DC. Among
the 40 pins, a total of 32 pins are allotted for the four parallel ports P0, P1, P2 and P3 i.e each port
occupies 8-pins .The remaining pins are VCC, GND, XTAL1, XTAL2, RST, EA, PSEN.
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RST: The RESET pin is an input pin and it is an active high pin. When a high pulse is applied to this pin
the microcontroller will reset and terminate all activities. Upon reset all the registers except PC will reset
to 0000 Value and PC register will reset to 0007 value.
(Exte rnal Access): This pin is an active low pin. This pin is connected to ground when
microcontroller is accessing the program code stored in the external memory and connected to Vcc when
it is accessing the program code in the on chip memory. This pin should not be left unconnected.
(Program Store Enable): This is an output pin which is active low. When the microcontroller
is accessing the program code stored in the external ROM, this pin is connected to the OE (Output
Enable) pin of the ROM.
ALE (Address latch enable): This is an output pin, which is active high. When connected to external
memory , port 0 provides both address and data i.e address and data are multiplexed through port 0 .This
ALE pin will de-multiplex the address and data bus .When the pin is High , the AD bus will act as address
bus otherwise the AD bus will act as Data bus.
P0.0- P0.7(AD0-AD7) : The port 0 pins multiplexed with Address/data pins .If the microcontroller is
accessing external memory these pins will act as address/data pins otherwise they are used for Port 0 pins.
P2.0- P2.7(A8-A15) : The port2 pins are multiplexed with the higher order address pins .When the
Fig.3. Internal Architecture of 8051 Microcontroller
microcontroller is accessing external memory these pins provide the higher order address byte otherwise
A and B Registers : The A and B registers are special function registers which hold the results of many
they act as Port 2 pins.
arithmetic and logical operations of 8051.The A register is also called the Accumulator and as its name
P1.0- P1.7: These 8-pins are dedicated for Port1 to perform input or output port operations. suggests, is used as a general register to accumulate the results of a large number of instructions. By
P3.0- P3.7: These 8-pins are meant for Port3 operations and also for some control operations like Read, default it is used for all mathematical operations and also data transfer operations between CPU and any
Write, Timer0, Timer1, INT0, INT1, RxD and TxD external memory.
The B register is mainly used for multiplication and division operations along with A register.
ARCHITECTURE & BLOCK DIAGRAM OF 8051 MICROCONTROLLER:
M UL A B : DIV A B.
The architecture of the 8051 microcontroller can be understood from the block diagram. It has Harvard
architecture with RISC (Reduced Instruction Set Computer) concept. The block diagram of 8051 It has no other function other than as a location where data may be stored.
microcontroller is shown in Fig 3. below1.It consists of an 8-bit ALU, one 8-bit PSW(Program Status The R registers: The "R" registers are a set of eight registers that are named R0, R1, etc. up to
Register), A and B registers , one 16-bit Program counter , one 16-bit Data pointer register(DPTR),128 R7. These registers are used as auxiliary registers in many operations. The "R" registers are also used to
bytes of RAM and 4kB of ROM and four parallel I/O ports each of 8-bit width. 8051 has 8-bit ALU temporarily store values.
which can perform all the 8-bit arithmetic and logical operations in one machine cycle. The ALU is
associated with two registers A & B
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Program Counter (PC): 8051 has a 16-bit program counter .The program counter always points to the Data Pointer Register (DPTR): It is a 16-bit register which is the only user-accessible. DPTR, as the
address of the next instruction to be executed. After execution of one instruction the program counter is name suggests, is used to point to data. It is used by a number of commands which allow the 8051 to
incremented to point to the address of the next instruction to be executed. It is the contents of the PC that access external memory. When the 8051 accesses external memory it will access external memory at the
are placed on the address bus to find and fetch the desired instruction. Since the PC is 16-bit width, 8051 address indicated by DPTR. This DPTR can also be used as two 8-registers DPH and DPL.
can access program addresses from 0000H to FFFFH, a total of 6kB of code. Program Status Register (PSW): The 8051 has a 8-bit PSW register which is also known as Flag
register. In the 8-bit register only 6-bits are used by 8051.The two unused bits are user definable bits. In
Stack Pointer Register (SP): It is an 8-bit register which stores the address of the stack top. i.e the Stack
the 6-bits four of them are conditional flags .They are Carry –CY, Auxiliary Carry-AC, Parity-P, and
Pointer is used to indicate where the next value to be removed from the stack should be taken from.
Overflow-OV .These flag bits indicate some conditions that resulted after an instruction was executed.
When a value is pushed onto the stack, the 8051 first increments the value of SP and then stores the value
at the resulting memory location. Similarly when a value is popped off the stack, the 8051 returns the
value from the memory location indicated by SP, and then decrements the value of SP. Since the SP is
only 8-bit wide it is incremented or decremented by two. SP is modified directly by the 8051 by six
instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an
interrupt is triggered. CY PSW.7 Carry Flag
STACK in 8051 Microcontrolle r: The stack is a part of RAM used by the CPU to store information AC PSW.6 Auxiliary Carry Flag
temporarily. This information may be either data or an address .The CPU needs this storage area as there
FO PSW.5 Flag 0 available for general purpose .
are only limited number of registers. The register used to access the stack is called the Stack pointer
which is an 8-bit register. So, it can take values of 00 to FF H. When the 8051 is powered up, the SP RS1 PSW.4 Register Bank select bit 1
register contains the value 07.i.e the RAM location value 08 is the first location being used for the stack RS0 PSW.3 Register bank select bit 0
by the 8051 controller OV PSW.2 Overflow flag
There are two important instructions to handle this stack. One is the PUSH and the other is the
--- PSW.1 User definable flag
POP. The loading of data from CPU registers to the stack is done by PUSH and the loading of the
contents of the stack back into a CPU register is done by POP. P PSW.0 Parity flag .set/cleared by hardware.
EX: MOV R6, #35 H The bits PSW3 and PSW4 are denoted as RS0 and RS1 and these bits are used to select the bank registers
MOV R1, #21 H of the RAM location. The meaning of various bits of PSW register is shown below.
PUSH 6 The selection of the register Banks and their addresses are given below.
PUSH 1
RS1 RS0 Register Bank Address
In the above instructions the contents of the Registers R6 and R1 are moved to stack and they occupy
0 0 0 00H-07H
the 08 and 09 locations of the stack. Now the contents of the SP are incremented by two and it is 0A
Similarly POP 3 instruction pops the contents of stack into R3 register. Now the contents of the SP is 0 1 1 08H-0FH
decremented by 1 1 0 2 10H-17H
In 8051 the RAM locations 08 to 1F (24 bytes) can be used for the Stack. In any program if we need more
1 1 3 18H-1FH
than 24 bytes of stack, we can change the SP point to RAM locations 30-7F H. This can be done with the
instruction MOV SP, # XX.
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 (iii) 80 bytes of general purpose area (Scratch pad memory) as shown in the diagram below.
This area is also utilized by the microcontroller as a storage area for the operating stack.
Memory Organization:
The 8051 microcontroller has 128 bytes of Internal RAM and 4kB of on chip ROM .The RAM is
also known as Data memory and the ROM is known as program memory. The program memory is also
known as Code memory .This Code memory holds the actual 8051 program that is to be executed. In
8051 this memory is limited to 64K .Code memory may be found on-chip, as ROM or EPROM. It may
also be stored completely off-chip in an external ROM or, more commonly, an external EPROM. The
8051 has only 128 bytes of Internal RAM but it supports 64kB of external RAM. As the name suggests,
external RAM is any random access memory which is off-chip. Since the memory is off-chip it is not as
flexible in terms of accessing, and is also slower. For example, to increment an Internal RAM location by The 32 bytes of RAM from address 00 H to 1FH are used as working registers organized as four banks of
1, it requires only 1 instruction and 1 instruction cycle b ut to increment a 1-byte value stored in External eight registers each. The registers are named as R0-R7 .Each register can be addressed by its name or by
RAM requires 4 instructions and 7 instruction cycles. So, here the external memory is 7 times slower. its RAM address.
Inte rnal RAM OF 8051: For EX: MOV A, R7 or MOV R7, #05H
This Internal RAM is found on-chip on the 8051 .So it is the fastest RAM available, and it is also the
most flexible in terms of reading, writing, and modifying it’s contents. Internal RAM is volatile, so when Inte rnal ROM (On –chip ROM): The 8051 microcontroller has 4kB of on chip ROM but it can be
the 8051 is reset this memory is cleared. The 128 bytes of internal RAM is organized as below. extended up to 64kB. This ROM is also called program memory or code memory. The CODE segment is
(i) Four register banks (Bank0, Bank1, Bank2 and Bank3) each of 8-bits (total 32 bytes). The accessed using the program counter (PC) for opcode fetches and by DPTR for data. The external ROM is
default bank register is Bank0. The remaining Banks are selected with the help of RS0 accessed when the EA(active low) pin is connected to ground or the contents of program counter exceeds
and RS1 bits of PSW Register. 0FFFH.When the Internal ROM address is exceeded the 8051 automatically fetches the code bytes from
(ii) 16 bytes of bit addressable area and the external program memory.
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 11 IE* Interrupt Enable control 0A8
12 TMOD Tmier mode register 89
13 TCON* Timer control register 88
14 TH0 Timer 0 Higher byte 8C
15 TL0 Timer 0 Lower byte 8A
16 TH1 Timer 1Higher byte 8D
17 TL1 Timer 1 lower byte 8B
18 SCON* Serial control register 98
19 SBUF Serial buffer register 99
SPECIAL FUNCTION REGISTERS (SFRs): In 8051 microcontroller there certain registers which
uses the RAM addresses from 80h to FFh and they are meant for certain specific operations. These 20 PCON Power control register 87
registers are called Special function registers (SFRs). Some of these registers are bit addressable also.
The * indicates the bit addressable SFRs
The list of SFRs and their functional names are given below. In these SFRs some of them are related to Table: SFRs of 8051 Microcontroller
I/O ports (P0, P1, P2 and P3) and some of them are meant for control operations (TCON, SCON,
PCON...) and remaining are the auxiliary SFRs, in the sense that they don't directly configure the 8051. PARALLEL I /O PORTS :
S.No Symbol Name of SFR Address (Hex) The 8051 microcontroller has four parallel I/O ports, each of 8-bits .So; it provides the user 32 I/O lines
for connecting the microcontroller to the peripherals. The four ports are P0 (Port 0), P1 (Port1), P2 (Port
1 ACC* Accumulator 0E0
2) and P3 (Port3). Upon reset all the ports are output ports. In order to make them input, all the ports must
2 B* B-Register 0F0
be set i.e a high bit must be sent to all the port pins. This is normally done by the instruction “SETB”.
3 PSW* Program Status word register 0DO Ex: MOV A, #0FFH ; A = FF
4 SP Stack Pointer Register 81 MOV P0, A ; make P0 an input port
PORT 0:
DPL Data pointer low byte 82
5 DPTR Port 0 is an 8-bit I/O port with dual purpose. If external memory is used, these port pins are used for the
DPH Data pointer high byte 83
lower address byte address/data (AD0 -AD7 ), otherwise all bits of the port are either input or output.
6 P0* Port 0 80 Unlike other ports, Port 0 is not provided with pull- up resistors internally, so for PORT0 pull- up resistors
P1* Port 1 90 of nearly 10k are to be connected externally as shown in the fig.2.
Dual role of port 0: Port 0 can also be used as address/data bus (AD0-AD7), allowing it to be used for
8 P2* Port 2 0A
both address and data. When connecting the 8051 to an external memory, port 0 provides both address
9 P3* Port 3 0B and data. The 8051 multiplexes address and data through port 0 to save the pins. ALE indicates whether
10 IP* Interrupt Priority control 0B8 P0 has address or data. When ALE = 0, it provides data D0-D7, and when ALE =1 it provides address
and data with the help of a 74LS373 latch.
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 PORT 3: Port3 is also an 8-bit parallel port with dual function. (Pins 10 to 17). The port pins can be used
for I/O operations as well as for control operations. The details of these additional operations are given
below in the table. Port 3 also do not need any external pull- up resistors as they are provided internally
similar to the case of Port2 & Port 1. Upon reset port 3 is configured as an output port. If the port is to be
used as input port, all the port bits must be made high by sending FF to the port. For ex,
MOV A, #0FFH ; A= FF hex
MOV P3 , A ; make P3 an input port by writing all 1’s to it
Alte rnate Functions of Port 3: P3.0 and P3.1 are used for the RxD (Receive Data) and TxD (Transmit
Data) serial communications signals. Bits P3.2 and P3.3 are meant for external interrupts. Bits P3.4 and
P3.5 are used for Timers 0 and 1 and P3.6 and P3.7 are used to provide the write and read signals of
external memories connected in 8031 based systems
Port 1: Port 1 occupies a total of 8 pins (pins 1 through 8). It has no dual application and acts only as
input or output port. In contrast to port 0, this port does not need any pull- up resistors since pull- up S. No Port 3 bit Pin No Function
resistors connected internally. Upon reset, Port 1 is configured as an output port. To configure it as an 1 P3.0 10 RxD
2 P3.1 11 TxD
input port, port bits must be set i.e a high bit must be sent to all the port pins. This is normally done by the
instruction “SETB”. For 3 P3.2 12
Ex: MOV A, #0FFH ; A=FF HEX 4 P3.3 13
MOV P1, A ; make P1 an input port by writing 1’s to all of its pins 5 P3.4 14 T0
6 P3.5 15 T1
Port 2: Port 2 is also an eight bit parallel port. (Pins 21- 28). It can be used as input or output port. As this 7 P3.6 16
port is provided with internal pull- up resistors it does not need any external pull- up resistors. Upon reset, 8 P3.7 17
Port 2 is configured as an output port. If the port is to be used as input port, all the port bits must be made
high by sending FF to the port. For ex, Table: PORT 3 alternate functions
MOV A, #0FFH ; A=FF hex Interrupt Structure : An interrupt is an external or internal event that disturbs the microcontroller to
MOV P2 , A ; make P2 an input port by writing all 1’s to it inform it that a device needs its service. The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler. Upon receiving the interrupt signal the
Dual role of port 2: Port2 lines are also associated with the higher order address lines A8-A15. In
Microcontroller, finish current instruction and saves the PC on stack. Jumps to a fixed location in
systems based on the 8751, 8951, and DS5000, Port2 is used as simple I/O port. But, in 8031-based
memory depending on type of interruptStarts to execute the interrupt service routine until RETI (return
systems, port 2 is used along with P0 to provide the 16-bit address for the external memory. Since an
from interrupt) upon executing the RETI the microcontroller returns to the place where it was interrupted.
8031 is capable of accessing 64K bytes of external memory, it needs a path for the 16 bits of the address.
Get pop PC from stack
While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide bits A8-A15 of the address. In
other words, when 8031 is connected to external memory, Port 2 is used for the upper 8 bits of the 16 bit
address, and it cannot be used for I/O operations.
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The 8051 microcontroller has FIVE interrupts in addition to Reset. They are Inte rrupt Priority Register:
 Timer 0 overflow Interrupt Upon reset the interrupts have the following priority. (Top to down). The interrupt with the highest
PRIORITY gets serviced first.
 Timer 1 overflow Interrupt
1. External interrupt 0 (INT0)
 External Interrupt 0(INT0)
2. Timer interrupt0 (TF0)
 External Interrupt 1(INT1)
3. External interrupt 1 (INT1)
 Serial Port events (buffer full, buffer empty, etc) Interrupt
4. Timer interrupt1 (TF1)
Each interrupt has a specific place in code memory where program execution (interrupt service routine)
begins. 5. Serial communication (RI+TI)
 External Interrupt 0: 0003 H Priority can also be set to “high” or “low” by 8-bit IP register.- Interrupt priority register
 Timer 0 overflow: 000B H
 External Interrupt 1: 0013 H
 Timer 1 overflow: 001B H
IP.7: reserved
 Serial Interrupt : 0023 H
IP.6: reserved
Upon reset all Interrupts are disabled & do not respond to the Microcontroller. These interrupts must be
IP.5: Timer 2 interrupt priority bit (8052 only)
enabled by software in order for the Microcontroller to respond to them. This is done by an 8-bit register
IP.4: Serial port interrupt priority bit
called Interrupt Enable Register (IE).
IP.3: Timer 1 interrupt priority bit
Inte rrupt Enable Register:
IP.2: External interrupt 1 priority bit
IP.1: Timer 0 interrupt priority bit
IP.0: External interrupt 0 priority bit
 EA : Global enable/disable. To enable the interrupts this bit must be set high. TIMERS in 8051 Microcontrollers :
 --- : Undefined-reserved for future use.
The 8051 microcontroller has two 16-bit timers Timer 0 (T0) and Timer 1(T1) which can be used
 ET2: Enable /disable Timer 2 overflow interrupt. either to generate accurate time delays or as event counters. These timers are accessed as two 8-bit
 ES : Enable/disable Serial port interrupts. registers TLO, THO & TL1, TH1 because the 8051 microcontroller has 8-bit architecture.
 ET1: Enable /disable Timer 1 overflow interrupt. TIMER 0 : The Timer 0 is a 16-bit register and can be treated as two 8-bit registers (TL0 & TH0) and
 EX1: Enable/disable External interrupt1. these registers can be accessed similar to any other registers like A,B or R1,R2,R3 etc…
 ET0: Enable /disable Timer 0 overflow interrupt. Ex: The instruction MOV TL0,#07 moves the value 07 into lower byte of Timer0.
 EX0 : Enable/disable External interrupt0
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Similarly MOV R5, TH0 saves the contents of TH0 in the R5 register. S. No M0 M1 Mode Ope ration
13-bit Timer mode
1 0 0 0 8-bit Timer/counter. THx with TLx as 5-bit
prescalar
16-bit Timer mode.16-bit timer /counter
2 0 1 1
without pre-scalar
8-bit auto reload. THx contains a value that
3 1 0 2 is to be loaded into TLx each time it
TIMER 1 : The Timer 1 is also a 16-bit register and can be treated as two 8-bit registers (TL1 & TH1) overflows
and these registers can be accessed similar to any other registers like A,B or R1,R2,R3 etc… 4 1 1 3 Split timer mode
Ex: The instruction MOV TL1,#05 moves the value 05 into lower byte of Timer1.
Similarly MOV R0, TH1 saves the contents of TH1 in the R0 register
TMOD Register:
The various operating modes of both the timers T0 and T1 are set by an 8-bit register called
TMOD register. In this TMOD register the lower 4-bits are meant for Timer 0 and the higher 4-bits are
meant for Timer1.
GATE: This bit is used to start or stop the timers by hardware .When GATE= 1, the timers can be started
/ stopped by the external sources. When GATE= 0, the timers can be started or stopped by software
instructions like SETB TR0 or SETB TR1
Let us understand the working of Time r Mode 1
C/T (clock/Timer): This bit decides whether the timer is used as delay generator or event counter. When
• For this , let us consider timer 0 as an example.
C/T = 0, the Timer is used as delay generator and if C/T=1 the timer is used as an event counter. The
clock source for the time delay is the crystal frequency of 8051. • 16-bit timer (TH0 and TL0)
M1, M0 (Mode): These two bits are the timer mode bits. The timers of the 8051 can be configured in • TH0-TL0 is incremented continuously when TR0 is set to 1. And the 8051 stops to increment
three modes. Mode0, Mode1 and Mode2. The selection and operation of the modes is shown below. TH0-TL0 when TR0 is cleared.
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 • The timer works with the internal system clock. In other words, the timer counts up each machine 8. Clear TR0 to stop the process.
cycle.
– CLR TR0
• When the timer (TH0-TL0) reaches its maximum of FFFFH, it rolls over to 0000, and TF0 is
9. Clear the TF flag for the next round.
raised.
– CLR TF0
• Programmer should check TF0 and stop the timer 0.
Steps of Mode 1 TCON Register:
1. Choose mode 1 timer 0
– MOV TMOD,#01H
2. Set the original value to TH0 and TL0.
Timer control register TMOD is a 8-bit register which is bit addressable and in which Upper nibble is
– MOV TH0,#FFH for timer/counter, lower nibble is for interrupts.
– MOV TL0,#FCH • TR (Timer run control bit)
3. You better to clear the TF: TF0=0. – TR0 for Timer/counter 0; TR1 for Timer/counter 1.
– CLR TF0 – TR is set by programmer to turn timer/counter on/off.
4. Start the timer. • TR=0 : off (stop)
– SETB TR0 • TR=1 : on (start)
5. The 8051 starts to count up by incrementing the TH0-TL0. • TF (timer flag, control flag)
– TH0-TL0= FFFCH,FFFDH,FFFEH,FFFFH,0000H – TF0 for timer/counter 0; TF1 for time r/counte r 1.
– TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from FFFFH, the
TF is set to 1.
• TF=0 : not reach
• TF=1: reach
• If we enable interrupt, TF=1 will trigger ISR.
Simple applications using Ports &Time rs
• Using a port, by a simple program you can generate a Square wave of any duty cycle.
6. When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set TF0=1. HERE: SETB P1.0 (Make bit of Port 0 High)
– TH0-TL0= FFFE H, FFFF H, 0000 H (Now TF0=1) LCALL DELAY
7. Keep monitoring the time r flag (TF) to see if it is raised. CLR P1.0
– AGAIN: JNB TF0, AGAIN LCALL DELAY
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 SJMP HERE ; Keep doing it
Here same delay is used for both High & low
Serial data transmission
After the Start Bit, the individual bits of the word of data are sent .Here each bit in the word is
transmitted for exactly the same amount of time as all of the other bits. When the entire data word has
been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity bit may be used
8051-SERIAL COMMUNICATION: by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter. If
the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be corrupted
Basics of Serial communication and will report a Framing Error.
Data transfer between two electronic devices (Ex Between a computer and microcontroller or a Baud rate is a measurement of transmission speed in asynchronous communication , it represents the
peripheral device) is generally done in two ways
number of bits/sec that are actually being sent over the serial link. The Baud count includes the overhead
(i).Serial data Transfer and bits Start, Stop and Parity that are generated by the sending UART and removed by the receiving UART.
(ii).Parallel data Transfer In the Synchronous data transfer method the receiver knows when to “read” the next bit coming from
the sender. This is achieved by sharing a clock between sender and receiver. In most forms of serial
Serial communication uses only one or two data lines to transfer data and is generally used for
Synchronous communication, if there is no data available at a given time to transmit, a fill character will
long distance communication. In serial communication the data is sent as one bit at a time in a timed
be sent instead so that data is always being transmitted. Synchronous communication is usually more
sequence on a single wire. Serial Communication takes place in two methods, Asynchronous data
efficient because only data bits are transmitted between sender and receiver, however it will be more
Transfer and Synchronous data Transfer.
costly because extra wiring and control circuits are required to share a clock signal between the sender
and receiver.
Devices that use serial cables for their communication are split into two cate gories.
1. DTE (Data Terminal Equipment). Examples of DTE are computers, printers & terminals.
2. DCE (Data Communication Equipment). Example of DCE is modems.
Parallel Data Transfer:
Parallel communication uses multiple wires (bus) running parallel to each other, and can transmit data
Asynchronous data transfer allows data to be transmitted without the sender having to send a clock
on all the wires simultaneously. i.e all the bits of the byte are transmitted at a time. So, speed of the
signal to the receiver. Instead, special bits will be added to each word in order to synchronize the sending
parallel data transfer is extremely high compared to serial data transfer. An 8-bit parallel data transfer is
and receiving of the data. When a word is given to the UART for Asynchronous transmissions, a bit
8-times faster than serial data transfer. Hence with in the computer all data transfer is mainly based on
called the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used
Parallel data transfer. But only limitation is due to the high cost ,this method is limited to only short
to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into
distance communications.
synchronization with the clock in the transmitter.
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Differences between Serial data transfer and Parallel data transfer SCON (Serial Control) Register:
S.No Serial Communication Parallel Communication
1 Data is transmitted bit after the bit in a Data is transmitted simultaneously
single line through group of lines(Bus)
SM0 SCON.7 Serial port mode selector
2 Data congestion takes place No, Data congestion
SM1 SCON.6 Serial port mode selector
3 Low speed transmission High speed transmission
4 Implementation of serial links is not an Parallel data links are easily Used for multiprocessor mode communication
SM2 SCON.5
easy task. implemented in hardware (not applicable for 8051)
5. In terms of transmission channel costs It is more expensive
Receive enable. Set or cleared by making this bit
such as data bus cable length, data bus REN SCON.4
buffers, interface connectors, it is less either 1 or 0 foe enable /disable reception.
expensive
TB8 SCON.3 9th data bit transmitted in modes 2 and 3
6 No , crosstalk problem Crosstalk creates interference between
the parallel lines. 9th data bit received in modes 2 and 3.it is not
7 No effect of inter symbol interference and Parallel ports suffer extremely from RB8 SCON.2 used in mode 0 & mode 1.If SM2 = 0 RB8 is the
noise inter-symbol interference (ISI) and stop bit .
noise, and therefore the data can be
corrupted over long distances. TI SCON.1 Transmit interrupt flag
8 The bandwidth of serial wires is much The bandwidth of parallel wires is much RI SCON.0 Receive interrupt flag.
higher. lower.
9 Serial interface is more flexible to Parallel data transfer mechanism rely on
 SM0, SM1: These two bits of SCON register determine the framing of data by specifying the
upgrade , without changing the hardware hardware resources and hence not
number of bits per character and start bit and stop bits. There are 4 serial modes.
flexible to upgrade.
10 Serial communication work effectively Parallel buses are hard to run at high SM0 SM1
even at high frequencies. frequencies. 0 0 : Serial Mode 0
0 1 : Serial Mode 1, 8 bit data, 1 stop bit, 1 start bit
SERIAL COMMUNICATION IN 8051 MICROCONTROLLER 1 0 : Serial Mode 2
The 8051 has two pins for transferring and receiving data by serial communication. These two pins are 1 1 : Serial Mode 3
part of the Port3(P3.0 &P3.1) .These pins are TTL compatible and hence they require a line driver to
make them RS232 compatible .Max232 chip is one such line driver in use. Serial communication is
 REN (Receive Enable) also referred as SCON.4. When it is high,it allows the 8051 to receive data
controlled by an 8-bit register called SCON register,it is a bit addressable register.
on the RxD pin. So to receive and transfer data REN must be set to 1.When REN=0,the receiver is
disabled. This is achieved as below
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 SETB SCON.4
& CLR SCON.4
 TI (Transmit interrupt) is the D1 bit of SCON register. When 8051 finishes the transfer of 8-bit
character, it raises the TI flag to indicate that it is ready to transfer another byte. The TI bit is
raised at the beginning of the stop bit.
RI (Receive interrupt) is the D0 bit of the SCON register. When the 8051 receives data serially ,via RxD,
it gets rid of the start and stop bits and places the byte in the SBUF register. Then it raises the RI flag bit
to indicate that a byte has been received and should be picked up before it is lost. RI is raised halfway
through the stop bit.
Communication through RS232
A personal computer has a serial port known as communication port or COM Port used to connect a
ADDRESSING MODES OF 8051:
modem for example or any other device, there could be more then one COM Port in a PC. Serial ports are
controlled by a special chip called UART (Universal Asynchronous Receiver Transmitter). The way in which the data operands are accessed by different instructions is known as the addressing
modes. There are various methods of denoting the data operands in the instruction. The 8051
RS 232 standard describes a communication method where information is sent bit by bit on a physical microcontroller supports mainly 5 addressing modes. They are
channel. The RS stands for Recommended Standard. The information must be broken up in data
words. The length of a data word is variable. 1. Immediate addressing mode
2. Direct Addressing mode
It is one of the popularly known interface standard for serial communication between DTE &
DCE. This RS-232-C is the commonly used standard when data are transmitted as voltage .This standard 3. Register addressing mode
was first developed by Electronic industries association(EIA). For the RS-232C, a 25 pin D type 4. Register Indirect addressing mode
connector is used . DB-25P male and DB-25S female. RS-232 standard was first introduced in 1960’s by 5. Indexed addressing mode
Telecommunications Industry Association(TIA).
Immediate addressing mode : The addressing mode in which the data operand is a constant and it is a
Inte rfacing the 8051 Microcontroller to PC: part of the instruction itself is known as Immediate addressing mode. Normally the data must be preceded
by a # sign. This addressing mode can be used to transfer the data into any of the registers including
As the RS-232 standard is developed earlier to TTL devices ,a USART such as 8251 is not
DPTR.
directly compatible with these signal levels .Because of this ,voltage transistors called line drivers and
line receivers are used to interface TTL logic with RS-232 signals . The line driver MC 1488 is used to Ex: MOV A , # 27 H : The data (constant) 27 is moved to the accumulator register
convert RS-232 to TTL.The microcontroller is connected to the PC using the DB9 connector. ADD R1 ,#45 H : Add the constant 45 to the contents of the accumulator
The TxD and Rx D pins are connected to the TI in and RI in pins of the MAX 232 IC and the TI MOV DPTR ,# 8245H :Move the data 8245 into the data pointer register.
out and RI in pins of the MAX IC are connected to the RxD and TxD pins of the DB9 connector as shown MOV P1,#21 H
in the interface diagram.
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 8051 Instruction Set:
Direct addressing mode: The addressing mode in which the data operand is in the RAM location (00 -
7FH) and the address of the data operand is given in the instruction is known as Direct addressing mode. • Assembly language is machine dependant.
The direct addressing mode uses the lower 128 bytes of Internal RAM and the SFRs • Each family of microprocessors or microncontrollers has its own instruction set.
MOV R1, 42H : Move the contents of RAM location 42 into R1 register • Each instruction has an 8 bit op-code with an associated mnemonic.
• Some instructions have one or two additional bytes for operand (data or addresses).
MOV 49H,A : Move the contents of the accumulator into the RAM location 49.
• The 8051 has 255 instructions
ADD A, 56H : Add the contents of the RAM location 56 to the accumulator
Every 8-bit opcode from 00 to FF is used except for A5.
Register addressing mode :The addressing mode in which the data operand to be manipulated lies in
• The instructions are grouped into 5 groups
one of the registers is known as register addressing mode.
 Arithmetic
MOV A,R0 : Move the contents of the register R0 to the accumulator
 Logic
ADD A,R6 :Add the contents of R6 register to the accumulator  Data Transfer
MOV P1, R2 : Move the contents of the R2 register into port 1  Boolean
 Branching
MOV R5, R2 : This is invalid .The data transfer between the registers is not allowed.
Arithmetic Instructions:
Register Indirect addressing mode :The addressing mode in which a register is used as a pointer to the
data memory block is known as Register indirect addressing mode. • ADD
– 8-bit addition between the accumulator (A) and a second operand.
MOV A,@ R0 :Move the contents of RAM location whose address is in R0 into A (accumulator)
• The result is always in the accumulator.
MOV @ R1 , B : Move the contents of B into RAM location whose address is held by R1
• The CY flag is set/reset appropriately.
When R0 and R1 are used as pointers, they must be preceded by @ sign
• ADDC
One of the advantages of register indirect addressing mode is that it makes accessing the data more – 8-bit addition between the accumulator, a second operand and the previous value of the
dynamic than static as in the case of direct addressing mode. CY flag.
• Useful for 16-bit addition in two steps.
Indexed addressing mode : This addressing mode is used in accessing the data elements of lookup table
entries located in program ROM space of 8051. • The CY flag is set/reset appropriately.
Example – 16-bit Addition
Ex : MOVC A, @ A+DPTR
ADD 1E44H to 56CAH
The 16-bit register DPTR and register A are used to form the address of the data element stored in on-
chip ROM. Here C denotes code .In this instruction the contents of A are added to the 16-bit DPTR CLR C ; Clear the CY flag
register to form the 16-bit address of the data operand.
MOV A, #44H ; The lower 8-bits of the 1st number
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 ADD A, #CAH ; The lower 8-bits of the 2nd number • DEC
MOV R1, A ; The result 0EH will be in R1. CY = 1. – Decrement the operand by one.
MOV A, #1EH ; The upper 8-bits of the 1st number • The operand can be a register, a direct address, an indirect address.
ADDC A, #56H ; The upper 8-bits of the 2nd number • MUL AB / DIV AB
MOV R2, A ; The result of the addition is 75H – Multiply A by B and place result in A:B.
– Divide A by B and place result in A:B.
The overall result: 750EH will be in R2:R1. CY = 0.
• DAA Logical Operations:
– Decimal adjust the accumulator.
• ANL / ORL
• Format the accumulator into a proper 2 digit packed BCD number. – Work on byte sized operands or the CY flag.
• ANL A, Rn
• Operates only on the accumulator. • ANL A, direct
• ANL A, @Ri
• Works only after the ADD instruction.
• ANL A, #data
• SUBB • ANL direct, A
• ANL direct, #data
– Subtract with Borrow. • ANL C, bit
• Subtract an operand and the previous value of the borrow (carry) flag from the • ANL C, /bit
• XRL
accumulator.
– Works on bytes only.
– A  A - <operand> - CY. – CPL / CLR
– Complement / Clear.
– The result is always saved in the accumulator. – Work on the accumulator or a bit.
– The CY flag is set/reset appropriately. • CLR P1.2
• RL / RLC / RR / RRC
Example – BCD addition – Rotate the accumulator.
• RL and RR without the carry
ADD 34 to 49 BCD
• RLC and RRC rotate through the carry.
CLR C ; Clear the CY flag • SWAP A
– Swap the upper and lower nibbles of the accumulator.
MOV A, #34H ; Place 1st number in A • No compare instruction.
– Built into conditional branching instructions.
ADD A, #49H ; Add the 2nd number.
; A = 7DH
Data Transfer Instructions:
DAA ; A = 83H
• Data is stored at the source address and moved (copied) to a destination address.
• INC
• The way these addresses are specified are determined by the addressing mode.
– Increment the operand by one.
• There are 28 different instructions for data transfer, which can be categorized into three types:
• The operand can be a register, a direct address, an indirect address, the data pointer. – MOV <dest>, <src>
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 – Push <source> or Pop <dest> • POP 40H
– XCH <dest>,<src> • XCH
• MOV – Exchange accumulator and a byte variable
– 8-bit data transfer for internal RAM and the SFR. • XCH A, Rn
• MOV A, Rn • XCH A, direct
• MOV A, direct • XCH A, @Ri
• MOV A, @Ri • XCHD
• MOV A, #data – Exchange lower digit of accumulator with the lower digit of the memory location
• MOV Rn, A specified.
• MOV Rn, direct XCHD A, @Ri
• MOV Rn, #data • The lower 4-bits of the accumulator are exchanged with the lower 4-bits of the
• MOV direct, A internal memory location identified indirectly by the index register.
• MOV direct, Rn • The upper 4-bits of each are not modified.
• MOV direct, direct
• MOV direct, @Ri Boolean Operations:
• MOV direct, #data
• This group of instructions is associated with the single-bit operations of the 8051.
• MOV @Ri, A
• This group allows manipulating the individual bits of bit addressable registers and memory
• MOV @Ri, direct
locations as well as the CY flag.
• MOVC
– The P, OV, and AC flags cannot be directly altered.
– Move Code Byte
• This group includes:
• Load the accumulator with a byte from program memory.
– Set, clear, and, or complement, move.
• Must use indexed addressing
– Conditional jumps.
• MOVC A, @A+DPTR
• CLR
• MOVC A, @A+PC
– Clear a bit or the CY flag.
• MOVX
• CLR P1.1
– Data transfer between the accumulator and a byte from external data memory.
• CLR C
• MOVX A, @Ri
• SETB
• MOVX A, @DPTR
– Set a bit or the CY flag.
• MOVX @Ri, A
• SETB A.2
• MOVX @DPTR, A
• SETB C
• PUSH / POP
• CPL
– Push and Pop a data byte onto the stack.
– Complement a bit or the CY flag.
– The data byte is identified by a direct address from the internal RAM locations.
• CPL 40H ; Complement bit 40 of the bit addressable memory
• PUSH DPL
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 • ORL / ANL • The 11-bit address is substituted for the lower 11- bits of the PC to calculate the
– OR / AND a bit with the CY flag. 16-bit address of the target.
• ORL C, 20H ; OR bit 20 of bit addressable memory with the CY • The location referenced must be within the 2K Byte memory page
flag containing the AJMP instruction.
• ANL C, /34H ; AND complement of bit 34 of bit addressable – Indirect Jump – JMP
memory with the CY flag. JMP @A + DPTR
• MOV • The 8051 provides 2 forms for the CALL instruction:
– Data transfer between a bit and the CY flag. – Absolute Call – ACALL
• MOV C, 3FH ; Copy the CY flag to bit 3F of the bit addressable • Uses an 11-bit address similar to AJMP
memory. • The subroutine must be within the same 2K page.
• MOV P1.2, C ; Copy the CY flag to bit 2 of P1. – Long Call – LCALL
• JC / JNC • Uses a 16-bit address similar to LJMP
• Jump to a relative address if CY is set / cleared. • The subroutine can be anywhere.
• JB / JNB – Both forms push the 16-bit address of the next instruction on the stack and update the stack
• Jump to a relative address if a bit is set / cleared. pointer.
• JB ACC.2, <label> • The 8051 provides 2 forms for the return instruction:
• JBC – Return from subroutine – RET
• Jump to a relative address if a bit is set and clear the bit. • Pop the return address from the stack and continue execution there.
– Return from ISV – RETI
Branching Instructions: • Pop the return address from the stack.
• The 8051 provides four different types of unconditional jump instructions: • Restore the interrupt logic to accept additional interrupts at the same priority level
– Short Jump – SJMP as the one just processed.
• Uses an 8-bit signed offset relative to the 1st byte of the next instruction. • Continue execution at the address retrieved from the stack.
– Long Jump – LJMP • The PSW is not automatically restored.
• Uses a 16-bit address. • The 8051 supports 5 different conditional jump instructions.
• 3 byte instruction capable of referencing any location in the entire 64K of program – ALL conditional jump instructions use an 8-bit signed offset.
memory. – Jump on Zero – JZ / JNZ
– Absolute Jump – AJMP • Jump if the A == 0 / A != 0
• Uses an 11-bit address. • The check is done at the time of the instruction execution.
• 2 byte instruction – Jump on Carry – JC / JNC
• The upper 3-bits of the address combine with the 5-bit opcode to form the • Jump if the C flag is set / cleared.
1st byte and the lower 8-bits of the address form the 2nd byte. – Jump on Bit – JB / JNB
• Jump if the specified bit is set / cleared.
• Any addressable bit can be specified.
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 – Jump if the Bit is set then Clear the bit – JBC
Seven segment Interfacing
• Jump if the specified bit is set.
• Then clear the bit.
• Compare and Jump if Not Equal – CJNE
– Compare the magnitude of the two operands and jump if they are not equal.
• The values are considered to be unsigned.
• The Carry flag is set / cleared appropriately.
• CJNE A, direct, rel
• CJNE A, #data, rel
• CJNE Rn, #data, rel
• CJNE @Ri, #data, rel
• Decrement and Jump if Not Zero – DJNZ
– Decrement the first operand by 1 and jump to the location identified by the second operand
if the resulting value is not zero.
• DJNZ Rn, rel
• DJNZ direct, rel Traffic light controller
• No Operation
– NOP
Applications of Microcontrollers
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Interfacing Keyboard/ Displays: Keyboard is organized in a matrix of rows and columns as shown in the figure. The microcontroller
accesses both rows and columns through the port.
The key board here we are interfacing is a matrix keyboard. This key board is designed with a
particular rows and columns. These rows and columns are connected to the microcontroller through its 1. The 8051 has 4 I/O ports P0 to P3 each with 8 I/O pins, P0.0 to P0.7, P1.0 to P1.7, P2.0 to P2.7,
ports of the micro controller 8051. We normally use 8*8 matrix key board. So only two ports of 8051 and P3.0 to P3.7. The one of the port P1 (it understood that P1 means P1.0 to P1.7) as an I/P port
can be easily connected to the rows and columns of the key board.
for microcontroller 8051, port P0 as an O/P port of microcontroller 8051 and port P2 is used for
Whenever a key is pressed, a row and a column gets shorted through that pressed key and all the displaying the number of pressed key.
other keys are left open. When a key is pressed only a bit in the port goes high. Which indicates
microcontroller that the key is pressed. By this high on the bit key in the corresponding column is 2. Make all rows of port P0 high so that it gives high signal when key is pressed.
identified. 3. See if any key is pressed by scanning the port P1 by checking all columns for non zero
Once we are sure that one of key in the key board is pressed next our aim is to identify that key. To condition.
do this we firstly check for particular row and then we check the corresponding column the key board. 4. If any key is pressed, to identify which key is pressed make one row high at a time.
To check the row of the pressed key in the keyboard, one of the row is made high by making one of 5. Initiate a counter to hold the count so that each key is counted.
bit in the output port of 8051 high . This is done until the row is found out. Once we get the row next 6. Check port P1 for nonzero condition. If any nonzero number is there in [accumulator], start
out job is to find out the column of the pressed key. The column is detected by contents in the input
ports with the help of a counter. The content of the input port is rotated with carry until the carry bit is column scanning by following step 9.
set. 7. Otherwise make next row high in port P1.
The contents of the counter is then compared and displayed in the display. This display is designed 8. Add a count of 08h to the counter to move to the next row by repeating steps from step 6.
using a seven segment display and a BCD to seven segment decoder IC 7447. 9. If any key pressed is found, the [accumulator] content is rotated right through the carry until
The BCD equivalent number of counter is sent through output part of 8051 displays the number of carry bit sets, while doing this increment the count in the counter till carry is found.
pressed key. 10. Move the content in the counter to display in data field or to memory location
11. To repeat the procedures go to step 2.
Interfacing seven segment display to 8051:
7 segment LED display is very popular and it can display digits from 0 to 9 and quite a few
Fig: Interfacing Key Board to 8051.
characters like A, b, C, ., H, E, e, F, n, o,t,u,y, etc. Knowledge about how to interface a seven segment
The programming algorithm, program and the circuit diagram is as follows. Here program is explained display to a micro controller is very essential in designing embedded systems. A seven segment display
with comments. consists of seven LEDs arranged in the form of a squarish „8‟ slightly inclined to the right and a single
LED as the dot character. Different characters can be displayed by selectively glowing the required LED
segments. Seven segment displays are of two types, common cathode and common anode. In common
cathode type , the cathode of all LEDs are tied together to a single terminal which is usually labeled as
„com„ and the anode of all LEDs are left alone as individual pins labeled as a, b, c, d, e, f, g & h (or
dot) . In common anode type, the anode of all LEDs are tied together as a single terminal and cathodes
are left alone as individual pins. The pin out scheme and picture of a typical 7 segment LED display is
shown in the image below.
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 Interfacing seven segment display to 8051
Digit drive pattern.
Digit drive pattern of a seven segment LED display is simply the different logic combinations of its
terminals „a‟ to „h„ in order to display different digits and characters. The common digit drive patterns
(0 to 9) of a seven segment display are shown in the table below.
Digit a b c d e f g
0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0 The circuit diagram shown above is of an AT89S51 microcontroller based 0 to 9 counter which
has a 7 segment LED display interfaced to it in order to display the count. This simple circuit illustrates
2 1 1 0 1 1 0 1 two things. How to setup simple 0 to 9 up counter using 8051 and more importantly how to interface a
seven segment LED display to 8051 in order to display a particular result. The common cathode seven
3 1 1 1 1 0 0 1
segment display D1 is connected to the Port 1 of the microcontroller (AT89S51) as shown in the circuit
4 0 1 1 0 0 1 1 diagram. R3 to R10 are current limiting resistors. S3 is the reset switch and R2, C3 forms a de-bouncing
circuitry. C1, C2 and X1 are related to the clock circuit. The software part of the project has to do the
5 1 0 1 1 0 1 1 following tasks.
 Form a 0 to 9 counter with a predetermined delay (around 1/2 second here).
6 1 0 1 1 1 1 1
 Convert the current count into digit drive pattern.
7 1 1 1 0 0 0 0  Put the current digit drive pattern into a port for displaying.
8 1 1 1 1 1 1 1
9 1 1 1 1 0 1 1
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All the above said tasks are accomplished by the program given below. DELAY: MOV R4,#05H // subroutine for delay
Program. WAIT1: MOV R3,#00H
ORG 000H //initial starting address WAIT2: MOV R2,#00H
START: MOV A,#00001001B // initial value of accumulator WAIT3: DJNZ R2,WAIT3
MOV B,A DJNZ R3,WAIT2
MOV R0,#0AH //Register R0 initialized as counter which counts from 10 to 0 DJNZ R4,WAIT1
LABEL: MOV A,B RET
INC A END
MOV B,A
MOVC A,@A+PC // adds the byte in A to the program counters address Multiplexing 7 segment displays to 8051.
MOV P1,A Suppose you need a three digit display connected to the 8051. Each 7 segment display have 8 pins
and so a total amount of 24 pins are to the connected to the microcontroller and there will be only 8 pins
ACALL DELAY // calls the delay of the timer
left with the microcontroller for other input output applications. Also the maximum number of displays
DEC R0 //Counter R0 decremented by 1
that can be connected to the 8051 is limited to 4 because 8051 has only 4 ports. More over three 3
MOV A,R0 // R0 moved to accumulator to check if it is zero in next displays will be ON always and this consumes a considerable amount of power. All these problems
instruction. associated with the straight forward method can be solved by multiplexing.
JZ START //Checks accumulator for zero and jumps to START. Done
In multiplexing all displays are connected in parallel to one port and only one display is allowed to
to check if counting has been finished. turn ON at a time, for a short period. This cycle is repeated for at a fast rate and due to the persistence of
SJMP LABEL vision of human eye, all digits seems to glow. The main advantages of this method are
DB 3FH // digit drive pattern for 0
 Fewer number of port pins are required .
DB 06H // digit drive pattern for 1  Consumes less power.
DB 5BH // digit drive pattern for 2  More number of display units can be interfaced (maximum 24).
DB 4FH // digit drive pattern for 3 The circuit diagram for multiplexing 2 seven segment displays to the 8051 is shown below.
DB 66H // digit drive pattern for 4
DB 6DH // digit drive pattern for 5
DB 7DH // digit drive pattern for 6
DB 07H // digit drive pattern for 7
DB 7FH // digit drive pattern for 8
DB 6FH // digit drive pattern for 9
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 Program:
ORG 000H // initial starting address
MOV P1,#00000000B // clears port 1
MOV R6,#1H // stores "1"
MOV R7,#6H // stores "6"
MOV P3,#00000000B // clears port 3
MOV DPTR,#LABEL1 // loads the address of line 29 to DPTR
MAIN: MOV A,R6 // "1" is moved to accumulator
SETB P3.0 // activates 1st display
ACALL DISPLAY // calls the display sub routine for getting the pattern for "1"
MOV P1,A // moves the pattern for "1" into port 1
ACALL DELAY // calls the 1ms delay
CLR P3.0 // deactivates the 1st display
MOV A,R7 // "2" is moved to accumulator
SETB P3.1 // activates 2nd display
ACALL DISPLAY // calls the display sub routine for getting the pattern for "2"
When assembled and powered on, the circuit will display the number ‟16‟ and let us see how it is MOV P1,A // moves the pattern for "2" into port 1
done. Initially the first display is activated by making P3.0 high and then digit drive pattern for “1” is ACALL DELAY // calls the 1ms delay
loaded to the Port 1. This will make the first display to show “1”. In the mean time P3.1 will be low and CLR P3.1 // deactivates the 2nd display
so do the second display will be OFF. This condition is maintained for around 1ms and then P3.0 is SJMP MAIN // jumps back to main and cycle is repeated
made low. Now both displays will be OFF. Then the second display is activated by making P3.1 high DELAY: MOV R3,#02H
and then the digit drive pattern for “6” is loaded to the port 1. This will make the second display to show DEL1: MOV R2,#0FAH
“6”. In the mean time P3.0 will be low and so the second display will be OFF. This condition is DEL2: DJNZ R2,DEL2
maintained for another 1ms and then port 3.1 is made low. This cycle is repeated and due to the DJNZ R3,DEL1
persistence of vision you will feel it as “16”. RET
DISPLAY: MOVC A,@A+DPTR // adds the byte in A to the address in DPTR and loads A with data
Transistor Q1 drives the first display (D1) and transistor Q2 drives the second display (D2). R11
and R12 are the base current limiting resistors of Q1 and Q2. The purposes of other components are present in the resultant address
explained in the first circuit. RET
LABEL1: DB 3FH
DB 06H
DB 5BH
DB 4FH
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 DB 66H And here we have used three potentiometers connected at pin 26, 27, and 28 of ADC0808.
DB 6DH
A 9 volt battery and a 5 volt voltage regulator namely 7805 are used for powering the circuit.
DB 7DH
DB 07H
DB 7FH
DB 6FH
END
Interfacing A/D and D/A converters:
A/D Converter:-
ADC is the Analog to Digital converter, which converts analog data into digital format; usually
it is used to convert analog voltage into digital format. Analog signal has infinite no of values like a sine
wave or our speech, ADC converts them into particular levels or states, which can be measured in
numbers as a physical quantity. Instead of continuous conversion, ADC converts data periodically,
which is usually known as sampling rate. Telephone modem is one of the examples of ADC, which is
used for internet, it converts analog data into digital data, so that computer can understand, because
computer can only understand Digital data. The major advantage, of using ADC is that, we noise can be
efficiently eliminated from the original signal and digital signal can travel more efficiently than analog
one. That‟s the reason that digital audio is very clear, while listening.
In present time there are lots of microcontrollers in market which has inbuilt ADC with one or
more channels. And by using their ADC register we can interface. When we select 8051
D/A Converter:-
microcontroller family for making any project, in which we need of an ADC conversion, then we The Digital to Analog converter (DAC) is a device, that is widely used for converting digital
use external ADC. Some external ADC chips are 0803,0804,0808,0809 and there are many more. pulses to analog signals. There are two methods of converting digital signals to analog signals. These
Today we are going to interface 8-channel ADC with AT89s52 Microcontroller namely ADC0808/0809. two methods are binary weighted method and R/2R ladder method. In this article we will use the
Circuit of “Interfacing ADC0808 with 8051” is little complex which contains more connecting MC1408 (DAC0808) Digital to Analog Converter. This chip uses R/2R ladder method. This method can
wire for connecting device to each other. In this circuit we have mainly used AT89s52 as 8051 achieve a much higher degree of precision. DACs are judged by its resolution. The resolution is a
microcontroller, ADC0808, Potentiometer and LCD. function of the number of binary inputs. The most common input counts are 8, 10, 12 etc. Number of
data inputs decides the resolution of DAC. So if there are n digital input pin, there are 2 n analog levels.
A 16x2 LCD is connected with 89s52 microcontroller in 4-bit mode. Control pin RS, RW and En So 8 inputs DAC has 256 discrete voltage levels.
are directly connected to pin P2.0, GND and P2.2. And data pin D4-D7 is connected to pins P2.4, P2.5,
The MC1408 DAC (or DAC0808)
P2.6 and P2.7 of 89s52. ADC0808 output pin are directly connected to port P1 of AT89s52. Address
line pins ADDA, ADDB, AADC are connected at P3.0, P3.1, and P3.2. In this chip the digital inputs are converted to current. The output current is known as Iout by connecting
a resistor to the output to convert into voltage. The total current provided by the Iout pin is basically a
ALE (Address latch enable), SC (Start conversion), EOC (End of conversion), OE (Output
function of the binary numbers at the input pins D0 - D7 (D0 is the LSB and D7 is the MSB) of DAC0808
enable) and clock pins are connected at P3.3, P3.4, P3.5, P3.6 and P3.7.
and the reference current Iref.
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The following formula is showing the function of Iout
Angle(in θ ) sinθ Vout (Voltage Magnitude) Values sent to DAC
300 -0.866 0.669 17
330 -0.5 2.5 64
360 0 5 128
The Iref is the input current. This must be provided into the pin 14. Generally 2.0mA is used as Iref
We connect the Iout pin to the resistor to convert the current to voltage. But in real life it may cause
inaccuracy since the input resistance of the load will also affect the output voltage. So practically
Iref current input is isolated by connecting it to an Op-Amp with Rf = 5KΩ as feedback resistor. The
feedback resistor value can be changed as per requirement.
Generating Sine wave using DAC and 8051 Microcontroller
For generating sine wave, at first we need a look-up table to represent the magnitude of the sine value of
angles between 0° to 360°. The sine function varies from -1 to +1. In the table only integer values are
applicable for DAC input. In this example we will consider 30° increments and calculate the values from
degree to DAC input. We are assuming full-scale voltage of 10V for DAC output. We can follow this
formula to get the voltage ranges.
Vout = 5V + (5 ×sinθ)
Let us see the lookup table according to the angle and other parameters for DAC.
Angle(in θ ) sinθ Vout (Voltage Magnitude) Values sent to DAC
0 0 5 128
30 0.5 7.5 192
60 0.866 9.33 238
90 1.0 10 255
120 0.866 9.33 238
150 0.5 7.5 192
180 0 5 128
210 -0.5 2.5 64
240 -0.866 0.669 17
270 -1.0 0 0
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 Evaluotfon of Microprocessor (o) History of .|.Functonal block dfogrorm of go8s
g085 MPt
). INTR INTA RS RST RST TRAP
1st Generaton : Va cc um Tubes C989 -54)
G.5 7-S
2nd Generaticn : Transí stors(1954 - 954) Tnterupt Cortroller Serlal IIo
Cortto
zrd Generation : Tnte qroted cicuits Ci459 - 1971)
4th qeneration : Microproce ssor (ia71 -upto present )
404o bts Accumu lato Temporey Flaq. Instuchan Mutiplexd
4004 or
(8) eisterCB) regikr(8)qtter Ch18)
C9 (8)44 Tegid Ce)z g
Compder micro prbcessor AttnetHc Tnstrucim
Year Ne of lonste MHe AHress Bus Date bus Byts
Logc UntDecocler k
ALUC8) Machine Drgisk Ergista
8065 poser
J476 G500 5MHz bits 64 kB
Supply L qNP -ng
SP (l6)
80B6 1978 29000 5MH 206bs
c o g and control uí t PC Cu)
5lypes ot Bits Microprbessors; Trrement/ Decrere
J1gStet DMA Address Lotcht
)8 bils:- intel 8oo8 2)4 Bits; -1) intel 4040 Cle)
t) întel 808D clock Rea REST RESTOUT
T) intel 4004 Out -dy
DWR AE So 5 I HLDA -(N
lii) intel Bo85 3)16 Bs MP: ) 8o 86 întel Adiress Dalalodtres
y Motoral cebo(M6800) ) fnlel 8088 Buffer I3utter
i) întel 884
4) 32 Bts MP:-) intel 808 B6 i)intel 8028
ii) intel Bo387 ) zilog 28os qeneral porpose Registers; o A1-Ais ADg-AD
iü) intel 8486 o 5) 64 sfts MP: ’ We have 6 general purpos e Addres Bus
i) intel pentiom ) intel OIe 2 registet min'y BicDE,HL are capable ot stoing
) intel pentium pb i) intel (ore Is 6 bitstuo regístex are combined to torn a
vi) real pro ) T4ils. L,I Zu segister pair [èc,DE, HL) -ter (6Bt operatia,
* Archítectcue of 8085 ’ These
t consísts ot system bus,Micoprocessor:
are used to store data
gen tial dumg regísters temporail4
the executioo of pro grar and ore
Traning 2 control,Aithmettc Logic Uoit,purpo Se vegiste, to the user
thauyh instrctions.
acressdk
Ilo control ,interopt special pupose o
Tegistet, Sulal contrller . ’W and z are alss temporary regístet that
Bus: The set ot
called buses oy Systen communicatien
nes are used to .hold he data duing he execut
are called Bs, Tt diides nto 6f sbme fnstrucions ond are hot avai lable t
) Adde ss Bus
2) Data Bus the progqrammers
) Contol Bus
 MP BoRS
3) Tnterupt Control Uoft nstructin regtster Decocder decodu the înstruchon
INTR (Interupt Requs:t s us cd to request -to
operoti on e ard establ sh'he sequence ot even ts -to the
te micro process or to suspect normal -tolloos.Tnstrucien tegfsker to store the cur ent
We solve th interupt request înstructin that is being and it is not
pogromabe
INTA (Interupt Acko):It is used to sndica ted that can and not accessed by ang snstructin,
be fnterupt is accepted . tlo slemporary Regíser- The purpose ot Temporamy the
RST 5-5 (Restart):-t is a vector & Maskable
interupt Dot giste is to holdl k data tenporaiy duning
RST 6-S: It is a ýector LMaskable ttw nkrupt.
executin ot instroctns, /reaister: CY-Cang
RsT 7-s:- ( Flag Pegistes ot so8s MP),D2 Do LSB
P-pait
MSB Da D: Ds Da
TRAP: Vector e non - mas kable Hlw nterupt SXAc XPX Ac -Aulay
cary
) spectal Purpose vegister Block ot ttag rqte. Z-zerb
S-Sign Hleg
pregram counter (pe):- 1t is t6-bi t registeu EYàrnde:
sequening the exe cution ot operation.Tt fs also MOU A
D6 4
called as memorg pointer.-Tthe -function of this fa to
-find the menoy address trom ohich the net byte
or nect instrucen the execoted
tack pointer (sp):It pofrts to reacl &ofte menoy Pn diagram af 8085 MicroproceSSor:
called stack and it is l6 St vegfster.The be ginning 40
ot the stack is defined by the (o Gt address in -HLDE Setal
sD
the stack poiner egíste: So
q3 33|tHo,D
CLK OUT RAP-G
31
5)-Aithmetic and Logl Unit: SID
RESE7N
RTGA8
-All the-Atbmeie e togico ope rcrins are. 10
b!
1C
pertomed în kic unit. t consisks ot . Aceomslato 8 3, 9085
HOLDS8
2.Flag registe 3.Tnstructin regiske aTenporay veg INTRo MiD 32 MP slals
Accumultor - 1t is a 8-bit register .Al he 30
ALE
afthmetic 2 logie operation ave performed and ht AD,-13 294
28LAs
So
resut is temporanly store thee. Result AL operatlas fi5
Can be transfered to RSET cloct
purpoce regís ler
nemoy or periphexals general
OUT
251
24 Au
23 Ao
Unstruction register sdecoder ~1t s a 8Bbit regis , 22
instructi an etched and are loadled trom
Plinots -Functional bliling Bocks of processor : 4 Sefal Llo porls.
’ 8085 s an 8-bit microprocess oY as t opera ks on B-bíts SID - Send nput pin &Ste pín
o mba
humbee ir s Ths pir
The size of the address bus in BO8sEc8s (s le Bits
data i soi ally ed to h pro ceSLoY direcy thgb p
vtt 45V
’ B085 MP is an Tc vtb 40 pins and operates der'ces
pouer supdy SoD- Set al olp dala pho g ste din pum bur ou'4'
4. pouer supply and cloct sinals 5- Centrdl &statu
’An number 40 denetes Vec ALE- Address Latchignals.
&hahle & in Dunbe & 30 he
->An external pocer supply of 4sv is prouided to This pin. Pin get enable at the 45one
mutiplexed addre s < DB . talben address
* Vss: i present t
-’ Pin number is 20
RD- pin nunber Ss B 2otuoise,
St gets duabco
’Ths pin shoas the grounded cornection of the
MP.
louo senal tht fin hcs
These are Tepresented by pin number 1 and
2. Tead operatin -from the
>These 2 pins are comected vth a crystal to maintan the pin homber e "z1" tous memors unit shauscofte
signal fn
fnternal -freqoency of The clock qenertion.
t CLK COUT):
operatton -from he memcy uit ths pin'
1o|M - pny number t "34" 2 fneicate the
membry address or tlp-olp device selec-Hon
ot a
It acts as the sys cock that kecps Tecord of ime dra ti
of each operotion'get completed. en This pín
2. Address Bus high signal op at memoy locatn
op at tlo deviCLS
>Ths category contain 8pins
’1t can corry (6.6its at a tme.
->8 are multiplered tb the dtabu and the left over 9 are
sapentey shoon by pin numbet sr to 28.
>These ae used to carry the Address ot data &instructien
-from the processo to -the memory (o cation and st is
undirectonal în patuÝe.
’These are deroted by g to As that represent gMSB of
he memt locaton
|2 Dota Bus ustt
t6s cate qoy also
Malplered oddes b::
To sedu cc the Cerrtdins 8 pin
mulplecd stNoot bus lincs.these bft bou (nes are
These ax ahocn bys-b4pin addets bus.
Pn contgoreti denotsnumker (ouer ota mu4plexed ti
AD, to AD
 I. RST 7-5
* Interrupts of B08s Mroproces as 2. RST 6S
There are 4 type ot Sntemptr 3 RST SS
4 TRAP
I. vectored 9ntemupts ave ditt.d as
S INTR
2.Non- Vectored Sntepls
*
3. Masked Tntemups 2.4tlusatt
Memay orgenízotin ofof B085 MP:
4. Non macked înterups
temduoare înterups: Memory
. Vectore d Dntemupt : Here he Sntemupt addiess s
knousn as the p0 COSS OY CB085) pímary Secondang
Eg: RST 7s,RST 6.5,RST S.5, RAP Memory Memory
2. Non -vectored Interrupt : Here the Snterupt address Serdal
Semi
$s not knoon as the proesson Read Tandon Access
RAM only
S7 INTR acceAs
MemOTy memory
3. Masked Interrupt : Here, uoe can disable ntenupt (Ro) thpel
Flepp cD DVD Hord
Sorme Snstructions nto he pogram static Dyncm rasede permann
' RsT 7.5, RST G.5, RST 5-5. RAM RAM ROM ROM
CsRAM)CORnM)
4 Non- Masked Interupt: Here, e can't dsable he Fast slotd
Gnstrucions Gnto the PROg
fnterrapt by woitng Some PROMEE PROM
erauable prgn electied cxucse pg
TolM enabl
pro gram
|Sottware Datenupt : Melin Feoutures of 80B4 (6-data
90 -address
’ Sn sluo oterupt proprammay har add nutuctny -’ (b-brt data
Into the > 20 Address
pro qra to execute he Sotenupt all (e -bfts but total no-bt
Thre are 8 typs of sluo Snteropl4.
RST, RSTI RST2 ' RST 3 RST 4t RST S.
..RST 7 use tor 8 or qYegists
tHardusare Tnterupt:
These frterups are Gn bilt gogC mícropro ser PDass speedfne fnoree’3m[
There coc 5 types.
 -form -for erteina deda menory
Ty Ieac cyde
Bos1 Micto comtroller Iing
daqrams ALE
PsEN
ALE RD
PSEN porto Ao Dada a Ao-An NITR
RO
port D InSTR povt
X P2.0-P or Ae-A A8-A S
CNe formms tor exenal dada memoy nk cycle.
port 2 Pg-A
ALE
PSEN
Poito
Ao-A9 DATA OUT A INSTR
IN
Y P20-P27 6r A8-Ar X Ae-AS
 * Suvo Metor (alor king witt
Interfacing oit BoI mi uDcontl
’ Servo metor ave self-contained mechanical denias fat
Applications
*Softwae &Harduwe Snterrupt are Cused to comtrol the machins wth predsion,
Hardusane Interupt: These arr -tocund Sn many applications from toys to
fndstrial automttm
any pehpheral deva by
’ Hlw fnterupt coe caused by ->There art vanous kinds of motor, but servo motor a
especialy designcd for spcihc angulon posihm to
snding a signal hvaugh acpoiticd pin to mlcroproass0. control the machincs.
> Usually the seno motor uked to contol te angular
NMÎ ;- 4 it osingle pin non-naska ble Snterupt ahch
)NM?:- moton among -from oto (96 o° to Go.
can't be dicabled. (ype - intmupt)
D(NTR :- Dt iuinterupt reqest markable nteupt cchich The lorking principal of Sevo motor is pulse coidt
modulation CPM)
provida single requrt Litt activatd by o port. -> It consistt of 3oires aberc of them ae used to
piovde power e grd wir und to provde contol sigrak
Sottcoxe Inkrpti Langular position is detncd by wdts ot pulk at centd p
’ Sro motor having angle ot rotati fom o' to (86° and
2 Slo fnkmopt can be generated by însectng he inhuchins angular posi tion can be centrolled by vanyng the duty
CNT itbin the pro gram: cycle omong 1ms o 2ms
’ Here the black oi fr
connected to qrond
? Thae ae 2s6 luo fntesrupt avai lable în 8036 mp motor
gck pour froy red uoire.
Format: ’ The Centol ot senro moto fa
INT
Connected to pot-b ot
86S| me.
gee rang tram oo to FFH Appli cattons ot Servo moto
SHotrg address fem oooooH do oo 3 FF H I. Tt s wed fn pyess machins or ctting te peu in siz
Sni buctn INT IPCnumher staton.
Imoedek value functin
OPCOde
 Enable
t Aplicetiors of Automrtin syskm
pulse
step pi'cornba)
( motoy Assem blirng: Tku obecl can be grocp inte a sigl gyeop
Drction Su-brdge| G
-Thvendig
Cunent fead bact -packagtHg maerial na
n votary mo-kon
-
This ol cuts away h
Encoder fedback
>The nw contol technlque combines Sro performana
ceating
oith sleppa motor cesd -Measaing
Dilling
Explarutan: -înspctin prduct
’ Servo metor reguye a pulse sidts moda latn (Pwm
a
-
Debugaing:-remaving smdl Gmperfectons thom macine mal
signl -to centrol its position. -procce Contro
’A stepper metor requbu a sequct ot pulses -to votate
I. Dnttialze imer & -Fogin2:-shaping metal int e Anlahed shape
Senolstepper pins tena ortb apolet
2.
Gencra te Pm signal for sevo or sequtna of pubes for falletzng :-staclig large quanttiea of ieenteal
steppeu tor hpein?
3. Use to control pulse cwdt &priod.
Note;
Ad ust timpr vaus adeby acerdigy t motoY
Sprciticahins.
2- Use a suitabe driver 1C to Snterfaa oit5 8os Hc.
stpper motor Interface! tV motoY
4-phay
fnverting stepper
80S| buHcrs motoy
þort
PinJ