EEE201 CMOS Digital Integrated Circuits

CMOS IC Layout Design Project

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 ABSTRACT

In this report, the plan and design of an IC layout of a 2-input CMOS NOR gate are presented,
with emphasis on the size of CMOS transistors. After examining the aspect ratios of the
transistors, the key CMOS parameters that were given attention include carrier mobility, the
threshold voltage, and the oxide capacitance. Because the hole mobility in the PMOS transistors
is less than the electron mobility in the NMOS transistors, the w/l ratio of the PMOS devices has
been appropriately changed to make a balance. Through thorough planning of the placement of
the transistors, the physical layout became very compact, and by proper placement of the input
and output lines, extra points were saved. To enhance manufacturability, parameters such as
minimum identifiable line width and overlay accuracy were used. For NOR gate logic
implementation, you will find two PMOS transistors enabled in parallel perform the pull-up
action to guarantee the output ( F ) is at a high logic level (logic 1). At the same time, two
NMOS transistors are connected in the series for controlling the pull down in order that output
( F ) is low, or at logic O, level.

INTRODUCTION

The goal of this work is to design and show an efficient layout for a 2-input CMOS NOR gate.
The design process aims at achieving the usage of fewer masks and the layout occupation area
while ensuring its functional correctness in the fabrication stage. Important parameters including
feature size, gate oxide capacitance, threshold voltage, and carrier mobility have been taken into
consideration because of their impact in CMOS technology. These parameters were useful in
deciding the best size of PMOS and NMOS transistors to offer symmetrical operating currents
and enough drive current. The design incorporates calculations regarding the transistor aspect
ratios as well as the use of metal-1 layers and poly silicon. Further, a layout view of the IC is
presented and the position of the inputs and the outputs highlighted, the conformance to layout
restrictions, and the structure of the transistors. Thus, following the CMOS design rules in this
work to a T, this work presents a manufacturable NOR gate circuit topology.

CIRCUIT DESIGN AT SCHEMATIC LEVEL

The voltage levels, drive current, switching sped of this device is directly proportional to its size
determination. Both NMOS and PMOS circuit networks must work together to implement the
NOR logic successfully. It has been taken into account the fact that only one path is required to
remain active at a time. The Pull Up Network which is the PMOS transistors. They connected in
series network and are responsible for pulling up the output F to a higher voltage which is simply
at logic 1. The Pull-Down Network which is the NMOS transistors. They are connected in
parallel network and are responsible for pulling down the output F to a lower voltage at logic 0.
rise and fall time balance, power dissipation verses reliability, speed verses power consumption,
noise margin and speed are the trade-off performance considered in the design.

Below is the truth table of the circuit network.

As shown in the aspect ratio section below, the NMOS and PMOS sizes have been computed as
an equivalent respective aspect ratios. The minimum fabrication technology allowed is the
channel length. Its width is adjusted in order to achieve the desired current balance and carrier
mobility.

A Pseudo-NMOS NOR gate is similar to an NMOS NOR gate but nonetheless

outputs a high impedance when the inputs to the last NOR gate are low. This
design has the advantage of greatly decreasing the number of transistors required in
the circuit. In the pull-down network, the gate of each NMOS transistor is
connected with one of the inputs. The drain terminals of the NMOS transistors are
connected to the output node, the source terminals of the NMOS transistors are
connected to the ground.
The pull-up network features a single PMOS transistor that is incorporated as the
pull-up element. E hence the gate of the PMOS transistor which makes the
transistor always “on”. The source terminal is connected with the positive supply
line and the drain terminal is tied to output node. The output is taken from the point
where common node of PMOS drain is connected with the NMOS transistors as
shown in the figure.

Advantages of the Pseudo-NMOS NOR Gate:

1. Reduced Transistor Count: It has a smaller number of transistors than a standard

CMOS NOR gate.

2. Simple Design: A simple topology, which would require fewer elements in the
system.

3. Faster Pull-Down: The parallel NMOS arrangement made possible the effective
pull-down operation as well.

Disadvantages of the Pseudo-NMOS NOR Gate:

1. Poor Noise Margin: Improved noise immunity, which in turn degrades signal
quality.

2. Degraded High Output Voltage: It is not fully at the supply level as the output
high-voltage, hence the device’s performance is affected.

3. Unsuitable for Low-Power Applications: Current flow in the pull-up network is

direct and consequently, results in higher power dissipation with the conduction.

4. Static Power Dissipation: A direct consequence of passive components is that

power is dissipated also during signal idle periods, hence low efficiency.

IC LAYOUT DESIGN

The below CMOS parameters were provided I order to come up with the desired design.
Optimal aspect ratio and the shared diffusion regions to reduce the number of diffusion contacts
are the specific optimizations considered in order to minimize the area of chip while increasing
its performance.

The layout design considerations considered to reduce the parasitic capacitance, inductance and
resistance are shared diffusion, shorter interconnections and guard rings.

Aspect Ratio

Aspect ratio is the ratio of the width of the transistor to its length. In order to ensure a symmetric
behavior between PMOS and NMOS transistors, the aspect ratio of the PMOS should be
increased to compensate for its lower µp even though they differ in mobility, (µn>µp), both of
them should ensure equal drive strengths (ID).
Transistor Sizing
Propagation delay

Power Analysis
Static Power

Technical and Utility Advantages of the CMOS NOR Gate

1. Functionality of the CMOS NOR Gate

The CMOS NOR gate is one of the simplest devices that is integrated into complex schemes in
the digital analytice. Its function can be defined as being equal to the NOT of the presence of the

OR operator. following the Boolean equation: where Y is the output, given A and
B as the inputs.

Key Features of CMOS NOR Functionality:

High Noise Immunity: The structure is noise immune, which allows it work stably in the
conditions of electric interference characteristic for the CMOS structure.

Low Power Dissipation: In particular, under the steady-state situation (which means inputs do
not change), there is no current through the CMOS NOR gates, and the gates are power saving.

Dual Transistor Networks: Since there is no NMOS channel, the gate control of the output bit-
line involves the complementary NMOS and PMOS structures. If either of the inputs is high then
NMOS network output is low and, when both of the inputs are low, then PMOS network pulls
low its output.

Cost-Saving and Efficiency

Thus it can be concluded that the structure of the CMOS NOR gate has several positive aspects
included automatically that define an opportunity to produce cheaper required digital circuits.

a) Power Efficiency

Another significant and tough design consideration that has emerged is power consuming in
actual response to battery power deployments in smart phones and dispose in IoT gadgets.
The CMOS NOR gate achieves:

Negligible Static Power: It can also be explained that the 30nW leakage current of the Off
transistors is actually negligible, because the mUses are asserted only when all these transistors
are Off, and hence no power is consumed. These power efficiencies were as far reaching as
reducing operational costs to systems that incorporated millions of transistors for example in
processors and memory chips.

Low Dynamic Power: Through the same analysis as above, the gate also delivers a negligible
power during the switch as determined earlier 0.45mW It has been estimated to draw a power
consumption of 45mW, due to the check that is taken on charging and discharging of the circuit.

b) High Density and Compactness

The CMOS NOR gate can therefore be fabricated with a small transistor dimension for example
a device that operates on a minimum feature size of 0.2 𝜇 m 0.2μm. This allows:

High Integration Density: A designer can integrate anything between tens of millions of NOR
gates into a single chip which means that density is not an issue where a designer is interested in
having important functions occurring within a relatively small area.

Material Cost Reduction: It will also mean that they will be using less space on a silicon wafer
for production, a factor which will lower the cost of production significantly.

c) Versatility in Applications

The CMOS NOR gate serves as a building block for several applications, offering flexibility in
design:

Universal Logic Gate: A stable function for the NOR gate is the ability to combine it and design
circuits without necessarily the need of coming up with multiple gate types.

Memory Circuits: NOR gates are used to construct static memory cells, creating high
performance memory systems as well (such as SRAMs).

Programmable Logic Arrays (PLAs): In PLAs, NOR gates are employed to implement specific
functions making them the most suitable for low price programmable devices. This portability of
the NOR gate reduces the utilization of other complex circuits that are usually time consuming to
design and expensive to develop.

The design rules taken into consideration are as follows: well substrate contact rule, spacing and
overlap rules and minimum feature size.

The trade-off performance considerations are interconnected parasitic, routing simplicity and
manufacturability.

IC layout

Below are changes made in order to come up with the layout:

Transistor sizing adjustments, where by in the schematic, transistor sizes are based on theoretical
performance but in layout drawing, adjustments are made to meet routing constraints and
physical area.

Routing optimization for PMOS, where by the schematic suggested equal sizes for NMOS and
PMOS while in the layout, PMOS are usually increased in width to account for their lower
mobility. This change in turn ensure performance goals are met like voltage levels and speed are
met.
 SUMMARY AND CONCLUSION

Since there is a need to interconnect both the pull down and pull up network circuits through
proper configuration of the NMOS and PMOS the layout was optimized carefully and this
greatly assisted in achieving the NOR gate logic. So long as the transistor functionality is held
strict, layout area constraints and proper routing into considerations the principles of designing
CMOS can yield good results in the real work as has been demonstrated and illustrated by this
nice CMOS 2-input NOR gate IC layout design. CMOS in efficient in integrated network design
and this project has also demonstrated its reliability and flexibility in implementing the logic
functions for the digital circuits.

Often it is highly desirable if there is a balanced relationship between manufacturing limitations

on one hand and design requirements on the other and this is the extra accomplishment, which
this design has actually done. Integrating metal 1 layers for the interconnection and poly-silicon
layers for the gate connections has led to a small layout of the design for manufacturing. To
avoid any blocking in the while optimizing the area, the output F, the inputs A and B, have all
been wired in parallel. These are the major factors that will ensure the design is scalable for
enhanced applications, and suitable for to be adapted into bigger circuit systems.
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