INSTRUCTION MANUAL

Digital Electronics lab.

(LESCS-101)

Prepared By-
Er. Priyanka Arora
Department of Computer Science & Engineering
Guru Nanak Dev Engineering College, Ludhiana
 SYLLABUS
LESCS 101 Digital Electronics Lab.
1. Truth-table verification of OR, AND, NOT, XOR, NAND and NOR gates using various IC’s.
2. Realization of OR, AND, NOT and XOR functions using universal gates IC’s 7400 and 7402.
3. Half Adder / Full Adder: Realization using basic and XOR gates IC’s.
4. Half Subtractor / Full Subtractor: Realization using IC’s 7400 and 7402.
5. Realization of IC7483 as Parallel adder/subtractor.
6. 4-Bit Binary-to-Gray and Gray-to-Binary Code Converter: Realization using basic, XOR gates and
universal gates.
7. 4-Bit and 8-Bit Comparator: Implementation using IC7485 magnitude comparator chips.
8. Multiplexer: Truth-table verification and realization of Half adder and Full adder using IC74153
chip.
9. Demultiplexer: Truth-table verification and realization of Half subtractor and Full subtractor using
IC74139 chip.
10. Flip Flops: Truth-table verification of JK Master Slave FF, T-type and D-type FF using IC7476
chip.
11. Asynchronous Counter: Realization of 4-bit up counter and Mod-N counter using IC7490 &
IC7493 chip.
12. Synchronous Counter: Realization of 4-bit up/down counter and Mod-N counter using IC74192 &
IC74193 chip.
 EXPERIMENT NO. 1
Aim: Truth-table verification of OR, AND, NOT, XOR, NAND and NOR gates using various IC’s.
Apparatus: Regulated power supply, trainer kit, IC’s 7400,7402,7404,74098,7432,7486, tweezer,
connecting leads etc.

Theory:

AND Gate (7408)

A circuit which perform an and operation is shown in figure (a). It has N inputs (N>=2) and one output.
Digital signals are applied at the input terminals marked A, B………N, the other terminals being ground
which is not shown in the diagram. The output is obtained at the output terminal marked Y and it is also a
digital signal.

Mathematically, it is written as

Y = A AND B AND C……………….AND N

Y =A.B.C…………….. N

Y = ABC………….. N

For 2 inputs,

Y = AB

Figure: IC-7408 (AND Gate)

OR Gate (7432)

The adjoin Figure(b) shows a OR gate with N inputs(N>=2) and one output. The OR operation is defined
as the operation in which output is 1 if one of the input is 1. Its logical equation is given by

Y= A OR B OR C………………………………..OR N

Y= A+B+C+……………………………………….+N
For 2 inputs,

Y= A+B

Figure: IC-7432 (OR Gate)

NAND Gate (7400)

The adjoining figure(c) shows a NAND gate. The NOT-AND operation is known as NAND operation.
This gate is considered as an AND gate followed by a NOT gate.
The operation of this circuit (figure(b)) can be described in the following way

Output of AND gate(Y1)

Y1 = AB………………….N

Output of NOT gate can be written as

Y =Y1 = (AB……………..N)

For 2 inputs

Y =AB

A bubble on the output side of NAND gate represents NOT operation, inversion or complementation.
 Figure: IC-7400 (NAND Gate)

NOR Gate (7402)

The adjoining figure(d) shows a NOR gate. The OT-OR operation is known as the NOR operation. This
gate is considered as an OR gate followed by a NOT gate.

The operation of this circuit (figure(d)) can be described in the following way

Output of OR gate Y1 can be written as

Y1 = A+B+…………………. +N

And the output of NOT gate Y can be written as

Y =Y1 = (A+B+…………..+N)

For 2 inputs

Y =A+B

A bubble on the output side of NOR gate represents NOT operation, inversion or complementation.
 Figure: IC-7402 (NOR Gate)

NOT Gate (7404)

The adjoining figure(e) shows a NOT gate which is also known as inverter. It has one input(A) and one
output(Y) and the logical equation is written as

Y = NOT A

Y=A

It is read as Y equals NOT A or Y equals compliments of A. It is also referred to as an inversion or

complementation.
The presence of a small circle, known as the bubble always denote inversion in digital circuits.

Figure: IC-7404 (NOT Gate)

EX-OR Gate (7486)

The adjoining figure(f) shows an EX-OR gate. EX-OR operation is widely used in digital circuits. It is
not a basic operation and can be performed using the basic gates ----- AND, OR and NOT. Its logic
equation is

Y = A EX-OR B

Y=A+B

Y = AB + AB

When both inputs are same the output is 0, whereas when inputs are not same, the output is 1.
 Figure: IC-7486 (Ex-OR Gate)

Procedure:

1. Insert the desired IC into the bread board present in the trainer kit.
2. To verify the truth table of AND, OR, NAND, EX-OR gate apply the input at 1st and 2nd pin and
take the output at 3rd pin. Put GND and Vcc at pins 7 and 14 of the IC’s.
3. To verify the truth table of NOR gate, apply the input at 2nd and 3rd pin and take output at 1st pin.
For NOT gate input is given at 1st pin and output is taken at 2nd pin.
4. Remove the IC’s with the help of tweezers.

Result: The truth table of all the logic gates has been verified.

Precautions:

1. Connections should be neat and clean.

2. Insert and remove the IC’s with care.
3. Apply GND at pin no. 7 and Vcc at pin no. 14 of both the IC’s.
 EXPERIMENT NO. 2
AIM: - Realization of OR, AND, NOT and XOR functions using universal gates IC’s 7400 and 7402.

APPARATUS: - Power Supply, trainer kit, connecting leads, IC 7400(NAND), IC7402(NOR),

tweezers.

THEORY:- NAND and NOR are called as Universal gates because all the gates like AND, OR, NOT,
XOR, XNOR can be realized by these gates.

NAND gate as universal gate:-

1.) Realizing AND gate using NAND gates

A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted,

overall output will be that of an AND gate.

Y=((A.B)’)’

=A.B

TRUTH TABLE-
A B (A.B)’ ((A.B)’)’
0 0 1 0
0 1 1 0
1 0 1 0
1 1 0 1

2.) Realizing OR gate using NAND gates

From DeMorgan’s theorems: (A.B)’ = A’ + B’. Similarly, (A’.B’)’ = A’’ + B’’ = A

+ B So, give the inverted inputs to a NAND gate, obtain OR operation at output.

TRUTH TABLE-
A B A’ B’ (A’.B’)’=A+B
0 0 1 1 0
0 1 1 0 1
 1 0 0 1 1
1 1 0 0 1

3.) Realizing NOT gate using NAND gates

A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND

gate together. Now it will work as a NOT gate.

Y= (A.A)’

=A’

TRUTH TABLE-
A A.A (A.A)’ A’
0 0 1 1
1 1 0 0

4.) Realizing XOR gate using NAND gates

Let A and B be the inputs and Y be the output.

Y=((A(A.B)’)’.((A.B)’B)’)’

=A B
 TRUTH TABLE
A B A.B (A.B)’ (A(A.B)’) ((A.B)’B) A B
’ ’
0 0 0 1 1 1 0
0 1 0 1 1 1 1
1 0 0 1 0 1 1
1 1 1 0 1 1 0

5.) Realize X-NOR gate using NAND gates

X-NOR gate is actually X-OR gate followed by NOT gate. So give the output of X-OR gate to a NOT
gate, overall output is that of an X-NOR gate.

TRUTH TABLE-
A B (A.B)’ (A(A.B)’) ((A.B)’B) A B A B
’ ’
0 0 1 1 1 0 1
0 1 1 1 1 1 0
1 0 1 1 0 1 0
1 1 0 0 1 0 1

NOR gate as universal gate-

1.) Realizing AND gate using NOR gates

From DeMorgan’s theorems: (A+B)’ = A’. B’. Similarly, (A’+B’)’ = A’’. B’’ =

A.B So, give the inverted inputs to a NOR gate, obtain AND operation at output.
 TRUTH TABLE-
A B A’ B’ (A’+B’)’ A.B
0 0 1 1 0 0
0 1 1 0 0 0
1 0 0 1 0 0
1 1 0 0 1 1

2.) Realizing OR gate using NOR gates

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overall output will

be that of an OR gate.

Y = ((A+B)’)’= (A+B)

TRUTH TABLE-
A B (A+B)’ ((A+B)’)’
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1

3.) Realizing NOT gate using NOR gates

A NOT produces complement of the input. It can have only one input, tie the inputs of a NOR gate

together. Now it will work as a NOT gate. Its output is

Y = (A+A)’ = (A)’

TRUTH TABLE-

A A+A (A+A)’ (A)’

0 0 1 1
1 1 0 0

4.) Realizing XOR gate using NOR gates

EX-OR gate is actually EX-NOR gate followed by NOT gate. So give the output of EX-NOR gate to a

NOT gate, overall output is that of an EX-OR gate.

Y = A’.B+ A.B’

TRUTH TABLE-
A B A’ B’ A’.B A.B’ (A’.B)+(A.B
’)
0 0 1 1 0 0 0
0 1 1 0 1 0 1
1 0 0 1 0 1 1
1 1 0 0 0 0 0

5.) Realizing X-NOR gate using NOR gates

Let A and B are the inputs and Y be the output.

The output of a two input EX-NOR gate is given by:

Y = AB + A’B’

TRUTH TABLE-
A B A’ B’ A.B A’.B’ (A.B)+(A’.B
’)
0 0 1 1 0 1 1
0 1 1 0 0 0 0
1 0 0 1 0 1 0
1 1 0 0 1 0 1
PROCEDURE:-

1.) Insert the desired ICs into the bread board present in the trainer kit.

2.) Apply two inputs and one output. Put GND and VCC at pins 7 and 14 of the ICs.

3.) For NOT gate only one input is applied and one output.

4.) After verifying all gates remove the ICs with the help of a tweezer.

RESULT:- The truth tables of realization of all gates using NAND and NOR are verified.

PRECAUTIONS:-

1.) Connections should be neat and clean.

2.) Insert and remove all ICs with care.

3.) Apply GND at pin no. 7 and VCC at pin no. 14of both the ICs.
 EXPERIMENT NO. 3
AIM: - Half adder / Full adder: Realization using basic and XOR gates IC’s.

APPARATUS: - Regulated power supply, trainer kit, IC’s 7408, 7486, tweezers, connecting leads etc.

THEORY:-

Half Adder

A logic circuit for the addition of 2- one-bit numbers is referred to as a Half

Adder. As there are two inputs A and B then according to the formula,

2n =M

Here n=2, we get M=4

i.e. No. of possible combinations are 4.

Functional block diagram of Half Adder is shown

TRUTH TABLE
Inputs Outputs
A B Sum
0 0 0
0 1 1
1 0 1
1 1 0
Full Adder

A logic circuit for the addition of three one-bit number is referred to as Full adder. A half adder has only
two numbers and there is no provision to add carry coming from the lower order bits when multi bit
addition is performed.

Functional block diagram and circuit of full adder is as shown

Functional Block Diagram

After the addition of three bits in full adder circuit, two outputs gets generated out of which, one is sum
and other is carry out (). This circuit can also be derived by using two half adders and one OR gate. Thus,
in total, it uses two XOR, two AND gates and one OR gate.
Truth table of Full adder:

A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The circuit for both Half Adder and Full Adder using basic and XOR gates is shown below :

PROCEDURE:-

1.) Insert the desired ICs into the bread board present in the trainer kit

2.) Make the connections as shown in circuit

3.) Apply the inputs at 1st and 2nd pin of both the ICs and take output on 3rd pin. Put GND and V CC
at pins 7 and 14 of ICs.

4.) Output from the IC7408 gives Carry and IC7486 gives the Sum.

5.) By charging the inputs of the two ICs, truth table of half adder can be verified.
6.) Remove the ICs with the help of a tweezer.

RESULT:-

The truth table of half adder and full adder has been verified.

PRECAUTIONS:-

1.) Connections should be neat, clean and tight.

2.) Insert and remove the ICs with care.

3.) Apply GND at pin no. 7 and VCC at pin no. 14 of both the ICs.
 EXPERIMENT NO. 4
AIM:- Half subtractor / Full subtractor: Realization using IC’s 7400 and 7402.

APPARATUS:- IC 7400, IC 7408, IC 7486, Patch Cords & IC Trainer Kit.

THEORY:-

HALF-SUBTRACTOR:- Subtracting a single-bit binary value B from another A (i.e. A -B) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit to
realize it is called a half subtractor.

The Boolean functions describing the Half-Subtractor are:

S =A ⊕B

BOOLEAN EXPRESSIONS:-

D = A ⊕B

Br = A`B

Truth Table
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Figure: Logic Diagram

 Block diagram of half subtractor

Half Subtractor using NAND gate and NOR gate

Full Subtractor
Design for full subtractor:
Truth table:
Inputs Outputs

A B C Diff(Do) Borrow(Bo)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
 1 1 1 1 1

Full subtractor using NAND gates and NOR gates:

Half Subtractor/Full Subtractor using XOR and Basic Gates

PROCEDURE:-

1.) Check the components for their working.

2.) Insert the appropriate IC into the IC base.
3.) Make connections as shown in the circuit diagram.
4.) Verify the Truth Table and observe the outputs.
RESULT: - The truth table of the above circuit is verified.

PRECAUTIONS:-

1.) Make connections properly.

2.) Insert and remove ICs with care.

 EXPERIMENT NO. 5
AIM :- Realization of IC7483 as Parallel adder/subtractor.

APPARATUS :- IC 7483, IC 7486, breadboard, logic probe etc..

THEORY:-
IC 7483 performs the addition of two 4-bit binary numbers A3A2 A1A0 and B3B2B1B0 and carry input
to give the output S3 S2 S1S0 and carry out. So for adding the two numbers A3A2 A1A0 and
B3B2B1B0 , the two numbers are given to input terminals 1,3,8,10 and 16,4,7,11 of the IC 7483 and
carry in the terminal 13 is set to zero. To subtract two numbers by two’s compliment method, we are
adding the 2’s compliment of the second number to each of the four bits of the first numbers. The final
carry is neglected and the difference is taken from S3 S2 S1S0.
In the circuit a mode control is set such that when the mode control is zero, addition is performed and
subtraction is performed when the mode control is one. We use XOR gates to feed the input so that when
mode control is one, the complement of each of the four bits are fed and when mode control is zero, the
input as such is fed. In 1’s complement subtraction, the complement of the subtraction is taken and added
with the other number. The final carry is then added to the LSB of the result.
In case there is no carry, the complement of the result is taken and this will be a negative number. This
indicates that, subtraction is performed from a smaller number.
Pin Diagram IC7483

IC7483 as Binary Adder

IC7483 as Binary Subtractor

IC7483 as Binary Adder/Subtractor using MOD select line (M)

Procedure:
1. The IC is fixed on the IC trainer and VCC and GND connections are given from 5-volt supply.
2. Connections are made as shown in the logic diagrams.
3. All the inputs are connected to the switches and outputs to the LEDs.
4. The truth table is verified for different combination of inputs.
Result: - The above circuit is verified.
Precautions:
1. Take the readings properly.
2. Make the connections properly.
 EXPERIMENT NO. 6
Aim: 4-Bit Binary-to-Gray and Gray-to-Binary Code Converter: Realization using basic, XOR
gates and universal gates.
Apparatus: Regulated power supply, trainer kit, IC’s 7486, tweezer, connecting leads etc.

Theory:

The input to the 4-bit binary-to-Gray-code converter circuit is a 4-bit binary and the output is a 4-bit
Gray code. There are 16 possible combinations of 4-bit binary input and all of them are valid. Hence no
don’t care. The 4bit binary and the corresponding Gray code are shown in the conversion table. From the
conversion table, we observe that the expression for the outputs G4, G3, G2, and G1 are as follows:

The minimal expressions for the outputs obtained from the K-map are:

Logic Diagram for Gray to Binary Code Converter using XOR Gates:-

Logic Diagram for Gray to Binary Code Converter using NAND Gates:-
Truth-Table :- Binary To Gray Code Converter
Logic Diagram for Binary to Gray Code Converter using XOR Gates:-

Logic Diagram for Binary to Gray Code Converter using NAND Gates:-
Truth-Table:-

Procedure :

1. Insert the desired ICs into the bread board present in the trainer kit

2. Make the connections as shown in circuit

3. Put GND and VCC at pins 7 and 14 respectively.

4. Now give various inputs and verify the truth table i.e. In the case of gray-to-binary conversion, the
inputs G0,G1,G2 and G3 are giver at respective pins and outputs B0,B1,B2 and B3 are taken for all the
16 combination of inputs.

5. Remove the ICs with the help of a tweezer

Procedure :
1. Insert the desired ICs into the bread board present in the trainer kit
2. Make the connections as shown in circuit Put GND and VCC at pins 7 and 14 respectively.
3. Now give various inputs and verify the truth table. i.e. In the case of binary-to-gray conversion, the
inputs B0, B1,B2 and B3 are giver at respective pins and outputs G0,G1,G2 and G3 are taken for all the
16 combination of inputs. Remove the ICs with the help of a tweezer.
Result: 1. The truth table has been verified.
 EXPERIMENT NO. 7
Aim: 4-bit and 8-bit comparator Implementation using IC 7485 magnitude comparator chips

Apparatus: CONNECTING WIRES, BREAD BOARD, IC 7485 etc.

Theory:

A magnitude digital comparator is a combinational circuit that compares two digital or binary numbers
(consider A and B) and determines their relative magnitudes in order to find out whether one number is
equal, less than or greater than the other digital number.

Three binary variables are used to indicate the outcome of the comparison as A>B, A<B, or A=B. The
below figure shows the block diagram of a n-bit comparator which compares the two numbers of n-bit
length and generates their relation between themselves.

4-BIT MAGNITUDE COMPARATOR

The SN54/74LS85 is a 4-Bit Magnitude Camparator which compares two 4-bit words (A, B), each word
having four Parallel Inputs (A0–A3, B0–B3); A3, B3 being the most significant inputs. The 4-bit
comparator is mostly available in IC form and common type of this IC is 7485. This IC can be used to
compare two 4-bit binary words by grounding I (A>B), I (A<B) and I (A=B) connector inputs to Vcc
terminal. The figure below shows the pin diagram of IC7485 comparator.

In addition to the normal comparator, this IC is provided with cascading inputs in order to facilitate the
cascading several comparators. Any number of bits can be compared by cascading several of these
comparator ICs.
 Figure: IC7485 Magnitude
Comparator

8-Bit Magnitude Comparator (Equality Detector) General Description

An 8-bit comparator compares the two 8-bit numbers by cascading of two 4-bit comparators. The circuit
connection of this comparator is shown below in which the lower order comparator A<B, A=B and A>B
outputs are connected to the respective cascade inputs of the higher order comparator.

For the lower order comparator, the A=B cascade input must be connected High, while the other two
cascading inputs A ,B must be connected to LOW. The outputs of the higher order comparator become
the outputs of this eight-bit comparator.

Figure: 8-Bit magnitude comparator using two IC7485

Procedure:

1. Insert the desired ICs into the bread board present in the trainer kit
2. Make the connections as shown in circuit
3. Put GND and VCC at pins 8 and 16 respectively.
4. Now give various inputs and verify the truth table for both 4-bit and 8-bit magnitude comparisons.
5. Remove the ICs with the help of a tweezer.
Result:
1. The truth table has been verified.
 EXPERIMENT NO. 8
Aim:- Multiplexer: Truth-table verification and realization of half adder and Full adder using
IC74153 chip.

Apparatus: Power supply, digital trainer kit, connecting leads, IC 74153

Theory: A multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output lines. The selection of particular input line is controlled by a set of
selection lines. Normally, there are (2)n input line and n- selection lines whose combinations determine
which input is selected. 74153 is a dual 4 line-to-1 line multiplexer.

(i) Half Adder: A logic circuit for the addition of two bits is called half adder. After the addition of
two bits, two outputs are generated one is sum and other is carry. While designing multiplexer, these two
bits act as selection lines. So, two selection lines are used. Thus 22=4 i.e. 4:1 multiplexer is used to
design a half adder. The IC used is 74153 and it is 16 pin IC.

Truth Table:
A B Sum Carry
0 0 0 0

0 1 1 0
1 0 1 0
1 1 0 1
Pin Diagram of IC 74153

The inputs A & B are provided at the selection line S1 & S0. Sum is realized on MUX A and carry is
realized on MUX B.
For Sum:
A=0, B=0 A=0, B=1 A=1, B=0 A=1, B=1
I0(a) = 0 I1(a) = 1 I2(a) = 1 I3(a) =0

For Carry:

A=0, B=0 A=0, B=1 A=1, B=0 A=1, B=1

I0(a) = 0 I1(a) = 0 I2(a) = 0 I3(a) =1

Half Adder using 74153 :

(ii) Full Adder: A logic circuit for the addition of three bits is called full adder. After the addition of
three bits, two outputs are generated one is sum and other is carry. While designing multiplexer, these
two bits act as selection lines and line act as input line. So, two selection lines are used and one input line
is used. Thus, 22=4 i.e. 4:1 multiplexer is used to design a full adder.

Truth Table:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
For Sum:
C A=0, B=0 A=0, B=1 A=1, B=0 A=1, B=1
0 0 1 1 0
1 1 0 0 1
I0(a)= C I1(a)=C’ I2(a)=C’ I3(a)=C

For Carry:
 C A=0, B=0 A=0, B=1 A=1, B=0 A=1, B=1

0 0 0 0 1
1 0 1 1 1
I0(a)= 0 I1(a)=C I2(a)=C I3(a)=1

Procedure:
1. Insert the IC into the bread board of the trainer kit.

2. The Pin [16] is connected to + Vcc.

3. Pin [8] is connected to ground.

4. The inputs are applied to S1, S0 to the multiplexer and verify the truth table of half adder & full
adder circuit for both sum and carry.

5. Based on the selection lines one of the inputs will be selected at the output and thus verify the truth
table.
6. Remove the IC with the help of tweezers.

Result:
The truth table of half adder and full adder circuits has been verified.
Precautions:
1. Take the readings properly.
2. Make the connections properly.
 EXPERIMENT NO. 9
Aim: Demultiplexer- Demultiplexer: Truth-table verification and realization of Half subtractor
and Full subtractor using IC74139 chip.

Apparatus: IC 74139, connecting leading, battery supply, tweezer.

Theory: IC - 74139
IC – 74139 package contains two decoders. Each of these decoders has two address lines and four output
pins. The input address lines for one of the decoders is labelled 1A and 1B. The input pins for the other
decoder are labelled 2A and 2B. The output pins that are selectable because of a logic pattern on 1A and
1B are identified as 1Y0, 1Y1, 1Y2 and 1Y3.The output pins that are selectable because of a logic
pattern placed on the 2A and 2B input pins control the selection of the output pins identified as 2Y0,
2Y1, 2Y2, 2Y3.The integrated circuit 74LS139 contains two demultiplexers with 4 ways. Each one of
them has 2 entries of selection A and B, an input G and 4 exits (Y0 with Y3). The 74139 is also useful as
a learning tool to practice the use of the base 16 numbering system (HEX)to mentally represent a 16-bit
binary pattern.

Pin diagram of IC-74139

Truth-table of IC-74139

Half-Subtractor using IC-74139

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two
inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).
 Half-Subtractor circuit

Full-Subtractor using IC-74139

a full subtractor is made by combining two half-subtractors and an additional OR-gate. A full subtractor
has the borrow in capability (denoted as BORIN in the diagram below) and so allows cascading which
results in the possibility of multi-bit subtraction. The circuit diagram for a full subtractor is given below.
 Full Subtractor Circuit

Procedure :

1. Insert the desired IC's into the breadboard present in the trainer kit.
2. Make the connections as shown in the theory above.

3. Pin 16 must be connected to logic high and pin 8 must be grounded.

4. The enable input must be connected to the lower level (since it is active low circuit) i.e. 1G and 2G
input.

5. Now give the various inputs and verify the truth table for the both half subtractor and full
subtractor.

6. Remove the IC with the help of tweezer.

Result : The aim of experiment is verified.

Precautions :

1. Connections should be neat and clean.

2. Insert and remove all ICs with care

3. Apply GND at pin no. 8 and VCC at pin no. 16 of the IC-74139.
 EXPERIMENT NO. 10
Aim: Flip Flops: Truth-table verification of JK Master Slave FF, T-type and D-type FF using
IC7476 chip.

Apparatus: Regulated power supply, trainer kit, tweezers, connecting leads, IC-7476.

Theory:

Basically Flip-Flops are the bistable multivibrators that stores logic 1 and logic 0. Shift registers,
memory, and counters are built by using Flip – Flops. Any complex sequential machines are build using
Flip – Flops. Sequential circuit (machine) output depends on the present state and input applied at that
instant. Mealy Machine is one whose output depends on both the present state and the input. Moore
machines one whose output depends only on the present state of the sequential circuit. Note that the truth
table of J – K Flip – Flop is same as the Master – Slave. J – K Flip Flop and they must be remain same
because IC – 7476is –ve edge trigged flip – flop and we know that race around condition is eliminated by
edge triggered flip – flop. Another way of eliminating race around condition is by using Master – Slave J
–K Flip – Flop. When J = K = 1 (logic HIGH), J – K Flip – Flop changes output many times for single
clock pulse, it is Smaller than width of the clock pulse.

Race around condition is eliminated by using edge triggered clock pulse and using Master – Slave J - K
Flip Flops.
IC-7476

IC-7476 package contains two J-K F/F. Each F/F has two outputs and two inputs along with clock, preset
and clear inputs.
Implementation of Master Slave J-K Flip-Flop

It consists of one J-K flip flop, one slave S-R

& one inverter. In fig. clock signal is
connected directly to the master J-K F/F but it
is connected through inverter to the slave S-R
F/F. thus the master J-K flip flop is triggered
on the positive clock pulse but the inverter
used as the input of slave S-R flip flop force it
to trigger at the negative clock pulse. Also, the
O/P of slave S-R F/F is connected as a third
I/P for master J-K F/F. thus, overall circuit is
called master-slave J-K F/F. There are two
conditions for clock either ‘1’ or ‘0’, when
clock is 1 i.e. positive level, the master is active & slave is inactive. But when clock is 0, i.e. negative
level, the slave is active.
 Preset Clear J K Clock Qm /Qm Qs /Qs Status

0 1 x x x 1 0 1 0 Set

1 0 x x x 0 1 0 1 Reset
1 1 0 0 /Qm Qs /Qs
Qm
No change
1 1 0 1 0 1 0 1 Reset

1 1 1 0 0 1 0 Set
1

1 1 1 1 /Qm Qm /Qs Qs Toggles

D type F/F:

It can be designed from SR- F/F & JK- F/F by putting an inverter or NOT gate between S & R or J & K
inputs are connected together to make a single input as shown in figure.

D type F/F is used whenever S = R=0 & S=R=1 combinations are not required for particular flip flop to
be used. This input D is called data input & thus it is named as D Flip flop. For d=0 either S=0 & r=1.
For this input, output Q is always reset i.e. 0.
Preset Clear D Clock Q /Q Status

1 1 0 Q /Q Reset

1 1 1 /Q Q Set
T type Flip Flop:
It can be designed using J-K flip flop by connecting J & K inputs together to make a single input T as
shown.
Due to toggling property it is known as toggle flip flop & are extensively used in counters to count the
pulses.

Preset Clear T Clock Q /Q Status

1 1 0 Q /Q No
Change
1 1 1 /Q Q Toggle

Procedure:

1. Insert the IC into the breadboard.

2. Make the connections as shown in the theory above
in figure.
3. Pin 5 must be connected to logic high and pin 13
must be grounded.
4. All combination of inputs is applied & observations
are taken in table.
5. Repeat the steps from 2 to 5 for fig: 2 and fig: 3.
6. Remove the IC with the help of tweezer.

Result: The aim of experiment is verified.

Precautions:
1. Connections should be neat and clean.
2. Insert and remove all ICs with care.
3. Apply GND at pin no. 13 and VCC at pin no. 5 of the IC-7476.
 EXPERIMENT NO. 11
Aim: Asynchronous Counter: Realization of 4-bit up counter and Mod-N counter using IC7490 &
IC7493 chip. Apparatus: Power supply, digital trainer kit, connecting leads, IC7490 and IC7493.
Theory: In asynchronous, events do not occur at the same time as the clock is given to the first flip flop
and other successive flip flops are clocked by the output of preceding flip flop. In this every flip flop is
independent of input clock.

(i) 4-bit up counter: The clock pulse fed into 1st flip-flop is rippled through other flip-flops after
some propagation delay like ripple. As it is a 4-bit counter, this counter counts sequences from 0 to 15.
The IC which is used for 4-bit asynchronous counter is IC 7493.

Truth Table:
Count Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Counter counts sequences from 0 to 15

The following points should be taken into consideration for its working.

1. Connect pin 1 and 12.

2. Pins R01 and R02 are provided low inputs.

3. At pin 14, clock is provided.

Pin Description:

Pin Function Name

No
1 Clock input 2 Input2
2 Reset1 R1
3 Reset2 R2
4 Not connected NC
5 Supply voltage; 5V (4.75V – 5.25V) Vcc
6 Reset3 R3
7 Reset4 R4
8 Output 3, BCD Output bit 2 QC
9 Output 2, BCD Output bit 1 QB
10 Ground (0V) Ground
11 Output 4, BCD Output bit 3 QD
12 Output 1, BCD Output bit 0 QA
13 Not connected NC
14 Clock input 1 Input1

(ii) Mod-N asynchronous counter

Mod-5 asynchronous counter:

1. A 3-bit binary counter is normally counting from 000 to 111. The actual output of a 3 bit binary
counter at the fifth clock pulse is 101.

2. A two input NAND gate is used to make a Mod 5 counter.

3. The outputs of the first and third flip flops (QA and QC) are connected to the input of the give
NAND gate, and its output is connected to the RESET terminal of the counter,

4. Hence the counter is reset at the fifth clock pulse, which produces the output QC,QB,QA as 000. It
is called divide by 5th counter or mod 5 counter.

Truth Table:
Count Qc Qb Qa
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0

Internal Diagram:
 Internal diagram of IC 7490

Procedure:
1. Insert the IC into the bread board of the trainer kit.

2. Make the connections as shown in the diagram.

3. Connect pin 1 & pin 12.

4. Pins R01 and R02 are provided low inputs.

5. On pin 14 i.e. A, a clock is provided.

6. On pin 4,6,7, 13 no connection is to be made.

7. Outputs are obtained on pin 12, 11, 9, 8.

8. Apply the inputs and clock, the output is obtained from the circuit.

9. The Pin [16] is connected to +Vcc.

10. Pin [8] is connected to ground.

11. Remove the IC with the help of tweezers.

Result: The working of 4 bit asynchronous counter & Mod-N Asynchronous counters is verified .

Precautions:

1. Connections should be neat & clean..

2. Insert and remove the IC’s with care.

3. Handle the trainer kit with care.

4. Always apply GND to pin no. 10 and Vcc on pin no. 5 of IC

5. Take the readings properly.

 EXPERIMENT NO. 12
Aim: Synchronous Counter: Realization of 4-bit up/down counter and Mod-N counter using
IC74192 & IC74193 chip.
Apparatus: Power supply, digital trainer kit, connecting leads, IC74192 and IC74193.

Theory: In Synchronous Counter, the external clock signal is connected to the clock input of EVERY
individual flip-flop within the Counter so that all of the flip-flops are clocked together simultaneously (in
parallel) at the same time giving a fixed time relationship. In other words, changes in the output occur in
“synchronization” with the clock signal. The result of this synchronization is that all the individual output
bits changing state at exactly the same time in response to the common clock signal with no ripple effect
and therefore, no propagation delay.

IC-7490 is a TTL MSI decade counter. It contains four master slave flip flops and additional gating to
provide a divide-by-two counter and a three-stage binary counter which provides a divide-by-5 counter.

Internal Structure of IC74192 & IC 74193

4-bit synchronous up/down counter:

The up/ down counter has “Up” and “Down” count modes by having 2 input AND gates, which
are used to detect the appropriate bit conditions for counting operation. OR gates are used to
combine the outputs of AND gate, from each JK flip flop.

We provide a up/ down control line which enables upper or lower series of AND gates to pass
the outputs of JK flip flops, Q , Q’ to the next stage of flip flop, in the cascaded arrangement.
If the up /down control line is set to HIGH, then the top AND gates are in enable state and the
circuit acts as UP counter. If the up /down control line is set to low, then the bottom AND gates
are in enable state and the circuit acts as DOWN counter.

Modulo-10 synchronous counter

A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a
count sequence from 0 to 9. A standard binary counter can be converted to a decade (decimal 10) counter
with the aid of some additional logic to implement the desired state sequence. After reaching the count of
“1001”, the counter recycles back to “0000”. We now have a decade or Modulo-10 counter.
The additional AND gates detect when the counting sequence reaches “1001”, (Binary 10) and causes
flip-flop FFC to toggle on the next clock pulse. Flip-flop FFA toggles on every clock pulse. Thus, the
count is reset and starts over again at “0000” producing a synchronous decade counter.

Result: The circuit for all the cases has been verified .
Precautions:

1. Take the readings properly.

2. Make the connections properly.