Sequential logic circuits

In a sequential logic circuit, the outputs depend not just on the current values of the
inputs, but also on the past values of the inputs. The circuit has memory. Sequential
circuits can do two things that combinational circuits can not:

• Recognize sequences of inputs

• Generate sequence of outputs.

A sequential circuit consists of a combinational circuit to which the storage elements

are connected to form a feedback path. The storage elements are devices capable of
storing binary information. The binary information stored in these elements at any given
time defines the state of the sequential circuit at that time. The sequential circuit receive
binary from the information from the external inputs. These inputs together with the
present state of the storage element, determine the binary value of the outputs.

A sequential circuit can be made by adding feedback to a combinational circuit as

shown in figure 1.1 .In this circuit, depending on the design of the combinational logic,
the value of the output Y, will depend both on the two inputs A and B and the internal
feedback signal. With one feedback signal the circuit can have two behaviours for any
particular values of the inputs from the outside: one with the feedback signal = 0, and
one with the feedback signal = 1. the circuit has two states, with different behaviours. A
circuit with two feedback signals can have up to four different states, and one with n
feedback signals, up to 2n states.

Figure 1.1. A Sequential logic circuit

Synchronous sequential logic

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In an asynchronous circuit, the state of the circuit , i.e. the value of the feed back
signal(s), can change at any time in response to an input change. Asynchronous circuits
are tricky to design, and so most sequential logic circuits are designed in a slightly
different way, as synchronous circuits. In a synchronous sequential circuit, changes of
state are only allowed to happen at times synchronous to a special timing signal, called
the clock. The simplest synchronous circuit is a one-bit storage element, which is also
referred to as a flip-flop. There are four popular types of flip-flops i.e. JK, D, T and SR flip-
flops.

Flip-flops record states while clock controls the transitions from one state to the next.
These are called finite state machines because they can have at most a finite number of
states.

Types of State Machines

There are two types of finite state machines that can be built from sequential logic
circuits:

• Moore machine

• Mealy machine

In the Moore state machine shown in figure 1.2, the outputs depend only on the internal
state and any inputs that are synchronized with the circuit.

In the Mealy state machine, the outputs are determined by both the internal state and by
inputs that are not synchronized with the circuit, as indicated in figure 1.3

Figure 1.2 Moore state machine

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Figure 1.3 Mealy state machine

Algorithmic State Machine(ASM)

The logic design of a digital system can be divided into two distinct parts. One part is
concerned with the design of the digital circuits that perform the data processing
operations. The other part is concerned with the design of control circuits that
determines the sequence in which the various actions are performed. The relationship
between the control logic and the data processing in a digital system is as shown in fig.
1.4.

Figure 1.4 Partitioning of a digital system

The Algorithmic State Machines are similar to finite state machines, yet they are more
expressive in that, during each state (i.e. clock pulse), register operations may be
specified and performed during the transition.(i.e next positive clock transition). Fig. 1.5
shows a model of an Algorithmic State Machine.

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Figure 1.5 Model of an Algorithmic State Machine

Algorithmic State Machine Chart

The ASM chart is a convenient tool that translates the system specifications to an
information diagram in which the sequence of operations and the conditions necessary
for execution are indicated. It is a special type of flow chart describing the sequential
operations of a digital system. The ASM chart consists of a set of one or more blocks.
Each block may be viewed as a directed simple graph that has three kinds of nodes.

• State box. Represents a state and it is equivalent to a node in a state diagram or a row
in a state table. A block has one state box which is symbolically represented as a
rectangular box. The state box represents which state the system is in when block is
being executed. Within the box is a listing one or more register operations that take place
during the next rising clock edge when control passes from that block to the next
block/state. The edge leaving the state box may

a) Loop back to itself

b) Be directed towards the state box of a different block, or

c) Be directed to a decision box within the block.

The state is given a symbolic name which is placed at the upper left corner of the box.
The binary code assigned to the state is placed at the upper right corner as shown in
figure 1.6.

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Figure 1.6 State box

• Decision box. A decision box is symbolically shaped like a diamond with two or
more exit paths, as shown in figure 1.7(a), alternate symbol of a decision box is as
illustrated in figure 1.7(b). It describes the effect of an input on the control
subsystem. The input condition to be tested is written inside the box. Edges
leaving the decision box may
a) Be directed towards the state box of any block,
b) Another decision box within the block, or
c) A conditional block.

Figure 1.7. Decision boxes

• Conditional box. A conditional box is symbolically shaped like a rectangular
box with rounded sides as shown in figure 1.8. Within the box are one or more

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register operations which take place during the next rising clock edge, on
condition that execution passes through the box . Edges leaving the conditional
box may be
a) Be directed towards the state box of any other block or
b) Another decision box within that block.

Figure 1.8 Conditional box

The data processing path(Datapath) manipulates data in the registers according
to the system requirements. The control logic initiates a sequence of commands
to the Datapath. The control logic uses status condition from the Datapath to
serve a decision variables for determining the sequence of the control signals.

At any given time, the state of the sequential control initiates a prescribed set of
commands. Depending on the status conditions and other external inputs, the
sequential control goes to the next state to initiate other operations. The digital
circuit that act as the control logic provide a time sequence of signals for
initiating the operations in the Datapath and also determine the next state of the
subsection. The ASM chart describes the sequence of events as well as the
timing relationship between the states of a sequential controller and the events
that occur while going from one state to the next. The timing of the Algorithmic
State Machine is illustrated in figure 1.9.

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 Figure 1.9. Timing of an ASM
The operations specified inside the state boxes and the conditional boxes of each
block are performed in the Datapath subsystem while the change from one state
to the next is realized in the controller.
The design for the Datapath requires both the interpretation of the operations and
their implementation adopting digital components such as registers, counters,
adders and so on. State diagrams can become very messy. In many cases just
drawing a state diagram includes assumptions that are not true in general.
Perhaps certain cases of the inputs will never happen, hence the corresponding
arcs are simply not drawn. Certain cases of the outputs are not significant and
sometimes are left out. An algorithmic State machine(ASM) charts offers several
advantages over state diagrams;
• Often easier to interpret
• Conditions for a proper state diagram are automatically satisfied
• May be easily converted to other forms

Sequential circuit characteristics

Many problems require the detection or generation of a sequence of events. As
examples, an electronic combination-lock door controller must detect when a particular
sequence of numbered buttons has been pressed, and an elevator controller must
create a sequence of signals to shut the doors, move the cabin, and then reopen doors.
In such situations, a circuit can only advance to the next action (or next state) if the
current action is known. For example, an elevator should not move until the doors are
shut, and pressing a “2” at some point on a combination lock may or may not contribute
to the unlock sequence. A circuit that operates according to a specific sequence of
events is called a “state machine” or “sequential circuit”. A state machine requires
memory to store information about past actions, and it uses that memory to help
determine what action to take next. Outputs from sequential circuits are functions of the
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current inputs and memorized past inputs – this is in contrast to a combinational circuit,
where the outputs are strictly a function of the current inputs.

Most memory-containing circuits provide data storage for computing devices. Examples
include RAM arrays for computers, registers and register files for microprocessors,
cache memories, accumulators, status indicators, etc. These memory circuits may use
flip-flops, latches, or RAM cells (depending on the particular application), and they are
only used to store data elements in a processor environment. Memory devices used in
sequential circuits do not store data, but rather the operating state of the circuit. The
state of a sequential circuit is defined by the collective contents of all of its memory
devices. The value stored in each memory device in a state machine is referred to as a
state variable. Since a state variable can only take one of two values (‘0’ or ‘1’), a circuit
with N state variables must be in one of 2N states, and each state is defined by a unique
N-bit binary number. The memory devices in a given state machine are collectively
referred to as the state register.

The sequential machine design process is greatly simplified if memory devices with
certain characteristics are used. Those characteristics are: the ability to be driven to a
stable operating state (‘0’ or ‘1’); a timing signal that generates the smallest possible
sampling window to dictate exactly when new data can be written; a single data input
that directly programs the memory device; and a single reset signal that can drive the
output to ‘0’ regardless of the data or clock input signals. All of these characteristics are
contained in a DFF, and DFF’s are used in practically all sequential circuits. In fact, DFFs
can be used to construct any sequential circuit, and their use will always yield the
smallest, simplest sequential circuits.

A sequential circuit follows the general model shown below. The state register is
controlled directly by an external clock and reset signal. Data inputs to the state register
arise from a “next state” logic block that combines circuit inputs with state register
outputs - this feedback of the state variables is the reason a sequential circuit can
implement a given sequence of events. Without this feedback, future state register
changes could not be based on past events, and so ordered sequences could not be
implemented. The output from the state register is called the “present state”, and the
input to the state register is called the “next state”. At each edge of the clock, the next
state is written into the state register and so becomes the current state.

Like the next-state logic circuit, the output logic circuit contains only combinational
devices. In the figure below, the most general state machine model is shown, with
circuit inputs fed forward to the output logic block where they can be combined with
state variables to determine overall circuit outputs. This most general model is called
the “Mealy” model; in the simpler “Moore” model, only the state variables drive the
output logic block, so the feed-forward signal would not be shown (i.e., the red line
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would be absent). In simpler state machines like counters and other basic sequence
generators, the output logic block may not be present at all. In such cases, the state
register outputs are used as the overall circuit outputs.

The example timing diagram below shows the behavior of a hypothetical state machine
(what the state machine does is not important here – just examine the timing diagram).
Note that every rising clock edge causes a state transition, where the “next state” is
clocked into the state register flipflops to become the “present state”. Each state is
uniquely identified by the contents of the state register, called the “state code”. This
example shows three state variables, so eight distinct states are possible. The state
machine progresses from state 0 to states 1, 3, 2, 2, 6, and 4 based on the inputs I0 and
I1 and the current state code. Note also that the outputs Y0, Y1, and Y2 change just after
the clock – this is generally the case, because the state codes change just after the
clock edge, and the state codes are inputs to the output logic block.

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Designing Sequential Circuits
The most difficult task in designing sequential circuits occurs at the very start of the
design, in determining what characteristics of a given problem require sequential
operations, and more particularly, what behaviors must be represented by a unique
state. A poor choice of states coupled with a poor understanding of the problem can
make a design lengthy, difficult and error prone. With better understanding and a better
choice of states, the same problem might well be trivial. Whereas it is relatively straight-
forward to describe sequential circuit structure and define applicable engineering
design methods, it is relatively challenging to find analytical methods capable of
matching design problem requirements to eventual machine states. The initial and most
important design task, identifying behaviors in the solution-space to a problem that
require unique states, can be presented through examples. In general, the first step in
designing a new state machine is to identify all behaviors that might need states, and all
branching dependencies between states. Then, as an understanding of the problem and
solution evolve, original choices can be rethought, challenged, and improved.

One method of capturing the behavioral requirements of a state machine is through the
creation of a state table. A state table is nothing more than a truth table that specifies
the requirements for the nextstate logic, with inputs coming from the state register and
from outside the circuit. The state table lists all required states, and all possible next
states that might follow a given present state.

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State-to-state transitions can be directed by input signals, so the table must list any
input signals required to cause a given transition. The figure above shows an expanded
model of a state machine, and illustrates how the state/truth table can be used to find
the next-state logic. In the state table, the first four rows all show “000” for the state
variables. This is because there are two inputs, and a next state must be specified for all
possible combinations of inputs. From the state table, you can deduce that if the
machine is in state “000” and the inputs are both ‘0’, then the next state will be “001”; if
the machine is in state “000” and the inputs are ‘0’ and ‘1’, then the next state will be
“011”; and so on.

The output truth table shows how the state variables and any Mealy inputs are
combined to form outputs. In this example, only one of the two inputs (I1) is used by the
output logic circuit. The state and output tables can be combined into a single truth
table (also called a state table) to specify all combinational logic requirements (i.e., both
next-state and output requirements) in a single table.

The next-state truth table requires at maximum N input columns for each of N state
variables, and M input columns for each of M circuit inputs. It is not required that all
possible states nor all possible combinations of inputs be used; hence, the next-state

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truth table need not have all 2(N+M) rows present. Just which rows are required in the
truth table depends on which of the 2N possible states are used in a given sequential
circuit, as well as which inputs are used in each state. For each row of the truth table,
the next state output values are assigned according to the desired next state. The use of
DFFs in the state register is assumed, so a '1' in an output column will cause the
corresponding DFF to transition to a '1' on the next clock edge.

Although truth tables (or state tables) can always be used to specify next-state and
output logic, they suffer from a significant drawback: it is difficult to visualize the
sequential nature of a circuit’s behavior. A more useful method exists for specifying
next-state and output logic that has a powerful advantage – it lets us not only specify
logic requirements, but also clearly visualize the sequential and/or algorithmic behavior
of a circuit.

Designing sequential circuits using state diagrams

A state diagram represents states with circles, and transitions between states by arrows
exiting one circle and arriving at another. A binary number called the “state code” can be
written in the state-circle to indicate the value stored in the state register when the state
machine is in that state. Directed arrows leaving one state and arriving at another show
permissible state transitions. Input variable requirements for transitions are shown
immediately next to each transition; the indicated transition will only take place if the
input conditions shown are present. Transitions (also called branches) occur at every
clock edge; thus, at every edge, the present state is exited, and the next-state entered.
Often, it is required that for some input conditions, the machine hold in a given state –
this holding condition is shown as a directed arrow leaving and re-entering the same
state. In the partial state diagram shown, the state register contains three flip-flops: if
the state register is storing “000”, then it will remain in that state if A is ‘0’ at the next
clock edge; otherwise it will transition out of the state if A is ‘1’. The figure on the right
uses VHDL syntax for checking and assigning logic values. Many texts use conventional
logic equation symbols instead.

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When a state diagram is used as a conceptual tool to help arrive at a given problem
solution, it is typically sketched and modified in an iterative fashion. Circles are drawn
representing possible states, interconnected according to problem requirements, and
redrawn and reconnected as the problem and solution become clearer in the designer's
mind. Once a state diagram has been created that captures the design specifications, a
fairly automatic procedure can be applied to create a circuit from the diagram.

State-to-state transitions occur when the state register is loaded with new next-state
values. Since the state register can only be written on a CLK edge, state-to-state
transitions can only occur on the CLK edge. Thus, the presence of the CLK signal is
implied in a state machine, and the CLK signal is not shown in the state diagram.
Likewise, RST or PRE signals are not shown in a state diagram; rather, an arrow is shown
pointing to an initial state that the machine should assume whenever a “reset” signal is
asserted. A ‘0’ bit in the reset state requires the RST input of the corresponding state
register DFF to be connected to the reset signal, and a ‘1’ in the reset state requires the
PRE input to be connected to the reset signal. Thus, RST and PRE signals are not shown
in the state diagram – their presence is implied when an initial state is identified. Only
signals that are needed by the next-state or output logic circuits are shown in the state
diagram.

An example of a simple state diagram is shown below. This machine receives input from
three buttons labeled X, Y, and Z, and asserts two signals called "RED" and “GRN”: RED
if and only if the proper three-button-press sequence X-Z-Y is detected; GRN when a
new sequence starts. This “early stage” state diagram does not show state variables or
state names. The diagram has evolved by the iterative process– states and branching
conditions were added and modified as the needs of the problem became clearer, until
a complete solution was found.

Note that for each state, the branching conditions take into account all possible input
combinations, and no ambiguous branching conditions are present. If some input

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combinations are not accounted for, or if branching conditions indicate more than one
next state, unpredictable operation can occur. The partial state diagrams below
illustrate these points – in the diagram below, if both A and B are ‘1’, or if C = ‘0’, it is not
clear which branch to take. The need to unambiguously show possible next states is
important enough that many texts name two rules: the “sum rule” states that all inputs
leaving a given state must OR to a logic ‘1’; and the “mutual exclusion rule” states that
any combination of inputs can indicate only one next state.

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