304 rurcnopnocEssoRSANDMtcRocoNTRoLLERS

DSP processors are processing chips that have flexibility in hardware and (iii) 128 b.vtes of t-n+t
software, to implement signal-processing algorithms. These processors have an (v) two l6-brt uroen
extended arithmetic and logic unit for operation on floating or fixed point number (vii) on-chiP clocl '---t
formats. Like microcontrollers, DSP processors also have on-chip memory, VO al:
Figures 9.1 'a' !
ports, A/D conyerters, and serial ports. They are used in mobile phones, digital
8051, resPectiveit'
cameras, PBX systems, and smart card readers.
In addition tr-a 'ir!€
Chapters 9-12 give a complete idea about the Intel 8-bit microcontroller's
intemrPt caPabilrtrn -'ao
architecture, instruction set, programming, and hardware interfacing. Readers of
The 8051 is an r-ml
these chapters are expected to know the fundarnentals of microprocessors, memory
chip is eight brt-t u:je
structures, and assembly language programming.
address 64KB of mem:
data bus, as in the tl-+: 1

9.2 INTEL'S MCS.51 SERIES MICROCONTROLLERS

multiplexed addres' aad
Intel Corporation has many microcontrollers in both 8-bit and 16'bit configurations. The 8051 is a r--F
The 8-bit microcontrollers are available in many part numbers, with MCS-51 as and the built-rn ;i.li '
the family name. Figure 9.1 shows the various microcontrollers in the MCS-51 connecting the '1 st'r*.
series, with their constituent differences. For example, 8xC5lRD comes with an The four conrr--tl .l!
internal ROM of 64K8, while 8XC51FC comes with only a32KB ROM. shown in Fig' 9.-1 oi Pr
the controller cLuP T:e
for at lea:t rlur rrtr
high
| ,r*r
lr
I I 64KB I
processor to ferh ar.j e:
lexalll6KBllftilllRoMl clock cycles taken fcr r:
lRoMllRoMlllll
I I
t4CRoM_l
t--"1 I I I I I I

8XC51 8XC52 sxCSlFB AXCS1FC BXCS1RD i

8XC51FA BXCSIRB aXCstnc
8XC51RA

Fig. 9.1 Microcontrollers in lntel's MCS-51 series

Table 9. I lists the t'eatures of the 8051 family of microcontrollers.

Table 9.1 Features of the 8051 family of microcontrollers

Device number Data bus width (bits) i RAM capacity (bytas) ROItt capacity

8031 8 128 Nil

8051
8751H
8 t28 4KB
Genetal-
r--
L_-
8 128 4 KB EPROM purpose are€ lP
8052AH 8 256 8KB lro
87528H 256 KB EPROM
tsa
8 8
I sc(
I TC(
All the microcontroller chips listed in Table 9. t have the same basic architecture.
area
lrx
The Intel 8051 is considered for further discussion in the topics that deal with BANK 4 In
instruction set, and software and hardware interfacing in chapters 9-12.
BANK 3 ln
BANK2 ln
r------=
BANK 1 I rr
9.3 INTEL 8051 ARCHITECTURE tntamalRAM SFR

The main features available in the 8051 chips are as follows:

(i) S-bit CPU (ii) 4KB of on-chip program memory
 INTRODUCTIONTO8OSl MICROCONTROLLERS 305

I in hardware and (iiDl28bytesofon-chipdataRAM(iv)fourportsofeightbitseach

)rocessors have an (v) two 16-bit timers (vi) full-duplex serial port
fired point number (vii) on-chip clock oscillator
<hip memory, VO Figures 9.2 (a) and9.2 (b) show the architecture and block diagram
of the
:iIe phones, digital 8051, respectivelY.
In addition these features, the 8051 provides Boolean processing, six
to
t microcontroller's interrupt capabilities, and an 8-bit cPU for control applications.
rtacing. Readers of Th; 8051 is an 8-bit microcontroller, i.e., the data bus within and outside the
So it can
,rocessors, memory
chip is eight bits wide. The address bus of the 8051 is 16 bits wide'
bus is multiplexed with the
address 54KB of memory. The lower-order address
port pins of the 8051 form the
data bus, as in the 8085 piocessor. The port 0 and 2
rnultiplexed address and data bus.
The 8051 is a 40-pin chip' The power supply +V"" and Vr. takes two
pins
ibit configurations.
and the built-in clock oscillator requires two pins (-XTALI and
XTAL2) for
s. q'ith MCS-51 as
in the MCS-51
,ers connecting the crYstal.
The four control signal pins of the 8051 are PSEN, ALE' EA' and RST
as
LRD comes with an
to restart
2KB ROM. shown in Fig. 9.3 on page 307. RST is an active-high reset signal used
high input only if the RST is held
the conrroller chip. The 805 1 ."rpords to an RST
high for at least two machine cycles. A machine cycle is the period taken by any
prlcessor to fetch and execute one instruction. In the 805 1, the maximum number of
at least
;
clock cycles taken for a machine cycle is 12. So the RST pin must be high for
i
I
'l 6.bit address bus
8XC51RD

rollers.

lers

ROll capacity

\il
lKB It l/o
Befleral. lnterrupl
1 KB EPROM purpose area
IP
Counter
PCON
8KB Sarial data
SBUF RDMIR
8 KB EPROM
scoN
TCON
alea
e basic architecture. TMOD
BANK 4
pics that deal with TLO
BANK 3 THO
xers 9-12. BANK 2 TLI

BANK 1 TH1

lniomalMM SFR aroa

rii:ii:i:::r;llriIP;:rr:r{a"l::i tF!*:ii:::rrii::ri!1

Fig. 9.2 (a) 8051 architecture

)rL'r_gram memory
306 MtcRopRocEssoRSANDMtcRocoNTRorLERs

POH)7 P20-P27

V^- ------i c1i.''

.,* l
*I
:
I
I

[-
Program merc:'
I

I
+
-l
Pl 0-P1 7 p3 S+3 7 tnternal (4KB)

Fig. 9.2 (b) 8051 internal block diagram

microeontroller can a'
24 clock periods. PSEN, ALE, and EA are the signals used in conjunction with The user can conrtg'-l
the external memory access of the 8051. They are discussed in detail in Chapters inside antl 60KB trut:
I I and 12. addresses and the er:
data memorY that
'31
9.4 MEMORY ORGANIZATION

in the 8051, the mernory is organized iogically into program memory g.5INTERNAL MM
and data
memory separately. The program memory is read-only rype; the data memory is The 8051 has llS r'
organized as read--write memory. Again, both prograrn and data memories can sometimes as bits. Tl
be within the chip or outside. Figure 9.4 shows the r.arious options available for The address rrf i
memory organization in the 8051. 7FH. The RAN'I -'P't
The Intel 8051 has l28bytes of RAM and 4KB of RoM within the chip. The addressable memon
address bus of the 8051 is 16 bits wide. so it can access d4KR of memory. As the The 805i-has fri
memory is organized separately as program memory and data memory, the 805 I 00H to lliH.In asse
 INTRODUCTIONTOSOS1 MICROCONTROLLERS 307

TZP1.0 n 1 vm
I
T2BJP1.1 I--'l122 P0.0/AD0
-l Ecr/P1.2 q3
3 P0.1/ADl

cEx0/P1.3 q44 PO.UAm

I
I cExl/P1-4 Ej 5 P0.3/AD3

cEx2/Pl.5 I
:lt66
i, PO,4/AD4
l'
I cEx3/P1.6 I--t17 P0.5/AD5

i cEx4/P1.7 -I 8' P0.6tAD6

I *., ilnI P0.7/AD7
I

**r,rr.o F',0
8051 a. EA/vPP
'1 10 Duat in-line
I
I
I
rxolpr.r f1
-1 rr
'11 package 30 ALE

rNTo/P3.2 fl'--1 12
i2 29 PSEN
I
iNTTrpg.s Tl 13
re 28 P2.71A15
I
rolp:a T1 ra14 27 P2.6tA14
I ,,,or.u tr',u
15
.A P2.5iA13
I

l n
wR1P3-6 --1 16 25 P2.4tA12

I RD/P3.7 n1l
17 24. P2.3/A11
I

i
*ru, ilr*18 23 Pz,ANO

I
*r*, il',,
--l n P2.1tAS
t, v$ n2o 21 P2.0/A8
.

: {.ri:.r'. .:
I

I Fig. 9.3 Pin details of 8051 DIP lC

l. lvlemory

I
I

I
I
Program memory Dats memory

-J

tntemal (4 KB) Extffnal {64K8) lnternal (128bytes)

Fig. 9.4 Memory organization in the 8051

microcontroller can access 64KB of program memory and 64KB of data memory.
n conjunction with
The user can configure the entire program memory outside the chip or use 4KB
l detail in Chapters
inside and 60KB outside the chip. The internal data memory is accessed with 8-bit
addresses and the external data memory with 16-bit addresses. So the maximum
data memory that can be connected to the 8051 system is 64KB.

memory and data 9.5 INTERNAL RAM STRUGTURE

he data memory is
The 8051 has 128bytes of internal data RAM, which is accessible as bytes or
lau memories can sometimes as bits. The mapping of the internal RAM is shown in Fig. 9.5.
,tions available for
The address of the internal RAM starts at 00H and occupies space up to
7FH. The RAM space is divided into three blocks-the register banks, the bit-
itbrn the chip. The
addressable rnemory, and the scratch pad memory.
oimemory. As the
The 8051 has four register banks of eight registers each, with addresses from
memory, the 8051
00H to lFH. In assembly language, they are addressed by the names R0-R7. The
 308 MtcRopRocEssoRsANDMtcRocoNTRoLLERS

memory are the registers

only by direct addressine
The registers avaiiablr
(i) Accumulators-.{
(ii) Processor status ui
(iii) YO port registers-
(iv) Data pointers-Dp
(v) Serial dara buffer r,
(vi) Stack pointer-Sp
(vii) Timerregisters-T
(viii) Timer control regis
(ix) Power and porr con
(x) intemrpt controi rer
2f
Programmers should n
2E
,n
the SFRs), as they are used
8051. The 8051 has rno a
2C

2B
accumulator for multiplica
2A can be accessed as a gener
2S The stack in the 8051
28 pointer is eight bits wide ar
When the 8051 is reset, the
26
is incremented before stor
25

24
from the stack, the data is r
23
Table
22

21 Direcladdressad SFR
20 memory address
4
I
Regishr banks
I
I
80 PO
Bit-addressabls
: ;;""::l::,:i::::,::: 81 SP
Fig.9.5 oosr irt.rurRAM 82
register banks are identified.with
map 83
DPL
DPH
two bits in the processor
status word (pSw). 88
I.i[lli,'nfi: if lT,,,r"ilil1"1,,,". uunr, i
",
bank 2, and ll.tepresentsl;rri;." bank
The
bo;;;;,;,,.
0, 01 89
TCO
T]10
In the g051, bir*ir..p."rents 8A
operations are also possible TLI:)
the birrdd;;;;;ile rith;;;;iistructions using 8B TL1

fi ,I;kl:J[H,l*r;l,TH:]",ffil:%i,i:r,:[T**jl:[fl",ff
general-purpose
'f 8C
8D
IHLi
THl
,^_^U_r]r, scratch pad memo
data at any time roi unv programmers can
to the address 7FH.
,r;;.:";"";::'^':-t'y'
y purpose' This memory read and write
ranges from the byte
9.5.2 Processor Status Won
address ;lOH
The PSW contains all the flz
9.5.1 Special Function of this flag register is gir en
Registers
special function registers are seven flag bits in the pS
(sFRs), which occupy
the upper I 2g bytes bit register, with the address
of the internal
 INTRODUCTIONTOsosl MICROCONTROLLERS 309
tl

IT
memory are the registers that control the entire processor. They can be accessed
only by direct addressing. The common sFRs are listed in Table 9.2.
*
The registers available in the 8051 are as follows:
i (i) Accumulators-A and B
Ii'
I
t
(ii) Processor status word-PSW
'*r
(iii) VO port registers-P0, PI,PZ, and p3
(iv) Data pointers-DPH and DPL
(v) Serial data buffer register-SBUF
(vi) Stack pointer-SP
(vii) Timer registers-TH0, THI and TL0, TLI
(viii) Timer control registers-TCON and TMOD
(ix) Power and port control-PCON and SCON
(x) intemrpt control registers-Ip and IE
Programmers should not use the addresses in the range g0H-FFH (other than
the SFRs), as they are used by Intel corporation for expanding the functions of the
8051. The 8051 has two accumulators-registers A and B. Register B forms the
accumulator for multiplication and division instructions; for other instructions it
can be accessed as a general-pu{pose register.
The stack in the 8051 is organized within the internal RAM area. The stack
pointer is eight bits wide and has to be initialized with an address in the RAM area.
s when the 8051 is reset, the stack pointer is by default set to 07H. The stack pointer
is incremented before storing a data in the stack. similarly, while readin g data
from the stack, the data is read first and then the stack pointer is decremented.

Table 9.2 Special function registers of 80Sl

Direct address€d SFR Dirccladdressed .SFR.

rnemory address mornory addiers
"' .',., .

I
I
80 PO 90 P1
I 8l SP 98 SCON
:*o- 82 DPL 99 SBUF
83 DPH AO P2
88 TCON A8
S\l'r. The IE
rnk I,t. Ql 89 TMOD BO P3
8A TLO B8 IP
rns using 8B TL1 DO PSW
rom 0fJH 8C THO EO ACC
elptul in 8D THI FO B

nd urite 9.5.2 Processor Status Word

ess -1[]H The PSW contains all the flags of the g05l and is eight bits wide. The bit pattern
of this flag register is given in Table 9.3. From the table, it can be seen that there
are seven flag bits in the PSW of the 8051. The pSW is accessible fully
as an g_
bit register, with the address D0H. Meanwhile, individual bits of the pSW can be
intemal
 310 MtcRopRocESSoRSANDMtcRocoNTRoLLERS

accessed with the bit addresses given

in Table g.3. The contents of the pSW the accumulator and register
reset are given in the third row. upon
bits of the accumulator and r

Table 9.3 pSW format

of g0S1 Table 9,5 (a)

PSW Cy AC F0 RSI RSO OV _P

Bitaddnss Accumulatorbib ACC.:
DlH D6H D5H D4H D3H DZH DlH DOH
Contents upon reset 0 0 0 ooo x0 Bit addross E7

Parity bit (P) It is set to 1 if the accumulator contains

an odd number Contents upon nsst 0
an arithmetic or logical operation.
of 1s, after

overflow flag (ov) flag is set during ALU operations, to indicare

Thi:
in the result. It is ser to-r overflow Table 9.5 (b)
if there is
a carry lut of either the D7 bit or
the D6 bit of
the accumulator. overflow flag is set
when arithmetic operations such as add
subtract result in sign conflict. and
The conditions under which the OV flag
is set are as follows:
Positive + positive =Negative
Negative + Negative = positive
Positive -Negative = Negative
ConhnBuponreeet 0 t

Negative - positive = positive

9.6 POWER CONTROL IN 8
Register bank select bits (RS, and RSl)
These bits are user-programmabre.
They can be set by the programmer to point The 8051 has various power
to the correct register banks. The
register bank selection in the programs consumed by the microcontr<
can be changed using thJse iwo bits.
Tabre 9.4 explains how these bits can go into a 'sleep'mode, whic
be changed to ilect the appropriate
register bank. operation. The power contn
Register PCON" Table 9.6 gi
Table 9.4 Register bank selection using pSW
Table 9.(
RSI RS0 Selec{ed bank Address range
Bit Name
0 0 Bank 0 00H-{7H
0 1 Bank I 7 SMOD
O8H-OFH
I 0 Bank 2 6
r0H-17H
I I Bank 3 5
I8H-IFH
4
General-purpose flag (F0) This is a user-prograrnmable J GF1
program and store any bit of his/her flug; th" user can
choice in this flag, using ,rr" ii 2 GFO
address.
Auxiliary carry flag (AC) It is used in I PD
association with BCD aritrrmetic.
flag is set when there is a carry out This
of the D3 bit of the accumurator. 0 IPL
carry flag (cy) This flag is used to indicate
the carry generated after arithmetic 9.6.1 ldle Mode
operations. It can also be used as
an accumulator, to store one of The microcontroller enters tt
bit-related the data bits for
Boolean instructionsl
the idle mode, the clock pul
The 8051 supports bit manipulation
instructions. This means that in addition units such as intemrpt contr<
to the byte operations, bit opeiations
can arso be done using bit data. For are not affected in the idle mo
purpose, the contents of the pSw this
are bit-addressable. similaily, the by applying either a hardu'a
contents of
 INTRoDUCTIoN To 805,I MIcRocoNTRoLLERS 311

rc PSW upon the accumulator and register B are also bit-addressable. The bit addresses of all the
bits of the accumulator and register B are given in Tables 9.5 (a) and 9.5 (b).

Table 9.5 (a) Addresses and contents of accumulator bits

P' ICCUMuIaIoTUT ACC.1: ACC.6: ACC.5 ACC.4: ACC.3] ACC.2. ACC.I ACC.O
irn DoH
,0r Btry: E7 :, E6 , E5 , E4 E3 E2 El E0

er of ls, after Contentsuponncet}00:0001

ate overflow Table 9.5 (b) Addresses and contents of register B bits
rhe D6 bit of
h as add and Reglster B btrs 8.6 B.5 B.4 8.3 B.l B.0

Blt address F7 F6 F4 F3 lFz FI FO

Conhntruponrcsot 0

9,6 POWER CONTROL IN 8051

prammable.
The 8051 has various power control modes, which are used to control the power
banks. The
consumed by the microcontroller chip. Some of these modes let the microcontroller
o bits. go into a 'sleep'mode, which makes it consume lesser power than during normal
appropriate
operation. The power control modes are selected through the Special Function
Register PCON. Table 9.6 gives the bit patrern of the pcoN register (g7H).

Table 9.6 Bit pattem for PCON (87H) register

Bit ilame Funcdon

7 SMOD Serial port baud rate set bit

6- Reserved
5- Reserved
4- Reserved

E USer can
3 GFl General-purpose flag I

ldress. 2 GFO General-purpose flag 0

lPD Power down mode set bit
metic. This
O IPL Idle mode set bit

rarithmetic 9.6.1 ldle Mode

hta bits for The microcontroller enters the idle mode whenever the pcoN.0 bit is set to l. In
Y the idle mode, the clock pulses applied to the cpu are masked, while all other
in addition units such as intemrpt controllers, etc. are kept active. The contents of the cpu
a. For this are not affected in the idle mode. The processor can be revoked from the idle mode
:ontents of by applying either a hardware intemrpt or a hardware reset siglal. These two
 312 MtcRopRocEssoRs AND MtcRocoNTRoLLERS

actions will reset PCON.O and processor execution will resume at the instruction
following the instruction that set the idle rnode.

9.6.2 Power Down Mode

Datamemory It is a read
The power down mode is initiated by making pcoN.l Flags These are the bis u
bit 1. In this mode, the
clock generator is switched off and only the internar logical operations.
memory is active. The supply
voltage v.. can be reduced to 2 v and the power consumption can be reduced. The Processor Status Word (P
only way to revoke the processor from power down used to indicate the starus of
moJe is to reset the system.
Program memory It is a r
9.7 STACK OPEMTION Special Function Registers
for specific functions and cor
In the 8051, the stack is configured as a series of memory
locations folrowing the
Last-In First-out (LIFO) pattern. In general, the stack
is initialized in the internal
RAM area. Any 8-bit data can be stored and retrieved from the
stack using pusH
and POP instructions, with the help of the stack pointer.
The stack pointer (SP) is an 8-bit register witrrin the
81H. This register can hold one g-bit address at a time,
sFR area, with the address l. Differentiate between m
which is actually the 2. Why are microcontrolle
memory location at top of the stack. A push operation
in the g051 is used to store 3. How does the 8031 difft
an 8-bit data in the stack. The pUSH instruction
first increments the value of sp and
then stores the data mentioned in the instruction 4. Write the format of the I
in the mernory location pointed
to by SP. similarly, the pop instruction stores the varue 5. What is a special funcu<
from ,h" ,op of the stack
in the register mentioned in the instruction and then decrements 6. Which port of the 8051
the value of sp.
The stack pointer is initialized to the value 07H when
the g05l microcontroller is
7. What is the function of I
reset. The other instructions of the g051 that affect
the stack and the stack pointer 8. What is the address rang
are ACALL, LCALL, RET, and RETI. The stack pointer 9. Write a note on memorJ'
can be initiarized to any
internal RAM address the prograrnmer, by writing the required address 10. Draw
SP SFR address 8lH.
\r in the and explain the an

fl 11. How can you put the 80:

12. Explain the stack operat

Intel MCS-51 is a family of microconkollers and g05l

is the familiar IC in the
family. Different versions of the basic g051 are available 1. Find the contents of the fl
from Inter and other chip
manufacfurers. and 11000101B.
The 8051 is an S-bit microcontrolrer with built-in
RAM, uo ports, timers, and intemrpt 2. Write the binary word to
facility. bank 2 in the internal RA.\
The functioning of the microcontroller is conkolled
using a set of registers called special 3. Give at least two example
function registers (SFRs). 4. What does a '0' in the zen
The 8051 can itself act as an independent system,
with all memory and ports inside it.
Ifnecessary, memory and UO ports can Ue
aOaea externally.
The processor supports many operating modes
such as power down mode, idle mode,
etc.
rntioned in the

:tlon.
I !,r the contents
HARDWARE FEATURES OF BO51
LEARNI}IG OUTCOiJiES
After studying this chapter, you will be able to understand the following:
. Structure, addresses, and operation of 8051 ports
. Extemal memory interfacing in the 8051
. Features, op€ration, and programming of 8051 timers

the instruction.
. lnterrupts in the 8051, their sources, priorities, and timing

ls ior each.
. Features, operation, and programming of 8051 serial port

ruetions of the

11.1 INTRODUCTION

memory to the
The major benefit of microcontrollers lies in their built-in parallel ports' The
parallel ports can be used to interface all data converters (ADCs, DACs, etc.) and
display devices (LEDs. LCDs, etc').
Any microcontroller-based system needs to transfer data between the external
peripherals and the microcontroller. The microcontroller needs to read data fed
DDC. When is by the user from the external interface, process it, and give the output to the
peripherals or to the user again. To comrnunicate data with the external world, the
microcontroller needs ports. The ports may support either parallel or serial data
transfer.

I !tr)re the result 11.2 PARALLEL PORTS IN 8051

lmemory.l
The 805 i has four VO ports-port 0, port 1 , port2, and port 3. The major constraint
. br the number
H in microcontroller chips is the number of pins. To reduce the number of pins, the
\t Identify and pins allotted for parallel ports are assigned some alternative functions as well.
Out of the four parallel ports available in the 8051, port 1 is used exclusively for
br. input and output functions. The other port pins have functions other than input and
output. So, the 24 pins of ports 0,2, and 3 perform functions other than parallel
data transfer. These functions are decided by the hardware interfaced and the
instructions being executed.
All the four ports are bidirectional, i.e., they can be programmed to perform
t3cution of the
input or output operation. The eight port pins are connected through eight D-type
tre same SJMP
port latches. A D-type latch connects the data in it to a port pin, when the port is
used as an output port.
The user can access all the four ports using their addresses mapped in the
special function register (SFR) area. Tables 11.1 (a) and 11.1 (b) list the SFR
addresses of the parallel ports and the addresses of the individual parallel port
pins, respectively. Note that it is possible to address individual bits of all the four
 330 MtcRopRocESsoRSANDMtcRocoNTRoLLERs

ports by their bit addresses. Using these bit addresses, individual

bits can be read
or changed.

Table 11.1 (a) Addresses of paraltet ports of 9051

Port Byte address Port Byte address

Port 0 80 Port2 AO vz
Port I n33r
90 Port 3 BO
,-4 U-
(b)
n_
Table 11.1 Addresses of paraltet port pins of g051 I
x:

Porl plns

Port 0.0
Bit address

80
Port pins

Port 2.0
Bit address

AO
H. l lssrt

Port 0. I 8l Port2.1 A1
Port0.2 82 Port2.2 A2
Port 0.3 83 Port 2.3 A3
Port 0.4 84 Port2.4 A4
Port 0.5 85 Port 2.5 A5
Port 0.6 86 Port2.6 A6
Port 0.7 87 Port2.7 A7
Port 1.0 90 Port 3.0 BO
Port 1.1 9t Port 3.1 B1
Port 1.2 92 Port 3.2 B2
Port 1.3 93 Port 3.3 B3 Frs
Port 1.4 94 Port 3.4 B4
Port 1.5 95 Port 3.5 B5
Port 1.6 96 Port 3.6 B6
Read latdt
Port 1.7 97 Port3.7 B7

Figure I 1. I shows the parallel ports in the g05 1 and their pins.
lnternal bus
11.2.1 Structure of port 1
Vllrite to laldr
Port 1 is the only port in the g051 that is used exclusively
for input and output
operations. The structure of port 1 is shown in Fig.
r1.2. The output of the port
latch is connected to the port pin through a transistor
driver with an internal pulr-
up resistor. The port can be operated as an input port Read pin
after writing the data .1, in
all the bits of the port I latch.
The 8051 ports are organized such that most instructions
read the data from the
pin for the read operation and some read the data from
the latch. So, to distinguish
between these instructions, the input buffer contains
the select logic and the related
control signals-Read latch and Read pin. 11.2.2 Structure of Porfi
Pins of ports 0 and 2 c
corresponding port latch
 HARDWARE rrnrunEs or eost 331

ual bits can be read

P0.0/AD0
P0,1/AD1
P0.2lAD2
P0.3/AD3
c2

.4
P0.4/AD4
PO,s/AD5
PO,6/AD6

I
P0.7/AD7

l----n
Bt address
t2
+cl
P2.0/AD8
P2,1/ADg
P2.2lAD10
P2.3/AD11
AO
P2.4lAD12
P2.s/ADt3
AI
P2.6/A014

A2 P2.7/AD15

A-1 P3.0/RXD
P3,1,TXD
.\+ P3.2/iNTf
P3,3/iN7i
A5 P3.4n0
P3.5ff1
A6 pa.offiF
pe.rfiD
A7
BO

BI
B:
B3 Fig. 11.1 Parallel ports and port pins of 8051

BJ
V".
B5

B6 Read lalch

B7

f,n s. lnlernal bus

Write to latdr

x input and output

: output of the port
ith an internal pull- Read pin
iting the data'f in
lnput buffer Latch OuQut drivsr

rd the data from the

Fig. '11.2 lnternal structure of port 1
r. So, to distinguish
ogic and the related 11.2.2 Skucture of Ports 0 and 2
Pins of ports 0 and 2 can be used as input port pins if a 'f is written in the
corresponding port latches by the programmer. For using the pins of ports 0 and
 332 MIcRoPRocESSoRSANDMIcRocoNTRoLLERS

2 as output pins, a pull-up resistor may have to be connected to

the corresponding
port pins. The internal structure of port 0 is shown in Fig.
1 1.3.
ril
Addr/Data
::
Road latch :'-' -

:_'_'

:: <

-/: -

The interni ::*-a

lnpul buffer Latch output driver
it can be unils--i---r
data'l rs '\:-.-: f
Fig. 11.3 lnternal structure of port 0

Besides input and output, ports 0 and2have an alternative function-they

can
be used as address/data bus when external memory or I/o devices
are accessed. Rfgc
Port 0 acts as the lower-order address bus and port 2 acts as the
higher_order I
address bus. The drivers of ports 0 and 2 have an intemal
multiplexer for this I
purpose. The intemal structure of port 2 is shown in Fig. I
1 1.4. I

lnte.ca IE

Read latch
Wrl€EG
--l I
I
rc-
-t

\\'rth resp.e,.-: :,.

The read rn-.inL-xo!
difference ls rnrje i
hput buffer Latch
Output driver
of the r olnee ie r el
data. and'*nte tire d
Fig. 'll ,4 lnternal structure of port 2 latches and not the p
11.2.3 Shucture of Port 3 the port pins onll E

Port 3 is different from the other ports in the aspect ANL 01. :
that its individuar port pins 92, :
can be programmed forinput and output operations. ORL
Each pin of port 3 can be
programmed separately for input operation, output AKL -i. -
operation, or other alternative -
functions. The alternative functions allotted to I ri -
port 3 pin
"u"t bared on are given in
Table 1L.2. All the port 3 pins serve an alternative function, Dt.: :-
the hardware 't:- :' -:
signals and interfacing.
cD- :i.,
 HARDWARE FEATURES OF 8051 333

he corresponding Table 11.2 Alternative functions of port 3 pins

Port pin Alternative function

v_
P3.0 RXD-Serial input data line
l P3.1 TXD-Transmit data line
P3.2 INT0-External intemrpt 0
ri P3.3 INTI-External intemrpt I
P3.4 T0-Timer 0 external input
P3.5 Tl-Timer 1 external input
P3.6 WR-External data memory write strobe
P3.7 RD-External data memory read enable

The internal structure of the port 3 pins is shown in Fig. 11.5. From the figure
i*, it can be understood that the alternative functions can be activated only if the
data 'f is written in the port 3 bits.

nction-they can
ces are accessed.
the higher-order
iltiplexer for this

,_
I
I
L
hemalpull-up
irB*tor

Allemate inDut
lnput buffer Latch
function Output driver

Fig. 1 1.5 lnternal structure of port 3

With respect to port access, there are two possibilities for the read operation.
The read instruction for a port can read either the port latch or the port pins. This
difference is made in the internal hardware of the 8051, to avoid misinterpretation
l€t
of the voltage level at the pins. Some of the instructions read a port, modify the
data, and write the data back into the port. These instructions read the data from the
latches and not the pins. All other instructions accessing the ports read the data from
the port pins only. Examples of instructions that read the port latch are as follows:
ANL P1, A
ir idual port pins ORL P2, A
of port 3 can be XRL P3, A
other altemative ]NC PO
rin are given in DEC P1
on the hardware JBC P1.1, DELAY
CPL P3.O
334 MIcRoPRocEssoRs AND MIcRocoNTRoLLERs

DJNZ P3, LABEL Connecting the E

CLR P3. 1 microconffoller tc-' ug
SETB P1.2 at 0000H. Arter the a
M]u P2.2, C mqory is accEssed
Note that these instructions read the port, modify the contents, and then write If EA: 0, the internal
the data back into the port. Hence, the port latches are read and not the pins. If EA: l, the rnternal
OFFFH (or the avarlab
11.3 EXTERNAL MEMORY INTERFACING IN 8051 addresses greater than

External memory interfaced with the 8051 can be of two Example ll.l:
ffies---external program
memory and extemal data memory. External memory accesses are accomplished Design an interface cr
with ports 0 and 2 of the 805 1, as they serve as the multiplexed address/data buses.
The external memory in the 8051 is always accessed with l6-bit addresses. The Solution:
805 1 outputs the ALE (address latch enable) signal to de-multiplex the lower-order
As the 27128 has 161
address and data bus. In addition, the microcontroller sends the control signals
select one memory lo
on address range for the r
the port 3 lines.
as 0000H-3FFFH. Th
11"3.1 Program Memory lnterfacing select the chip. For de
In addition to the internal program memory additional program memory The 74139 has a du,l
can
be placed outside the chip. In another method, the entire program memory EPROM chip. The co
can be
placed outside the chip, neglecting the internal program memory. Applying register IC 74373 is u
the
proper voltage level on the input line EA of the g05l can select one of these OE is the data read er
two
methods. output of the 8051.
connecting EA to the gro,nd will disable the internal program memory; only the
external program memory will be accessible. The Read strobe signal given
by the
microcontroller is PS-EN. This active low signal is connected to the Read selection
line of the memory chips. Figure 11.6 shows the hardware signal connections m
for Ful
such a memory interface to the 8051.
AE
8051

'lwqq,w.@&rwe.r-i,.e

Fig. 11,6 lnterfacing external program memory to g051

F;
 HARDWARE renruRrs or aosr 339

diagram in Fig. 11.10 (a), the memory access for the data memory can be started
.-l in the fifth state, 55, of a machine cycle and completed in the fourth state, 54, of
the next machine cycle.
ls1 The external memory read access also follows the timing diagram given in
Fig. I l.l0 (b) with the control signal WR replaced with RD. The data is rransferred
from the memory devices to the microcontroller. The active low RD signal is sent
out through the P3.7 line.

f-
a.48051TIMERS
The basic Intel 8051 has two l6-bit timers. These timers are accessible to the
programmer through the corresponding SFR registers. They can be initialized,
run, read, and controlled by these registers. The 8051 timers have three general
functions:
(i) Producing a delay for a definite time and then issuing an intemrpt request
(ii) Counting the transitions on an external pin
(iii) Generating baud rates for the serial port
Basically, timers are digital counters that are incremented when a pulse is given
to them. They can be controlled to do any of their functions, using four SFRs-
TMOD, TCON, THO/TL0, and TH1/TLl. A timer overflows when it counts ro
the highest value and resets to 0 on next count. The overflow in the timers sets
the two bits in the TCoN sFR. This overflow can be programmed to interrupt the
microcontroller execution and execute a predefined subroutine.
If the timer registers are incremented by the internal clock pulses from the
microcontroller, the operation is called timing.If the timer registers get their clock
pulses from an extemal device through the port 3 pins of the 8051, the operation
is called counting. Timer 0 external input pin p3.4 (T0) is used to give clock input
to timer 0 to act as a counter. Timer 1 external input pin p3.5 (T1) is used to give
clock input to timer 1.

11.4.'l Timer SFRs

The 8051 has two timers, both of which have similar operations and functions.
The timer in the 8051 is basically a 16-bit register, which can be incremented
based on the clock pulses applied to it. These timer registers are configured as
SFRs. one timer is Timer 0 and the other is Timer 1. Each timer has two g-bit
SFRs. THO and rLO form the higher- and lower-order bytes of rimer 0; TH1
and rl-l form the higher- and lower-order bytes of rimer 1. These SFRs, at any
time, have the timer/counter register content. so, the timers can be stopped at any
7 time and the contents can be read from these registers. As the timers have 16 bits,
ilng diagram for
the timer content/count value can vary from 0 to 65,535. The timer content will
become 0 after counting up to 65,535. This is called as overflow. The overflow
will be indicated by the setting of the timer overflow intemrpt flag.
is sent by the The two timers share two SFRs for control-the TMOD and rcoN registers.
r access timing Table 11.3 shows the timer-related SFRs and their addresses.
 340 MtcRopRocEssoRSANDMtcRocoNTRoLLERS

Table'11,3 SFRs related to timers

TabL

SFR name Descrlption SFR address Bir l{ame Bit

THO Timer 0 higher-order byte 8CH addl
TLO Timer 0 lower-order byte 8AH TFI SFH
THl Timer t higher-order byte 8DH
TLI Timer 1 lower-order byte
TRI 8EH
8BH
TCON Timer control 88H
TMOD Timer mode 89H D5 TFO 8DH

TMOD SFR
D4 TRO 8CH
The TMoD sFR in the 8051 controls the timer operation. The TMOD register
bits
are used to select the timer operating modes, counting or timing operation,
and
gate control. The higher-order four bits are used for Timer 1 and the lower_order
four bits are used for Timer 0. The individual bits of rMoD have the functions The higher-order four b
shown in Table 11.4. lower-order four bits an
Note that the individual t
Table 11.4 Bit patterns for TMOD (89H)SFR
bit addresses. This allou,
D5 instructions and check t}
D7 D6 II4 D3 D2 D1 D(l

GATEl C/T1
TI TI
GATEO
TO TO 11 .4.2 Timer Operati ng I
Ml MO
C/TO
Ml MO The two 16-bit timers of
1---count l- count Mode set 1--count 1- Mode set selection can be done b,
only if puises on 00-13-bit only if INT0 count modes of operation are u
00--13-bit
INTI pin the pin T1 timer pin (P3.2) pulses timer
(P3.3) (P3.s) input is high Tab
on the
input is 01-16-bir p1n 01-16-bit
high 0----count timer 0-count r0(P3.4)
TxMl Til
timer
on every regardless of 0 0
0---count machine 10-8-bit INT0 pin 0- 10-8-bir 0 I
regardless cycle auto reload count auto reload
of INTI mode on every I 0
mode
pin
machine 1 I
1l-Split cycle 1l-Split
timer mode timer mode Mode 0-13-bitTimer Ho
For each timer, two bits are used to specify the mode of operation. Timer mode 0 is a l3-bit
So each timer
can be operated in any one of four modes. are used. Five bits of the
are used in mode 0. The lr
rcorvsFR
is incremented from 31. it
The SFR that controls the two timers and provides valuable information contain 8192 values from
about
them is TCON. The TCON SFR bit pattern is given in Table Figure 11.11 shows h
11.5.
explained earlier, the time
as a counter with external
for Timer 0 and D6 bit of
 HARDWARE FEATURES OF 8051 341

Table 11.5 Bit patterns for SFR TCON (SSH) SFR

Bit Name Bit Explanation of function Timer

address

D7 TFI 8FH Timer 1 overflow-The microcontroller sets

this bit when Timer 1 overflows.
D6 TRI 8EH Timer 1 run-The microcontroller turns on
Timer 1 when this bit is set. When this bit is
cleared, Timer 1 is turned off.
D5 TFO 8DH Timer 0 overflow-The microcontroller sets
this bit when Timer 0 overflows.
D4 TRO 8CH Timer 0 run-The microcontroller turns on
D register bits Timer 0 when this bit is set. When this bit is
peration, and cleared, Timer 0 is turned off.
e lower-order
the functions The higher-order four bits of the TCON SFR are described in Table 11.5. The
lower-order four bits are related to intemrpts and are explained in section 11.5.
Note that the individual bits of TCON regisrer can be addressed separately by their
bit addresses. This allows the programmer to run the timers using bit-addressable
instruclions and check the overflow independently.
Dl D()

TO TO 11.4.2 Timer Operatlng Modes

}T1 MO The two 16-bit timers of the 8051 can be operated in any one of four modes. Mode
\tode set selection can be done by seuing the proper bits in rhe TMOD sFR. The basic
m-13-bit modes of operation are tabulated in Table 11.6.
timer
Table 11.6 Operating modes of 8051 timers

0l-16-bit TxMl TxM0 Timermode Description of mode

trmer
0 0 0 l3-bit timer
l0--8-bit 0 I 1 16-bit timer
auto reload
I 0 2 8-bit auto reload
mode
1 I J Split timer mode
t l-Split
rimer mode Mode Fl3-bitTimer Mode
Timer mode 0 is a 13-bit timer. of the 16 bits available for the timer, only 13 bits
io each timer are used. Five bits of the lower-order byte and eight bits of the higher-order byte
are used in mode 0. The lower-order byte TL0/1 counts from 0 to 31. when TLO/I
is incremented from 31, it resets to 0 and increments TH0/1. So the timer can only
mation about contain 8192 values from 0 to 8191.
Figure 11.11 shows how the timer of the 8051 is operated in mode 0. As
explained earlier, the timer can be operated as a timer with internal clock pulses or
as a counter with external clock pulses. This selection is done by D2bit of TMoD
for Timer 0 and D6 bit of TMOD for Timer 1, as shown in Table 11.4.
342 MtcRopRocESSoRS AND MIcRocoNTRoLLERS

For exampie. let us ;

FEH. At the nert cLruntlr
next pulse, the TLO u rll o
T1 pin
TLO will be loaded rr rtlr r
change. TH0/1 is set to :
incremented. The autt-r rel
tNn pm
rate for serial communr--a
Timer operation ln m(
Fig. 11.11 Mode 0 operation of Timer 1 of 805'1 are shown in Fig. I l.l -r.

The clock pulses selected by D2 and D6 bits of TMOD are then controlled by
programmer setting and connected to the timer registers. The control is done by
three different means. The first is the Timer Run control bits D4 and D6 of the
TCON register. The timer will run only when the Timer Run control bits are set
T1 pin
to 1. Other controls for the timer are through the GATE control bits D4 and D7 of
TMOD and the extemal inputs for the timer. Setting GATE to 1 allows the timer
to count only if the external control input INT0 or INT1 is set to I. Setting GATE ffiprn
to 0 will disable the corresponding external timer control inputs INT0 and INTl.
Setting the timer to mode 0 will make it overflow back to zero, after 8192
Fir .l1

counts. This will set the TFI and TFO bits for Timer 1 and Timer 0, respectively.
Mode 3-SplitTimq llodl
Mode 1-1 6-bit Timer Mode
The operation Lri lhc Li:cl
In timer mode 1 of the 8051, each timer is operated as a 16-bit timer. This is a
timer is a splrt trr:e: .'-,-.J
very commonly used mode. It functions just like mode 0, except that all 16 bits are
operated in molle -:. :: srs
used. As mode I uses 16 bits, the counter will count from 0 to 65,535. 'fhe clock
is TLO and Timer i r. TI
pulses are applied to the lower-order eight bits and the overflow from this lower-
to 0.
order tryte will be counted by the higher-order byte.
Tinier operation in mode 1 and control of its gating are similar to mode 0, as
shown in Fig. 11.12.

T0 pin

tNTpin
T1 pin

tNTt pin

Fi1.11.12 Mode I operation of Timer 1 of 8051

Fig.ll
Mode 2-8-bitTimer Auto Reload Mode
Timer mode 2 is an 8-bit auto reload mode. When a timer is in mode 2,THDll In mode 3, all the birs
holds the 'reload value' and rL0/1 is used as the timer. Thus, TL0/1 starts counting count and do not run. Ttx
up. Overflow from TL0/1 after counting up to 255 sets the bits TF0/1 in TCON timer mode of Timer 0. th
register and also reloads the timer register TL0/1 with the contents of TH0/1. The stopped, since the related c
reload does not affect TH0/1 and leaves it unchanged. this case, will be incremen
When two separate tim
 HARDWARE FEATURES oF Bosl 343

For example, let us say THO holds the value FDH and TLO holds the value
FEH. At the next counting pulse, TLO will be incremented to FFH. Then for the
next pulse, the TLO will overflow and will become 00H. As it is in reload mode, the
TLO will be loaded with the value in TH0, i.e., FDH. The value of THO will never
change. TH0/1 is set to a known value and TL0/1 is the SFR that is constantly
incremented. The auto reload mode is very commonly used for establishing a baud
rate for serial communications.
Timer operation in mode 1 and control of its gating are similar to mode 0, and
are shown in Fig. 11.13.

rontrolled by
rl is done by
nd D6 of the
>l bits are set
T1 pin
)-l and D7 of
ru s the timer
ettrng GATE lNTi pin

ttand INTl.
r. after 8192 Fig, 11.13 Mode 2 operation of Timer 1 of 8051
respectively.
ll{ode 3-Sp lit Timer Mode
The operation of the timers in mode 3 is shown in Fig. I 1. 14. Mode 3 of the 805 1
rer. This is a
timer is a split timer mode and is applicable only for Timer 0. When Timer 0 is
all 16 bits are
operated in mode 3, it essentially becomes two separate 8-bit timers, i.e., Tirner 0
l-i. The clock
is TLO and Timer 1 is TH0. Both timers count from 0 to 255 and overflow back
m this lower-
to 0.

.o mode 0, as

T0 pin

tNTo pin

Fig. 11.14 Mode 3 operation of Timer 0 of 8051

In mode 3, all the bits that are related to the real Timer 1 simply hold their
rde 2. TH0/1
count and do not run. The situation is similar to maintaining TRl at 0. In split
nrts counting
timer mode of rimer 0, the real rimer 1 (i.e., TH1 and rL1) cannot be started or
0,'l in TCON
stopped, since the related control bits are now linked to TH0. The real Timer 1, in
f TH0/1. The
this case, will be incremented every machine cycle.
When two separate timers, in addition to a baud rate generator, are required in
3U MlcRopRocESSoRSANoMtcRocoNTRoLLERS

an application, the real Timer 1 can be used as a baud rate generator and TH0/TL0 11.4.4 Using Timers as Cc
can be used as two separate timers in mode 3. Timers in the 8051 can be
practice, these pulses can I
11,4.3 Timer Control and Operation
a conveyor belt can gir e o
For timer operation (C/T = 0 in TMOD), the timer register counts the divided- pulse can be counted br
down clock. The timer register is incremented once every $OSCll2) in standard sensor can be given as an ,
mode. If the clock frequency is 1,10,59,000kH2, the counter will be incremented timer can be programmed
at the rate of (1,10,59,000kJ12112) = 9,21,583kH2. This means the counter will For example, after counrin
be incremented 921,583 times in a second. Thus, to produce a delay of, say, 0.1 in the timer, an intemtpt n
seconds, the counter must be initialized to the count value (0.1 x 92I,583) = another action such as pac
92158. The 8051 microcontrol
For counter operation (C/T = 1), the timer register counts the negative transitions applied on the externai pr
on the T0/T1 external input pin (altemative function of port 3). The external input
microcontroller will scan
is sampled every clock cycle. When the sample is high in one cycle and low in the cycle, i.e., every 12 clock
next, the counter is incremented. Since it takes two cycles to recognize a negative pulse input, the microcont
transition, the maximum count rate is (FOSC/24) in standard mode. So, the maximum frequer
The following steps describe the algorithm to initialize and use a timer in the microcontroller is I/24 of
8051. The algorithm is shown in the form of a flowchart in Fig. 1 1.15. maximum frequency that c
(i) Decide what mode the timer should be in. frequencies, the microcont
(ii) Initialize the TMOD SFR.
(iii) Write the timer value into the timer 1 1.4.5 Programming Exam
register. In this section, we shall di:
(iv) Start the timer by setting the TR0/1 bit
in the TCON register. Example 11.3:
(v) Check for TF0/1 bit or program to Write a program to genera'
handle timer overflow as an intemrpt port pins, using Timer 0. ar
and execute intemrpt subroutine. t2MHz.

To set the bit TR1 of TCON (D6 bit), any one Solution:
of the following two commands can be used: As a continuous square u'a'
MOV TCON, #40H or SETB TR1 is selected for this operario
As TRl is a bit-addressable location, SETB by 12, the counter will get
instruction is used. This has the benefit of will be incremented after e
setting the TRI bit of TCON without changing To generate a square
the value of any other bit of the SFR. (llZkHz). This means th;
There are two common ways of reading the 250prs and logic 0 for anor
value of a 16-bit timer: be generated. Here, as the
(i) Read the actual valueof the timer as
counter has to count up to -
a 16-bit number from THO/TLO or During an overflow, the lo
THl/TL1. Fig. 1 1 .15 Steps in timer control continuously, a square u'av
(ii) Detect when the timer has overflowed, from the TF0/1 bits of TCON. If This program uses rhe p
TFO is set, it means that Timer 0 has overflowed; if TFl is set, it means occurred. The LSB ofporr
that Timer t has overflowed. This overflow can act as an interrupt and can N10V TM0D, /100000010B :

directly run an interrupt service routine, if enabled properly. CLR TFO :

 HARDWARE FEATURES OF 8051 345

LO 11.4.4 Using Timers as Counters

Timers in the 8051 can be programmed to count pulses from external devices. In
practice, these pulses can be due to any event. For example, a sensor placed along
a conveyor belt can give one pulse for every object moving on the conveyor. This
ed- pulse can be counted by the 8051 timer in counter mode. The pulses from the
ard sensor can be given as an external input to a timer and programmed to count. The
Ied timer can be programmed to produce an intemrpt after a predefined count value.
r ill For example, after counting 12 objects in the conveyor or after counting 12 pulses
0.1 in the timer, an interrupt may be given to the 8051 system to produce a signal for
l= another action such as packing the 12 items. Example 11.5 explains this concept.
The 8051 microcontroller timers when operated as counters, can count pulses
ons applied on the externai pin P3.4 in Timer 0 and on pin P3.5 in Timer 1. The
Put microcontroller will scan the voltage levels on these pins after every machine
the cycle, i.e., every 12 clock cycles. To detect the rise and fall on these pins as a
tr\ e pulse input, the microcontroller requires 24 clock cycles or two machine cycles.
So, the maximum frequency of the extemal pulses that can be counted by the
the microcontroller is I/24 of the system clock frequency. For the lZMHz clock, the
maximum frequency that can be counted is 5,00,000 pulses per second. For higher
frequencies, the microcontroller cannot count accurately.

1 1.4.5 Programming Examples

In this section, we shall discuss some programs involving 8051 timers.

Example 11.3:
Write a program to generate a square wave of frequency 2kHz on any one of the
port pins, using Timer 0, assuming that the clock frequency of the 8051 system is
l2MHz.
Solution:
As a continuous square wave has to be generated, the 8-bit timer auto reload mode
is selected for this operation. Since the clock frequency is 12 MH z, after dividing
by 12, the counter will get the clock pulses at the rate of 1MHz. So, the counter
will be incremented after every 1 ps.
To generate a square wave of ZkHz, the period should be set to 500ps
(l/2Y,.}rz). This means that the program must give an output of logic 1 for
250prs and logic 0 for another 250trrs, so that a square wave of 500ps period can
be generated. Here, as the counter is incremented after every microsecond, the
counter has to count up to 250. The counter will overflow after every 250 counts.
During an overflow, the logic output on the pin will be inverted. By doing this
; continuously, a square wave can be generated.
This program uses the polled method to check whether the timer overflow has
\. If
occurred. The LSB of port 1 is used to generate the square wave.
eans
I can
l'40V TMOD, /100000010B ; Set Timer 0 i n mode 2.
C LR TFO ; Clear Timer 0 overflow f1ag.
 HARDWARE FEATURES oF 8051 U7

p:ft 0. Example ll.5:

- 250D) so that Write a program to count 10,000 objects on a conveyor belt, assuming that a sensor
gives a pulse for every object moving on the conveyor belt. Generate an intemrpt
; the TR0 bit. after that. Use the ISR to give a logic 1 output on any port pin.
le overf I ow
Solution:
s--.
To count the external pulses, Timer 1 is initialized as a counter by setting the D6
bit of TMOD. Mode 1 of Timer 1 is used in this example, as 10,000 objects are to
be counted and this can be accomplished by the 16-bit timer mode only. Timer 1
r'-ow bit.
is loaded with the value 55,535 (i.e., 65,535 - 10,000), which in hexadecimal form
is D8EF. This gives an intemrpt after 10,000 counts.
on any one of the The program is written in two parts. The main program initializes the timer and
he 8051 system is runs it. After that, the main program does nothing. Detecting the count value of
10,000 is done automatically by running the timer and generating an intemrpt at
every overflow. Then the intemrpt service routine is used to give a logic 1 output
on the port pin.
I a square wave of
-bit counter mode Main program:
MAIN: MOV TMOD. #010100008 Set Timer 1 in mode 1 (counter
runter will
get the operati on ) .
ed every 1 ps. The MOV THl . /TOD8H Load the Timer t higher-onder byte.
br another 500prs, M0v rL1. /l0rrH Load the Timer" l lower^-order byte.
Mo\/ rE, #10001000B Enable Timer/Counter 1 internupt.
reload option with STTB TR1 Start Timer/Counter 1.
d the count value L00P: LJMP L00P Loop a nd do noth i ng .
of 500ps. So, the (Refer Section 11.5 for 8051 intemrpts)
The hexadecimal Interrupt s ervice routine :
order eight bits of ISR-TIMERl: CLR TRl ; Stop Timer 1 temporarily.
o FEH. Pl.0
SETB ; Set the LSB of P1.
r hether the timer RETI ; Return from interrupt.
e square wave.
:oerati on ) .
11.5 8051 INTERRUPTS
el.
p:-t 0. Intemrpt is a mechanism that makes the microcontroller interrupt the current
e- ,i wi th the program execution and execute another program. The program that is executed
upon intemrpt is called intemrpt service routine (ISR). These routines are
considered high-priority routines, in comparison with the main progpm.
lE :ne TRO bit.
11.5.1 lnterrupt Sources and lnterrupt Vector Addresses
h: cverf .l ow bi t
The 8051 has the following five intemrpt sources, i.e., any of the following events
will make the 8051 execute an intemrpt service routine.
(i) Timer 0 overflow
(ii) Timer 1 overflow
a'i:ng the (iii) Receptior/transmission of serial character
(iv) External hardware interrupt 0
(v) External hardware interrupt 1
 348 MTRopRocESSoRSANDMtcRocoNTRoLLERS

The different intemrpt sources have to be distinguished and the g051 must
no intemrpts occur, evet
execute different subroutines depending on which intemrpt was triggered. This
enables all the intemryt
is accomplished by jumping to or calling a fixed address, when a given interrupt
SFR.
occurs. These addresses are called intemrpt vector addresses or intemrpt handlir
addresses. Table 11.7 lists the intemrpt vector addresses for the five intemrpts. 1 1.5.3 lntenupt Priqfirt
Table 11,7 lnterrupts and their vector addresses
After every instnrcooo-
should occur. lnternryr o
Intonufi Flag lnhmrptvec,torddrect (i) External0 rntemt
External 0 IEo 0003H
(ii) Timer 0 intemryt
(iii) Extemal I intem{
Timer 0 TFO OOOBH
(iv) Timer I intemryt
External I IEI 0013H (v) Serial intemrpt
Timer I TFl OO1BH
t
This list also gives
Serial RVTI OO23H
intemrpt and Timer I int
executes the intemrPt se
whenever Timer 0 overflows (i.e., the TFO bit is set), the main program is Then the 8051 returns t
suspended temporarily and control is transferred to 0008H. It is assumed that the
service routine at address 000BH handles the Timer 0 overflow
executes the intemryt -l
This also 6gans thd
11.5.2 Enabling and Disabling of lnterrupts External 0 intemrpt ocs
when the microcontroller is turned on, all intemrpts are disabled by default. This then the serial intem.pt I
means that even if, for example, the TFO bit is set, the g05l will not execute the -{, There are two levels
intemrpt. Programming must be done specifically to enable intemrpts. intemrpt priorities, the d
The intemrpt enable special function register IE SFR at the address AgH is used priority categories.
to enable and disable intemrpts by modifying its bits. Table I Lg gives the various Intemrpt priorities a
bit patterns for enabling the intemrpts, individually and globally. Intemrpts can shown in Table 11.9. Fo
be enabled individually by using the bit addresses of the individual bits the Timer 0 intemrpr d
of the IE r
register. Table 11.8 also gives the bit addresses ofthe bits ofthe IE register. can be programmed to
assigning a high priorrq
Table 11.8 Bit pattems for lE (A8H) SFR intemrpt. By setting the I
andbymakingtheDl bi
Bil poeition D7 D4 D3 D2 DI DO
that the priority can be sr
Bit address AF AC AB AA A9 A8
For example, the Timer I
llane EA ES ET1 EXI ETO EX0
of the IP SFR, So, the fol
Exdanat$on Global Undefined Undefined Enable Enable Enable Enable Enable and MOV IP, #82H.
interrupt serial Timer I External Timer 0 Extemal
enable/ intemrpt interrupt I intemrpt 0 T
disable intemrpt intemrpt
Bttpoclfon Dz
Each 8051 intemrpt has its own bit in the IE sFR. A particular intemrpt Bltddrs
can
be enabled by setting the corresponding bit. For example, to enable
the Timer I
ilame EA
intemrpt, one of the following instructions can be executed: Mov IE. Exphtdot Enable L'!
#OgH or Intemrpts-
SETB ETI.
Made 0 to
However, before the Tirner I intemrpt (or any other intemrpt) is truly
enabled, disable all
bit 7 of the IE sFR must also be set. Bit 7, which is the global intemrpt enable/
, intemryts
disable, enables or disables all intemrpts at the same time, i.e., if
bitT is cleared,
 HARDWARE FEATURES oF 8051 349

rnd the 8051 must no intemrpts occur, even if all the other bits of the IE SFR are set. Setting bit 7
enables all the intemrpts that have been selected, by setting other bits in the
IE
ras triggered. This
SFR.
n a given intemrpt
r intemrpt handler I1.5.3 lntenupt Priorities and Polling Sequence
rfive intemrpts.
After every instruction, the 8051 automatically evaluates whether an intemrpt
should occur. Intemrpt conditions are checked for in the following order:
(i) External0 intemrPt
(ii) TimerO intemrPt
(iii) Extemal 1 intemrPt
(iv) Timer I i4temrPt
(v) Serial intemrPt
This list also gives the priority of the intemrpts. So, whenever the External
0

intemrpt and Timer 1 intemrpt occur at the same instant, the 8051 microcontroller
executes the intemrpt service routine corresponding to External 0 intemrpt
first'
one instruction, and then
r mam program ls Then the 8051 returns to the main program, executes
executes the intemrpt service routine corresponding to the Timer I intemrpt'
is assumed that the
v.
This also means that if a serial intemrpt occurs at the same instant that an
External 0 intemrpt occurs, the External 0 intemrpt routine is executed first
and
then the serial interqrpt routine is executed.
hd by default. This There are two levels of intemrpt priority in the 8051-high and low. Using
rill not execute the intemrpt priorities, the above intemrpts can be divided into two separate intemrpt
terrupts. priority
- categories.
rddressASH is used Intemrpt priorities are controlled by the IP SFR (B8H), which has the format
.8 gives the various shown in Table 11.9. For example, if the serial intemrpt is more important than
ally. Intemrpts can the Timer 0 intemrpt, the Intemrpt Priority register IP SFR at the address BSH
can be programmed to set the priority appropriately. This can be accomplished
by
ridual bits of the IE
assigning a high priority to the serial intemrpt and a low priority to the Timer 0
rc IE register.
intemrpt. By setting the D4 bit to 1, the serial intemrpt will be set to higher priority
and by making the Dl bit 0, the Timer 0 intemrpt will be set to lower priority' Note
DI DO that the priority can be set individually by using the bit addresses of the IP register.
A9 A8 For example, the Timer 0 intemrpt priority can be made high by setting the Dl bit
ETO EX0 of the IP SFR. So, the following instructions can be used: SETB PTO, SETB B9H,
and MOV IP, #82H.
Enable Enable
rl Timer 0 External Table 11.9 Bit patterns for lP (B8H) SFR
interrupt 0
intemrpt BltpGfro0 D7 D6 D5 D4 D3 D2 Dl DO

Blldm* BC BB BA 89 88

[cular intemrpt can Nanr EA PS PTI PXI PTO PXO

Enable Undefined Undefined Serial Timer External Timer 0 Extemal
enable the Timer 1 Exflana{on 1

MOV IE, #08H or Interrupts- htemrpt interrupt I intemrpt 0

Made 0 to priority priority interrupt prioritY intemrPl
disable all priority prioritY
pt) is truly enabled,
, interrupts
ral intemrpt enable/
r.. if bit 7 is cleared,
 350 MrcRopRocESSoRsAND MtcRocoNTRoLLERs

Based on the two-level priority set by the lp register, intemrpt subroutines are
executed as follows under various conditions: one machine cycle, the inte
available for at least 12 cloc
(i) when a high-priority intemipt and a low-priority intemrpt appear at the External intemtpts are a;
same time, the high-priority intemrpt will be serviced first. voltage level applied to this p
(ii) when a high-priority intemrpt appears during the execution of a low- can be either level-triggered
priority intemrpt service routine, the high-priority intemrpt will be serviced the SFR. TCON, as shoul r,
after suspending the low-priority service routine. both the hardware interrups
(iiD A low-priority intemrpt cannot intemrpt a high-priorigu intemrpt. a low-level voltage on the in

If there is more than one high-priority intemrpt and if any two of them appear Table 11.1
at the same time, the priority among these two will be decided by the order in
which the intemrpt conditions are checked by the hardware.
D7
Bit position D6

The complete structure ofthe 805 I intemrpts can be understood well by referring
8F
Bit address 8E

to Fig. ll.16. The five intemrpt sources are first passed through the IE register,
Name TFl TRI

which decides the enabling and disabling of intemrpts. The global intemrpt enable
signal is also shown in the figure. The Ip register sets two priority levels among
the available intemrpts. This is shown in the figure as the high priority and low Timer

priority blocks. The bits IT0 and ITI can be set by the TCON sFR; they are used I run
to decide whether the hardware intemrpt is level-triggered or edge-triggered.
Timer 1 control
Explanation overflou bit. Ser i

flag rolbi I

softu are
IO run

A ' l' on the IT0 and IT I

intemrpts as edge-triggered.
voltage from a high state to a
When an intemrpt is rnggera
automatically:
(i) The lower-order brre
pointed to by the stac
next consecutive locan
(ii) The priority amons aU
priorities are blocked.
(iii) If the intemrpt selecreC
lnterrud intemrpt flags are clea
enabl6 (iv) The correspondin_e Ln
Fig. 11.16 Structure of 8051 interrupts counter. This resulr-s rn
(v) The RETI instructitrn a
11.5.4 Timing of lnterrupts
execution to the marn p
The 8051 microcontroller samples the hardware signal level on its pins to the program counrer
once in
every machine cycle. A machine cycle is the time taken by the controller
to access
one memory location or vo device. As the g05l takes 12 clock
cycles to complete
The internal architecrure
intemrptswill be cleared at
 HARDwARE FEATURES oF 8051 35.|

t subroutines are one machine cycle, the intemrpt signal applied at the pins of the 8051 must be
avaiiable for at least 12 clock periods.
External intemrpts are applied at the pins INT0 and INTI. The sensing of the
upt appear at the
voltage level applied to this pin can also be programmed in the 8051 . The intemrpts
t.
can be either level-triggered or edge-triggered, as set by the IT0 and ITI bits of
cution of a low- the SFR. TCON, as shown in Table 11.10. A'0'in these bit positions will make
r will be serviced both the hardware intemrpts level-triggered. When an intemrpt is level-triggered,
a low-level voltage on the intemrpt pin will activate the intemrpt'
[errupt.
Table 11.10 Bit patterns for the TCON (88H) SFR
ro ofthem appear
d by the order in Bit position ol D6 D5 D4 D3 D2 Dl DO

Bit address 8F 8E 8D 8C 88 8A 89 88

Name TF1 TR1 TFO TRO IE1 ITI IEO ITO

d well by referring
InterruPt Intemrpt
;h the IE register, I type 0 type
rl intemrpt enable control. control.
rity levels among Timer Timer
Set to Set to
r priority and low 1 run 0run
Extemal I by Extemal 1bv
,FR; they are used Timer 1 conkol Timer 0 control
interrupt software intem.rPt software
Explanation overflow bit. Set overflow bit. Set
lge-triggered. I edge for edge- 0 edge for edge-
flag to I bY flag to I by detect bit triggering detect bit triggering
software software
and and
to run. to run.
cleared cleared
for level- for level-
triggering triggering

A'1'on the IT0 and ITi bits of the SFR TCON will program the hardware
intemrpts as edge-trjggered. when an interrupt is edge-triggered, a change of
voltage from a high state to a low state will activate the intemrpt'
When an intemrpt is triggered, the microcontroller performs the following actions
automatically:
(i) The lower-order byte of the program countef is stored in the location
pointed to by the stack pointer and the higher-order byte is stored in the
next consecutive location.
(ii) The priority among all the intemrpts received is resolved, the lower-order
priorities are blocked, and only one intemrpt is considered for execution.
(iii) If the intemrpt selected is a timer or an extemal intemrpt, the corresponding
intemrpt flags are cleared.
(iv) The corresponding intemrpt vector address is loaded into the program
counter. This results in the execution of the intemrpt service routine.
(v) The RETI instruction at the end of the intemrpt service routine transfers the
execution to the main program by popping the return address from the stack
to the program counter.
rn its pins once in
nntroller to access The internal architecture of the 8051 is such that the external hardware
c1-cles to complete intemrpts will be cleared automatically when the intemrpt service routine is