Microprocessor and

Interfacing Techniques

Lecture 09
9–1 PIN-OUTS AND THE PIN FUNCTIONS

• In this section, we explain the function and

the multiple functions of each of the microprocessor’s
pins.
• In addition, we discuss the DC characteristics to provide a
basis for understanding the later sections on buffering and
latching.
The Pin-Out
• Figure 9–1 illustrates pin-outs of 8086 & 8088.
• both are packaged in 40-pin dual in-line packages (DIPs)

• 8086 is a 16-bit microprocessor with a 16-bit

data bus; 8088 has an 8-bit data bus.
– 8086 has pin connections AD0–AD15
– 8088 has pin connections AD0–AD7
• Data bus width is the only major difference.
• thus 8086 transfers 16-bit data more efficiently
Figure 9–1 (a) The pin-out of the 8086 in maximum mode; (b) the pin-out of the 8086 in minimum mode.
Power Supply Requirements
• Both microprocessors require +5.0 V with a supply voltage
tolerance of +10 percent.
• 8086 uses a maximum supply current of 360 mA
• 8088 draws a maximum of 340 mA
• Both microprocessors operate in ambient temperatures of
between 32° F and 180° F.
• 80C88 and 80C86 are CMOS versions that require only 10
mA of power supply current.
• and function in temperature extremes of –40° F through +225° F
DC Characteristics
• It is impossible to connect anything to a
microprocessor without knowing input current
requirement for an input pin.
• and the output current drive capability for an output pin
(Fanout)
• This knowledge allows hardware designers
to select proper interface components for use with the
microprocessor
• without the fear of damaging anything
Input Characteristics
• Input characteristics of these microprocessors are
compatible with all the standard logic components
available today.
• Table 9–1 depicts input voltage levels and
the input current requirements for any input pin on either
microprocessor.
• The input current levels are very small because the inputs
are the gate connections of MOSFETs and represent only
leakage currents.
Output Characteristics
• Table 9–2 illustrates output characteristics of all the output
pins of these microprocessors.
• The logic 1 voltage level of the 8086/8088 is compatible
with most standard logic families.
• logic 0 level is not
• Standard logic circuits have a maximum logic 0 voltage of
0.4 V; 8086/8088 has a maximum of 0.45 V.
• a difference of 0.05 V
• This difference reduces the noise immunity from 400 mV
(0.8 V – 0.45 V) to 350 mV.
• noise immunity is the difference between logic 0 output voltage
and logic 0 input voltage levels
• Reduction in noise immunity may result in problems with
long wire connections or too many loads.
• No more than 10 loads of any type should be connected
to an output pin without buffering
• if this factor is exceeded, noise will begin to take its toll in timing
problems
Pin Connections AD7 - AD0
• 8088 address/data bus lines are multiplexed
• and contain the rightmost 8 bits (Lower-half) of the memory
address or I/O port number whenever ALE (Address Latch
Enable) is active (logic 1)
• or data whenever ALE is inactive (logic 0)
• These pins are at their high-impedance state during a hold
acknowledge.
Pin Connections A15 - A8
• 8088 address bus provides the upper-half memory
address bits that are present throughout a bus cycle.
• These address connections go to their high-impedance
state during a hold acknowledge.
Pin Connections AD15 - AD8
• 8086 address/data bus lines compose upper multiplexed
address/data bus on the 8086.
• These lines contain address bits A15–A8 whenever ALE is a
logic 1, and data bus connections D15–D8 when ALE is a
logic 0.
• These pins enter a high-impedance state when a hold
acknowledge occurs.
Pin Connections A19/S6 - A16/S3
• Address/status bus bits are multiplexed to provide
address signals A19–A16 and status bits S6–S3.
• high-impedance state during hold acknowledge
• status bit S6 is always logic 0,
• bit S5 indicates the condition of the IF flag bit
• S4 and S3 show which segment is accessed during the
current bus cycle.
• these status bits can address four separate 1M byte memory
banks by decoding as A21 and A20
Pin Connections RD
• When read signal is logic 0, the data bus is receptive to
data from memory or I/O devices
• pin floats high-impedance state during a hold acknowledge

Ready
• Inserts wait states into the timing.
– if placed at a logic 0, the microprocessor enters
into wait states and remains idle
– if logic 1, no effect on the operation
Pin Connections INTR
• Interrupt request is used to request a hardware interrupt.
• If INTR is held high when IF = 1, 8086/8088
enters an interrupt acknowledge cycle after the current
instruction has completed execution

NMI
• The non-maskable interrupt input is similar
to INTR.
– does not check IF flag bit for logic 1
– if activated, uses interrupt vector 2
Pin Connections TEST
• The Test pin is an input that is tested by the WAIT
instruction.
• If TEST is a logic 0, the WAIT instruction functions as an
NOP.
• If TEST is a logic 1, the WAIT instruction
waits for TEST to become a logic 0.
• The TEST pin is most often connected to
the 8087 numeric coprocessor.
Pin Connections RESET
• Causes the microprocessor to reset itself if held high a
minimum of four clocking periods.
• when 8086/8088 is reset, it executes instructions at memory
location FFFF0H
• also disables future interrupts by clearing IF flag

CLK
• The clock pin provides the basic timing signal.
– must have a duty cycle of 33 % (high for one third
of clocking period, low for two thirds) to provide
proper internal timing
Pin Connections VCC
• This power supply input provides a +5.0 V, ±+10 % signal
to the microprocessor.

GND
• The ground connection is the return for the
power supply.
– 8086/8088 microprocessors have two pins
labeled GND—both must be connected to
ground for proper operation
Pin Connections MN/MX
• Minimum/maximum mode pin selects either minimum or
maximum mode operation.
• if minimum mode selected, the MN/MX pin must
be connected directly to +5.0 V

BHE/S7
• The bus high enable pin is used in 8086 to
enable the most-significant data bus bits
(D15–D8) during a read or a write operation.
• The state of S7 is always a logic 1.
Minimum Mode Pins
• Minimum mode operation is obtained by connecting the
MN/MX pin directly to +5.0 V.
• do not connect to +5.0 V through a pull-up register; it will not
function correctly

IO/M or M/IO
• The IO/M (8088) or M/IO (8086) pin selects
memory or I/O.
– indicates the address bus contains either a
memory address or an I/O port address.
– high-impedance state during hold acknowledge
Minimum Mode Pins WR
• Write line indicates 8086/8088 is outputting data to a
memory or I/O device.
• during the time WR is a logic 0, the data bus contains valid data
for memory or I/O
• high-impedance during a hold acknowledge

INTA
• The interrupt acknowledge signal is a
response to the INTR input pin.
– normally used to gate the interrupt vector number
onto the data bus in response to an interrupt
Minimum Mode Pins ALE
• Address latch enable shows the 8086/8088 address/data
bus contains an address.
• can be a memory address or an I/O port number
• ALE signal doesn’t float during hold acknowledge

DT/R
• The data transmit/receive signal shows that
the microprocessor data bus is transmitting
(DT/R = 1) or receiving (DT/R = 0) data.
– used to enable external data bus buffers
Minimum Mode Pins DEN
• Data bus enable activates external data bus buffers.

HOLD
• Hold input requests a direct memory access
(DMA).
– if HOLD signal is a logic 1, the microprocessor
stops executing software and places address,
data, and control bus at high-impedance
– if a logic 0, software executes normally
Minimum Mode Pins HLDA
• Hold acknowledge indicates the 8086/8088 has entered
the hold state.

SS0
• The SS0 status line is equivalent to the S0
pin in maximum mode operation.
• Signal is combined with IO/M and DT/R to
decode the function of the current bus cycle.
Maximum Mode Pins
• In order to achieve maximum mode for use with external
coprocessors, connect the MN/MX pin to ground.

S2, S1, and S0

• Status bits indicate function of the current
bus cycle.
– normally decoded by the 8288 bus controller
Maximum Mode Pins RQ/GT1
• The request/grant pins request direct memory accesses
(DMA) during maximum mode operation.
• bidirectional; used to request and grant a DMA operation

LOCK
• The lock output is used to lock peripherals off
the system. This pin is activated by using the
LOCK: prefix on any instruction.
Maximum Mode Pins QS1 and QS0
• The queue status bits show the status of the internal
instruction queue.
• provided for access by the 8087 coprocessor
9–2 CLOCK GENERATOR (8284A)
• This section describes the 8284A clock generator and the
RESET signal.
• also introduces the READY signal for 8086/8088

• With no clock generator, many circuits would

be required to generate the clock (CLK).
• 8284A provides the following basic functions:
– clock generation; RESET & READY synch;
– TTL-level peripheral clock signal
• Figure 9–2 shows pin-outs of the 8284A
Figure 9–2 The pin-out of the 8284A clock generator.
8284A Pin Functions
• 8284A is an 18-pin integrated circuit designed specifically
for use 8086/8086.

AEN1 and AEN2

• The address enable pins are provided to
qualify bus ready signals, RDY1 and RDY2.
– used to cause wait states
• Wait states are generated by the READY pin
of 8086/8088 controlled by these two inputs.
Pin Functions RDY1 and RDY2
• The bus ready inputs are provided, in conjunction with the
AEN1 & AEN2 pins,
to cause wait states in 8086/8088.

ASYNC
• The ready synchronization selection input
selects either one or two stages of
synchronization for the RDY1 and RDY2
inputs.
Pin Functions READY
• Ready is an output pin that connects to the 8086/8088
READY input.
• synchronized with the RDY1 and RDY2 inputs

X1 and X2
• The crystal oscillator pins connect to an
external crystal used as the timing source
for the clock generator and all its functions
Pin Functions F/C
• The frequency/crystal select input chooses the clocking
source for the 8284A.
• if held high, an external clock is provided to the EFI input pin
• if held low, the internal crystal oscillator provides the timing
signal
• The external frequency input is used when the F/C pin is
pulled high.
• EFI supplies timing when the F/C pin is high.
Pin Functions CLK
• The clock output pin provides the CLK input signal to
8086/8088 and other components.
• output signal is one third of the crystal or EFI
input frequency
• 33% duty cycle required by the 8086/8088

PCLK
• The peripheral clock signal is one sixth the
crystal or EFI input frequency.
– PCLK output provides a clock signal to the
peripheral equipment in the system
8284 Clock Generator

33% Duty Cycle

Engr 4862 Microprocessors

Pin Functions OSC
• Oscillator output is a TTL-level signal at the same
frequency as crystal or EFI input.
• OSC output provides EFI input to other 8284A clock generators in
multiple-processor systems

RES
• Reset input is an active-low input to 8284A.
– often connected to an RC network that provides
power-on resetting
Pin Functions RESET
• Reset output is connected to the 8086/8088 RESET input
pin.

CSYNCH
• The clock synchronization pin is used when
the EFI input provides synchronization in
systems with multiple processors.
– if internal crystal oscillator is used, this pin must
be grounded
Pin Functions GND
• The ground pin connects to ground.

VCC
• This power supply pin connects to +5.0 V
with a tolerance of +10%.
Operation of the 8284A
• The 8284A is a relatively easy component
to understand.
• Figure 9–3 illustrates the internal timing diagram of the
8284A clock generator.
• The top half of the logic diagram represents the clock and
synchronization section of the 8284A clock generator.
Figure 9–3 The internal block diagram of the 8284A clock generator.
Operation of the Clock Section
• Crystal oscillator has two inputs: X1 and X2.
• if a crystal is attached to X1 and X2, the oscillator generates a
square-wave signal at the same frequency as the crystal
• The square-wave is fed to an AND gate & an inverting
buffer to provide an OSC output.
• The OSC signal is sometimes used as an EFI input to other
8284A circuits in a system.
• Figure 9–4 shows how an 8284A is connected to the
8086/8088.
Figure 9–4 The clock generator (8284A) and the 8086 and 8088 microprocessors illustrating the
connection for the clock and reset signals. A 15 MHz crystal provides the 5 MHz clock for the
microprocessor.
Operation of the Reset Section
• The reset section of 8284A consists of a Schmitt trigger
buffer and a D-type flip-flop.
• the D-type flip-flop ensures timing requirements
of 8086/8088 RESET input are met
• This circuit applies the RESET signal on the negative edge
(1-to-0 transition) of each clock.
• 8086/8088 microprocessors sample RESET at the positive
edge (0-to-1 transition) clocks.
• thus, this circuit meets 8086/8088 timing requirements
9–6 MINIMUM VS MAXIMUM MODE
• Minimum mode is obtained by connecting the mode
selection MN/MX pin to +5.0 V,
• maximum mode selected by grounding the pin
• The mode of operation provided by minimum mode is
similar to that of the 8085A
• the most recent Intel 8-bit microprocessor
• Maximum mode is designed to be used whenever a
coprocessor exists in a system.
• maximum mode was dropped with 80286
Minimum Mode Operation
• Least expensive way to operate 8086/8088.
• because all control signals for the memory & I/O are generated
by the microprocessor
• Control signals are identical to Intel 8085A.
• The minimum mode allows 8085A 8-bit peripherals to be
used with the 8086/8088 without any special
considerations.
Maximum Mode Operation
• Differs from minimum mode in that some control signals
must be externally generated.
• requires addition of the 8288 bus controller
• There are not enough pins on the 8086/8088 for bus
control during maximum mode
• new pins and features replaced some of them
• Minimum mod pin INTA, ALE,DEN, DT/R , M/IO, WR,HLDA, HOLD
are not available in maxmode
• These pins are required for interfacing IO and memory devices.
• Maximum mode used only when the system contains
external coprocessors such as 8087.
The 8288 Bus Controller
• Provides the signals eliminated from the 8086/8088 by the
maximum mode operation.

Figure 9–21 The 8288 bus controller; (a) block diagram and (b) pin-out.
8288 Pin Functions
S2, S1, and S0
• Status inputs are connected to the status output pins on
8086/8088.
• three signals decoded to generate timing signals

CLK
• The clock input provides internal timing.
– must be connected to the CLK output pin of
the 8284A clock generator
8288 Pin Functions
ALE
• The address latch enable output is used to DE multiplex
the address/data bus.

DEN
• The data bus enable pin controls the
bidirectional data bus buffers in the system.
DT/R
• Data transmit/receive signal output to control
direction of the bidirectional data bus buffers.
8288 Pin Functions
AEN
• The address enable input causes the 8288 to enable the
memory control signals.

CEN
• The control enable input enables the
command output pins on the 8288.
IOB
• The I/O bus mode input selects either I/O
bus mode or system bus mode operation.
8288 Pin Functions
AIOWC
• Advanced I/O write is a command output to an advanced
I/O write control signal.

IORC
• The I/O read command output provides
I/O with its read control signal.
IOWC
• The I/O write command output provides I/O
with its main write signal.
8288 Pin Functions
AMWT
• Advanced memory write control pin provides memory
with an early/advanced write signal.

MWTC
• The memory write control pin provides
memory with its normal write control signal.
MRDC
• The memory read control pin provides
memory with a read control signal.
8288 Pin Functions
INTA
• The interrupt acknowledge output acknowledges an
interrupt request input applied to the INTR pin.

MCE/PDEN
• The master cascade/peripheral data output
selects cascade operation for an interrupt
controller if IOB is grounded, and enables the
I/O bus transceivers if IOB is tied high.
9–3 BUS BUFFERING AND LATCHING

• Before 8086/8088 can be used with memory

or I/O interfaces, their multiplexed buses must be
demultiplexed.
• This section provides detail required to demultiplex the
buses and illustrates how
the buses are buffered for very large systems.
• because the maximum fan-out is 10, the system must be
buffered if it contains more than 10 other components
Demultiplexing the Buses
• The address/data bus of the 8086/8088 is multiplexed
(shared) to reduce the number
of pins required for the integrated circuit
• the hardware designer must extract or
demultiplex information from these pins
• Memory & I/O require the address remain valid and stable
throughout a read/write cycle.
• If buses are multiplexed, the address changes at the
memory and I/O, causing them to read or write data in the
wrong locations
• All computer systems have three buses:
• an address bus that provides memory and I/O with the memory
address or the I/O port number
• a data bus that transfers data between the microprocessor and
the memory and I/O
• a control bus that provides control signals to
the memory and I/O
• These buses must be present in order to interface to
memory and I/O.
Demultiplexing the 8086
• Fig 9–6 illustrates a demultiplexed 8086 with all three
buses:
• address (A19–A0 and BHE )
• data (D15–D0),
• control (M/IO,RD, and WR )
• Here, the memory and I/O system see the 8086 as a device
with:
• a 20-bit address bus;16-bit data bus
• and a three-line control bus
Figure 9–6 The 8086 microprocessor shown with a demultiplexed address bus. This is the
model used to build many 8086-based systems.
The Buffered System
• If more than 10 unit loads are attached to any bus pin,
the entire system must be buffered.
• Buffer output currents have been increased
so that more TTL unit loads may be driven.
• A fully buffered signal will introduce a timing delay to the
system.
• No difficulty unless memory or I/O devices
are used which function at near maximum
bus speed.
The Fully Buffered 8086
• Figure 9–8 illustrates a fully buffered 8086.
• a fully buffered 8086 system requires one 74LS244, two
74LS245s, and three 74LS373s
• 8086 requires one more buffer than 8088 because of the
extra eight data bus connections, D15–D8.
• It also has a BHE signal that is buffered for memory-bank
selection.
Figure 9–8 A fully buffered 8086 microprocessor.