Digital Design &Computer Organization (Bcs302) Module 3

MODULE – 3

Basic Structure of Computers & Machine Instructions

and Programs
Topics:
Basic Structure of Computers:
Functional Units
Basic Operational
Concepts Bus Structures
Performance –Processor Clock
Basic Performance Equation
Clock Rate Performance
Measurement.
Machine Instructions and Programs:
Memory Location and
Address Memory
Operations
Instructions and Instruction
Sequencing Addressing Modes
Functional Units
Computer consists of 5 functional units
1. Input
2. Memory
3. ALU
4. Output unit
5. Control units

Fig : Basic Functional Unit

Input Unit
The computer accepts the information in the form of program & data through an
input- device.
Eg: keyboard
 Digital Design &Computer Organization (Bcs302) Module 3

Whenever a key is pressed, the corresponding letter/digit is automatically

translated into its corresponding binary-code and transmitted over a cable to
either the memory or the processor.
Memory Unit: used to store programs & data.
There are 2 classes of storage:
Primary-storage is a fast-memory that operates at electronic-speed. Programs must be stored
in the memory while they are being executed.
Secondary-storage is used when large amounts of data & many programs have to be stored.
Eg:magnetic disks and optical disks(CD-ROMs).
The memory contains a large number of semiconductor storage cells(i.e. flip-flops), each
capable of storing one bit of information.
The memory is organized so that the contents of one word(containing n-bits) can be stored or
retrieved in one basic operation.
Programs must reside in the memory during execution. instructions and data can be
written into the memory or read out under the control of the processor
Memory in which any location can be reached in a short and fixed amount of time after
specifying its address is called RAM (Random Access Memory).
The time required to access one word is called the memory access time

ALU (Arithmetic & Logic Unit)

This unit is used for performing arithmetic & logical operations.
Any arithmetic operation is initiated by bringing the required operand into the processor (i.e.
registers), where the operation is performed by the ALU.
Output Unit
This unit is used to send processed-results to the outside world. Eg: printer, graphic
displays etc.
Classified according to their printing methodology
1)Impact Printers.
2) Non-Impact Printers.
Control Unit
This unit is used for controlling the activities of the other units, All computer operations are
controlled by the control unit. (such as memory, I/O device).
This unit sends control-signals (read/write) to other units and senses their states.
Data transfers between processor and memory are also controlled by the control-
unit through timing-signals.
Timing-signals are signals that determine when a given action is to take place.
The timing signals that govern the I/O transfers are also generated by the control unit.
Control unit is usually distributed throughout the machine instead of standing alone.

BASIC OPERATIONAL CONCEPTS:

The program to be executed is stored in memory. Instructions are accessed from
memory to the processor one by one and executed.
STEPS FOR INSTRUCTION EXECUTION
Consider the following instruction
Ex: 1 Add LOCA, R0
This instruction is in the form of the following instruction
format Opcode Source, Destination
 Digital Design &Computer Organization (Bcs302) Module 3

Where Add is the operation code, LOCA is the Memory operand and R0 is
Register operand This instruction adds the contents of memory location LOCA
with the contents of Register R0 and the result is stored in R0 Register.
The symbolic representation of this instruction is
R0 [LOCA] + [R0]

The contents of memory location LOCA and Register R0 before and after the
execution of thisinstruction is as follows

Before instruction execution After instruction execution

LOCA = 23H LOCA = 23H
R0 = 22H R0 = 45H
The steps for instruction execution are as follows
1. Fetch the instruction from memory into the IR (instruction register in CPU).
2. Decode the instruction 1111000000 10011010
3. Access the Memory Operand
4. Access the Register Operand
5. Perform the operation according to the Operation Code.
6. Store the result into the Destination Memory location or
Destination Register.

Ex:2 Add R1, R2, R3

This instruction is in the form of the following instruction
format Opcode, Source-1, Source-2, Destination
Where R1 is Source Operand-1, R2 is the Source Operand-2 and R3 is the
Destination. This instruction adds the contents of Register R1 with the contents of
R2 and the result is placed in R3 Register.
The symbolic representation of this instruction is
R3 [R1] + [R2]
The contents of Registers R1,R2,R3 before and after the execution of this instruction
is as follows. Before instruction execution After instruction execution
R1 = 24H R1 = 24H
R2 = 34H R2 = 34H
R3 = 38H R3 = 58H
The steps for instruction execution is as follows
1. Fetch the instruction from memory into the IR.
2. Decode the instruction
3. Access the First Register Operand R1
4. Access the Second Register Operand R2
5. Perform the operation according to the Operation Code.
6. Store the result into the Destination Register R3.
Digital Design &Computer Organization (Bcs302) Module 3

CONNECTION BETWEEN MEMORY AND PROCESSOR

The connection between Memory and Processor is as shown in the figure.

The Processor consists of different types of registers.

MAR (Memory Address Register)
MDR (Memory Data Register)
Control Unit
PC (Program Counter)
General Purpose Registers
IR (Instruction Register)
ALU (Arithmetic and Logic Unit)

The functions of these registers are as follows

1.MAR
It establishes communication between Memory and Processor
It stores the address of the Memory Location as shown in the figure.
MAR
Memory
5000h
5000 23h
5001 43h
5002 78h
5003 65h
Digital Design &Computer Organization (Bcs302) Module 3

2. MDR
 It also establishes communication between Memory and the Processor.
 It stores the contents of the memory location (data or operand), written into or read from
memory as shown in the figure.

3. CONTROL UNIT
 It controls the data transfer operations between memory and the processor.
 It controls the data transfer operations between I/O and processor.
 It generates control signals for Memory and I/O devices.
4. PC (PROGRAM COUNTER)
 It is a special purpose register used to hold the address of the next instruction to
be executed.
 The contents of PC are incremented by 1 or 2 or 4, during the execution of current
instruction.
 The contents of PC are incremented by 1 for 8 bit CPU, 2 for 16 bit CPU and for 4 for
32bit CPU.
5 GENERAL PURPOSE REGISTER / REGISTER ARRAY
The structure of register file is as shown in the figure
R0
R1
R2
.
Rn-1

 It consists of set of registers.

 A register is defined as group of flip flops. Each flip flop is designed to
store 1 bit of data.
 It is a storage element.
 It is used to store the data temporarily during the execution of the
program(eg: result).
It can be used as a pointer to Memory.
 The Register size depends on the processing speed of the CPU
 EX: Register size = 8 bits for 8 bit CPU
6 IR (INSTRUCTION REGISTER)
It holds the instruction to be executed. It notifies the control unit, which
generates timing signals that controls various operations in the execution of that
instruction.
 Digital Design &Computer Organization (Bcs302) Module 3

7 ALU (ARITHMETIC and LOGIC UNIT)

 It performs arithmetic and logical operations on given data.

Steps for reading the instruction.

PC contents are transferred to MAR and read signal is sent to memory by control unit. The
data from memory location is read and sent to MDR.
The content of MDR is moved to IR.

[PC]  MAR CU ( read signal) Memory  MDR  IR

a. BUS STRUCTURE
Bus is defined as set of parallel wires used for data communication between
different parts of computer. Each wire carries 1 bit of data. There are 3 types of
buses, namely
i. Address bus
ii. Data bus and
iii. Control bus.
1. Address bus :
It is unidirectional.
• The processor (CPU) sends the address of an I/O device or Memory device
by means of this bus.
2. Data bus
• It is a bidirectional bus.
• The CPU sends data from Memory to CPU and vice versa as well as from I/O
to CPU and vice versa by means of this bus
3. Control bus:
 This bus carries control signals for Memory and I/O devices. It generates
control signals for Memory namely MEMRD and MEMWR and control signals
for I/O devices namely IORD and IOWR.
The structure of single bus organization is as shown in the figure

Fig: Single Bus Structure

 The I/O devices, Memory and CPU are connected to this bus is as shown in
the figure.
 Digital Design &Computer Organization (Bcs302) Module 3

 It establishes communication between two devices, at a time.

Features of Single bus organization are

 Less Expensive
 Flexible to connect I/O devices.
 Poor performance due to single bus.
There is a variation in the devices connected to this bus in terms of speed of
operation. Few devices like keyboard, are very slow. Devices like optical disk are
faster. Memory and processor are faster, but all these devices uses the same bus.
Hence to provide the synchronization between two devices, a buffer register is
attached to each device. It holds the data temporarily during the data transfer
between two devices.

3. PERFORMANCE
 The performance of a Computer System is based on hardware design of the
processor and the instruction set of the processors.
 To obtain high performance of computer system it is necessary to reduce the
execution time of the processor.
Execution time: It is defined as total time required executing one complete
program.
 The processing time of a program includes time taken to read inputs, display
outputs, system services, execution time etc.
 The performance of the processor is inversely proportional to execution time
of the processor.
More performance = Les Execution time.
Less Performance = More Execution time.
The Performance of the Computer System is based on the following factors
1. Cache Memory
2. Processor clock
3. Basic Performance Equation
4. Instructions
5. Compiler
CACHE MEMORY: It is defined as a fast access memory located in between CPU and
Memory. It is part of the processor as shown in the fig

Fig : The Processor Cache

Digital Design &Computer Organization (Bcs302) Module 3

The processor needs more time to read the data and instructions from main
memory because main memory is away from the processor as shown in the
figure. Hence it slowdown the performance of the system.
The processor needs less time to read the data and instructions from
Cache Memory because it is part of the processor. Hence it improves the
performance of the system.

PROCESSOR CLOCK: The processor circuits are controlled by timing signals

called as Clock. It defines constant time intervals and are called as Clock Cycles.
To execute one instruction there are 3 basic steps namely
1. Fetch
2. Decode
3. Execute.
The processor uses one clock cycle to perform one operation as
shown in the figure
Clock Cycle → T1 T2 T3
Instruction → Fetch Decode Execute

The performance of the processor depends on the length of the clock

cycle. To obtain high performance reduce the length of the clock cycle. Let ‘ P ’
be the number of clock cycles generated by the Processor and ‘ R ‘ be the Clock
rate .

The Clock rate is inversely proportional to the number of clock cycles.

i.e R = 1/P.
Cycles/second is measured in Hertz (Hz). Eg: 500MHz, 1.25GHz.
Two ways to increase the clock rate –
 Improve the IC technology by making the logical circuit work faster, so
that the time taken for the basic steps reduces.
 Reduce the clock period, P.

BASIC PERFORMANCE EQUATION

Let ‘T ‘be processor time required to execute the program.
Let ‘N ‘be the number of instructions contained in the program.
Let ‘S ‘be the average number of steps required to one instruction.
Let ‘R’ be number of clock cycles per second generated by the processor
to execute one program.

Processor Execution Time is given by

T=N*S/R

This equation is called as Basic Performance Equation.

 Digital Design &Computer Organization (Bcs302) Module 3

For the programmer the value of T is important. To obtain high performance it

is necessary to reduce the values of N & S and increase the value of R.
There are two possibilities for increasing the clock rate:
• Improve the Integrated-circuit(IC) technology to make the logic circuits
faster which reduces the time needed to complete a basic step.
• Reduce the amount of processing done in one basic step also makes it
possible to reduce the clock period P
Performance of a computer can also be measured by using benchmark
programs.
SPEC (System Performance Evaluation Corporation) is an non-profitable
organization, that measures performance of computer using SPEC rating.
The organization publishes the application programs and also time taken to execute
these programs in standard systems.

𝑆𝑃𝐸𝐶 𝑅𝑢𝑛𝑛𝑖𝑛𝑔
𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑜𝑓 𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 𝐶𝑜𝑚𝑝𝑢𝑡𝑒𝑟
= 𝑡𝑖𝑚𝑒 𝑜𝑓 𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟 𝑢𝑛𝑑𝑒𝑟 𝑡𝑒𝑠𝑡

DIFFERENCES MULTIPROCESSOR AND MULTICOMPUTER

MULTIPROCESSOR MULTICOMPUTER
1. It is a process of interconnection of two or It is a process of interconnection of two or
more processors by means of system bus. more computers by means of system bus.
2. It uses common memory to hold the data It has its own memory to store data and
and instructions. instructions.
3. Complexity in hardware design. Not much complexity in hardware design.
4. Difficult to program for multiprocessor Easy to program for multiprocessor system
system.
Digital Design &Computer Organization (Bcs302) Module 3

Chapter 02
Machine instruction and programs:
2.2 Memory Locations And Addresses
2.3 Memory Operations
2.3 Instruction And Instruction Sequencing
2.4 Addressing Modes
2.2 MEMORY LOCATIONS AND ADDRESSES

1. Memory is a storage device. It is used to store character operands, data operands and
instructions.
2. It consists of number of semiconductor cells and each cell holds 1 bit of information. A
group of 8 bits is called as byte and a group of 16 or 32 or 64 bits is called as word.
World length = 16 for 16 bit CPU and World length = 32 for 32 bit CPU. Word length is defined
as number of bits in a word.
 Memory is organized in terms of bytes or words.
 The organization of memory for 32
 bit processor is as shown in the fig.

The contents of memory location can be accessed for read and write operation. The memory is
accessed either by specifying address of the memory location or by name of the memory location.

 Address space : It is defined as number of bytes accessible to CPU and it depends on

the number of address lines.
Digital Design &Computer Organization (Bcs302) Module 3

BYTE ADDRESSABILITY
Each byte of the memory are addressed, this addressing used in most
computers are called byte addressability. Hence Byte Addressability is the
process of assignment of address to successive bytes of the memory. The
successive bytes have the addresses 1, 2, 3, 4….....................................2n-1.
The
memory is accessed in words.

In a 32 bit machine, each word is 32 bit and the successive addresses are 0,4,8,12,… and
so on.
Address 32 – bit word

0000 0th byte 1st byte 2nd byte 3rd byte

0004 4th byte 5th byte 6th byte 7th byte
0008 8th byte 9th byte 10th byte 11th byte
0012 12th byte 13th byte 14th byte 15th byte
….. ….. ….. ….. …..
n-3 n-3th byte n-2th byte n-1th byte nth byte

BIG ENDIAN and LITTLE ENDIAN ASSIGNMENT

Two ways in which byte addresses can be assigned

in a word.Or
Two ways in which a word is stored in memory.
1. Big endian
2. Little endian
BIG ENDIAN ASSIGNMENT

In this technique lower byte of data is assigned to higher address of the

memory and higherbyte of data is assigned to lower address of the memory.
The structure of memory to represent 32 bit number for big endian assignment
is as shown in theabove figure.
Digital Design &Computer Organization (Bcs302) Module 3

LITTLE ENDIAN ASSIGNMENT

In this technique lower byte of data is assigned to lower address of the
memory and higher byteof data is assigned to higher address of the memory.
The structure of memory to represent 32 bit number for little endian
assignment is as shown inthe fig.

Eg – store a word “JOHNSENA” in memory starting from word 1000,

using Big Endianand Little endian.

Bigendian -
1000 J O H N
1000 1001 1002 1003
1004 S E N A
1004 1005 1006 1007

Little endian -
1000 J O H N
1003 1002 1001 1000
1004 S E N A
1007 1006 1005 1004

WORD ALLIGNMENT

16 bit
Word 32 bit
size 64 bit
Digital Design &Computer Organization (Bcs302) Module 3

The structure of memory for 16 bit CPU, 32 bit CPU and 64 bit CPU are as
shown in the figures1,2 and 3 respectively

For 16 bit CPU For 32 bit CPU For 64 bit CPU

5000 34H 5000 34H 5000 34H
It 5002
is process
65Hof assignment of
5004 addresses
65H of two successive words and this
5008 65H
address
5004 is86H
the number of 5008
bytes in86H
the word is called as Word alignment.
5016 86H
5006 93H 5012 93H 5024 93H
ACCESSING
5008 45HCHARACTERS AND45H
5016 NUMBERS 5032 45H

The character occupies 1 byte of memory and hence byte address for
memory. The numbers occupies 2 bytes(word) of memory and hence word
address for numbers.
2.3 MEMORY OPERATION
Both program instructions and operands are in memory. To execute each
instruction has to be read from memory and after execution the results must be
written to memory. Thereare two types of memory operations namely 1. Memory
read and 2. Memory write
Memory read operation [ Load/ Read / Fetch ]
Memory write operation [ Store/ write ]

1. MEMORY READ OPERATION:

 It is the process of transferring of 1 word of data from memory into Accumulator (GPR).
 It is also called as Memory fetch operation.
 The Memory read operation can be implemented by means of LOAD instruction.
 The LOAD instruction transfers 1 word of data (1 word = 32 bits) from Memory into
the Accumulator as shown in the fig.

Memory
Accumulator 32 bits
5000
5004
32 bits
5008
5012
5016
5020
Digital Design &Computer Organization (Bcs302) Module 3

Steps for Memory Read Operation

(1) The processor loads MAR (Memory Address Register) with the address of the memory
location.
(2) The Control unit of processor issues memory read control signal to enable the memory
component for read operation.
(3) The processor reads the data from memory into the Accumulator by means of bi-directional
data bus.

[MAR]  Memory  Accumulator

MEMORY WRITE OPERATION

 It is the process of transferring the 1 word of data from Accumulator into the Memory.
 The Memory write operation can be implemented by means of STORE instruction.
The STORE instruction transfers 1 word of data from Accumulator into the Memory
location as shown in the fig.
Accumulator
5000
5004
32 bits
5008
5012
5016
5020
32 bits
Steps for Memory Write Operation
 The processor loads MAR with the address of the Memory location.
 The Control Unit issues the Memory Write control signal.
 The processor transfers 1 word of data from the Accumulator into the
Memory locationby means of bi-directional data bus.

2.4 COMPUTER OPERATIONS (OR) INSTRUCTIONSAND
INSTRUCTION SEQUENCING
The Computer is designed to perform 4 types of operations, namely
 Data transfer operations
 ALU Operations
 I/O Operations.
 Program sequencing and control.
Digital Design &Computer Organization (Bcs302) Module 3

1. Data Transfer Operations

a) Data transfer between two registers.

Format: Opcode Source1 , Destination

The processor uses MOV instruction to perform data transfer operation between
two registersThe mathematical representation of this instruction is R1 → R2.
Ex : MOV R1 , R2 : R1 and R2 are the registers.
Where MOV is the operation code, R1 is the source operand and R2 is the
destination operand.This instruction transfers the contents of R1 to R2.
EX: Before the execution of MOV R1,R2, the contents of R1 and R2 are
as followsR1 = 34h and R2 = 65h
After the execution of MOV R1, R2, the contents of R1 and R2 are as
followsR1 = 34H and R2 = 34H

b) Data transfer from memory to register

The processor uses LOAD instruction to perform data transfer operation from
memory toregister. The mathematical representation of this instruction is
[LOCA] → ACC. Where ACC is the Accumulator.
Format : opcode operand
Ex: LOAD LOCA
For this instruction Memory Location is the source and Accumulator is the
destination.

c) Data transfer from Accumulator register to memory

The processor uses STORE instruction to perform data transfer operation from
Accumulator register to memory location. The mathematical representation of this
instruction is
[ACC] → LOCA. Where, ACC is the Accumulator.
Format: opcode operand
Ex: STORE LOCA
For this instruction accumulator is the source and memory location is the
destination.

2. ALU Operations

The instructions are designed to perform arithmetic operations such as Addition,

Subtraction, Multiplication and Division as well as logical operations such as AND,
OR and NOT operations.
Ex1: ADD R0, R1
The mathematical representation of this instruction is as follows:
R1← [R0] + [R1]; Adds the content of R0 with the content of R1 and result is
placed in R1.
 Digital Design &Computer Organization (Bcs302) Module 3
Ex2: SUB R0, R1
The mathematical representation of this instruction is as follows:
R1← [R0] - [R1] ; Subtracts the content of R0 from the content of R1 and result
is placedin R1.
EX3: AND R0, R1
; It Logically multiplies the content of R0 with the content of R1 and result isstored in
R1. (R1= R0 AND R1)
Ex4: NOT R0
It performs the function of complementation.
3) I/O Operations: The instructions are designed to perform INPUT and
OUTPUT operations. The processor uses MOV instruction to perform I/O
operations.
The input Device consists of one temporary register called as DATAIN register and
output registerconsists of one temporary register called as DATAOUT register.

a) Input Operation: It is a process of transferring one WORD of data from DATA IN

register to processor register.
Ex: MOV DATAIN, R0
The mathematical representation of this instruction is as follows,
R0← [DATAIN]
b) Output Operation: It is a process of transferring one WORD of data from processor
register to DATAOUT register.

Ex: MOV R0, DATAOUT

The mathematical representation of this instruction is as follows,
[R0]→ DATAOUT

REGISTER TRANSFER NOTATION

 Data Transfer B/w processor register & memory processor register &
I/O system.
 Represented by Standard Notations.
 processor register Represented R0, R1, R2 so on
 Address of memory location LOC, PLACE, MEM etc.
 I/O registers DATAIN , DATAOUT & so on.
 Content of registers or memory locations denoted by placing the Square
Brackets around the name of the register or memory location.
 “Add the contents of R0 with the contents of R1 and result is stored in R2”
The mathematical representation of this statement is given byR2 ←[R0] + [R1].
Such a notation is called as “Register Transfer Notation”.It uses two symbols
1. A pair of square brackets [] to indicate the contents of Memory location and
2. ← to indicate the data transfer operation. Examples

3. R2 ← [LOC]
4. R3 ←[R1]+[R2]
5. R3 ←[R1]-[R2]
Digital Design &Computer Organization (Bcs302) Module 3
ASSEMBLY LANGUAGE NOTATION
• Represent machine instructions and programs.
• These Notations use assembly language formats. Register names, names of
memory locations same as register notation.
• Move R2, R1
R1←[R2]
Contains Operaion, Source, Destination.
Consider the second statement to add data between two registers
 “Add the contents of R0 with the contents of R1 and result is stored in R2”
 The assembly language notation of this statement is given by
ADD R0 , R1, R2
Opcode source1, Source2, Destination
This instruction adds the contents of R0 with the contents of R1 and result is
stored in R2.
 The mathematical representation of this statement is given by
R2 ←[R0] + [R1].
Such a notations are called as “Assembly Language Notations”

BASIC INSTRUCTION TYPES

There are 3 types basic instructions namely
1. Three address instruction format
2. Two address instruction format
3. One address instruction format

Consider the arithmetic expression Z = A + B, Where A,B,Z are the Memory

locations.
Steps for evaluation
1. Access the first memory operand whose symbolic name is given by A.
2. Access the second memory operand whose symbolic name is given by B.
3. Perform the addition operation between two memory operands.
4. Store the result into the 3rd memory location Z.
5. The mathematical representation is Z ←[A] + [B].

a) Three address instruction format : Its format is as follows

opcode Source-1 Source-2 destination

Destination ← [source-1]+[source-2]
Ex: ADD A, B, Z
Z ← [A] + [B]
b) Two address instruction format : Its format is as follows

opcode Source Destination

Destination ← [source] + [destination]

The sequence of two address m/c instructions to evaluate the arithmetic expression
Z ← A + B are as follows
Digital Design &Computer Organization (Bcs302) Module 3

MOV A, R0
MOV B, R1
ADD R0, R1
MOV R1, Z

c) One address instruction format : Its format is as follows

opcode Operand

Ex1: LOAD B
This instruction copies the contents of memory location whose symbolic
name is given by ‘B’ into the Accumulator as shown in the figure.
The mathematical representation of this instruction is as followsACC ← [B]

Accumulator Memory

Ex2: STORE B
This instruction copies the contents of Accumulator into memory location
whose symbolic name is given by ‘B’ as shown in the figure. The mathematical
representation is as follows B ← [ACC].

Accumulator Memory

Ex3: ADD B
 This instruction adds the contents of Accumulator with the
contents of Memorylocation ‘B’ and result is stored in Accumulator.
 The mathematical representation of this instruction
is as followsACC ←[ACC]+ [B]

STRAIGHT LINE SEQUENCING AND INSTRUCTION EXECUTION

Consider the arithmetic expression

C = A+B , Where A,B,C are the memory operands.
The mathematical representation of this instruction is
C = [A] + [B].
 Digital Design &Computer Organization (Bcs302) Module 3
The sequence of instructions using two address instruction format are as
follows MOV A, R0
ADD B,
R0
MOV R0, C
Such a program is called as 3 instruction program.
NOTE: The size of each instruction is 32 bits.
The 3 instruction program is stored in successive memory locations of the processor is as
shown in the fig.

 The system bus consists of uni-directional address bus,bi-directional data

bus and control bus “It is the process of accessing the 1st instruction from
memory whose address is stored in programcounter into Instruction Register (IR)
by means of bi-directional data bus and at the same time after instruction
access the contents of PC are incremented by 4 in order to access the next
instruction. Such a process is called as “Straight Line Sequencing”.

INSTRUCTION EXECUTION
There are 4 steps for instruction execution
1. Fetch the instruction from memory into the Instruction Register (IR) whose
addressis stored in PC.
IR ← [PC]
2. Decode the instruction.
3. Perform the operation according to the opcode of an instruction

4. Load the result into the destination.

Digital Design &Computer Organization (Bcs302) Module 3
 Digital Design &Computer Organization (Bcs302) Module 3
During this process, Increment the contents of PC to point to next instruction (
In 32 bit machine increment by 4 address)
PC ← [PC] + 4.
The next instruction is fetched, from the address pointed by PC.

BRANCHING
Suppose a list of ‘N’ numbers have to be added. Instead of adding one after the
other, the add statement can be put in a loop. The loop is a straight-line of
instructions executed as many times as needed.

The ‘N’ value is copied to R1 and R1 is decremented by 1 each time in loop. In

the loop find thevalue of next elemet and add it with Ro.
In conditional branch instruction, the loop continues by coming out of sequence
only if the condition is true. Here the PC value is set to ‘LLOP’ if the condition is true.

Branch > 0 LOOP // if >0 go to LOOP

The PC value is set to LOOP, if the previous statement value is >0 ie. after
decrementing R1 valueis greater than 0.

If R1 value is not greater than 0, the PC value is incremented in a normal

sequential way and thenext instruction is executed.

Prof. Anitha C S , Dept. of CSE(Data Science) 20

 Digital Design &Computer Organization (Bcs302) Module 3
CONDITION CODE BITS

 The processor consists of series of flip-flops to store the status information

after ALU operation.
 It keeps track of the results of various operations, for subsequent usage.
 The series of flip-flip-flops used to store the status and control information
of the processor is called as “Condition Code Register”. It defines 4 flags. The
format of condition code registeris as follows.

C V Z N

1 N (NEGATIVE) Flag:
It is designed to differentiate between positive and negative
result.It is set 1 if the result is negative, and set to 0 if result is
positive.
2 Z (ZERO) Flag:
It is set to 1 when the result of an ALU operation is found to zero,
otherwise it is cleared.
3 V (OVER FLOW) Flag:
In case of 2s Complement number system n-bit number is capable of representing
a range of numbers and is given by -2 n-1 to +2n-1. . The Over-Flow flag is set to 1 if
the resultis found to be out of this range.
4 C (CARRY) Flag :
This flag is set to 1 if there is a carry from addition or borrow from subtraction, otherwise
it is cleared.

2.5 Addressing Modes

The various formats of representing operand in an instruction or location of an
operand is calledas “Addressing Mode”. The different types of Addressing Modes
are

a) Register Addressing
b) Direct Addressing
c) Immediate Addressing
d) Indirect Addressing
e) Index Addressing
f) Relative Addressing
g) Auto Increment Addressing
h) Auto Decrement Addressing

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 Digital Design &Computer Organization (Bcs302) Module 3

a. REGISTER ADDRESSING:
In this mode operands are stored in the registers of CPU. The name of the
register is directly specified in the instruction.
Ex: MOVE R1,R2 Where R1 and R2 are the Source and Destination registers
respectively. This instruction transfers 32 bits of data from R1 registerinto R2
register. This instruction does not refer memory for operands. The operands are
directly available in the registers.

b. DIRECT ADDRESSING
It is also called as Absolute Addressing Mode. In this addressing mode operands
are stored in thememory locations. The name of the memory location is directly
specified in the instruction.
Ex: MOVE LOC, R1 : Where LOC is the memory location and R1 is the
Register.This instruction transfers 32 bits of data from memory location X
into the General PurposeRegister R1.

c. IMMEDIATE ADDRESSING
In this Addressing Mode operands are directly specified in the instruction. The
source field is usedto represent the operands. The operands are represented by
# (hash) sign.
EX:MOVE #23,R0

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 Digital Design &Computer Organization (Bcs302) Module 3

d. INDIRECT ADDRESSING
In this Addressing Mode effective address of an operand is stored in the memory location or
General Purpose Register.

The memory locations or GPRs are used as the memory pointers.

Memory pointer: It stores the address of the memory location.

There are two types Indirect Addressing

i) Indirect through GPRs

ii) Indirect through memory location
i) Indirect Addressing Mode through GPRs
In this Addressing Mode the effective address of an operand is stored in the one of
the GeneralPurpose Register of the CPU.

Ex: ADD (R1), R0 ; Where R1 and R0 are GPRs

This instruction adds the data from the memory location whose address is
stored in R1 with the contents of R0 Register and the result is stored in R0
register as shown in the fig

Th. e diagrammatic representation of this addressing mode is as

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 Digital Design &Computer Organization (Bcs302) Module 3

ii) Indirect Addressing Mode through Memory Location.

In this Addressing Mode, effective address of an operand is stored in the memory location.

Ex: ADD (X), R0

This instruction adds the data from the memory location whose address is stored in ‘X’memory
location with the contents of R0 and result is stored in R0 register.

The diagrammatic representation of this addressing mode is as shown in the fig

e. INDEX ADDRESSING MODE

In this addressing mode, the effective address of an operand is computed by adding constant
value with the contents of Index Register and any one of the General Purpose Register namely
R0 to Rn-1 can be used as the Index Register. The constant value is directly specified in the
instruction.
The symbolic representations of this mode are as follows
1. X (Ri) where X is the Constant value and Ri is the GPR.
It can be represented as
EA of an operand = X + (Ri )
2. (Ri , RJ) Where Ri and Rj are the General Purpose Registers used to store
addresses of an operand and constant value respectively. It can be represented as
The EA of an operand is given by
EA = (Ri) + (Rj)
3. X (Ri , Rj) Where X is the constant value and RI and RJ are the General Purpose
Registers used to store the addresses of the operands. It can be represented as
The EA of an operand is given by EA = (Ri) + (Rj) + X

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 Digital Design &Computer Organization (Bcs302) Module 3

There are two types of Index Addressing Modes

i) Offset is given as constant.

ii) Offset is in Index Register.
Note : Offset : It is the difference between the starting effective address of the memory location and the effectiv
i) Offset is given as constant

Ex: ADD 20(R1), R2

The EA of an operand is given by EA = 20 + [R1]

This instruction adds the contents of memory location whose EA is the sum of contents of R1
with 20 and with the contents of R2 and result is placed in R2 register. The diagrammatic representation of t

ii)Offset is in Index Register

Ex: ADD 1000(R1) , R2 R1 holds the offset address of an operand.The EA of an operand is given
by EA = 1000 + [R1]
This instruction adds the data from the memory location whose address is given by [1000 +
[R1] with the contents of R2 and result is placed in R2 register.

The diagrammatic representation of this mode is as shown in the fig.

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 Digital Design &Computer Organization (Bcs302) Module 3

f. RELATIVE ADDRESSING MODE:

In this Addressing Mode EA of an operand is computed by the Index Addressing Mode. This Addressing
Mode uses PC (Program Counter)to store the EA of the next instruction instead of GPR.

The symbolic representation of this mode is X (PC).Where X is the offset value and PC is theProgram
Counter to store the address of the next instruction to be executed.

It can be represented as
EA of an operand = X + (PC).
This Addressing Mode is useful to calculate the EA of the target memory location.

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 Digital Design &Computer Organization (Bcs302) Module 3
g. AUTO INCREMENT ADDRESSING MODE
In this Addressing Mode , EA of an operand is stored in the one of the GPRs of the CPU.
This Addressing Mode increment the contents of memory register by 4 memory locations after
Operand access.
The symbolic representation is
(RI)+ Where Ri is the one of the GPR.

Ex: MOVE (R1)+ , R2

This instruction transfer’s data from the memory location whose address is stored in R1 into R3 register
and then it increments the contents of R1 by 2 memory locations(Assume operand size = 2 bytes.).in
below eg:

 After fetching the operand

6B, the instruction register
RAUTO will be automatically
incremented by 2.
 Then, updated value of RAUTO
will be 3300 + 2 = 3302.
 At memory address 3302,
the next operand will be
found.

h. AUTO DECREMENT ADDRESSING MODE

In this Addressing Mode , EA of an operand is stored in the one of the GPRs of the CPU. This
Addressing Mode decrements the contents of memory register by 4 memory locations and then
transfers the data to destination.

The symbolic representation is

-(RI) Where Ri is the one of the GPR.Ex:
MOVE - (R1) , R2
This instruction first decrements the contents of R1 by 2 memory locations and then transfer’s data of
that location to destination register.

Assume operand size = 2 bytes. Here,

 First, the instruction register

RAUTO will be decremented by 2.
 Then, updated value of RAUTO
will be 3302 – 2 = 3300.
 At memory address 3300,
the operand will be found.

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