GINEERING™ DF Ktiated to VTU, Belagavi) us Insti Cy sign and Embedded Systems) Techni SYSTEM DESIGN ; Maximum Marks: 100 ons of 20 marks each. Meno Coe vecting one from each unit. il questions selec UNIT-1 the memory hierarchy followed in embedded systems with lighting unit of data transfer between different levels. _ the advantages of interrupt driven systems over polling capacity planning for a two-level memory hierarchy stem. The first level, M1 is a cache with three capacity choices 64 Kbytes, 128 Kbytes and 256 Kbytes,. The second level, M2 is a main memory with a 4 Mbyte capacity. Let C1 and C2 be the cost Per byte and 1 and ¢2 the access times for M1 and M2 respectively. Assume Cl = 20C2 and t2 = 10t1. The cache hit ratios for the three capacities are assumed to be 0.7,0.9 and 0.98 respectively. 1) What is the average access time t, in terms of t1 = 20ns in the three cache designs? Express the average byte cost of the entire memory hierarchy if C2 = $0.2/Kbyte ’ Compare the three memory designs and indicate the order of merit in terms of average costs and average access times respectively. ‘hoose the optimal design based on the product of average cost & | average access times. | 0) 1m) | OR Design MCU system to control temperature of the furnace with following specifications. The furnace temperature must maintain at 30+5°C. Connect suitable sensors & actuators. Display the temperature on LCD. The power consumption must be minimized. Write block diagram & pseudo code of above system implementation, Show the behavior of the system using FSM. Suggest suitable MCU to be used. What is VLIW architecture? Describe code compaction. illustrate the use of hardware accelerators with suitable examples.[16-bit np counter registers of Cortex M4 CPUS- Show set and reset the same. ‘om OV to SV, and a 12 ~ bit sncoding 1.2 V and then trace ach to find the correct different interrupt masking orresponding CMSI/S functions UNIT -3 AT2ACI6A provides 16K bits (2048 Bytes) of electrically erasable vnable read-only memory (EEPROM) with serial (/2C) program: th pin diagram is shown in fig. 9.(ai) Nog epvec c gq 7pN ‘SDA; 12C data line N G3 psc. % ‘Connected to be ee ass Fig. 5.(ai); Ping diagram of AT24C164 ‘The 2048 bytes are organized into 8 pages with 256 bytes each. Addressing scheme is as follows. «Additional 3 bits are require «Each page requires 8 — bits to access ‘The device address for 12C interface is 101 ThE Soa nf the first byte indicate page addre: .d to address 8 pages. the 256 locations 0. The remaining bits ss as shown inCeltel robs ‘Write Operation: ee ae oe US acca) some COUPLE SLE LL Lo ii a Figure S(aiv); Read operation sequence Write pc 1857 firmware (BSP) to support AT24C16A assuming [2C chip support library is provided with following APIs by 12C_LPC.H and [2C_LPC18XX.c files. In the firmware, develop functions perform page write and byte read operation. Write an application program to demonstrate memory read & write operations. void I2C_Init (void); void I2C Start (void); void 12C_Stop (void); void 12C_Addr (uint8_t adr, uint8_t dir); % void I2C_Write (uint8_t byte); void 12C_Read (uint32_t ack, uint8_t *byte); An 8—bit MCU with program memory and data memory address space of 64KB with scratch pad (Part of data memory) is implemented to realize the address range FO0OH to FFFFH. The remaining memory map is realized using external memory interfacing. The read and write timing diagrams are shown in fig. 5-b. The program and data accessing is differentiated using a signal PS(PS = 1 to read program) Fig. 5.b Memory read and read ti Suitable scheme to interface d; Write iming diagram lata memory of 8KB an interfacing “diagram an lo} 4] 2 10{ 4 {2“capable of read 7Tc72 is a digital temperate apa features a cond femperatures from —55°C to + 125%. This oot controller or other ws communi at controller oF 6 Baripher thane TOT? omarface is compatible with SPI prot peripherals. The “ The am is shown in fig. 6.a() SDI: Serial data input DO: Serial data output | $CK: Serial clock “oa 00 CE: Chip enable The pin diag Fig. 6.(ai): Pin diagram of TC72 i ation into control The fig. 6.(aii) shows timing diagram for write operation into © register. FUTUNA UU UU st (C0, Sata hited o S ing de of SOX, deta cached on ating edge of SEK. AN) Fig. 6.(aii) write operati The fig. 6(aiii : peration Me iii) shows multibyte register read operation of ce sox {LULU Reed Opoation UL {Cet lad ny ee 9 oe eden a , SDI Address Byte = O2hex s00__HighZ. MSB Tere, Bye sro Bie cee Fig. 6.(aiii) Read Operation Write LPC 1857 firmware (BSP) to interface TC72 assuming following SPI support functions are available. Write an application program to demonstrate TC72 configuration write and temperature read operations. CSL of SPI is given as follows: void SPI_init() void SPI_Read (uint8_t *byte) void SPI_write (uint8_t byte) A memory system is needed in a new design to support a small amount of data storage outside of the processor. The design is based on 16 K bit CY7C128A SRAM organized as 2K x8 whose pin diagram is shown in fig. 6.b 10} 4 WE: Write Enable CE: Chip Enable Ato-Ao: 11-bit lines 1/O7-1/Oo: Data Fig. 6.bming diagram for the interface to the ata suming separate address and da Define any control signals may be | | La | terface ts, based on timing diagram UNrT.4 a Write | cotta Sea to aay software stacie 10, Show a b Mention any gy lal BHen Tay Y two Mrsiey oriefy. layers of emb application code with 46 Buideli mbedded system | tet c Write a cod Progra UNes to be § 7 le segment tan Statements, HWed while dev | complexity analysis, © Perform tin, linear | rent eloping | scare serch, Show the | OR 10 | Describe the advantages of programming in hi What is resource synchronization? Destiee level languages, < RL — RTX to synchronize resources in application Cue APIs of Perform the complexity analysis of the code se; code. Bab rotaltint ar yl], int n) ment given below: op int sum=0; s ienzit4y sum=sumtarray[i}; return sum; ‘UNIT-5 ° Write a multitasking application program to execute on Keil MCB 1800 to demonstrate creation of concurrently executing tasks to emulate the excitation of stepper motor coils by toggling of 4 LEDs. Each coil is represented by an LED. The ON status of LED indicate coil is excited. Create 4 tasks for controlling LEDs to generate pattern in fig 9a: ; 00 @ 00e0 fone) 20° @0 qQ00¢e Fig. 9.a LED Pattern F ‘and APIs of RL RTX real time kernel. .d with following BSPs: 'd corresponding LED_LPC18xx.c Use suitable kernel objects ‘The LED interface is supportes BSP of LED interface: LED ee pres void LED_Init (void); //Initializing i void LED_On (oe num); //Tarn on specified LED void LED_oif (uinta2_t num); // Turn off specified LED Define semaphore. With suitaimmmmmeem expla aavavent TPS of semaphores. 10; aes Sas OR 10} 4] 3Write a C application program using APIs of RL—ARM real time kernel to demonstrate interprocess communication using mailbox. Create a multitasking application program on Keil MCB 1800 to demonstrate creation of concurrently executing tasks. Task1 is fone ces to control the blinking of two LEDs and Task2 is to change ne and colour of the textual display on GLCD concurrently. Use to generis RIX real time kernel. Configure SysTick timer suitable Be See tick interval. BSP of LED is given in question 9 (a) can BSP of GLCD: GLED.h & Corresponding GLCD_LPC18xx.c extem void GLOD Init (void); extern void GLCD. 2x i ; extern void GLop setextColor (unsigned short color); 3ackColor (unsigned short color); LCD Clear (unsigned short color); extern void GLD_Disp : < layString (unisigned int In, unsigned int col, unsigned cher fi, unsigned char *s)