IES UNIVERSITY

IES College Of Technology Bhopal

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

SUBJECT NOTES - COMPUTER ORGANIZATION & ARCHITECTURE/
COMPUTER ARCHITECTURE

STRUCTURE OF DESKTOP COMPUTERS

The desktop computers are the computers which are usually found on a home or office desk. They
consist of processing unit, storage unit, visual display and audio as output units, and keyboard and
mouse as input units. Usually storage unit of such computer consists of hard disks, CD-ROMs, and
diskettes. Desktop computers are basically digital computers. They consist of five functionally
independent units: input, memory, arithmetic and logic, output and control units. Memory unit is also
known as storage unit, and arithmetic and logic unit (ALU) and control unit are combine as processing
unit. Fig.1.1 shows these five functional

Figure 1.1: Units of a computer

Input Unit - The input unit accepts the digital information from user with the help of input devices
such as keyboard, mouse, microphone etc. The information received from the input unit is either
stored in the memory for later use or immediately used by the arithmetic and logic unit to perform
the desired operations. The most commonly used input devices are keyboard and mouse, the
keyboard is used for entering text and numeric information. On the other hand, mouse is used to
position the screen cursor and thereby-enter the information by selecting option. Apart from
keyboard and mouse there are many other input devices are available, which include joysticks,
trackball, digitizers and scanners etc.

Memory Unit -Computer memory is a generic term for all of the different types of data storage
technology that a computer may use, including RAM, ROM, and flash memory. Some types of
computer memory are designed to be very fast, meaning that the central processing unit (CPU) can
access data stored there very quickly. Other types are designed to be very low cost, so that large
amounts of data can be stored there economically.
Another way that computer memory can vary is that some types are non-volatile, which means they
can store data on a long term basis even when there is no power. And some types are volatile, which
are often faster, but which lose all the data stored on them as soon as the power is switched off. A
computer system is built using a combination of these types of computer memory, and the exact
configuration can be optimized to produce the maximum data processing speed or the minimum cost

The key difference between primary and secondary memory is speed of access.

 Primary memory includes ROM and RAM, and is located close to the CPU on the computer
motherboard, enabling the CPU to read data from primary memory very quickly indeed. It is
used to store data that the CPU needs imminently so that it does not have to wait for it to be
delivered.

 Secondary memory by contrast, is usually physically located within a separate storage device,
such as a hard disk drive or solid state drive (SSD), which is connected to the computer system
either directly or over a network. The cost per gigabyte of secondary memory is much lower,
but the read and write speeds are significantly slower.

Output Unit-The third and final component of a computer system is the output unit. After processing
of data, it is converted into a format which humans can understand. After conversion, the output unit
displays this data to users. Examples of output devices include monitors, screens, printers and
speakers. Thus, output units basically reproduce the data formatted by the computer for users’
benefit.

CPU (CENTRAL PROCESSING UNIT)

The CPU is the brain of the Computer system. It works as an administrator of a system. All the
operations within the system are supervised and controlled by CPU. It interprets and co-ordinates the
Instructions. The data and instructions are temporarily stored in its memory unit. After performing
Operation, the result of operation can be stored in this memory unit.

Figure 1.2: CPU and its interaction with other units

The results of operation are sent towards output unit for the user. Thus, CPU controls all internal and
external devices, performs arithmetic and logical operations, and controls the memory usage and
control the sequence of operations. For performing all these operations, the CPU has three subunits.

- Arithmetic and Logic Unit (ALU)

- Control Unit
- Memory (CPU registers)
 GENERAL REGISTER ORGANIZATION-MEMORY REGISTER

Generally CPU has seven general registers. Register organization show how registers are selected
and how data flow between register and ALU. A decoder is used to select a particular register. The
output of each register is connected to two multiplexers to form the two buses A and B. The selection
lines in each multiplexer select the input data for the particular bus.
The A and B buses form the two inputs of an ALU. The operation select lines decide the micro
operation to be performed by ALU. The result of the micro operation is available at the output
bus. The output bus connected to the inputs of all registers, thus by selecting a destination register it
is possible to store the result in it.

Figure 1.3: CPU has seven general registers

Example: To perform the operation R3 = R1+R2 We have to provide following binary selection variable
to the select inputs.
1. SEL A : 001 -To place the contents of R1 into bus A.
2. SEL B : 010 - to place the contents of R2 into bus B
3. SEL OPR : 10010 – to perform the arithmetic addition A+B
4. SEL REG or SEL D : 011 – to place the result available on output bus in R3.

INSTRUCTION REGISTER

Instruction register (IR) or current instruction register (CIR) is the part of a CPU's control unit that
holds the instruction currently being executed or decoded. In simple processors, each instruction to
be executed is loaded into the instruction register, which holds it while it is decoded, prepared and
ultimately executed, which can take several steps.
Some of the complicated processors use a pipeline of instruction registers where each stage of the
pipeline does part of the decoding, preparation or execution and then passes it to the next stage for
its step. Modern processors can even do some of the steps out of order as decoding on several
instructions is done in parallel.
Decoding the op-code in the instruction register includes determining the instruction, determining
where its operands are in memory, retrieving the operands from memory, allocating processor
resources to execute the command (in super scalar processors).
The output of the IR is available to control circuits, which generate the timing signals that control the
various processing elements involved in executing the instruction.
In the instruction cycle, the instruction is loaded into the instruction register after the processor
fetches it from the memory location pointed to by the program counter.

CONTROL WORD

Consider a CPU where all the instructions require 6 clock cycles to complete their execution. Under
the instruction set there are 215 instructions and a total of 125 control signals are needed to be
generated by the control unit. While designing the horizontal micro programmed control unit single
address field format is used for branch control logic. What is the minimum size of control word and
control address register?
(a)Control word is the content of the microinstruction which contains various fields like branch
conditions, flags, control signal field, next microinstruction field. The control word to be used
currently is used in control data register just like we use MBR (Memory buffer register) in instruction
cycle.
(b) Control address means the address of a particular control word. This address is stored in control
address register just like MAR in instruction cycle. The address of the next microinstruction to be
performed is provided by micro sequencer just like program counter (PC) in instruction cycle.

Number of cycles = Number of microinstructions (Basic assumption is 1 microinstruction takes 1 cycle

to operate) = 6

Hence total number of microinstructions = 215 * 6 = 1290

Hence number of bits needed to refer to a microinstruction = ceil (log2 1290) = 11

Hence size of control address register = Number of bits for a microinstruction = 11

In horizontal microprogramming (also known as decoded version of control signals):

STACK ORGANIZATION

The computers which use Stack-based CPU Organization are based on a data structure called stack.
The stack is a list of data words. It uses Last in First out (LIFO) access method which is the most
popular access method in most of the CPU. A register is used to store the address of the topmost
element of the stack which is known as Stack pointer (SP). In this organization, ALU operations are
performed on stack data. It means both the operands are always required on the stack. After
manipulation, the result is placed in the stack

The main two operations that are performed on the operators of the stack are Push and Pop. These
two operations are performed from one end only.
1. Push –This operation results in inserting one operand at the top of the stack and it decrease the
stack pointer register. The format of the PUSH instruction is:
2. POP-This operation results in deleting one operand from the top of the stack and it increase the
stack pointer register.

INSTRUCTION FORMAT

Computer has a variety of instruction code formats, it is the control unit within the CPU that
interprets each instruction code and provides the necessary control functions needed to process the
instruction. The format of an instruction is usually depicted in a rectangular box symbolizing the bits
of the instruction as they appear in memory words or in a control register.
Operation code: - The operation code field in the instruction specifies the operation to be
performed.
The operation is specified by binary code hence the name operation code or simply opcode.

Source / Destination operand: - The source/destination operand field directly specifies the
source/destination operand for the instruction. Source operand address: - The operation specified by
the instruction may require one or more operands.

Destination operand address: - The operation executed by the CPU may produce result. Such
operand is known as destination operand. The instruction which produce result specifies the
destination operand address

ALU

Arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that carries out arithmetic and
logic operations on the operands in computer instruction words. In some processors, the ALU is
divided into two units, an arithmetic unit (AU) and a logic unit (LU). Some processors contain more
than one AU - for example, one for fixed-point operations and another for floating-point operations.
(In personal computers floating point operations are sometimes done by a floating point unit on a
separate chip called a numeric coprocessor.)

ALU has direct input and output access to the processor controller, main memory (random access
memory or RAM in a personal computer), and input/output devices. Inputs and outputs flow along an
electronic path that is called a bus. The input consists of an instruction word (sometimes called a
machine instruction word) that contains an operation code (sometimes called an "op code"), one or
more operands, and sometimes a format code. The operation code tells the ALU what operation to
perform and the operands are used in the operation. (For example, two operands might be added
together or compared logically.) The format may be combined with the op code and tells, for
example, whether this is a fixed-point or a floating-point instruction. The output consists of a result
that is placed in a storage register and settings that indicate whether the operation was performed
successfully. (If it isn't, some sort of status will be stored in a permanent place that is sometimes
called the machine status word.)

I/O SYSTEM BUS

The central processing unit memory unit and I/O unit are the hardware components/modules of the
computer. They work together with communicating each other and have paths for connecting the
Modules together. The collection of paths connecting the various modules is called the
interconnection structure. A group of wires called bus is used to provide necessary signals for
communication between modules. A bus is a shared transmission medium, it must only be used by
one device at a time and when used to connect major computer components (CPU, memory, I/O) is
‘called a system bus.

Data lines (data bus) - Move data between system modules. The data bus lines are bidirectional CPU
can read data on these lines from mentor or from a port, as well as send data out on these lines to a
memory location or to a port. Width is a key factor. It determines number of bytes that can be
transferred in one cycle and hence the overall system performance.
Address lines (address bus) - Designate source or destination of data on the data bus. It is an
unidirectional bus. Width determines the maximum possible memory capacity of the system. It also
used to address I/O ports. Typically: High -order bits select a particular module. Lower order bits
select a memory location or I/0 ports within the module.

CPU & Memory Program

The performance of the CPU is affected by the number of cores, clock speed and memory. There are
different types of volatile and non-volatile memory.

1. Processing: Computers require input hardware, processing hardware and output hardware. The
hardware that defines a computer is the CPU and memory. Without these a computer could not
function. The CPU and memory work together to run programs.
CPU - executes programs using the fetch-decode-execute cycle.
Memory - stores program operations and data while a program is being executed. There are several
types of memory, including: registers, cache, RAM and virtual memory.
Storage - stores programs and files long term, even when they are not in use. Devices such as hard
drives, USB memory sticks or SD cards are used to store files such as photos, music and software
applications long term.

2. Graphics: Most computers have a CPU and a separate graphics processing unit (GPU) for images.
The GPU can be around 10 times faster than the CPU. It is optimized to produce high-quality 3D
graphics for games and films. The GPU is responsible for handling images and frees up the CPU to do
all other tasks.

3. Measuring performance: CPU, memory and bus speeds will all affect the overall speed of a
computer. If one is significantly slower, then it will slow down the others. Benchmarking is a test used
to assess the performance of a computer. Different types of benchmark software are used for the
different kinds of application you might want a computer to do. It is difficult to assess the
performance of a CPU because a computer might excel at some tasks but not do so well at others. For
example, a computer that is going to be used for gaming will require the best combination of
hardware to handle intensive graphics quickly. The same computer might not perform so well if it was
used to analyze vast amounts of scientific data.

BUS STRUCTURE

A more efficient scheme for transferring information between registers in a multiple- register
configuration is a common bus system. A bus structure consists of a set of common lines, one for
each bit of a register, through which binary information is transferred one at a time. Control signals
determine which register is selected by the bus during each particular register transfer. A common
bus system can be constructed using multiplexers. These multiplexers select the source register
whose binary information is then placed on the bus.

Control Bus

The control bus carries the signals relating to the control and co-ordination of the various activities
across the computer, which can be sent from the control unit within the CPU.

Data Bus

This is used for the exchange of data between the processor, memory and peripherals, and is bi-
directional so that it allows data flow in both directions along the wires. Again, the number of wires
used in the data bus (sometimes known as the 'width') can differ.

Address Bus
The address bus contains the connections between the microprocessor and memory that carry the
signals relating to the addresses which the CPU is processing at that time, such as the locations that
the CPU is reading from or writing to.).

Bus structure is divided in two types

1. Single Bus Structure

Figure1.4: Single bus structure

2. Multiple Bus Structure

Multiple architecture is divided in to two types. A great number of devices on a bus will
cause performance.

REGISTER TRANSFER LANGUAGE

The digital system can be constructed with flip flops and gates using sequential logic design.
However, it is difficult redesign large digital systems using this approach. To overcome this
difficulty, large digital systems are designed using modular approach. In the modular approach,
system is partitioned into subsystems such that each subsystem performs some functional task.
Such modules are constructed from registers, counters, decoders, multiplexers, arithmetic and
logic elements and control Logic. The modules are then interconnected with common data and
control paths to form a digital system.

The features of register transfer logic

1. Uses registers as a primitive component in the digital system instead of flip-flops and gates.

2. The information flow and processing tasks among the data stored in the registers is
described in a concise and precise manner.

3. Uses a set of expressions and statements which resemble the statements used in
programming languages.

4. The presentation of digital functions in register transfer logic is very user friendly.

Register transfer

The symbolic notation used to describe the micro-operation belongs to transfers among registers
forms a syntax/ statement of a register transfer language. For example, the statement denotes a
transfer of the content of register R1 into register R2. After transfer the contents of register R2 are
replaced by the content of register R1, however the content of register R1 remain unchanged. The
term register transfer implies the availability of hardware logic circuit that can perform a stated
micro-operation and transfer the result of operation to the same or another register. Therefore just
like various programming languages we have register transfer language to specify the micro-
operations. Each statement in the register transfer language specifies the unique micro-operation.
A register transfer language also allows specifying control conditions in the statement. To specify
control conditions it uses control variable along with the colon at the leftmost side of the statement
as shown below.

Figure 1.5: Block diagram for representing R2<— R1 micro-operation

Here, T is used as a control variable it is basically a Boolean variable having value equal to 1 or 0. This
statement indicates that the content of R1 are transferred to R2 only when T=1; otherwise transfer
operation is not performed. In a computer, micro-operations are synchronized with the help of clock
signal. The micro- operation is initiated either at the rising edge or at the falling edge of the clock
signal depending on the circuit.

It is important to note that the clock is not included as a variable in the register transfer
statements. It is assumed that all transfers occur during a clock edge transition either positive or
negative. If hardware permits two micro-operations can be executed at the same time. For
example, statement exchanges the contents of two registers, they perform R2, R1, R3, R4 micro
operations simultaneously they are separated by coma in a statement.

BUS AND MEMORY TRANSFER

Bus Transfer

A digital computer has many registers and it is necessary to provide data path between them to
transfer information from one register to another. There will be excess number of wires and
controlling of those wires make circuit complex. Therefore, in multiple-register configuration a
common bus system is used to transfer information between two registers. A common bus consists
of a set of common lines, one for each bit of Register, through which binary information is
transferred one at a time control signals are used to determine which is the source register and
which is a destination register for that particular transfer. The common bus scheme can be
implemented in two ways.
1. Using multiplexers.
2. Using tri-state bus buffers.

Implementation of common bus using multiplexers four multiplexers are used to select four bits of
the source register. Each multiplexer has four input lines, two select lines and one output line. The
four input lines of multiplexer 0 (MUX 0) are connected to the bit 0 outputs of four registers such
that bit 0 of register is connected to input 0, bit 0 of register 1 is connected to input 1, bit 0 of
register 2 is connected to input 2 and bit 0 of register 3 is connected to input 3. Similarly, inputs for
MUX 1 are connected to bit 1 outputs, inputs for MUX 2 are connected to bit 2, and inputs for MUX
3 are connected to bit 3 outputs of registers 0 through 3. To avoid the complexity of the diagram,
only input connections for MUX 3 are physically shown. To show other connections labels are used.
Two same labels have connection between them.

The two selection lines S1 and S0 are connected to the selection inputs of all four multiplexers.
These lines choose the four bits of one register and transfer them into the four-line common bus
through OUT lines. When S1S0 = 00, the input 0 of all four multiplexers are selected and applied to
the outputs to transfer them on the common bus. As a result a common bus receives the contents
of register 0. Since the outputs of register 0 are connected to the input 0 of the multiplexers.
Similarly, the content of register 1 are transferred on the common bus when S1S1. The Table below
shows the register selection according to the status of S1 and S0 lines. Shown in the control input
decides the state of the output. When control input is 1, the data is available at the output, i.e. Y =
A. On the other hand, when control input is 0, the output gets to ’0’ high-impedance state.

As shown in the all tri-state buffers at the input side are control by a common control signal Rin.
When Rin is active the n-bit data from the common bus is loaded into the register. Similarly, at the
output, a common signal Rout controls all output tri—state buffers. When Rout is active the 4-bit
data from register is placed on the common bus.

Figure 1.6: Input and output tri-state buffers for the register

We can transfer the data from r1 register to R2 register by:

1. Activate the output enable signal of R1, R1 out = 1. This places the contents of R1 on the
common bus.
2. Activate the input enable signal of R2, R2 out = 1. This loads data from the common bus into the
register R2.
All operations and data transfers within the processor take place in synchronization with the clock
signal. The control signals which control a particular transfer are activated either at the rising edge
or at the falling edge of the clock cycle.

MEMORY TRANSFER

A memory is a collection of storage cells each cell store l-bit of information. The memory stores
binary information in groups of bits called words. To access information from a particular word from
main memory each word in the main memory has distinct address. This allows accessing any word
from the main memory by specifying corresponding address. The transfer of information from a
memory word to the outside environment is called a read operation. The transfer of new
information to be stored into the memory is called a write operation.

The number of words in the memory decides the size of the memory and the number of address
bits. For example, 8 -bit address can access up to 28 = 256 different words. The number of
information bits can be read or written at a time is decided by the word length (numbers of bits in
one word) of the memory. The Fig. 1.6 shows the typical connection between processor and
memory. The control lines from the processor decide the memory operation.

In case of read operation Read signal is activated. It is used to enable the active low output enable
signal of the memory. In case of write operation Write signal is activated to indicate the write
operation. The data transfer between the memory and processor takes place through the use of two
processor registers, usually called MAR (Memory Address Register) or simply AR (Address Register)
and MDR (Memory Data Register) or simply DR (Data Register).

Figure 1.7: Connection between memory and processor

It is important to note that for above operation the activation of Read signal-is not necessary; it is
necessary only when data is read from memory unit. The write operation transfers the contents of
Register A0 through A3 are the address registers. The MUX 1 selects one of the address sources for
memory. The MUX 2 selects one of data source for write operation of memory. The decoder selects
the destination register to read data from memory.
 Figure 1.8: Communication between memory unit and multiple

REGISTER ADDRESSING MODES

The address of the memory can be specified directly within the instruction. For example, MOV
[2000H], R1. In this instruction the memory address is fix, it cannot be dynamically changed in the
program itself. There are some situations where we need to change the memory address
dynamically. For example program of array, to add the data and get the total sum of all array
elements. In this we have to repeat the add instruction number of times equal to the array elements
and each time we have to add a number from a new successive memory location. Every time the
address of memory is different. So to change the address of memory each time when we enter the
loop address variable is used. Such addressing is called indirect addressing.

The operation to be performed is specified by the operation field of the instruction. The execution of
the operation is performed on some data stored in computer registers or memory words and the
way the operands are chosen during program. Selection of operands during program execution
depends on the addressing mode of the instruction. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction before the operand is actually referred.
The purpose of using address mode techniques by the computer is to accommodate one or both of
the following provisions:
 1. Fetch the instruction from memory.
2. Decode the instruction.

3. Execute the instruction.

The program counter or PC register in the computer hold the instruction in the program stored
memory. Each time when instruction is fetched from memory the PC is incremented, for it holds the
address of the instruction to be executed next. Decoding involves determination of the operation to
be performed, the addressing mode of the instruction, and the returns of the operands. The
computer then executes the instruction and returns to step 1 to fetch the next instruction in
sequence. Figure show the distinct addressing mode field of in instruction format.

The operation code (op-code) specifies the operation to be performed. The mode field issue to locate
the operands needed for the operation. An address field in an instruction may or may not be present.

1. Implied Mode: This mode specify the operands implicitly in the definition of the instruction. For
example, the instruction ‘‘complement accumulator’’ is an implied mode instruction because the
operand in the accumulator register is implied in the definition of the instruction. In fact, all
register references instructions that use an accumulator are implied mode instructions. Zero-
address introductions are implied mode instructions.

2. Immediate Mode: The operand is specified in the instruction it in this mode i.e. the immediate mode
instruction has an operand field rather than an address field. The actual operand to be used in
conjunction with the operation specified in the instruction is contained in the operand field.

3. Register Mode: In this mode the operands are in registers that reside within the CPU. The
register required is chosen from a register field in the instruction. Example: MOV R1, R2

4. Register Indirect Mode: In this mode the instruction specifies a register in the CPU that contains
the address of the operand and not the operand itself. Usage of register indirect mode instruction
necessitates the placing of memory address of the operand in the processor register with a previous
instruction. EA=R.

5.Auto increment or Auto decrement Mode: After execution of every instruction from the data in
memory it is necessary to increment or decrement the register. This is done by using the increment or
decrement instruction. Given upon its sheer necessity some computers use special mode that
increments or decrements the content of the registers automatically.

6. Direct Address Mode: In this mode the operand resides in memory and its address is given directly by
the address field of the instruction such that the affective address is equal to the address part of the
instruction.

7. Indirect Address Mode: Unlike direct address mode, in this mode give the address field gives the
address where the effective address is stored in memory. The instruction from memory is fetched
through control to read is address part to access memory again to read the effective address. A few
addressing modes require that the address field of the instruction be added to the content of a
specific register in the CPU. The effective address in these modes is obtained from the following
equation:

8. Relative Address Mode: This mode is applied often with branch type instruction where the branch
address position is relative to the address of the instruction word itself. As such in the mode the
content of the program counter is added to the address part of the instruction in order to obtain
the effective address whose position in memory is relative to the address of the next instruction.
Since the relative address can be specified with the smaller number of bits then those required the
design the entire memory address, it results in a shorter address field in the instruction format. EA =
PC + Address part of instruction

9. Indexed Addressing Mode: In this mode the effective address is obtained by adding the content of an
index register to the address part of the instruction. The index register is a special CPU register that
contains an index value and can be incremented after its value is used to access the memory. EA=
offset + R.

10. Base Register Addressing Mode: In this mode the effective address is obtained by adding the content
of a base register to the part of the instruction like that of the indexed addressing mode though the
register here is a base register and not a index register.

INSTRUCTION TYPES & FORMATS

A basic computer has three types of instructions:

1. Memory reference instructions

2. Register reference instructions

3. Input-Output instructions

Memory Reference Instructions - The Fig.1.9 shows the instruction format for memory reference
instructions. Each memory reference instruction has 16-bits. Out of 16-bits:
l-Bit (I) specifies addressing mode : Direct or indirect
3-Bits (Opcode) specify the opcode

12-Bits (Address) specify the address.

15 14 12 11 0
I Opcode Address

Figure1.9: Memory reference Instruction format

I=0 : Direct addressing mode

I=1 : Indirect addressing mode

Opcode: It can have value from 000 through 110 since there are 7 memory reference
instructions

FETCH AND EXECUTION CYCLE

Instruction Cycle

The most basic unit of computer processing in the simplest form, consists of two parts.

1. Opcode (operation code) – a portion of a machine language instruction that specifies the operation
to be performed.

2. Operands – a part of a machine language instruction that specifies the data to be Operated on

The simplest model of instruction processing can be a two step process. The CPU reads (fetches)
instructions (codes) from the memory one at a time, and executes. Instruction fetch involves reading
of an instruction from a memory location to the CPU register. The execution of this instruction may
involve several operations depending on the nature of the instruction. Instructions are processed by
the control unit in a systematic, step-by-step manner. The sequence of steps in which instructions
are loaded from memory and executed is called instruction cycle. Each step in the sequence is
referred to as a phase. Fundamentally, there are 6 phases.

1. FETCH (instruction) - This phase obtains the next instruction from memory and stores it in the IR. The
address of the next instruction to be executed is stored in the PC register. Proceeds in the following
manner

2. DECODE - In this phase the instruction stored in PC is examined in order to decide what portion of
the micro architecture needs to be involved in the execution of the instruction. For example, for a 4-
bit opcode, this can be implemented as a 4-to-16 decoder. This decoder will examine bits 12-15
stored in the IR and will activate the appropriate circuitry necessary to carry out the instruction
3. EVALUATE ADDRESS - This phase Compute the address of the memory location that is needed to
process the instruction. Some instructions do not need this phase, e.g., instructions that work
directly with the registers and do not require any operands to be loaded or stored form memory.

4. FETCH OPERANDS - In this phase, the source operands needed to carry out the instruction are
obtained from memory. For some instructions, this phase equals to loading values form the register
file. For others, this phase involves loading operands from memory

5. EXECUTE - In this phase instruction is carried out. Some instructions may not require this phase, e.g.,
data movement instructions for which all the work is actually done in the FETCH OPERANDS Phase 6.
STORE RESULTS - In this phase the result is written to its designated destination. After the 6 phases
of the instruction cycle are done, the control unit begins the next an instruction cycle basic involves
three sub cycles.

1. Fetch
2. Decode

3. Execute
The fetch phase reads the next instruction from memory into the CPU. The decode phase interprets the
opcode by decoding it. The execute phase performs the indicated operation.

Figure 1.10: Basic instruction cycles with interrupt cycle

HARDWIRED CONTROL UNIT

The control signals are generated in the control unit and provide control inputs for the multiplexers in
the common bus, control inputs in processor registers, and micro-operations for the accumulator. There
are two major types of control organization: Hardwired Control and Micro-programmed Control. In the
hardwired organization, the control logic is implemented with gates, flip-flops, decoders, and other
digital circuits. It has the advantage that it can be optimized to produce a fast mode of operation. In the
micro-programmed organization, the control information is stored in a control memory. The control
memory is programmed to initiate the required sequence of micro-operations. A hardwired control, as
the name implies, re- quires changes in the wiring among the various components if the design has to be
modified or changed. In the micro-programmed control, any required changes or modifications can be
done by updating the micro-program in control memory. A hardwired control for the basic computer is
presented in this section.

CONTROL MEMORY

Control units that use dynamic micro-programming use a writable control memory. This type of
memory can be used for writing (to change the micro-program) but is used mostly for reading. A
memory that is part of a control unit is called a Control Memory.

Micro-programmed control unit

A computer that uses a micro-programmed control unit usually has two separate memories - a main
memory and a control memory. The main memory is available to the user for storing their programs.
The contents of main memory may change when the data are manipulated and every Time the program
is changed. The user's program in main memory consists of machine instructions and data, whereas, the
control memory holds a fixed micro-program that cannot be altered by the occasional user. The micro-
program consists of micro-instructions that specify various internal control signals for execution of
register micro-operations. Each machine instruction initiates a series of microinstructions in control
memory. These microinstructions generate the micro-operations to fetch the instruction from main
memory; to evaluate the effective address, to execute the operation specified by the instruction, and to
return control to the fetch phase in order to repeat the cycle for the next instruction.

Figure 1.11: Micro-programmed Control Organization Input

The general configuration of a micro-programmed control unit is demonstrated in the block diagram
above. The control memory is assumed to be a ROM, within which all control information is
permanently stored. The control memory address register specifies the address of the microinstruction,
and the control data register holds the microinstruction read from memory. The microinstruction
contains a control word that specifies one or more micro-operations for the data processor. Once these
operations are executed, the control must determine the next address. The location of the next
microinstruction may be the following place:

1. One next in sequence, or

2. It may be located somewhere else in the control memory

3. The next address may also be a function of external input conditions.

For this reason it is necessary to use some bits of the present microinstruction to control the generation of
the address of the next microinstruction. While the micro- operations are being executed, the next address
is computed in the next address generator circuit and then transferred into the control address register to
read the next microinstruction. Thus a microinstruction contains bits for initiating micro-operations in the
data processor part and bits that determine the address sequence for the control memory.

The next address generator is sometimes called a Micro-program Sequencer, as it determines the address
sequence that is read from control memory. The address of the next microinstruction can be specified in
several ways, depending on the sequencer inputs. Typical functions of a micro-program sequencer are
incrementing the control address register by one, loading into the control address register an address from
control memory, transferring an external address, or loading an initial address to start the control
operations. The control data register holds the present microinstruction while the next address is
computed and read from memory. The data register is sometimes called a Pipeline Register. It allows the
execution of the micro-operations specified by the control word simultaneously with the generation of the
next microinstruction.

ADDRESS SEQUENCEING

A simple way to structure microinstructions is to assign one bit position to each control signal required
in the CPU. However, this scheme has one serious drawback assigning individual bits to each control
signal results in long microinstructions, because the number of required signals is usually large.
Moreover, only a few bits are used in any given instruction. The solution of this problem is to group the
control signals. Grouping technique is used to reduce the number of bits in the microinstruction.

Figure 1.12: Selection of address for control memory

Block diagram of a control memory and the associated hardware needed for selecting the next
microinstruction address. The diagram shows four different paths from which the control address
register (CAR) receives the address. The incremented increments the content of the control address
register by one, to select the next microinstruction in sequence. Branching is achieved by specifying the
branch address in one of the fields of the microinstruction. Conditional branching is obtained by using
part of the microinstruction to select a specific status bit in order to determine its condition. An
external address is transferred into control memory via a mapping logic

Special bits - Conditional branching is achieved by using part of the microinstruction to select a
specific status bit in order to determine its condition. Special bits are used to check Conditions such
as the sign bit of a number, carry- out of an adder; the mode bits in an instruction and input or output
status conditions The branch logic checks the status of these bits (1 or 0) together with the field in the
microinstruction that specifies a branch address and control the conditional branch decisions.

Branch logic - The branch logic hardware checks the status of bits reserved in the microinstruction to
take branching decision on the occurrences of specified conditions. One way to implement branch
logic hardware is given below. Suppose 8 different parameters are to be checked in a system; It
requires 8 status bits. A multiplexer can be used to implement branch logic hardware. In this case,
three bits in the microinstruction are used to specify any one of eight status bit conditions. These
three bits are used as selection input variables for the multiplexer. If the selected status bit is in the 1
state, the output of the multiplexer goes 1; otherwise it is 0. The 1 output of the multiplexer generates
a control signal that transfers the branch address from the microinstruction into the control address
register. A 0 output of the multiplexer increments the address register. When conditional branch
microinstruction is executed, the micro program follows one of two possible paths. The value of status
bit decides the selection of path. When an unconditional branch microinstruction is executed, the
branch address is loaded from control memory into the control address register. This can be
implemented by fixing the value of one status bit at the input of the multiplexer, so it. is always equal
to 1.

Mapping of Instruction

Figure 1.13: Mapping from instruction code to microinstruction address

 .

We have seen that the transformation from the instruction code bits to an address in control
memory where the micro program routine is located is referred to as a mapping process. A special
type of branch exists when a microinstruction specifies a branch to the first word in control
memory where a micro-program routine for an instruction is located. The status bits for this type of
branch are the bits in the operation code part of the instruction.

1. Placing a 0 in the most significant bit of the address.

2. Transferring the four operation code bits.

3. Clearing the two least significant bits of the control address register.

If the routine needs more than four microinstructions, it can use addresses 1000000
through 1111111. If it uses fewer than four microinstructions, the unused memory locations would
be available for other routines.

One can extend this concept to a more general mapping rule by using a ROM to specify the
mapping function. In this configuration, the bits of the instruction specify the address of a mapping
ROM. The contents of the mapping ROM give the bits for the control address register. In this way
the micro-program routine that executes the instruction can be placed in any desired location in
control memory. The mapping concept provides flexibility for adding instructions for control
memory as the need arises.

Subroutines

When a certain group of instructions is repeatedly required in a program, then instead of writing it
repeatedly, it can be stored separately and can be called in a main program whenever required.
This group of instructions is called subroutine. This is the way to use memory efficiently.

Subroutine Register

Subroutines can be used in micro programs to use control memory efficiently. When the micro
program (main routine) needs subroutine, the address of subroutine is to be loaded into the
control address register. This transfers program control from main routine to the subroutine. After
execution of subroutine, the control should be transferred back to the main routine. So, before
transferring control from main routine to the subroutine, it is necessary to store return address.
This may be accomplished by storing the incremented output from the control address register
(return address) into a subroutine register and then branching to the beginning of the Subroutine.
Upon completion of subroutine execution, the return address is restored into the control address
register from subroutine register. Thus, the subroutine register stores the return address during a
subroutine call and restores it during a subroutine return. The stack (registers organized in LIFO
fashion) can be used for the execution of subroutines.
 SEQUENCING AND EXECUTION OF MICRO INSTRUCTION.

Microinstruction Format

Figure 1.14 shows the microinstruction format for the control memory. As shown
in Fig 1.14 the microinstruction includes four fields.

1. F1, F2, F3: These are micro-operation fields. Each field is of three bits. They specify
micro-operations for the Computer.

2. CD: This two-bit field selects status bit conditions for branching operation.
The condition includes zero value in AC, sign bit of AC equal to 1 or 0, etc.

3. BR: This 2-bit field specifies the type of branch to be used. Branch types include
unconditional branch, branch if zero, and branch if negative and so on.

4. AD: This is an address field which contains a branch address. This field is of seven bits
since control memory has 128 words. (128 = 27).

Figure 1.14: Microinstruction format

MICRO-PROGRAM SEQUENCER

The subunit of the micro programmed control unit which presents an address to the control
memory is called micro program sequencer. The next-address logic of the sequencer determines
the specific address source to be loaded into the control address register.
Figure 1.15: Typical micro program sequencer organizations
AS per gives the function table for micro program sequencer. When S1S0 = 00, an external address is
transferred to CAR. The transfer from address field of microinstruction occurs when S1S0 = 01 and T =

1. When S1S0 = 10, stack register contents are transferred to CAR and when S1S0 = 11, incremented
contents of CAR are transferred to the CAR.

A call to subroutine is executed by activating push signal when S1S0 = 01. This causes a push stack
operation and a branch to the address specified by microinstruction. The return from subroutine is
executed by activating pop signal when S1S0 = 10. This cause a pop-stack operation and a branch to the
address stored on top of the stack.

Table 1.1 Function table of micro program sequence