Proceedings of the 1976 IEEE International Conference on Microelectronic Test Structures,Vol.

9, March 1996 17

Matching of MOS Transistors with Different Layout Styles

J. Bastos, M. Steyaert, B. Graindourze", W. Sansen

Katholieke Universiteit Leuven, ESAT-MICAS

Kard. Mercierlaan 94, B-3001 Heverlee, Belgium
*Alcatel Mietec, Westerring 15,9700 Oudenai3I.de,Belgium.

Abstract
A test chip with NMOS transistor pairs with different layout
styles to study its influence on matching is presented. Common
centroid structures are found to have much better matching
performance than finger style structures. They show no systematic
mismatch, and have a matching dependence on the channel area
which is in agreement with measurement results on simple
rectangle structures. Under die stress induced by packaging, finger
style transistor pairs show a spread on transistor matching up to 5
times higher than the value predicted by only considering random
fluctuation of the channel area.
Introduction
Apart from general transistor matching theory [l], little
information is available on the matching behavior of Merent
layout styles. Matching studies are typically made on simple
rectangular transistors, which become impractical for large
W/L ratios. Several layout rules are generally accepted for
optimum matching, based on assumption of process gradients,
temperature gradients, anisotropic effects, and boundary effects Fig. 1. Microphotograph of test chip with finger, quad, and waffle style
[2]. Common centroid geometries (or point symmetric) are transistors.
recommended for optimum matching. However, these
structures become increasingly complex for more than two Measurement Results
transistors, with severe penalties in area, In this paper a test
chip is described which investigates the matching behavior of Recent results on modem CMOS technologies show that
four different transistor layout styles for large WiL ratios, in a the influence of process gradients on transistor matching is
standard 0 . 7 CMOS~ technology. very weak. Indeed, no systematic mismatch can be seen on VT
The Test Chip for any of the 1iByOut structures. The matching dependence of
VT with transistor size follows the well established linear
The test structure, shown in Fig. 1, consists of a 8x6 relationship with the inverse of the transistor channel am
matrix of NMOS transistor pairs with four different layout (Fig. 3). Only, the finger structures show a slightly higher
styles and six gate areas ranging from 42pm2 to 1050pm2. random fluctuation.
Transistor dimensions are 1050/1, 660/0.7, 336/3, 36010.7, However, there is a significant systematic p mismatch
100/1, and 60/0.7 pm/pm. Transistors in one row have the observed in the simple finger structures (Fig. 4), which can
same layout style, but different area. Transistors in one not be explained by process gradients alone. It can be explained
column have the same gate area, The layout styles are by piezoresistance effects due to residual stresses induced into
presented in Fig. 2. Two layout styles are based on finger the silicon chip by packaging. It has been shown that this
structures. Fig. 2a presents two nominally equal finger style effect can significantly degrade the matching performance of
transistors. Fig. 2b presents an interdigitated finger structure. MOS transistors [4]. The observed systematic error depends on
Fig. 2c is a quad (common centroid) structure. Fig. 2d presents the transistor size, and especially on the transistor pair distance
an interdigitated waffle structure. 100 test dies have been to the center of the die. No significant systematic mismatch is
fabricated and eutectic bonded to a ceramic package. The current seen for the other structures.
factor P=pC,,WL and the threshold voltage VT are extracted. The P matching dependence on transistor size for the waffle
The extraction methodology has been described before [3]. and quad structures follows a linear relationship with the
Robust statistics are calculated on the parameter differences. inverse of the transistor channel area (Fig. 5). The extracted
mismatch modell parameter As [ 13, shown in Table I, is almost
0-7803-2783-7/36/$5.00 0 1996 IEEE
18

t I I I I 0

P I

I I I I I I I
0.02 0.04 0.06 0.08 0.1 0.17. 0.14 0.16
Ih‘nvL,[l/IJml
Fig. 3. Standard deviation of VT mismatch versus the inverse transistor
(c) area, for different layout styles.
Fig. 2. Transistor layout styles. (a) finger. (b) interdigitated finger. (c) quad.
(d) interdigitated waffle.
1050/1 D= - 4 0 0 p
- 1 -E+ 660/0.7 D= 200pm -
60% higher than the value extracted with simple rectangular E5 -B- 360/0.7 D= 200pm
structures. This can be explained by the fact that these 0.8
U
parameters are extracted on structures with small length using 9
the simple model [3].
The simple finger structure shows significant more
dispersion on 4 matching (Fig. 5 ) . This result means that, for
i o.6
0.4
this structure, the standard deviation is a measure of the
dispersion of the systematic error, and no longer reflects the 0.2
intrinsic random fluctuation of the channel area. The 0
interdigitated finger structure, surprisingly, also shows more
fluctuation on b than the waffle and quad structures. This -0.2
structure is point symmetric and should compensate for Layout Style
systematic errors. Fig. 4. Median of the relative mismatch values for different layout
styles and different transistor sizes. D is the relative distance from the die
center, in the x direction.
Conclusion
The interdigitated waffle and the quad (common centroid)
transistor layout structures show no systematic mismatch, and
the matching follows the well established linear relationship
with the inverse of the transistor channel area. Under i n d u d 0.5
die stress due to packaging, the finger style transistor pair
shows a significant /3 systematic mismatch, which is a 0.4

function of its position in the die. The finger style transistor 0

y
pair and the interdigitated finger structure show a /3 mismatch 0.3 m.7

up to 5 times higher than the value predicted by only

consideringrandom fluctuation of the channel area.
Acknowledgment
I I I I I I I
J. Bastos is supported by a grant from the Portuguese 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
I/.JnUU tllllml
National Research Board (JNICT).
Fig. 5. Standard deviation of relative B mismatch versus the inverse
transistor area, for different layout styles.
References
[l] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching TABLE I
properties of MOS transistors”, IEEEJ. Solid-state Circuits, Vol. SC-24, Mismatch fitting constants
pp.-1433-1439,1989.
[2] E. Vittoz, “The Design of High-Performance Analog Cicuits on Digital
CMOS Chips“, IEFE J. Solid State Cicuits, vol. SC 20, pp. 657-665, June small large
1985.
[3] J.-B&tos, M. Steyaert, R. Roovers, P.. Kinget, W. Sansen, B. unit
Graindourze, A. Pergoot, Er. Janssens, “Msmatch characterization of
small size MOS transistors”, Proc. IEEE Int. Conference on
Microelectronic Test Structures, Vol. 8, pp. 271-276, March 1995.
[4] J. Bastos, M. Steyaert, B. Graindourze, W. Sansen, “Influence of Die
Bonding on MOS Transistor Matching”, submitted to ICMTS’96, Trento,
Italy, March 26-28, 1996.