AN5188

Application note

External memory code execution on STM32F7x0 Value line, STM32H750 Value

line and STM32H7B0 Value line MCUs

Introduction
There is an increased demand for applications able to support new and complex features, and as a consequence there is an
increased demand for devices with a bigger Flash-memory area.
The use of external Flash memory provides higher storage capabilities with comparable performance levels while supplying a
cost efficient solution for the demand of an increased Flash-memory area.
The STM32F7x0 Value line, the STM32H750 Value line and the STM32H7B0 Value line devices respond to the market demand
with a reduced inner Flash-memory area.
This application note describes the steps needed to build an application with code execution from external memory on these
Value line devices.
It provides details on how to boot from internal Flash memory, and then jump to user-application execution from an external
memory.

Related documents
Available from the STMicroelectronics website at www.st.com:
• STM32Cube MCU Package for STM32F7 Series with HAL, low-layer drivers and dedicated middleware databrief (DB2601)
• STM32Cube MCU Package for STM32H7 Series with HAL and dedicated middleware databrief (DB3259)
• STM32F75xxx and STM32F74xxx advanced Arm®-based 32-bit MCUs reference manual (RM0385)
• STM32H743/753 advanced Arm®-based 32-bit MCUs reference manual (RM0433)
• STM32H7A3/B3 and STM32H7B0 Value line advanced Arm®-based 32-bit MCUs reference manual (RM0455)
• STM32F7 Series system architecture and performance application note (AN4667)
• Quad-SPI (QSPI) interface on STM32 microcontrollers application note (AN4760)
• Getting started with STM32H7x3 hardware development application note (AN4938)
• Getting started with STM32F7 Series MCU hardware development application note (AN4661)
• Octo-SPI (OSPI) interface on STM32 microcontrollers application note (AN5050)
• STM32CubeProgrammer software description user manual (UM2337)
• Evaluation board with STM32H7B3LI MCU user manual (UM2662)

AN5188 - Rev 2 - June 2020 www.st.com

For further information contact your local STMicroelectronics sales office.
 AN5188
General information

1 General information

This document applies to Arm®-based devices.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

AN5188 - Rev 2 page 2/21

 AN5188
External memory code execution overview

2 External memory code execution overview

2.1 External memory code execution principle
The STM32CubeF7 v1.12.0 and the STM32CubeH7 v1.7.0 firmware packages provide several applications to
demonstrate how to boot from internal Flash memory and how to configure the external memories and jump to
user application (located on the external memory). Two possible use cases are available: XiP and BootROM.
• The XiP use case is intended for "eXecute in Place" from external Flash memory (QSPI/OSPI or FMC-NOR
Flash memory). The user-application code must be linked with the target execution memory-address
(external QSPI/OSPI or FMC-NOR Flash memory).
• The BootROM use case is intended to demonstrate how to boot from the internal Flash memory, configure
the external RAM memories (SDRAM or SRAM), copy user-application binary from the code storage area
(an SDCARD or an SPI-Flash memory) to the external SDRAM or external SRAM, and then jump to the user
application. The user-application code must be linked with the target execution memory address (external
SDRAM or SRAM).
The applications described in the table below are available on the firmware package under \Applications
\ExtMem_CodeExecution for the following boards:
• 32F723EDISCOVERY board for the STM32F730 devices
• STM32756G-EVAL board for the STM32F750 devices
• STM32H743I-EVAL board for the STM32H750 devices
• STM32H7B3I_EVAL and STM32H7B3I-DK board for the STM32H7B0 devices

Table 1. Application details

Application Description

Shows how to boot from internal Flash memory, configure external memories
and then jump to user application located on external memory.
ExtMem_Boot
The user can select QSPI/OSPI Flash memory, FMC-NOR Flash memory,
external SDRAM or external SRAM for code execution.
Sample application running from external Flash memory (QSPI/OSPI Flash
ExtMem_Application\LedToggling
memory or FMC-NOR Flash memory), external SRAM or external SDRAM
Sample FreeRTOS application with execution from external Flash memory
ExtMem_Application\FreeRTOS (QSPI/OSPI Flash memory or FMC-NOR Flash memory), external SRAM or
external SDRAM

The external memory boot application is in charge of initializing the required resources to make the external
memories available and ready to use. This application initializes the required resources as per the user
configuration (see Section 3.3 Configuration).
The external memory boot application must setup the main stack pointer and configure the application to be
executed on external memory. This type of boot schema enables the support of sizable user applications.

AN5188 - Rev 2 page 3/21

 AN5188
External memory code execution principle

The external memory boot application ensures that any resources that are no longer needed after the setup
phase are reset or free before jumping to the user application. The figure below presents an overview of this boot
schema.

Figure 1. External memory code boot schema

1
Initialize volatile memory

6 FMC
Jump to the NOR PSRAM
PSRAM/
SRAM memory
user controller
SRAM
Configuration
application registers

CPU SDRAM memory

controller
SDRAM

PC

QSPI/OSPI
MSP
QSPI/OSPI QSPI/
memory OSPI
controller Flash
Configuration
5 registers
Update 3
MSP to use For BootROM
the user model, copy the
defined binary content
location from the storage
memory to the
execution
SDMMC memory

µSD memory
µSD
controller
Configuration
registers

2
Initialize the
non-volatile memory

4
De-initialize the non-
volatile memory

External memory initialization

BootROM code copy

Jump to user application

AN5188 - Rev 2 page 4/21

 AN5188
External memory boot application description

2.2 External memory boot application description

The external memory boot application contains a set of source files on the STM32CubeF7/H7 package which is
tailored to match the supported configuration for each hardware platform.
For the STM32H7B0 Value line devices, the settings of the clock and GPIO for the external memories are done
within the BSP drivers for each memory. The qspi.c file is replaced by ospi.c file .
The figure below shows an example of the superset of all files for all the supported configurations.

Figure 2. External memory boot application superset of source files

Configuration for all kind of memories controlled

by the FMC, PSRAM, SRAM, SDRAM, NOR

Main program that initializes the MCU, calls

for external memory initialization and
configuration then jump to user application.

Clock and GPIO setting

for all external memory.

Configuration procedure to initialize the QSPI-

Flash memory. Memory mapped mode for the XiP
model. 1-line regular mode for BootROM model
along with copy routine, shutdown procedure as no
longer needed after initialization.

Configuration and initialization of the

SDCARD. FatFS initialization along with
code copy routine.
Customized version of standard
system_stm32xxx.c file removing
unneeded code configuration.

AN5188 - Rev 2 page 5/21

 AN5188
Supported boot model

3 Supported boot model

The application supports two types of execution models:

• Execute in place support (XiP support)
• BootROM support
The users must select the configuration matching their needs by tuning the memory.h header file.

3.1 Execute in place (XiP) support

The XiP model is based on code execution directly from the external non-volatile memory that is used for code
storage. This execution model requires memory-mapped support to grant the CPU with direct access to the
executed-code user application. The XiP model is available on external NOR/QSPI/OSPI Flash memory through
the FMC/QSPI/OSPI interfaces.
Based on the user configuration in the memory.h file, the External memory boot application configures one of the
following volatile memories: SDRAM, SRAM, PSRAM or internal SRAM. In this model the volatile memory is used
for data only.
The following flowchart illustrates the operational flow for the XiP model.

Figure 3. XiP model operational flow

MCU reset

External memory boot initialization

DATA_AREA ≠ USE_INTERNAL_SRAM
Data memory
configuration

Configure external data memory in Memory-mapped

mode: PSRAM or SRAM or SDRAM

Configure external execution memory in Memory-

mapped mode: QSPI/OSPI-Flash or FMC NOR

Shutdown not needed resources

Cache, Systick

Main stack pointer update

Jump to user application on external memory

AN5188 - Rev 2 page 6/21

 AN5188
BootROM support

3.2 BootROM support

The BootROM model is based on code execution from a chosen volatile memory. This execution model is suitable
when binary data is stored in a memory that has no memory-mapped interface (like for SDCARD). This model is
also suitable when binary data is stored in a memory with low throughput (like for SPI-NOR (emulated using
QSPI/OSPI with 1- line)).
Based on the user configuration in the memory.h file, the external memory boot application configures two of the
following volatile memories: SDRAM, SRAM, PSRAM or internal SRAM. In this model, binary data is copied from
a non-volatile memory to one volatile memory prior to the execution by the external memory boot application. The
second volatile memory is used for data.
The following flowchart illustrates the operational flow for the BootROM model.

Figure 4. BootROM model operational flow

MCU reset

External memory boot initialization

DATA_AREA ≠ USE_INTERNAL_SRAM
Data memory
configuration

Configure external data memory in Memory-mapped

mode: PSRAM or SRAM or SDRAM

Initialize the memory used for binary storage:

SDCARD or SPI-NOR

Configure the external execution memory in Memory-

mapped mode: PSRAM or SRAM or SDRAM

Copy binary from the storage memory to the execution

memory

Shutdown not needed resources:

Storage memory, GPIO, CLK, Cache, Systick

Main stack pointer update

Jump to user application on external memory

AN5188 - Rev 2 page 7/21

 AN5188
Configuration

3.3 Configuration
The user configuration is defined by the following defines:
• DATA_AREA: it is used to specify the volatile memory that is used for data holding. Supported memories
(depending on the board used) are:
– USE_EXTERNAL_SDRAM: external SDRAM is used for data holding
– USE_EXTERNAL_SRAM: external SRAM is used for data holding
– USE_EXTERNAL_PSRAM: external PSRAM is used for data holding
– USE_INTERNAL_SRAM: internal SRAM is used for data holding
• CODE_AREA: it is used to specify the execution location of the user application. This area can be a volatile
memory for the BootROM schemas or a non-volatile for the XiP schemas. The supported memories
(depending on the hardware used) are:
– XiP model: BINARY_AREA must be undefined:
◦ USE_QSPI: QSPI Flash is used for code execution
◦ USE_OSPI: OSPI Flash is used for code execution
◦ USE_NOR: FMC-NOR is used for code execution
– BootROM model: BINARY_AREA must be defined
◦ USE_EXTERNAL_SDRAM: external SDRAM is used for code execution
◦ USE_EXTERNAL_SRAM: external SRAM is used for code execution
◦ USE_EXTERNAL_PSRAM: external PSRAM is used for code execution
◦ USE_INTERNAL_SRAM: internal SRAM is used for code execution
• BINARY_AREA: is defined in the BootROM model only. It is used to specify the location of the binary
containing the user application. Additional defines are needed depending on the chosen configuration.
Supported memories (depending on the hardware used):
– USE_SPI_NOR: SPI NOR Flash is used for binary storage
◦ BINARY_BASE_OFFSET: offset of the binary within SPI NOR Flash
◦ BINARY_SIZE: size of the binary image
– USE_SDCARD: SDCard is used for binary storage
◦ BINARY_FILENAME: name of the binary file to be executed
The user must make sure that the selected memories contain code and data to cover at least a proper user
application startup. Afterwards, the user application can initialize any other memory needed.

AN5188 - Rev 2 page 8/21

 AN5188
Summary of external memories part numbers

3.4 Summary of external memories part numbers

The following table summarizes the part numbers of the external memories used versus the board and boot
model. As there is not a dedicated board for devices of STM32F7x0 Value line, STM32H750 Value line and the
STM32H7B0 Value line, the boards (with compatible devices) that are used are:
• 32F723EDISCOVERY is used to emulate the STM32F730 devices.
• STM32F756G-EVAL is used to emulate the STM32F750 devices.
• STM32H743I-EVAL is used to emulate the STM32H750 devices.
• STM32H7B3I-EVAL and STM32H7B3I-DK are used to emulate the STM32H7B0 devices.

Table 2. External memories used on each board by boot model

32F723EDISCOVER STM32756G-EVAL STM32H743I-EVAL STM32H7B3I-EVAL STM32H7B3I-DK

Boot
Memory Y with STM32F730 with STM32F750 with STM32H750 with STM32H7B0 with STM32H7B0
model
devices devices devices devices devices

Two Quad-SPI Flash

MT25QL512ABB8ESF-
0SIT
MX25L51245GZ2I-08 N25Q512A13GSF4 Or Octo-SPI Flash NOR Octo-SPI Flash NOR
QSPI:OSPI
Flash G 0E MX25LM51245G MX25LM51245G
One twin Quad-SPI
memory (bus width : 4 lines) (bus width : 4 lines) Flash (bus width: 8 lines) (bus width: 8 lines)
XiP MT25TL01GHBB8ESF
-0SIT
(bus width : 8 lines)

NOR Flash PC28F128M29EWL

A MT28EW128ABA1L MT28EW128ABA1LP
memory - -
PC-0SI T C-0SIT
(on FMC) (bus width : 16-bit)
Two Quad-SPI Flash
MT25QL512ABB8ESF-
0SIT
SPI-NOR N25Q512A13GSF4 Or Octo-SPI Flash NOR Octo-SPI Flash NOR
(emulated 0E
- One twin Quad-SPI MX25LM51245G MX25LM51245G
with QSPI 1
BootRO line) (bus width : 2 lines) Flash (bus width: 1 line) (bus width: 1 line)
M MT25TL01GHBB8ESF
-0SIT
(bus width : 2 lines)
Transceiver
SDCARD - Native support IP4856CX25/ HSP051-4M10 HSP051-4M10
C_Module_REV
Internal
Native support Native support Native support Native support Native support
SRAM
IS61WV102416BL L IS61WV102416BL L
External IS42S32800J-6BLI
- -10ML I -10ML I -
SRAM (bus width : 32-bit)
(bus width : 16-bit) (bus width : 16-bit)
Volatile
memory External IS42S32800G-6BL I IS42S32800G-6BL I IS42S32800J-6BLI IS42S32800J-6BLI
-
SDRAM (bus width : 32-bit) (bus width : 32-bit) (bus width : 32-bit) (bus width : 16-bit)
IS66WV51216EBLL-5
External 5BLI - - - -
PSRAM
(bus width : 16-bit)

AN5188 - Rev 2 page 9/21

 AN5188
Resources constraints to be considered

4 Resources constraints to be considered

Any resources that are no longer needed after initialization (interruption, ongoing transfers, unused pins) must be
released before jumping to the user application. This must be done to avoid an extra power consumption and to
limit any interference with the user application. Especially for the BootROM model, as the peripherals used for
binary storage are no longer required, they must be reset.
The user must consider the amount of resources used by the external memory boot application in order to ensure
that the external memory interface remains up and running. The resources constraints are linked to:
• The allocation and configuration of the pins
• The configuration of the interface (QSPI/OSPI IP register must not be modified, the FMC IP register can be
partially updated)
• The RCC configuration to avoid IP reset clock disabling and clock frequency/source update in a harmful way.
The pin allocation table below is provided as reference and is valid for a pin selection according to the used
board. Other pin selection could be used based on the available alternate functions.

AN5188 - Rev 2 page 10/21

 AN5188
Resources constraints to be considered

Table 3. Pins allocated for each memory by board

32F723EDISCOVERY STM32756G-EVAL STM32H743I-EVAL STM32H7B3I-EVAL

Memory/ STM32H7B3I-DK with
with STM32F730 with STM32F750 with STM32H750 with STM32H7B0
board STM32H7B0 devices
devices devices devices devices

QSPI/OSPI PB2, PG(6,9,14), PG(6,14), PF(8, 9 ,7, PG(6,9), PB2,

PB(6, 2), PC(9,10),
Flash PB(6, 2), PF(8, 9, 8, 6) PF(6,7,8,9), PH(2,3), 6), PC(1,5), PH3, PD6, PD(11,7), PF(9,7,6),
PE2, PD13
memory PC11 PB2 PC(1,5), PH3
PD(0,1,4,5,6,7,8,9,10,1 PD(0,1,4,5,6,7,8,9,10,1
1,12,13,14,15) 1,12,13,14,15) PC(6,7),
PD(0,1,4,5,8,9,10,11,12
NOR Flash PE(2,3,4,5,6,7,8,9,10,1 PE(2,3,4,5,6,7,8,9,10,1 ,13,14,15),
memory (on - 1,12,13,14,15) 1,12,13,14,15) PE(0,1,7,8,9,10,11,12,1 -
FMC) PF(0,1,2,3,4,5,12,13,14 PF(0,1,2,3,4,5,12,13,14 3,14,15),
,15) ,15) PF(0,1,2,3,4,5,12,13,14
,15), PG(0,1,2,3,4,5)
PG(0,1,2,3,4,5) PG(0,1,2,3,4,5)
PD(0,1,3,4,5,8,9,10,11,
PD(0,1,3,4,5,8,9,10,11,
12,13,14,15)
12,13,14,15) PD(0,1,4,5,8,9,10,11,12
PE(0,1,3,4,7,8,9,10,11,
,13,14,15),
PE(0,1,3,4,7,8,9,10,11,
External 12,13,14,15) PE(0,1,7,8,9,10,11,12,1
- 12,13,14,15) -
SRAM 3,14,15),
PF(0,1,2,3,4,5,12,13,14
PF(0,1,2,3,4,5,12,13,14 PF(0,1,2,3,4,5,12,13,14
,15)
,15) ,15), PG(0,1,2,3,4,5,10)
PG(0,1,2,3,4,5,6,9,10,1
PG(0,1,2,3,4,5,10)
2,13,14)
PD(0,1,8,9,10,14,15) PD(0,1,8,9,10,14,15)
PE(0,1,7,8,9,10,11,12,1 PE(0,1,7,8,9,10,11,12,1
PA7, PD(0,1,8,9,10,14,15),
3,14,15) 3,14,15)
PD(0,1,8,9,10,14,15), PE(0,1,7,8,9,10,11,12,1
PF(0,1,2,3,4,5,11,12,13 PF(0,1,2,3,4,5,11,12,13 PE(0,1,7,8,9,10,11,12,1 3,14,15),
External
- ,14,15) ,14,15) 3,14,15), PF(0, PF(0,1,2,3,4,5,11,12,13
SDRAM
1,2,3,4,5,11,12,13,14,1 ,14,15),
PG(0,1,4,5,8,15) PG(0,1,2,3,4,5,8,15)
5), PG(0,1,4,5,8,15), PG(0,1,4,5,8,15),
PH(2,3,5,8,9,10,11,12,1 PH(5,6,7,8,9,10,11,12,1 PH(6,7) PH(5,6,7)
3,14,15) 3,14,15)
PI(0,1,2,3,4,5,6,7,9,10) PI(0,1,2,3,4,5,6,7,9,10)
PD(0,1,4,5,7,8,9,10,11,
12,14,15)
PE(0,1,7,8,9,10,11,12,1
External
3,14,15) - - - -
PSRAM
PF(0,1,2,3,4,5,12,13,14
,15)
PG(0,1,2,3,4,5)

AN5188 - Rev 2 page 11/21

 AN5188
Resources constraints to be considered

The following table summarizes the resources that must be kept unmodified. It describes a list of peripherals (or
part of peripheral) that must not be modified in order to avoid the unavailability of external storage. The mentioned
peripherals must not be reset or clock disabled, nor reconfigured in a manner that can alter their behavior.
Note: Some elements might change based on the external memory boot application configuration chosen for the
selected board. and on the platform's hardware.
Note: Single QSPI mode is not supported with the external loaders as long as the external memories are all Twin
Quad SPI Flash

Table 4. Peripherals required by memory type

32F723EDISCOVERY STM32756G-EVAL STM32H743I-EVAL STM32H7B3I-EVAL

STM32H7B3I-DK with
with STM32F730 with STM32F750 with STM32H750 with STM32H7B0
STM32H7B0 devices
devices devices devices devices

Dual QSPI Mode

QSPI/OSPI
QSPI1 (0x9000000) QSPI1 (0x9000000) QSPI is not supported OSPI (octal mode) OSPI (octal mode)
Flash memory
for this application
FMC-NOR FMC-NOR
NOR Flash FMC-NOR
- (No FMC-PSRAM / (No FMC-PSRAM / -
(on FMC) (No FMC-SRAM)
FMC-SRAM) FMC-SRAM)
FMC-SRAM FMC-SRAM
FMC-SRAM
External SRAM - (No FMC-PSRAM / (No FMC-PSRAM / -
(No FMC-NOR)
FMC-NOR) FMC-NOR)
FMC-SDRAM
External
- (200 MHz maximum FMC-SDRAM FMC-SDRAM FMC-SDRAM
SDRAM
system frequency)
FMC-SRAM
External
(No FMC-SRAM / - - - -
PSRAM
FMC-NOR)

AN5188 - Rev 2 page 12/21

 AN5188
Description of the external memory user application

5 Description of the external memory user application

5.1 Required updates
The external memory application is based on a specific boot schema, which is different from the standard one and
which supports a smooth transition from the on-chip application to the off-chip application.
There are two updates that must be done by the user as the location of the application has changed:
• Ensure the usage of the required linker file with memory mapping that corresponds to the selected boot
option.
• Update the settings of VTOR to use the right address.

5.2 Load and debug

The five boards 32F723EDISCOVERY, STM32756G-EVAL, STM32H743I-EVAL, STM32H7B3I-EVAL and
STM32H7B3I-DK have a loader for external non-volatile memories. Those loaders are provided within the
STM32CubeF7/H7 as:
• Patch for EWARM IDE
• Dedicated pack for MDK-ARM IDE
The XiP model provides a seamless load and debug experience similar to an internal Flash debugging. For
SW4STM32 IDE and STM32Cube IDE the STM32CubeProgrammer must be used for application loading on
external Flash memories.
In BootROM model, the application is compiled and linked for execution from an external volatile memory:
• External SDRAM : linker address 0xD0000000 for STM32H750 Value line and STM32H7B0 Value line, and
0xC0000000 for STM32F7x0 Value line
• External SRAM : linker address 0x68000000 for STM32H750 Value line, STM32H7B0 Value line, and
STM32F7x0 Value line
The application binary must be then stored either into the SPI_NOR Flash memory or into the SDCARD. It is up to
the boot application to copy the user application from the storage area to the execution RAM area.
As consequence, the application's load schema cannot be handled by the IDE (MDK-ARM or EWARM) external
memory Flash loader (as the application's link address and storage address are different).
Depending on the BINARY_AREA define (specified in the “memory.h” file of the boot application), this model
requires the use of the two different loading schemas below:
• SPI_NOR
The user application must be stored into the SPI-NOR Flash memory at the address 0x90000000. It has to
be done using the STM32CubeProgrammer. The output of the application must be in binary format in order
to be able to specify a different load address which is the SPI-Flash address. See details in the figure below.
• SDCARD
The user must manually copy the binary file, output of the build, into the SDCARD that is used to store the
user application, then plug the SDCARD into the evaluation board.
The figure below shows the steps to be followed to load and debug:

AN5188 - Rev 2 page 13/21

 AN5188
Debug using EWARM IDE

Figure 5. STM32CubeProgrammer

5.3 Debug using EWARM IDE

A special precaution is needed with the EWARM IDE when debugging the user application that is running from
the external memory. EWARM overrides the default CPU reset value of the PC (program counter) by the one
given in the user application (an address value within the external execution memory).
In this boot schema the user application PC address remains inaccessible until the external memory boot
application is executed (so the external memory is ready and memory mapped via the FMC or QSPI/OSPI). A
hardfault is generated if the EWARM jumps directly to the start point of the user application. To avoid the
hardfault, the user must add the "--drv_reset_to_cpu_start" command line in the debugger options as shown in
the figure below. This setting prevents the EWARM from forcing the PC and gives place to the external memory
boot application to configure the external memory before jumping to the user application.

AN5188 - Rev 2 page 14/21

 AN5188
Debug using EWARM IDE

Figure 6. Debugger command line options

AN5188 - Rev 2 page 15/21

 AN5188
Performance characterization

6 Performance characterization

When executing from external memory the performances are impacted due to the external Flash memory latency
and the longer instruction/data path. By using the STM32F7x0 Value line, STM32H750 Value line and
STM32H7B0 Value line devices, this impact is reduced thanks to the Cortex-M7 L1-cache.
The table below summarizes the EEMBC® CoreMark® scores achieved for each combination of ROM/RAM. The
best performances can be achieved when executing from the internal Flash memory. Nevertheless the loss is
significantly reduced when execution from an external memory.
These figures illustrate the impact on CPU performance when operating from external memories. The internal
Flash configuration score is provided as reference.

Table 5. EEMBC® CoreMark® score per configuration

32F723EDISCOVERY STM32H743I-EVAL STM32H7B3I-EVAL

STM32756G-EVAL with
with STM32F730 with STM32H750 with STM32H7B0
ROM memory RAM memory STM32F750 devices
devices devices devices
(I/D Cache 4K/4K)
(I/D Cache 8K/8K) (I/D Cache 16K/16K) (I/D Cache 16K/16K

Internal SRAM 1089 948 2020 1414

External SRAM - 940 1972 1380
QSPI/OSPI External
Flash memory - 871 1972 1380
SDRAM
External
1079 - - -
PSRAM
Internal SRAM - 906 2020 1414
NOR Flash External SRAM - 899 1972 1380
memory
External
- 833 1972 1380
SDRAM
External SRAM Internal SRAM - 1016 2020 1414
External
Internal SRAM - 989 2020 1414
SDRAM
Internal Flash Internal SRAM 1092 1082 2020 1414

AN5188 - Rev 2 page 16/21

 AN5188

Revision history

Table 6. Document revision history

Date Version Changes

11-Jul-2018 1 Initial release.

Added STM32H7B0 Value line in the whole document.
Updated cover.
Updated Section 2.1 External memory code execution principle.
Updated Section 2.2 External memory boot application description.
Updated Section 3.1 Execute in place (XiP) support.

16-Jun-2020 2 Updated Section 3.3 Configuration.

Added STM32H7B3I-EVAL and STM32H7B3I-DK with STM32H7B0 devices in:
• Table 2. External memories used on each board by boot model.
• Table 3. Pins allocated for each memory by board.
• Table 4. Peripherals required by memory type.
• Figure 5. STM32CubeProgrammer.
• Table 5. EEMBC® CoreMark® score per configuration.

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 AN5188
Contents

Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 External memory code execution overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 External memory code execution principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 External memory boot application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Supported boot model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Execute in place (XiP) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 BootROM support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Summary of external memories part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Resources constraints to be considered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5 Description of the external memory user application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.1 Required updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Load and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Debug using EWARM IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Performance characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

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 AN5188
List of tables

List of tables
Table 1. Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. External memories used on each board by boot model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Pins allocated for each memory by board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Peripherals required by memory type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. EEMBC® CoreMark® score per configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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 AN5188
List of figures

List of figures
Figure 1. External memory code boot schema . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. External memory boot application superset of source files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. XiP model operational flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. BootROM model operational flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. STM32CubeProgrammer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Debugger command line options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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 AN5188

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