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21301143

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SHAHED ABDULLAH
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30 views7 pages

21301143

Uploaded by

SHAHED ABDULLAH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Task-1

module fsm_1 (input wire clk,input wire reset,input wire input_w,output reg output_z);

parameter STATE0 = 3'b000, STATE1 = 3'b001, STATE2 = 3'b010, STATE3 = 3'b011, STATE4
= 3'b100;
reg [2:0] current_state, next_state;

always @(posedge clk or posedge reset) begin


if (reset)
current_state <= STATE0;
else
current_state <= next_state;
end

always @(*) begin


case (current_state)
STATE0: begin
output_z = 0;
if (input_w == 0)
next_state = STATE1;
else
next_state = STATE0;
end
STATE1: begin
output_z = 0;
if (input_w == 1)
next_state = STATE2;
else
next_state = STATE0;
end
STATE2: begin
output_z = 0;
if (input_w == 1)
next_state = STATE3;
else
next_state = STATE0;
end
STATE3: begin
output_z = 0;
if (input_w == 0)
next_state = STATE4;
else
next_state = STATE0;
end
STATE4: begin
output_z = 1;
if (input_w == 1)
next_state = STATE2;
else
next_state = STATE1;
end
default: begin
output_z = 0;
next_state = STATE0;
end
endcase
end

endmodule
Task-3

Code:

module fsm_done (input wire clk_in,input wire rst_n,input wire signal_a,input wire
signal_b,output reg match_out);

parameter IDLE = 3'b000, CHECK1 = 3'b001, CHECK2 = 3'b010, CHECK3 = 3'b011, MATCH
= 3'b100;

reg [2:0] state_reg, next_state_reg;

always @(posedge clk_in or negedge rst_n) begin


if (!rst_n)
state_reg <= IDLE;
else
state_reg <= next_state_reg;
end

always @(*) begin

next_state_reg = state_reg;
match_out = 0;

case (state_reg)
IDLE: begin
if (signal_a == signal_b)
next_state_reg = CHECK1;
end

CHECK1: begin
if (signal_a == signal_b)
next_state_reg = CHECK2;
else
next_state_reg = IDLE;
end

CHECK2: begin
if (signal_a == signal_b)
next_state_reg = CHECK3;
else
next_state_reg = IDLE;
end

CHECK3: begin
if (signal_a == signal_b)
next_state_reg = MATCH;
else
next_state_reg = IDLE;
end

MATCH: begin
match_out = 1;
if (signal_a == signal_b)
next_state_reg = CHECK1;
else
next_state_reg = IDLE;
end

default: begin
next_state_reg = IDLE;
end
endcase
End
endmodule
Task-4

module vending_machine (input clk,input reset,input [1:0] w,output reg z,output reg [1:0]
return_money );

parameter S0 = 3'b000, S5 = 3'b001, S10 = 3'b010, S15 = 3'b011,


S20 = 3'b100, S25 = 3'b101, S30 = 3'b110;

reg [2:0] state, next_state;

always @(posedge clk or posedge reset) begin


if (reset)
state <= S0;
else
state <= next_state;
end

always @(*) begin


z = 0;
return_money = 2'b00;
case (state)
S0: begin
case (w)
2'b01: next_state = S5;
2'b10: next_state = S10;
2'b11: next_state = S20;
default: next_state = S0;
endcase
end
S5: begin
case (w)
2'b01: next_state = S10;
2'b10: next_state = S15;
2'b11: next_state = S25;
default: next_state = S5;
endcase
end
S10: begin
case (w)
2'b01: next_state = S15;
2'b10: next_state = S20;
2'b11: next_state = S30;
default: next_state = S10;
endcase
end
S15: begin
case (w)
2'b01: next_state = S20;
2'b10: next_state = S25;
2'b11: next_state = S30;
default: next_state = S15;
endcase
end
S20: begin
z = 1;
next_state = S0;
end
S25: begin
z = 1;
return_money = 2'b01;
next_state = S0;
end
S30: begin
z = 1;
return_money = 2'b10;
next_state = S0;
end
default: next_state = S0;
endcase
end

endmodule

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