== 8 =— 7 Remainder in X : 100, a, Quotient in Q: 1101 (FED] FLOATING POINT NUMBER REPRESENTATION The floating point number has both umber as both an int The fo eget part a8 wel as fractional part. Thus, 0726, 23462, $85.55 et, are all floating point numbers. Similany, 10101; O40 ee ae i Point numbers in binary number systems, : The real number 555,555 also be writt r. d canals be written as 5.55555 x 10% Similarly, 0.00726 an be written as 7.26 x 10°. This form of floating point number consists of two parts Le. they are ete as a combination of mantissa (the fraction part) and the exponent. Hence, the {ting point number is ropresented by means of two pars The et par represents 8 aE jled manta he second part represents te exponent that nas Thus floating point number can be crpressed as Ne Mar where, M isthe mantissa and e represents exponent. Binary numbers are prevented exact pacer uring the For example, the binary number 11001101 ca ‘ tle proces ae aoa racer eat 1,101 can be expressed in the form of mantissa Anormalized number is the number in which the ignificant dij set Hence ry mean Mest seat gto he manta alized form. This number can be shifted i shifted left 2 places to gel x 270 that ge frm. Ts Sut Bpplaces to get 1101 x $0 that the ly in the same way except that it uses base 2 for the to make the most significant bit to be non-zero is known as normalisation eee Floating-Point Arithmetic ‘The four possible floating-point arithmetic operations are : ( Floating-point Addition {i) Floating-point Subtraction (ii) Floating-point Multiplication (i) Floating-point Division Foating-point arithmetic operations are more complicated as compared to fixed-point ons. They have its own rules and need additional hardware circuits compared to pint. Multiplication and division with floating-point numbers are easier than addition galaxy A34 5GPats ipl loes not require an alignment of thy fscas are multiplied and the exponen fone by dividing the mantissa ary Hoating-point multiplication and division d iE Pultiplication operations, the two manti mantissa get the the product term. Division can be di 1d Subtraction X is set to ze," Flosting-polnt Addition #0 z mn a Wo operand. subtraction algorithm can be stated as wo operands ar< The floating-point addition subtraction alg ponents are ads ree maner any of two number is 0; ifs0, the result is the another number, | fye exponent of J Sf he mantisas hy Finding the difference between the exponents, 50 that bog, Jyansferted to x 5 umbers have same exponent, Siponents =a 4, Perform adition or subtraction operation on two mantissas and determine the sg, Jyand ¥ te sum is of the result pethe mantissas is 4 Normalize the result value, if necessary. lipiation wit Consider X= A x Hand Y= B x1" are two floating point numbers where A and pq, |0st SH! nt bit ‘mantissas of X and Y, respectively, r is the radix (2 or 10) and a and b are the exponents whether he underf X and ¥ respectively. Before performing addition or subtraction, the two exponents a gu, most sismisTeant b must have same value. Thus, one of mantissas A or B have to be adjusted so that the tng | #ommaNeG: FF its | ‘exponents have same value. jeft so that the pr exponent is de, rnultiplication over there is no need to Example 2.2. Add two decimal floating-point numbers 1.03724237 x 19% 131701212 « 10°, “ Solution. Given, X = 1.03724237 x 10"* and ¥ = 1.31701212 x 19! Step I: Neither X or nor Y is 0. Hence, addition has to be performed. Step I right 3 times, Thus, Y = 0.00131701 x 10'° Step IIL: 1.03724237 + 0.00131701 1.03855938[Rone Remeron] Step IV: The addition float oA ibesseas «iclt* “ition of two given floaing-polas pombe Floating-Point Multiplication Multiplication of two floating-point numbers Requires to multiply the two mantissas and add the two exponents. The algorithm eae Igorithm can be explained (® Check for zeros. (i) Add the exponents. (ii) Multiply the mantissas, (i) Normalize the product. The flow chart of the algorithm is shown in Hig. 219, Th two operandgSre hat ietoed 221010 determine cine f the opemmiene eg, Ee) oF not. If any of the operand is Zero, the produ in X is set to zero and operation is stoner ane two operands are not equal to zero, the two exponents are added and the process continues The exponent of the multiplier is in q which is transferred to x since the adder is in between ‘exponents x and y. After adding the exponents xandy, the sum is transfer to x. The multiplication of the mantissas is. es as in the case of fixed point multiplication with the product in X and Q. The pyrnbers Where 4 ‘and 5 most significant bit in X is checked, to aaa and b are the exponen} whether the underflow has occurred or not. Ifthe Nn, the two exponents} most significant bit is 1, the product is already be adjusted ieee that ‘normalized. If it is 0, the mantissa in XQ is shifted to) jeft so that the product is normalized and the exponent is decremented by 1. During rs 1.03724237 x 19" ,y| multiplication overflow cannot occur and hence there is no need to check of overflow. 31701212 x 10° |BEEW IEEE STANDARD FLOATING-POINT REPRESENTATION IEEE Standard specifies two formats for representing floating-point number. One for 2 bits operand (known as single precision) and another for 64 bits operand (known as louble precision). The Institute of Electrical and Electronic Engineer (IEEE), U.S.A. mulated a standard, known as IEEE 754 floating point standard, for representing floating int numbers in computers and performing arithmetic operations with the floating point iumbers, Such standard is required to ensure portability between two different computers. Most CPU's these days have floating-points that confirm to the IEEE floating-point Standard, Both single and double precision formats use radix 2 for fractions and excess ;notation for exponents. inFig.2eee ee c In decimal number WA AyheAyAahydy 10°88 a Example 2.3: erat mel oe Meese where A,and Bare decimal digit Pony ciate oe] fo joer are Sea ae Breaking the: i eee (©) Doble paca” oot Fig. 2.14, IEEE Standard Floating-Point Formats. «sng ad tte ples cheval eT ne a eas em a et waa eS pan nd cts prea a sn yee sa cos eta | preson and 3-isin cae of double precision. Thus, a total of 32 bts i neeee forsi Tea Tosca rds dae se] tern Both formats work the same differing only by the number of | bits used to teach component of the real number. In general the components ofthe single-precivies t Iectaniueh eine Glas sti forme LF x 22-17) ere the sign of the valueis determined by the sign bit (-positive value, and Trego Yalue) Bis in unsigned binary representation. The following equation used for the douije By substitu Peat “ Sane -1.0110 Example z of the binary Solution. First, we w a single 1 to ¢ Seven positior 0.0( The numt The fract 10110100101, Lastly, th, Galaxy A34 5GExample 2.33. Convert the 32-bit single-precision IEEE standard 754 number shown below into its binary equivalent. the exponen, n 11030110101101101011000000000000 Solution. The given 32-bit number is a 1101011010110110101 1000000000000 - Breaking the 32-bit number into components, we get aa Terorr0r 01701101 ooeeeeee0000| mats starts Sionbt Exponent. € ration. nent, usi for do He cof simele A sign bit 1 means thatthe number isa negative number, {for single _ The exponent, E, will be used to determine the power of two by which our mantissa iMEle willbe multiplied. First ofall we convert tt. decal integer using the unsigned esent each Exponent, E = (10101101), n formats, XM 41x Prix Psix2e1 xP 28 +32484441 173); -negative By substituting these component in equation re double ALF x 2°"? we get =1.01101101011000000000000 x 2"7°=” — _1 01101101011 « 24° the IEEE Example 2.34. Create the 32-bit single-precision IEEE standard 754 representation s certain ofthe binary number ended to 0,900000110110100101 on. The olution. The given binary number is 5. 0.000000110110100101 First, we will change this binary number into the binary form of scientific notation with asingle 1 to the left of the decimal point. This can be done by moving the decimal point seven position to the right giving an exponent of ~7. Thus, 0.000000110110100101 = 1.10110100101 x 27 The number is positive, so the sign bit will be 0. The fraction (value after the decimal point and not including the leading 1) is 10110100101. Add 12 zeros to the end to make it 23 bits. Thus, the mantissa fraction F is - 10110100101000000000000 ix Lastly, the exponent must satisfy the equation E-127 =~7 Galaxy A34 5G= 1000000000000. | : cose 6 eens 901111000101 101001010000 ais Pr or : ision IEEE standard 754 representation os : var oF merry mnt ? er is negative. The sign bit in IEEE format is 1. - “te ey 01000000000000000000000 eee 4 127. 126 it unsigned binary value is (01111110), : y converting (126)p to binary, the -bit unsig ’ : Substhuting al of hese components into the IEEE 754 format we get Could change -cod 411 a non- as shown in F 5 E-127 < E [E]_ Lertsttio | [[ervoooooooo00000000000 on — ont Exponent, E Fraction, F : Therefore, the answer is 10111111001000000000000000000000 r ERROR-DETECTING CODES A code that uses n-bit strings need not contain 2" valid code words. An error-detecting |! fede has the property that corrupting or garbling a code word will likely produce bit string that is not a code word. The 4 system that uses an error-detecting code generates, transmits, and store only code the pari words. Thus, errors in a bit string can be detected by a simple rule ~ if the bit string is a parity c code word, it is assumed to be correct; if itis a non-code word, it contains an error. distang Galaxy A34 5G754 representation L sding 1) is 01. Add 2 is (01111110), error-detecting duce bit string ore only code bit string is a n error. Them in which an extea bit ot 1s either odd {@) Even-patity method parity method be stated in terms of the concer’ mur distance bet rsa to construct a sing! svord, called information 4 single errors ca on poeta The ability of a code to de A code detects all single errors if the mini A ae de is 2. In general, (n » 1) bits are Nee nde words. The first n bits of cod it strings minimum error bit. penta oles code word is 1) bit code wordt Setecting code with 2 se ay a which the total number of Is in a valid (n + 1) bi an eden Salty code- A code in which the total number of 188 an er Pesiied an odd-parity code. These codes are also sometimes called 1 parity is odds Chey cach usa single parity it The pay bitcan be Placed at iter ea code cod ior nat the receiver must be able to understand the pay bit and the actual 42 independent error model are {the vertices ofthe r-cube. ‘be immediately adjacent ive code words. Code gle failure ‘make ‘An n-bit code and its error-detecting properties under the i easly explained in terms of an n-cube. A code is simply a subset of ener for the code to detect all single errors, no code-word vertex can ordother code-word vertex. Figure 2.16 shows a 3-bit code with f tod 111 is immediately adjacent to code words 110, 011 and 101. Since a sin change 111 to 110, 011 oF 101 bits code does not detect all single errors. If we {ould change 11 fo 110,01 coultpon-code word, we obtain a code that does have the single-eror-detecting Property 1 tenin Hg, 2 16, No single ror can change one coe word into anther ey ba (girs | 101 Fo $001 (o) Minimum distance = 1 (6) Minimom distance does not detect all single erors. detects all single eros. Fig. 2.16. Code Words in Two different S-it Codes. The Lbit parity codes do not detect 2-bt errors since changing two Pits does not affect ‘odd number of bits. Actually, 1-bit the codes can detect errors in any theparty. However, stops after L-bit errors. Other codes, with minimum paity codes error-detection capability difance preater than 2, can be used to detect. Galaxy A34 5G____ a are Oa 's with Three Information Bi —_ - jstance 2 code Haein, TABLE 27. Dee eee Odd-parity code Aza pices OSes cadaeen oro | Oa) om 4 10 0 | 1 1 0 101 110 m1 2.12.1, Checksum ange the parity of the bits, the parity checker : re Upc oum met fe used 0 detect double errors ang will not indicate 20) ethe working of checksum method is explained as follows Poin ty ccond A 10110111 is transmitted. Next word B 00100010 is transmitted. The Initially ore vo words are added and the sum obtained is retained in the transmitter inary dia et transmitted and added to the previous sum and the new sum is retained, ae pees is added to the previous sum and after the transmission of all the words, the final sum, called checksum is also transmitted. The same operation is also done independently at the receiver and the final sum obtained at the receiver is checked against the transmitted checksum. If the two sums are equal, then there is no error. Since the double error err Error-Correcting Codes 0003010 1011000 sor1011 0011001 A code that is used t0 ,go,o11 correct errors is called an As ‘0001011f0} error-correcting _code. Ingeneral, if a code has 111001 eget y) can be used to correct errors, : ororor) ‘ that affect up to c bits. If a ue ae goot0o! code’s minimum distance is ooLsahy 1010001, 2c +d +1, it can be used to 1010011 correct errors in up to ¢ bits 0010010, and to detect in up to d eins additional bits. Consider a fragment— a yy cube for a code with ose wo minimum of 3. There are at ‘1110010 least two non-code words sarge between each pair of code a Aen words. Now, let us transmit Sez Some Code Words and Non-code Words in a 7-bit Distance 3 Code, Then a rec Be aioe inaicates 10 01010 (a) 4010110 © Non-code wordcon ret te eon BY Charging the pea Meee when ok sci ere ne Beate a woe jace a received Word is called i nd the rar was pret isp lecoding, and the hardware the Serer endo sig Tio) sea {i csi eae amet ccd have Produced it. So the boa ace this non-cod, s When a non-code word is Teceive transmitted; we only know which a g-bit error may: be corrected to. the Originally transmitted at does this is an error- ed, | We do not know w! es t know whi le Word is conan hich code word was originally what we have received: Thus 7 Wrong value as shown in Fi it y = aking this kind of mistake may pe ore! Ors ae te penalty arity checker Smite other hand, if we are cone Pea about Sy ce OE are ery une ae le errors and yf ie crore, Head Of Connecting the not eo" We can change, the decoding Erorecable 701s. Thus, we acnE same diane raalinen code tiers aa erors. Th ame distance d-code to detectap eee transain® puree M0 erors (=, gu te Mesa Fig. 21800, fae is retained, Il the words, : also done ked against 011001 | 1111001 ares easy ean tecins 228 reels) reorecay Con stng h vai eee . . ° oororor1 “S oo -\ fe All 0-3 eros are detectable (©) Correcting no Errors but Detecting upto 3-bit Errors. Fig. 2.18. Some Code and Non-code Words in a 3-bit Distance 4-Code, Galaxy A34 5G" J. Hamming developed a system that provides an orderly w Weleanipt a date charoetcyeen two code words la defined as the neck | Prove thats witie word to another, It is actualy a meme change If we chai group that co! correction. The I bits that must be changed for one postions are information bits. Each check bit is grouped with a subset of the informace oan ‘check matrix as shown in Fig. 2.19. Each check bit is group’ | of 2.bit erro with the information positions whose numbers have a 1 in the same bit when expresneee pot eae binary. For example, check bit 2 (010) is grouped with information bits 3(011), 6(110) ang 7{1), For a given combination of information bit values, each check bit is chosen to produ, —~ even parity, that is, so the total number of 1s in its group is even. “The bit positions of a parity-check matrix and the resulting code words are rearrange, so that all of the check bits are on the right, as in Fig. 2.19(b). The first two columns g Table 28 list the resulting code words, bits, as specified by a parity- Bit postion alias one 75 5 nae th 5 Groups Group name Check bits (a) Hamming Codes with Bit Positions in Numerical Order. Bit position Tame 8 een + P ‘ « ic i The prc ai IHammin, 4 parity, the Parity, the : Xd parity a Information bits (© Hamming Codes with Check Bits and Infos Galaxy A34 5GGroups ou a oF we 0100 0 0100 \ niet nor 101 101 \ toro ono. on ono | ono e a ms = 1001 100 1001 | root 1010 10. 1010 | rot 7 eh ie oa The proof also suggests how an error-correcting decoder can be designed for a received Hamming code word. First, check all of the parity groups. If all the groups have even parity, then the received word is assumed to be correct. If one or more groups have odd parity, then a single error is assumed to have occurred. The pattern of groups that have lodd parity called the syndrome must match one of the columns in the parity-check matrix; the corresponding bit position is assumed to contain the wrong value and is complemented. [For example, using the code defined by Fig. 2.19(b), suppose we receive the word 0101011 oups B and C have odd parity, corresponding to position 6 of the parity-check matrix ithe syndrome is 110,, or 6,.). By complementing the bit in position 6 of the rece'ved word, re determine that the correct word is 0001011.Ferro accrng cts on nly bo poled OC etcad , Ba Add one more rung od ca 2 tat the pay of al he bite including the ney since 2" Bees oe ome rh evnrparty cose tie it ensures ot al errors affecting, | Three pari one caber of bits are detectable ated ae de aing codes are commonly sted w dete andomag | Construct Distance-3 errors in compute ‘memory circuits acco 2.36. Encode data bits 0101 into a s Die Ds Pe yas sed ataael 1 dhe: Ongar code is received as 1111101. What is the corre semory systems, especially in large ‘mainframe computers wher, met for the bulk of the system's failures, Example seven bit even-parity Hamming Code, Solution. Dy he Example 2.97. A seven-bit Hamming code ? % Parity bits " P, checks olution Det Den Dy a Pin Damas cha sony abe ele ne ee ress 0 tae As (2) in this ¢ Bits 4,5, 6 and 7, no error G > eects Bits 2, 3, 6 and 7, error 's (2) in this : . These pa Bits 1, 3, 5 and 7, no error i in err rect is 1111111. ‘xample Bit 2 is in error, and the correct code is 111111: ae determine whether a single error occurred |__Solutio informatior Let Example 2.38. For received data 1100010, and, if so, correct the error. olution. Checking the three parity bit, groups for even-parity, we Rave: PepeouP, 4 eazaad ne ee 0e, Cogan) Pi+844+1 =14+0+040-F P,+8+241 =1+041+0=E (ever-parity) P,+4+2+1 = 0+0+140=F (failed even parity check) ‘Any even parity failure indicates an error has occurred, the bit 5 was in error. Thus, the correct digit is 6. te 2 S 4 5. 6 1 1 0 0 oO 2a J Parit 1 Pe) °0L be ommmeredee 18 9510 (=digit'6) thi pi Example 2.39. Determine the single i go Ba brane 250; Deceaeaae error-correcting code for the BCD number 10! ris Solution. First, find the number of parity bits required. Let P = 3. ‘ 2 ‘ ee be Let P = 3. ‘ n P= P=8 this x Galaxy A34 5G| (aa Romaneer ——. a rum distance since 2” 2m +p +1, wehavem+p+1=443+1=8 ling the alfecting a Thee parity bits are sufficient ) Total code bits = 4 +3 =7 and correct Construct a bit position table. uuters where Bit designation |,‘ mm ring Code, Bit position 1 3 eens Binary position number | 001 ror | uo fa Information bits as (soe it Parity bits o is the correct Parity bits are determined in the following steps = , checks bit positions 1, 3,5 and 7 and must be a 0 in order to have an even number of 4s 2) in this group. P, checks bit positions 2, 3, 6 and 7 and must be a 0 in order to have an even number of 1s (2) in this group. P, checks bit positions 4, 5, 6 and 7 and must be a 1in order to have an even number of 1s (2) in this group. ‘These parity bits are entered into the table, and the resulting combined code is 0011001. Example 2.40. Determine the single error-correcting code for the information code 10110 for odd-parity. Solution. Determine the number of parity bits required. In this case the number of information bits, m, is five. | Letp=4, 74 Verals Weknow that oo m+p+1 =5+4+1=10 Four parity bits are sufficient | Total code bits = 5+4=9 Construct a bit position table rror occurred [Bit designation Poll elle e le, |e. me Bit position Ae [a2al Sibudalede 6 fo%e | clad | ingry position number | 0001 /0010 0011} 0100101 Jorzo}ot11 | 2000 J 1001 Information bits 1 eet ie 0 | Parity bits 1 | 0 1 i Parity bits are determined as follows P, checks bit positions 1, 3, 5,7 and 9 an this group. _ Py checks bit positions 2, 3, group. ; Ps checks bit positions 4, 5, 6 and 7 and must be a 1 to have an odd number of 1s, @)in .d must be a 1 to have an odd number of 1s (3) in. 6 and 7 and must be a 0 to have an odd number of 1s (3) in Galaxy A34 5G‘Gourvten Onan P, checks bit positions 8 and 5 group. These party bits are entered into the table, and the resulting combined code is 101191) q Example 2.41. The code word 0011001 is transmitted and that 0010001 is rece, . The receiver does not know what was transmitted and must look for proper partcs¢ Example 2.44 determine ifthe code is correct. Designate any error that has occurred in transmipion Solution, even-parity is used << Solution. First, prepare a bit position table wd must be a1 to have an odd number of 1s 1) in Thus, Bit designation [ee] | [a] re ug pou puns) | oil (roe laa Rete aces act Example 24 Received code 0 | Oe etn | nas fers Oat ae ) First parity check : P, checks positions 1, 3, 5 and 7. a There are two 1s in this group. sown | Parity check is good, ~> 0 (LSB) = 3287 + Second parity check : P, checks positions 2, 3,6 and 7. = 20875 There are two 1s in this group. Thus, Parity check is good, —> 0 Example 2 Third parity check : P, checks positions 4, 5, 6 and 7, Solution. There is one 1s in this group. Parity check is bad, > 1 (MSB) Result: The error position code is 100 (binary 4). This says that the bit in the numbers position is in error. It is a 0 and should be a 1. The corrected code is 0011001, which agrees with the transmitted code Example ‘SOLVED EXAMPLES Solutior Example 2.42. Find the decimal equivalent of the binary number (1111111), Solution. The decimal equivalent number is H1x 241x241 x 241x241 x 241x241 x2 = 64432416 +8+44+241 17 Thus, (1111111), = (127). Ans. Example 2.43. Determine the decimal equivalent of the binary number (0.10101), Solution. The decimal equivalent number is tg = 1x2740x27 41x27 40x24 41x75 Exam Solut Galaxy A34 5G