Some New Methods of Timing Optimization

Yuyang Ye

Aug.31, 2024
Background

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 Timing Paths

Timing paths are composed of cell paths and wire paths.

Timing path
VDD VDD

Signal A1
A1 Wire B Z
R R A1 Z A2 Cell 3
R R ZN Wire A A2 Cell 2
A1
T1
A2
T2 A2 Cell 1

ZN

A1 R C
T3 Wire path

A2 R C
T4
Loop

VSS
Cell path

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 Timing Optimization

For each path in circuits, the slack is computed by:

slack = clock period − path delay (1)

“WNS" is the worst negative slack of circuits" and “TNS" is the total negative slack
of circuits. Thus, the timing optimization target can be formulated as:

µτ X
T ({e, e ∈ E}) = min{0, τ (e)} + µω min ω(e), (2)
N e∈E
e∈E
| {z } | {z }
TNS Target WNS Target

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 When and How?

Optimize timing during logic synthesis. Optimize timing during physical design.
Logic optimization, technology mapping Clock tree synthesis, Power planning,
and post-optimization. Placement, Routing and Gate sizing.

4x4
Path 1
Slack=-120ps 128x128
Gate U4 512x512
U1 U6 U9
Wire A after Detoured
U4 Re-routing

U2 U7 U10
Path 2 replaced Gate U4
U5 Slack=-90ps
U3 U8 U11
Path 3
Slack=-75ps

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Timing-driven Approximate Logic
synthesis

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 What is Approximate Logic Synthesis

Local Approximate Candidates (LACs) help us to achieve approximate logic

synthesis. There are two kinds of Local Approximate Candidates (LACs),
including wire-by-constant and wire-by-wire:
• Wire-by-constant substitutes a wire in the circuit with a constant logic value ‘1’ or ‘0’.
• Wire-by-wire replaces a wire (approximated wire) in the circuit with another wire
(approximation wire).

Accurate Circuit Approximate Path 1

W8 W9
Constant 0
W1 W7 W1 U1 U4
W8 FO
U1 U3 W3 1’b0
W2 W3 W5 Path 1 U2
W9 W6
W4 U2 W16 U4 FO U7 W16
W11 W6
W10 U5 W12 W14 U7 Approximate Path 2
W17 W18 W18
U6 U8 W13 U6 U8 FO
W19
W13 FO W15
W15 W19
W20 U9 W21 U10 U9 U10
W22 Path 2 W13 W22

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 Challenge 1 in Timing-driven ALS

Firstly, we should achieve tradeoffs between performance improvements and

logic errors (including error rate (ER) and error distance (ED)).

N N app
Xpi
Oacc
app
pi ̸= Opi Xpi
Ypacc
i
− Ypi
ER = ; NMED = . (3)
pi
Npi pi
Npi × (2MSB+1 − 1)

Timing optimization performance of LAC located on critical paths always

ALS under ER and ED constraints. cause high error distance results.

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 Challenge 2 in Timing-driven ALS

ALS can bring area improvements and path depth improvements. After
post-optimization, all these improvements can be converted to timing
improvements. Thus, we should achieve tradeoffs between area improvements
and path depth improvements during ALS for effective timing optimization.

Delay Accurate Circuit Optimization Gradients

Final Approximate Solutions
Gate Sizing Gradient with fastest
area decrease

Methods target only area

Gradient with fastest
Optimal Gradient timing decrease

Methods target only timing

Ours
(target both timing and area)
Area
accurate circuit area

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 Multi-modal in Timing-driven ALS

During logic synthesis, circuits can be represented at Boolean and Netlist levels.
At Boolean level, circuits are translated through CNF Formulae Encoding. At
Netlist level, circuits are translated to timing graphs to help us achieve timing
optimization.
Timing Path to bit1 (LSB) Timing Path to bit2 (MSB)
W1 W7 Input
W1 W7 Input W8
W8 W2 U1 U3 vector
W2 U1 U3 vector W5
W3
W3 W5 W9
W9
W4 U2 U4 FO Signal
W4 U2 U4 FO Signal Worst arrive
Value of time = 24ps
W6 W16 bit1 (LSB) Value of
W16
Logic depth= 1 W6 bit1 (LSB) Wire W6 W11 W12 Wire W6
W11 W12 W10 U5 U7
W10 U5 U7 W14
W14 W12 W18
U6 W17
W17 W18 U8 FO Signal
U6 Signal
U8 FO Value of
Value of W13 bit2 (MSB)
W13 W15 bit2 (MSB) Wire W12 W19 W15 Wire W12
W19 W22
W22
W20 U9 W21 U10
W20 U9 W21 U10

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 Multi-objective in Timing-driven ALS

ALS should target both timing and area to achieve the most effective timing
optimization.

CPDori (ci ) AREAori (ci )

Fit(ci ) = wcpd · + wa · . (4)
CPDapp (ci ) AREAapp (ci )

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Timing-driven Power Planning

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 What is Power Planning
A power network is designed to supply ideal voltage to various devices in the
chip and thus plays an essential role in signal integrity. One typical PG network
consists of power pads, power stripes, stacked vias, and power rails. The
configuration of a PG network strongly affects reliability issues such as IR drop
and electro-migration (EM). Moreover, the topology of a given PG network also
affects the routability and wirelength of the subsequent global routing stage.

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 Challenge 1 in Timing-driven Power Planning

Analyzing timing graphs helps us to collect timing information, including TNS

and WNS. Analyzing layouts helps us to collect physical information, including
IR drop and routability.

V-conges. H-conges. Gate Dens.

Gate Wire Path

Path 1
U1 U6 U9

U4
Path 2
U2 U7 U10

U5
Path 3
U3 U8 U11

Timing information in timing graphs. Physical information on layouts.

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 Challenge 2 in Timing-driven Power Planning
Different solutions of power planning cause different results of IR drop and
routability. The timing performance of circuits is influenced by both these results.
However, in many traditional methods, IR drop is just regarded as one constraint.

Different routability causes different

routing solutions. Thus, the wire delays
vary with routing solutions.
Different IR drops cause different cell
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 Multi-modal in Timing-driven Power Planning

During power planning, circuits can be represented at Layout and Netlist levels.
At Layout level, circuits are translated to multi-scale images. At Netlist level,
circuits are translated to timing graphs. Multi-modal helps to achieve effective
timing optimization. For example, we can give more routing spaces for cells on
critical paths rather than all paths.

Scale Scale Scale

U1 U6 U U4 U11
U4 U9 U2 4 U U3 U7
Path 1 Path 2 7 U10 Path 3

Timing Feature Encoder Timing Feature Encoder Timing Feature Encoder

U1 U4 U6 U9 U2 U4 U7 U10 U3 U4 U7 U11
Physical Feature encoder Physical Feature encoder Physical Feature encoder

Path-based Timing Feature Fusion: Scale-based Physical Feature Fusion

Critical encoding || Intra-Path encoding || Inter-Path encoding

Timing encoding Critical encoding Intra-Path encoding Inter-Path encoding

Gate-wise
U4 U4 || SUM { U1 U4 U6 U9 } || AVE { U4 U4 U4 } masking
||

U7 U7 || SUM { U2 U4 U7 U1 } || AVE { U7 U7 }
||

0
U3 U3 || SUM { U3 U4 U7 U11 } || AVE { U3 }
||

V-congestion H-congestion Gate density

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 Multi-objective in Timing-driven ALS

In past works, power planning is achieved by targeting routability under IR-drop

constraint. However, it can not be used to optimize timing effectively.

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Conclusion

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Effective Timing Optimization

Boolean Level IR drop, Routability

Netlist Level Half-perimeter wirelength

Circuit Timing
Layout Level Routed wirelength

Special Level ? Logic depth …….

Multi-modal => More information Multi-objective =>Less gap

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THANK YOU!

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