BITS Pilani

Pilani Campus

Synchronous system Timing

Using global clk signal
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Open loop global clk synchronous
system----Timing (Tclk) Parameters

R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

• Positive edge triggered system

• The setup and hold representation is more convenient in open-loop

timing systems where

• Tsetup figures in the maximum delay calculation and Thold figures in

the minimum delay calculation. 222
BITS Pilani, Pilani Campus
Edge triggered FF

Here the master latch samples the data on the

rising edge of the clock,

and the slave latch enables the data to the output

on the same edge

BITS Pilani, Pilani Campus

 FF operation-- Positive edge triggered

• Thus, the aperture time is determined by the master latch, a

• the delay is determined by the slave latch (unless the master

has an unusually high tdDQ

• When the clock goes low, the slave latch holds the output
stable.

• Note that for this arrangement to work, the contamination

delay, tcCQ, of the master latch must be greater than the
hold time, th, of the slave latch.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Timing Definitions
Register
D Q

CLK

CLK
t
tsu thold

D DATA
STABLE t

tc
2 q

Q
DATA
STABLE t

225
Timing properties of edge
triggered FF

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Edge triggered FF…..

• The aperture offset time, tao, is the time from the center of
the aperture to the rising edge of the clock.

• The output changes to its new value earliest at least a

contamination delay, tcCQ, after the clock

• The output changes to its new value (y) at most a

propagation delay, tdCQ, after the clock

BITS Pilani, Pilani Campus

Setup/ Hold Time

The setup time is the delay from the data's becoming valid
to the rising edge of the clock. because delays are
specified from the 50% point of the waveform,

So setup time is from tr /2 before the beginning of the

aperture to the rising edge of the clock.

the tr is specified from the 10% or 90% point of the

waveform.

BITS Pilani, Pilani Campus

Setup and hold time
Necessary to storing correct value in register/ FF

Setup time-----data should have its valid value ready when

register/ FF opens

Hold time----Do not change data immediately after the clk

edge has come because register takes time to ( turn off)
store the correct value at its intermediate nodes

BITS Pilani, Pilani Campus

230
 Mux-Based Latch

CLK

CLK

CLK

231
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Master-Slave (Positive Edge-
Triggered) Register

Two opposite latches trigger on edge

Also called master-slave latch pair

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Master-Slave Register--
schematic
Multiplexer-based latch pair

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

• Clk load = 6 transistors

• Transistor count = 24
• Single phase clk [ clk’ locally generated]
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Timing properties

When clk = 0
• T1 is on, T3, T4 off
• D is sampled on Qm

• Tset up= T1 + I3 + I2
• To ensure T2 has same voltage at its two
terminals else a wrong previous value may
change Qm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Timing properties
When clk = 1
• Tclk-Q = T3 + I6
• Thold = till T1 turns off / [0 (nearly]

• ----if D changes at the clk edge=1,

• ---- D goes to T1 through I1 (gets delayed)
• ---hence D reaches T1 after some delay
• If clk’ reaches T1 earlier, T1 will turn off and change
in D will not affect Qm
• If clk’ reaches T1 at the same time, T1 will turn off
and change in D will not affect Qm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Min logic delay---- Tcd

• An output may make several transitions before reaching the steady

state. The extra transitions are called a hazard or glitches.

• We denote the minimum time for output j to make its first transition
in response to a transition on input i as the contamination delay tcdji

• It is the minimum over all input states, s.

• It is the delay to the first transition caused by an input transition, or

equivalently

• it is the min. delay over all active paths in the circuit.

• It is the min. over process, temperature, and voltage variations

BITS Pilani, Pilani Campus

Max Logic Delay– Td-logic

• It is the maximum over all input states, s.

• It is the delay to the last transition caused by an input

transition, or equivalently

• it is the maximum delay over all active paths in the circuit.

• It is the maximum over process, temperature, and voltage

variations.

BITS Pilani, Pilani Campus

Open loop global clk synchronous
system----Timing (Tclk) Parameters

R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

• Positive edge triggered system

• The setup and hold representation is more convenient in open-loop

timing systems where

• Tsetup figures in the maximum delay calculation and Thold figures in

the minimum delay calculation. 238
BITS Pilani, Pilani Campus
Tclk. --- Computation time

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Timing constraint - proper
operation of data pipeline
Ideal clock

Minimum cycle time:

T > tc-q + tsu + tlogic

Hold time constraint:

thold < t(c-q, cd) + t(logic, cd)

BITS Pilani, Pilani Campus

Non ideal Clock

Two non idealities

• Clock skew
– Spatial variation in arrival time of a clock transition.

– It is caused by mismatches in clock path or clock load

– It can be positive or negative depending upon routing

direction and position of clock source

– Clock skew does not result in clock period variation but

only in phase shift

BITS Pilani, Pilani Campus

 Positive and Negative Skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

CLK tCLK1 tCLK2 tCLK3

delay delay
(a) Positive skew

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

tCLK1 tCLK2 tCLK3

delay delay CLK

(b) Negative skew

242
 Positive Skew

TCLK + d
TCLK
1 3
CLK1
d

CLK2 2 4
d + th

Launching edge arrives before the receiving edge

243
Impact of positive clock skew
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

Minimum cycle time:

T +  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

244
Race condition

Hold time constraint:

thold +  < t(c-q, cd) + t(logic, cd)

245
BITS Pilani, Pilani Campus
Negative Skew

TCLK - 
TCLK
1 3
CLK1

CLK2 2 4


Receiving edge arrives before the launching edge

246
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Impact of negative clock skew

R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

Minimum cycle time:

T -  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

247
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
No Race condition

• Probability of race condition is reduced or nil

thold -  < t(c-q, cd) + t(logic, cd)

• System never fails as new data latched on to R1 never

gets transferred to R2 as it would turn off

248
BITS Pilani, Pilani Campus
Period Jitter

Period Jitter is defined as the measure of maximum change in a clock

output transition from its ideal position during a single period.
This type of jitter is considered in high-speed designs.
Typically It is measured as:
Tjit (per) = Tcycle - 1/Fo,
where Fo is the frequency of the input clk signal.
Consider an input clock signal of 20 MHz being applied to a driver.
If the output on the driver has a measured period (Tcycle) of 51ns on the
oscilloscope then, Tjit = 51 -1/20Mhz =1ns
BITS Pilani, Pilani Campus
Cycle to cycle jitter
• Period jitter measures the clock across a large number of its own cycles
and provides the minimum, nominal, and maximum difference compared
to the statistical mean of those measurements.

• Cycle-to-cycle jitter measures the delta change from one clock period to
its adjacent clock period.

BITS Pilani, Pilani Campus

 Impact of Jitter---always slows down
 TC LK 
  t j itter
CLK 
-tji tte r 

REGS Combinat ional

In Logi c

CLK t log ic
tc-q , tc-q, cd t log ic, cd
ts u, thold
tjitter

251
Combined Impact

Minimum time available (neg. skew)

Tclk -δ - 2tjitter ≥ tc-q + tlogic + t su

or
Tclk ≥ tc-q + tlogic + t su +δ +2tjitter
Hold time constraint (pos/ neg skew)– same clk
edge at R1, and R2. No change in time period

thold +δ ≤ tc-q cd + tlogic, cd

•Minimum time available (pos skew)

Tclk +δ - 2tjitter ≥ tc-q + tlogic + t su

Tclk ≥ tc-q + tlogic + t su -δ +2tjitter 253

 BITS Pilani
Pilani Campus

END