MATERIA: Diseño Digital.

LAB #1 Getting Started with Vivado HLS

TECNOLÓGICO NACIONAL DE MÉXICO

Instituto Tecnológico de Oaxaca
Departamento de ingeniería electrónica

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MATERIA: ÁREA DE CONOCIMIENTO 1
Plataformas IDE
DISEÑO DIGITAL CON VERILOG
Plataforma Vivado HLS and Verilog
Catedrático: Ing. Miguel Ángel Pérez Solano
Language
Alumno:
Calificación:

OBJETIVES: After completing this LAB, you will be able to:

➢ Create a Vivado project with Verilog HDL model(s) and targeting a specific FPGA
device located on the Nexys 4 DDR board.
➢ Use the provided partially completed Xilinx Design Constraint (.xdc) file to
constrain some of the pin locations.
➢ Add additional constraints using the Tcl scripting feature of Vivado
➢ Simulate the design using the XSim simulator of Vivado.
➢ Synthesize and implement the design
➢ Generate the bitstream.
➢ Configure the FPGA using the generated bitstream and verify the functionality

I: INTRODUCTION

This LAB guides you through the design flow using Xilinx Vivado software to create a simple
digital circuit using Verilog HDL. A typical design flow consists of creating model(s), creating
user constraint file(s), creating a Vivado project, importing the created models, assigning
created constraint file(s), running behavioral simulation, synthesizing the design,
implementing the design, generating the bitstream, and finally verifying the functionality in
the hardware by downloading the generated bitstream file on the FPGA. You will go through
the typical design flow targeting the Artix-7 based Nexys 4 DDR board. The typical design
flow is shown below. The circled number indicates the corresponding step in this LAB.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

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Design Description: The design consists of implement the seven gates (AND, OR, NOT
NAND, NOR, XOR and XNOR) with 4 inputs type BUS each one. At the end of this LAB we
will use the Nexys4 DDR Development Board, stimulating the gates with switches and the
results in LEDs. See figure 2.

General Flow for this tutorial:

➢ Create a Vivado project and analyze source files.

➢ Simulate the design using XSim simulator.
➢ Synthesize the design.
➢ Perform the timing simulation.
➢ Implement the design.
➢ Verify the functionality in hardware using the Nexys4 DDR board.

1.1: Create a Vivado Project using IDE.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

✓ Launch Vivado and create a project targeting the XC7a100T-csg324-1 (Nexys4 DDR)
device and using the Verilog HDL. Use the provided CourseE3x.v and
Nexys4DDR_Master.xdc file, downloading it from page https://solano.org.com.

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✓ Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 3
2020.1 or with the icon in the desktop.

✓ In the Quick Start pane, Click Create New Project to start the wizard. You will see
Create a New Vivado Project dialog box. Click Next.

✓ Enter VivadoCourse in the Project name field. Make sure that the Create Project
Subdirectory box is checked.

✓ Click the Browse button of the Project location field of the New Project form and
select the location where will be saved your files. Click Next.

✓ Select RTL Project option in the Project Type form, and click Next. Make sure that
Do not specify sources at this time is checked. Click next.

✓ Select Verilog as the Target language and Simulator language in the Add Sources
form.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

✓ In the Default Part form, using the Parts option and various drop-down fields of the
Filter section, select the xc7a100tcsg324-1 part (for Nexys4 DDR). Click Next

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✓ Now we will obtain a New project summary. Check if all options selected are all right.

✓ Click Finish to create the Vivado project. Use the Windows Explorer and look at the
directory that you selected to save your project. You will see the following hierarchy
of directories. It will be used later:

1.2 Create the source file to describe the circuit.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

In the project manager, go to the sources window click in the plus sign (+).

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✓ In Add sources, select < add or create design sources >. Click next.
✓ In this pane, select create, then select in the file type <Verilog> and in the file name
write <_7Gates4in>, File location don´t change. click next. Then finish.

✓ Now define the module, you will be asked to enter inputs and outputs. Enter X [3:0]
as inputs and out [6:0] as outputs. Click ok.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

✓ Once the source file was created, click in its name in the sources window and check
that besides the project summary you will find the file tab.

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✓ Now open the file PR1_1.v of LAB #1 that was explained in class. Copy all the built-
in primitives that describe the 7 gates. You will have this code.

✓ Now you have to check if there aren’t errors.

✓ Notice in the Verilog code that the first line defines the timescale directive for the
simulator.
✓ Line 7: It is a comment line describing something related with the circuit.
✓ Line 3: This line defines the beginning (marked with keyword module) and,
✓ Line 15: Defines the end of the module (marked with keyword endmodule).
✓ Lines 4 y 5: These lines define the input and output ports whereas,
✓ Lines 8-14: Describe the actual functionality of the circuit.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

1.3 Synthesize the Design:

Synthesize the design with the Vivado synthesis tool and analyze the Project
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Summary output. 7

✓ Click on Run Synthesis under the Synthesis tasks of the Flow Navigator pane. The
synthesis process will be run on the PR1_1.v file. When the process is completed a
Synthesis Completed dialog box with three options will be displayed.

Click on the various links to see what information they provide and which allows you to
change the synthesis settings.

✓ Click on the Table tab in the Project Summary Tab. Notice that there are an estimated
two LUTs and 11 IOs (4 inputs and 7 outputs) that are used.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

✓ Once the project was synthetized, check the schematic diagram in the RTL analysis
in the flow navigator pane. Note: this is an RTL schematic diagram.

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✓ To view the schematic based in LUTs (technology implementation) Click on

Schematic under the Open Synthesized Design of the Flow Navigator pane to view
the synthesized design in a schematic with LUTs.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

Notice that IBUF and OBUF are automatically instantiated (added) to the design as the input
and output are buffered. The logical gates are implemented in LUTs. Seven gates in RTL
analysis output is mapped into four LUTs in the synthesized output.

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1.4 Simulate the Design using the XSim Simulator: 9

In the project manager, go to the sources window click in the plus sign (+).

✓ In Add sources, select < add or create simulation sources >. Click next.
✓ In this pane, select create, then select in the file type <Verilog> and in the file name
write <TB_7Gates4in>, don´t change file location. click next. Then finish.

✓ Select the Sources tab and expand the Simulation Sources group. The
<TB_7Gates4in.v> file is added under the Simulation Sources group, and
<_7Gates4in.v> is automatically placed in its hierarchy.

✓ Newly ask for input and output ports. Write the same names that in the source file.
Click in sources window on TB_Gates4in and it will be open next to project summary.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

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✓ Now, write the code for testbench in the following way.

The testbench defines the simulation step size and the resolution in line 1. The testbench
module definition begins on line 3. Line 9 instantiates the dut (device/module under test).
Lines 13 through 19 define the stimuli applied to the circuit, each one with delay of 50 ns.
Line 20 ends the testbench. The $monitor helps to automatically print out variable or
expression values.

✓ Once the code is complete, select <run simulation> in the flow navigator pane.
After some time, the simulator shows the waveforms in function of the stimulus
applied.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

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✓ With this results, check if the circuit is working fine.
✓ Click on the Zoom Fit button, located left of the waveform window to see
the entire waveform.
✓ Notice that the output changes when the input changes.
✓ You can also float the simulation waveform window by clicking on the Float button
on the upper right hand side of the view. This will allow you to have a wider window to
view the simulation waveforms. To reintegrate the floating window back into the GUI,
simply click on the Dock Window button.
✓ In the waveforms windows, select X [3:0], right-click, select Radix, and then select
binary or Hex. Similarly, change the radix of out[6:0] to Hexadecimal. Also you can
change signal color for better interpretation.

1.5 Include the Xilinx Design Constraints file (.xdc).

✓ In Add sources, select < add or create constraints >. Click next.
✓ In this pane, select create, then select in the file type <XDC> and in the file name
write <_7Gates4in>, File location don´t change. click next. Then finish.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

✓ Select the Sources tab and expand the Constraint group. The <_7Gates4in.xdc>
file is added under the Constrains group.

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✓ Now Open the file <Nexys4DDR_Master.xdc> and copy; SW[3:0] and LED [6:0]
lines and paste them into _7gates4in.xdc file. This file contains these lines:

✓ Now, assign the binary variables and uncomment the lines, as follows:

✓ Save the file. You are assigned the variable to pines of the Artix 7 Nexys4 DDR.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

1.6 Implement the Design.

✓ Implement the design with the Vivado Defaults Implementation settings and analyze
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the Project Summary output. 13
✓ Click on Run Implementation under the Implementation tasks of the Flow Navigator
pane.

✓ The implementation process will be run on the synthesis output files. When the
process is completed an Implementation Completed dialog box with three options will
be displayed.

✓ Select Open implemented design and click OK as we want to look at the implemented
design in a Device view tab.

1.7 Generate the Bitstream and Verify Functionality.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

✓ Make sure that in the Nexys4 DDR, the power supply source jumper is set to USB.
Connect the board to the PC and power it ON. Generate the bitstream, open a
hardware session, and program the FPGA.
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✓ Click ok, Analyze the report.

✓ Open target.

1.8 Program device.

Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano

 MATERIA: Diseño Digital.
LAB #1 Getting Started with Vivado HLS

In the time that the code is downloading to the board, LED done is flashing, at the end if all
is ok, the LED done is kept illuminated.

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Departamento de Ingeniería Electrónica DOCENTE: Ing. Miguel Ángel Pérez solano